TimeQuest Timing Analyzer report for SUSKA-III-C
Thu Dec 09 15:58:29 2021
Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow Model Fmax Summary
  7. Slow Model Setup Summary
  8. Slow Model Hold Summary
  9. Slow Model Recovery Summary
 10. Slow Model Removal Summary
 11. Slow Model Minimum Pulse Width Summary
 12. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
 13. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
 14. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 15. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 16. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 17. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 18. Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 19. Slow Model Setup: 'CODEC_SCLK'
 20. Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 21. Slow Model Setup: 'CLK_PLL1'
 22. Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 23. Slow Model Hold: 'CODEC_SCLK'
 24. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 25. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 26. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 27. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 28. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
 29. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
 30. Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 31. Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 32. Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 33. Slow Model Hold: 'CLK_PLL1'
 34. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 35. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 36. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 37. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 38. Slow Model Recovery: 'CODEC_SCLK'
 39. Slow Model Removal: 'CODEC_SCLK'
 40. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 41. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 42. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 43. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 44. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
 45. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
 46. Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 47. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 48. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 49. Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 50. Slow Model Minimum Pulse Width: 'CLK_PLL1'
 51. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 52. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 53. Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 54. Slow Model Minimum Pulse Width: 'CLK_PLL2'
 55. Slow Model Minimum Pulse Width: 'CRT_PIN4_CLK1'
 56. Slow Model Minimum Pulse Width: 'CODEC_SCLK'
 57. Setup Times
 58. Hold Times
 59. Clock to Output Times
 60. Minimum Clock to Output Times
 61. Propagation Delay
 62. Minimum Propagation Delay
 63. Output Enable Times
 64. Minimum Output Enable Times
 65. Output Disable Times
 66. Minimum Output Disable Times
 67. Fast Model Setup Summary
 68. Fast Model Hold Summary
 69. Fast Model Recovery Summary
 70. Fast Model Removal Summary
 71. Fast Model Minimum Pulse Width Summary
 72. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
 73. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
 74. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 75. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 76. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 77. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 78. Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 79. Fast Model Setup: 'CODEC_SCLK'
 80. Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 81. Fast Model Setup: 'CLK_PLL1'
 82. Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 83. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 84. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 85. Fast Model Hold: 'CODEC_SCLK'
 86. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 87. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 88. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
 89. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
 90. Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 91. Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 92. Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 93. Fast Model Hold: 'CLK_PLL1'
 94. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 95. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 96. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 97. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 98. Fast Model Recovery: 'CODEC_SCLK'
 99. Fast Model Removal: 'CODEC_SCLK'
100. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
101. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
102. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
103. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
104. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
105. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
106. Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
107. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
108. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
109. Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
110. Fast Model Minimum Pulse Width: 'CLK_PLL1'
111. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
112. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
113. Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
114. Fast Model Minimum Pulse Width: 'CLK_PLL2'
115. Fast Model Minimum Pulse Width: 'CRT_PIN4_CLK1'
116. Fast Model Minimum Pulse Width: 'CODEC_SCLK'
117. Setup Times
118. Hold Times
119. Clock to Output Times
120. Minimum Clock to Output Times
121. Propagation Delay
122. Minimum Propagation Delay
123. Output Enable Times
124. Minimum Output Enable Times
125. Output Disable Times
126. Minimum Output Disable Times
127. Multicorner Timing Analysis Summary
128. Setup Times
129. Hold Times
130. Clock to Output Times
131. Minimum Clock to Output Times
132. Progagation Delay
133. Minimum Progagation Delay
134. Setup Transfers
135. Hold Transfers
136. Recovery Transfers
137. Removal Transfers
138. Report TCCS
139. Report RSKM
140. Unconstrained Paths
141. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
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(including device programming or simulation files), and any 
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Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
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Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                    ;
+--------------------+-----------------------------------------------------------------+
; Quartus II Version ; Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition ;
; Revision Name      ; SUSKA-III-C                                                     ;
; Device Family      ; Cyclone II                                                      ;
; Device Name        ; EP2C35F484C7                                                    ;
; Timing Models      ; Final                                                           ;
; Delay Model        ; Combined                                                        ;
; Rise/Fall Delays   ; Unavailable                                                     ;
+--------------------+-----------------------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+------------------------------------------------------------------------------------------------+
; SDC File List                                                                                  ;
+------------------------------------------------------------+--------+--------------------------+
; SDC File Path                                              ; Status ; Read at                  ;
+------------------------------------------------------------+--------+--------------------------+
; ../../../rtl/vhdl/SUSKA-III-C/suska_cycloneII_core_ste.sdc ; OK     ; Thu Dec 09 15:57:51 2021 ;
+------------------------------------------------------------+--------+--------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                             ;
+------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------+-------------------------------------------+---------------------------------------------+
; Clock Name                                                 ; Type      ; Period ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master        ; Source                                    ; Targets                                     ;
+------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------+-------------------------------------------+---------------------------------------------+
; CLK_PLL1                                                   ; Base      ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { CLK_PLL1 }                                ;
; CLK_PLL2                                                   ; Base      ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { CLK_PLL2 }                                ;
; CODEC_SCLK                                                 ; Base      ; 81.400 ; 12.29 MHz ; 0.000 ; 40.700 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { CODEC_SCLK }                              ;
; CRT_PIN4_CLK1                                              ; Base      ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { CRT_PIN4_CLK1 }                           ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; Generated ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CLK_PLL1      ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ; { I_SYSCLOCKS|altpll_component|pll|clk[0] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Generated ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CRT_PIN4_CLK1 ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ; { I_SYSCLOCKS|altpll_component|pll|clk[0] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; Generated ; 31.250 ; 32.0 MHz  ; 0.000 ; 15.625 ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; CLK_PLL1      ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ; { I_SYSCLOCKS|altpll_component|pll|clk[1] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Generated ; 31.250 ; 32.0 MHz  ; 0.000 ; 15.625 ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; CRT_PIN4_CLK1 ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ; { I_SYSCLOCKS|altpll_component|pll|clk[1] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; Generated ; 20.833 ; 48.0 MHz  ; 0.000 ; 10.416 ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; CLK_PLL1      ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ; { I_SYSCLOCKS|altpll_component|pll|clk[2] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Generated ; 20.833 ; 48.0 MHz  ; 0.000 ; 10.416 ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; CRT_PIN4_CLK1 ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ; { I_SYSCLOCKS|altpll_component|pll|clk[2] } ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; Generated ; 39.062 ; 25.6 MHz  ; 0.000 ; 19.531 ; 50.00      ; 5         ; 8           ;       ;        ;           ;            ; false    ; CLK_PLL2      ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ; { I_AUXCLOCKS|altpll_component|pll|clk[0] } ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; Generated ; 25.390 ; 39.39 MHz ; 0.000 ; 12.695 ; 50.00      ; 13        ; 32          ;       ;        ;           ;            ; false    ; CLK_PLL2      ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ; { I_AUXCLOCKS|altpll_component|pll|clk[1] } ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; Generated ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CLK_PLL2      ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ; { I_AUXCLOCKS|altpll_component|pll|clk[2] } ;
+------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------+-------------------------------------------+---------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Fmax Summary                                                                                                                            ;
+-------------+-----------------+------------------------------------------------------------+-------------------------------------------------------+
; Fmax        ; Restricted Fmax ; Clock Name                                                 ; Note                                                  ;
+-------------+-----------------+------------------------------------------------------------+-------------------------------------------------------+
; 9.86 MHz    ; 9.86 MHz        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;                                                       ;
; 9.86 MHz    ; 9.86 MHz        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;                                                       ;
; 37.35 MHz   ; 37.35 MHz       ; CODEC_SCLK                                                 ;                                                       ;
; 44.46 MHz   ; 44.46 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;                                                       ;
; 44.46 MHz   ; 44.46 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;                                                       ;
; 61.58 MHz   ; 61.58 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;                                                       ;
; 61.58 MHz   ; 61.58 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;                                                       ;
; 352.86 MHz  ; 352.86 MHz      ; CLK_PLL1                                                   ;                                                       ;
; 448.43 MHz  ; 448.43 MHz      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ;                                                       ;
; 523.29 MHz  ; 450.05 MHz      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; limit due to high minimum pulse width violation (tch) ;
; 1158.75 MHz ; 450.05 MHz      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; limit due to high minimum pulse width violation (tch) ;
+-------------+-----------------+------------------------------------------------------------+-------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------+
; Slow Model Setup Summary                                                             ;
+------------------------------------------------------------+---------+---------------+
; Clock                                                      ; Slack   ; End Point TNS ;
+------------------------------------------------------------+---------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; -36.638 ; -1643.620     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; -36.638 ; -1643.620     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; -21.205 ; -4262.856     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; -21.205 ; -4262.856     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -19.476 ; -32535.297    ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -19.476 ; -32535.297    ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 23.160  ; 0.000         ;
; CODEC_SCLK                                                 ; 27.313  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 38.199  ; 0.000         ;
; CLK_PLL1                                                   ; 59.666  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 60.589  ; 0.000         ;
+------------------------------------------------------------+---------+---------------+


+-------------------------------------------------------------------------------------+
; Slow Model Hold Summary                                                             ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; CODEC_SCLK                                                 ; -0.086 ; -0.248        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 0.224  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.224  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 0.445  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.445  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 0.445  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.445  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 0.445  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 0.445  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 0.445  ; 0.000         ;
; CLK_PLL1                                                   ; 0.629  ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------+
; Slow Model Recovery Summary                                                         ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 22.437 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 22.437 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 22.439 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 22.439 ; 0.000         ;
; CODEC_SCLK                                                 ; 78.982 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------+
; Slow Model Removal Summary                                                         ;
+------------------------------------------------------------+-------+---------------+
; Clock                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------+-------+---------------+
; CODEC_SCLK                                                 ; 2.128 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 2.403 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 2.403 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 3.362 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 3.362 ; 0.000         ;
+------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width Summary                                              ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 7.852  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 7.852  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 11.584 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 13.061 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 13.061 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 18.420 ; 0.000         ;
; CLK_PLL1                                                   ; 30.139 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 30.139 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 30.139 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 30.139 ; 0.000         ;
; CLK_PLL2                                                   ; 31.250 ; 0.000         ;
; CRT_PIN4_CLK1                                              ; 31.250 ; 0.000         ;
; CODEC_SCLK                                                 ; 38.136 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                                                                        ;
+---------+----------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                            ; To Node                                           ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -36.638 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 47.105     ;
; -36.638 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 47.105     ;
; -36.494 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.961     ;
; -36.494 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.961     ;
; -36.459 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.926     ;
; -36.459 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.926     ;
; -36.420 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.887     ;
; -36.420 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.887     ;
; -36.407 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.874     ;
; -36.407 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.874     ;
; -36.275 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.742     ;
; -36.275 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.742     ;
; -36.162 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.629     ;
; -36.162 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.629     ;
; -36.140 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.607     ;
; -36.140 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.607     ;
; -36.100 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.567     ;
; -36.100 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.567     ;
; -36.084 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.551     ;
; -36.084 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.551     ;
; -36.031 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.498     ;
; -36.031 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.498     ;
; -35.903 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 46.366     ;
; -35.903 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 46.366     ;
; -35.901 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.368     ;
; -35.901 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 46.368     ;
; -35.759 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 46.222     ;
; -35.759 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 46.222     ;
; -35.724 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 46.187     ;
; -35.724 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 46.187     ;
; -35.685 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 46.148     ;
; -35.685 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 46.148     ;
; -35.672 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 46.135     ;
; -35.672 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 46.135     ;
; -35.612 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 46.077     ;
; -35.612 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 46.077     ;
; -35.540 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 46.003     ;
; -35.540 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 46.003     ;
; -35.468 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.933     ;
; -35.468 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.933     ;
; -35.433 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.898     ;
; -35.433 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.898     ;
; -35.427 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.890     ;
; -35.427 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.890     ;
; -35.419 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.882     ;
; -35.419 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.882     ;
; -35.405 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.868     ;
; -35.405 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.868     ;
; -35.394 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.859     ;
; -35.394 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.859     ;
; -35.389 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.005      ; 45.848     ;
; -35.389 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.005      ; 45.848     ;
; -35.381 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.846     ;
; -35.381 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.846     ;
; -35.365 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.828     ;
; -35.365 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.828     ;
; -35.349 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.812     ;
; -35.349 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.812     ;
; -35.296 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.759     ;
; -35.296 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.759     ;
; -35.275 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.738     ;
; -35.275 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.738     ;
; -35.249 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.714     ;
; -35.249 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.714     ;
; -35.240 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.703     ;
; -35.240 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.703     ;
; -35.204 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.000      ; 45.658     ;
; -35.204 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.000      ; 45.658     ;
; -35.201 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.664     ;
; -35.201 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.664     ;
; -35.188 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.651     ;
; -35.188 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.651     ;
; -35.180 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.000      ; 45.634     ;
; -35.180 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.000      ; 45.634     ;
; -35.166 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.629     ;
; -35.166 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.629     ;
; -35.136 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.601     ;
; -35.136 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.601     ;
; -35.129 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.594     ;
; -35.129 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.594     ;
; -35.114 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.579     ;
; -35.114 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.579     ;
; -35.109 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.005      ; 45.568     ;
; -35.109 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.005      ; 45.568     ;
; -35.074 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.539     ;
; -35.074 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.539     ;
; -35.065 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 45.532     ;
; -35.065 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 45.532     ;
; -35.060 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.000      ; 45.514     ;
; -35.060 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.000      ; 45.514     ;
; -35.058 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.523     ;
; -35.058 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.523     ;
; -35.056 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.519     ;
; -35.056 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.009      ; 45.519     ;
; -35.044 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.509     ;
; -35.044 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.011      ; 45.509     ;
; -35.036 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.000      ; 45.490     ;
; -35.036 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.000      ; 45.490     ;
; -35.025 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.000      ; 45.479     ;
; -35.025 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.000      ; 45.479     ;
+---------+----------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                                                                        ;
+---------+----------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                            ; To Node                                           ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -36.638 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 47.105     ;
; -36.638 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 47.105     ;
; -36.494 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.961     ;
; -36.494 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.961     ;
; -36.459 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.926     ;
; -36.459 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.926     ;
; -36.420 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.887     ;
; -36.420 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.887     ;
; -36.407 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.874     ;
; -36.407 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.874     ;
; -36.275 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.742     ;
; -36.275 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.742     ;
; -36.162 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.629     ;
; -36.162 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.629     ;
; -36.140 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.607     ;
; -36.140 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.607     ;
; -36.100 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.567     ;
; -36.100 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.567     ;
; -36.084 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.551     ;
; -36.084 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.551     ;
; -36.031 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.498     ;
; -36.031 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.498     ;
; -35.903 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 46.366     ;
; -35.903 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 46.366     ;
; -35.901 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.368     ;
; -35.901 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 46.368     ;
; -35.759 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 46.222     ;
; -35.759 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 46.222     ;
; -35.724 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 46.187     ;
; -35.724 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 46.187     ;
; -35.685 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 46.148     ;
; -35.685 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 46.148     ;
; -35.672 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 46.135     ;
; -35.672 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 46.135     ;
; -35.612 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 46.077     ;
; -35.612 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 46.077     ;
; -35.540 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 46.003     ;
; -35.540 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 46.003     ;
; -35.468 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.933     ;
; -35.468 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.933     ;
; -35.433 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.898     ;
; -35.433 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.898     ;
; -35.427 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.890     ;
; -35.427 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.890     ;
; -35.419 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.882     ;
; -35.419 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.882     ;
; -35.405 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.868     ;
; -35.405 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.868     ;
; -35.394 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.859     ;
; -35.394 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.859     ;
; -35.389 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.005      ; 45.848     ;
; -35.389 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.005      ; 45.848     ;
; -35.381 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.846     ;
; -35.381 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.846     ;
; -35.365 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.828     ;
; -35.365 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.828     ;
; -35.349 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.812     ;
; -35.349 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.812     ;
; -35.296 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.759     ;
; -35.296 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.759     ;
; -35.275 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.738     ;
; -35.275 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.738     ;
; -35.249 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.714     ;
; -35.249 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.714     ;
; -35.240 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.703     ;
; -35.240 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.703     ;
; -35.204 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.000      ; 45.658     ;
; -35.204 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.000      ; 45.658     ;
; -35.201 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.664     ;
; -35.201 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.664     ;
; -35.188 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.651     ;
; -35.188 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.651     ;
; -35.180 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.000      ; 45.634     ;
; -35.180 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.000      ; 45.634     ;
; -35.166 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.629     ;
; -35.166 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.629     ;
; -35.136 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.601     ;
; -35.136 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.601     ;
; -35.129 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.594     ;
; -35.129 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.594     ;
; -35.114 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.579     ;
; -35.114 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.579     ;
; -35.109 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.005      ; 45.568     ;
; -35.109 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.005      ; 45.568     ;
; -35.074 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.539     ;
; -35.074 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.539     ;
; -35.065 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 45.532     ;
; -35.065 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 45.532     ;
; -35.060 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.000      ; 45.514     ;
; -35.060 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.000      ; 45.514     ;
; -35.058 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.523     ;
; -35.058 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.523     ;
; -35.056 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.519     ;
; -35.056 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.009      ; 45.519     ;
; -35.044 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.509     ;
; -35.044 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.011      ; 45.509     ;
; -35.036 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.000      ; 45.490     ;
; -35.036 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.000      ; 45.490     ;
; -35.025 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.000      ; 45.479     ;
; -35.025 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.000      ; 45.479     ;
+---------+----------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                              ;
+---------+----------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                            ; To Node                                                                                 ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -21.205 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.833     ;
; -21.205 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.833     ;
; -21.205 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.833     ;
; -21.205 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.833     ;
; -21.061 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.689     ;
; -21.061 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.689     ;
; -21.061 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.689     ;
; -21.061 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.689     ;
; -21.026 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.654     ;
; -21.026 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.654     ;
; -21.026 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.654     ;
; -21.026 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.654     ;
; -20.987 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.615     ;
; -20.987 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.615     ;
; -20.987 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.615     ;
; -20.987 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.615     ;
; -20.974 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.602     ;
; -20.974 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.602     ;
; -20.974 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.602     ;
; -20.974 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.602     ;
; -20.842 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.470     ;
; -20.842 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.470     ;
; -20.842 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.470     ;
; -20.842 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.470     ;
; -20.729 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.357     ;
; -20.729 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.357     ;
; -20.729 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.357     ;
; -20.729 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.357     ;
; -20.707 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.335     ;
; -20.707 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.335     ;
; -20.707 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.335     ;
; -20.707 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.335     ;
; -20.667 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.295     ;
; -20.667 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.295     ;
; -20.667 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.295     ;
; -20.667 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.295     ;
; -20.651 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.279     ;
; -20.651 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.279     ;
; -20.651 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.279     ;
; -20.651 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.279     ;
; -20.598 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.226     ;
; -20.598 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.226     ;
; -20.598 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.226     ;
; -20.598 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.226     ;
; -20.468 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.096     ;
; -20.468 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.096     ;
; -20.468 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.096     ;
; -20.468 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.035     ; 36.096     ;
; -19.956 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.043     ; 35.576     ;
; -19.956 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.043     ; 35.576     ;
; -19.956 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.043     ; 35.576     ;
; -19.956 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.043     ; 35.576     ;
; -19.676 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.043     ; 35.296     ;
; -19.676 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.043     ; 35.296     ;
; -19.676 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.043     ; 35.296     ;
; -19.676 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.043     ; 35.296     ;
; -19.533 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][14] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.042     ; 35.154     ;
; -19.533 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][14] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.042     ; 35.154     ;
; -19.533 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][14] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.042     ; 35.154     ;
; -19.533 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][14] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.042     ; 35.154     ;
; -19.323 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][13] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.042     ; 34.944     ;
; -19.323 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][13] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.042     ; 34.944     ;
; -19.323 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][13] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.042     ; 34.944     ;
; -19.323 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][13] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.042     ; 34.944     ;
; -16.964 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.043     ; 32.584     ;
; -16.964 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.043     ; 32.584     ;
; -16.964 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.043     ; 32.584     ;
; -16.964 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 15.625       ; -0.043     ; 32.584     ;
; -16.250 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.509     ;
; -16.250 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.509     ;
; -16.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.504     ;
; -16.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.504     ;
; -16.199 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.007     ; 47.480     ;
; -16.199 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.007     ; 47.480     ;
; -16.107 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.003      ; 47.398     ;
; -16.107 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.003      ; 47.398     ;
; -16.106 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.365     ;
; -16.106 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.365     ;
; -16.101 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.360     ;
; -16.101 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.360     ;
; -16.071 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.330     ;
; -16.071 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.330     ;
; -16.066 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.325     ;
; -16.066 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.325     ;
; -16.055 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.007     ; 47.336     ;
; -16.055 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.007     ; 47.336     ;
; -16.052 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[7]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.024     ; 47.316     ;
; -16.052 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[7]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.024     ; 47.316     ;
; -16.045 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[15]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 47.317     ;
; -16.045 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[15]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 47.317     ;
; -16.032 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.013     ; 47.307     ;
; -16.032 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.291     ;
; -16.032 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.013     ; 47.307     ;
; -16.032 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.291     ;
; -16.027 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.286     ;
; -16.027 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.286     ;
; -16.020 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.007     ; 47.301     ;
; -16.020 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.007     ; 47.301     ;
; -16.019 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.278     ;
; -16.019 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 47.278     ;
+---------+----------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                                              ;
+---------+----------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                            ; To Node                                                                                 ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -21.205 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.833     ;
; -21.205 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.833     ;
; -21.205 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.833     ;
; -21.205 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.833     ;
; -21.061 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.689     ;
; -21.061 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.689     ;
; -21.061 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.689     ;
; -21.061 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.689     ;
; -21.026 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.654     ;
; -21.026 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.654     ;
; -21.026 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.654     ;
; -21.026 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.654     ;
; -20.987 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.615     ;
; -20.987 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.615     ;
; -20.987 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.615     ;
; -20.987 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.615     ;
; -20.974 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.602     ;
; -20.974 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.602     ;
; -20.974 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.602     ;
; -20.974 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.602     ;
; -20.842 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.470     ;
; -20.842 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.470     ;
; -20.842 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.470     ;
; -20.842 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.470     ;
; -20.729 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.357     ;
; -20.729 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.357     ;
; -20.729 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.357     ;
; -20.729 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.357     ;
; -20.707 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.335     ;
; -20.707 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.335     ;
; -20.707 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.335     ;
; -20.707 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.335     ;
; -20.667 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.295     ;
; -20.667 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.295     ;
; -20.667 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.295     ;
; -20.667 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.295     ;
; -20.651 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.279     ;
; -20.651 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.279     ;
; -20.651 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.279     ;
; -20.651 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.279     ;
; -20.598 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.226     ;
; -20.598 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.226     ;
; -20.598 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.226     ;
; -20.598 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.226     ;
; -20.468 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.096     ;
; -20.468 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.096     ;
; -20.468 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.096     ;
; -20.468 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.035     ; 36.096     ;
; -19.956 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.043     ; 35.576     ;
; -19.956 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.043     ; 35.576     ;
; -19.956 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.043     ; 35.576     ;
; -19.956 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.043     ; 35.576     ;
; -19.676 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.043     ; 35.296     ;
; -19.676 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.043     ; 35.296     ;
; -19.676 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.043     ; 35.296     ;
; -19.676 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.043     ; 35.296     ;
; -19.533 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][14] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.042     ; 35.154     ;
; -19.533 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][14] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.042     ; 35.154     ;
; -19.533 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][14] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.042     ; 35.154     ;
; -19.533 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][14] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.042     ; 35.154     ;
; -19.323 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][13] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.042     ; 34.944     ;
; -19.323 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][13] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.042     ; 34.944     ;
; -19.323 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][13] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.042     ; 34.944     ;
; -19.323 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][13] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.042     ; 34.944     ;
; -16.964 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.043     ; 32.584     ;
; -16.964 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.043     ; 32.584     ;
; -16.964 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.043     ; 32.584     ;
; -16.964 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 15.625       ; -0.043     ; 32.584     ;
; -16.250 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.509     ;
; -16.250 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.509     ;
; -16.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.504     ;
; -16.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.504     ;
; -16.199 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.007     ; 47.480     ;
; -16.199 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.007     ; 47.480     ;
; -16.107 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.003      ; 47.398     ;
; -16.107 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.003      ; 47.398     ;
; -16.106 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.365     ;
; -16.106 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.365     ;
; -16.101 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.360     ;
; -16.101 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.360     ;
; -16.071 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.330     ;
; -16.071 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.330     ;
; -16.066 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.325     ;
; -16.066 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.325     ;
; -16.055 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.007     ; 47.336     ;
; -16.055 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.007     ; 47.336     ;
; -16.052 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[7]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.024     ; 47.316     ;
; -16.052 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[7]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.024     ; 47.316     ;
; -16.045 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[15]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 47.317     ;
; -16.045 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[15]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 47.317     ;
; -16.032 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.013     ; 47.307     ;
; -16.032 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.291     ;
; -16.032 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.013     ; 47.307     ;
; -16.032 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.291     ;
; -16.027 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.286     ;
; -16.027 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.286     ;
; -16.020 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.007     ; 47.301     ;
; -16.020 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.007     ; 47.301     ;
; -16.019 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.278     ;
; -16.019 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 47.278     ;
+---------+----------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                      ;
+---------+----------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                            ; To Node                                                                                                         ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.760     ;
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.760     ;
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.760     ;
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.760     ;
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.760     ;
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.760     ;
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.760     ;
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.760     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.616     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.616     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.616     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.616     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.616     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.616     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.616     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.616     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.581     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.581     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.581     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.581     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.581     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.581     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.581     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.581     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.542     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.542     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.542     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.542     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.542     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.542     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.542     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.542     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.529     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.529     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.529     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.529     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.529     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.529     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.529     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.529     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.397     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.397     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.397     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.397     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.397     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.397     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.397     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.397     ;
; -19.083 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 50.391     ;
; -19.083 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 50.391     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.284     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.284     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.284     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.284     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.284     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.284     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.284     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.284     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.262     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.262     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.262     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.262     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.262     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.262     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.262     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.262     ;
; -18.939 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 50.247     ;
; -18.939 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 50.247     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.222     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.222     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.222     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.222     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.222     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.222     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.222     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.222     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.206     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.206     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.206     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.206     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.206     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.206     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.206     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.206     ;
; -18.904 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 50.212     ;
; -18.904 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 50.212     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.153     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.153     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.153     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.153     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.153     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.153     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.153     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 50.153     ;
; -18.865 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 50.173     ;
; -18.865 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 50.173     ;
; -18.852 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 50.160     ;
; -18.852 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 50.160     ;
; -18.755 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:8:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[8] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.041     ; 50.002     ;
; -18.755 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:8:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[8] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.041     ; 50.002     ;
+---------+----------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                                                                                      ;
+---------+----------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                            ; To Node                                                                                                         ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.760     ;
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.760     ;
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.760     ;
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.760     ;
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.760     ;
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.760     ;
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.760     ;
; -19.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.760     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.616     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.616     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.616     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.616     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.616     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.616     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.616     ;
; -19.332 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.616     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.581     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.581     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.581     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.581     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.581     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.581     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.581     ;
; -19.297 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.581     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.542     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.542     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.542     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.542     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.542     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.542     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.542     ;
; -19.258 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.542     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.529     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.529     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.529     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.529     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.529     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.529     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.529     ;
; -19.245 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.529     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.397     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.397     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.397     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.397     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.397     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.397     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.397     ;
; -19.113 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.397     ;
; -19.083 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 50.391     ;
; -19.083 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 50.391     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.284     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.284     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.284     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.284     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.284     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.284     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.284     ;
; -19.000 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.284     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.262     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.262     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.262     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.262     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.262     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.262     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.262     ;
; -18.978 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.262     ;
; -18.939 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 50.247     ;
; -18.939 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 50.247     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.222     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.222     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.222     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.222     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.222     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.222     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.222     ;
; -18.938 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.222     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.206     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.206     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.206     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.206     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.206     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.206     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.206     ;
; -18.922 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.206     ;
; -18.904 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 50.212     ;
; -18.904 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 50.212     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.153     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.153     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.153     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.153     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.153     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.153     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.153     ;
; -18.869 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 50.153     ;
; -18.865 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 50.173     ;
; -18.865 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 50.173     ;
; -18.852 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 50.160     ;
; -18.852 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 50.160     ;
; -18.755 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:8:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[8] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.041     ; 50.002     ;
; -18.755 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:8:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[8] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.041     ; 50.002     ;
+---------+----------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                          ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node             ; To Node               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 23.160 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 2.268      ;
; 23.199 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 2.229      ;
; 23.239 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 2.189      ;
; 23.659 ; CLK_24576             ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.769      ;
; 23.707 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.721      ;
; 23.746 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.682      ;
; 24.138 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.290      ;
; 24.139 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.289      ;
; 24.178 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.250      ;
; 24.697 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.731      ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'CODEC_SCLK'                                                                                                                              ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                   ; To Node                                        ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 27.313 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[119] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.581      ; 14.006     ;
; 27.313 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[118] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.581      ; 14.006     ;
; 27.313 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[117] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.581      ; 14.006     ;
; 27.313 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[116] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.581      ; 14.006     ;
; 27.313 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[115] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.581      ; 14.006     ;
; 27.313 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[114] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.581      ; 14.006     ;
; 27.313 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[113] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.581      ; 14.006     ;
; 27.313 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[112] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.581      ; 14.006     ;
; 27.313 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[11]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.581      ; 14.006     ;
; 27.313 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[10]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.581      ; 14.006     ;
; 27.313 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[9]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.581      ; 14.006     ;
; 27.313 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[8]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.581      ; 14.006     ;
; 27.313 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[7]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.581      ; 14.006     ;
; 27.313 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[6]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.581      ; 14.006     ;
; 27.313 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[3]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.581      ; 14.006     ;
; 27.391 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[138] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.726      ; 14.073     ;
; 27.391 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[137] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.726      ; 14.073     ;
; 27.391 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[136] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.726      ; 14.073     ;
; 27.391 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[135] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.726      ; 14.073     ;
; 27.391 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[130] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.726      ; 14.073     ;
; 27.391 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[129] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.726      ; 14.073     ;
; 27.391 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[128] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.726      ; 14.073     ;
; 27.391 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[103] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.726      ; 14.073     ;
; 27.392 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[142] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.724      ; 14.070     ;
; 27.392 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[141] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.724      ; 14.070     ;
; 27.392 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[140] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.724      ; 14.070     ;
; 27.392 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[139] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.724      ; 14.070     ;
; 27.392 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[134] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.724      ; 14.070     ;
; 27.392 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[104] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.724      ; 14.070     ;
; 27.392 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[27]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.724      ; 14.070     ;
; 27.392 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[26]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.724      ; 14.070     ;
; 27.392 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[25]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.724      ; 14.070     ;
; 27.392 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[19]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.724      ; 14.070     ;
; 27.392 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[18]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.724      ; 14.070     ;
; 27.392 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[17]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.724      ; 14.070     ;
; 27.392 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[16]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.724      ; 14.070     ;
; 27.392 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[15]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.724      ; 14.070     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[97]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[96]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[95]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[94]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[93]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[92]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[91]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[90]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[89]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[61]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[60]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[59]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[58]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[57]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[56]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.486 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[0]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.585      ; 13.837     ;
; 27.601 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[126] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.597      ; 13.734     ;
; 27.601 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[125] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.597      ; 13.734     ;
; 27.601 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[124] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.597      ; 13.734     ;
; 27.601 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[123] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.597      ; 13.734     ;
; 27.601 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[122] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.597      ; 13.734     ;
; 27.601 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[121] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.597      ; 13.734     ;
; 27.601 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[120] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.597      ; 13.734     ;
; 27.601 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[5]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.597      ; 13.734     ;
; 27.601 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[4]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.597      ; 13.734     ;
; 27.601 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[2]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.597      ; 13.734     ;
; 27.601 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[1]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.597      ; 13.734     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[127] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.598      ; 13.733     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[102] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.598      ; 13.733     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[101] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.598      ; 13.733     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[100] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.598      ; 13.733     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[99]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.598      ; 13.733     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[98]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.598      ; 13.733     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[75]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[74]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[73]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[72]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[71]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[70]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[69]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[68]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[67]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[66]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[65]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[64]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[63]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[62]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.598      ; 13.733     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[55]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.598      ; 13.733     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[54]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.598      ; 13.733     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[53]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.598      ; 13.733     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[52]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.598      ; 13.733     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[51]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.598      ; 13.733     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[50]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[49]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.603 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[12]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.590      ; 13.725     ;
; 27.636 ; A4299:I_4299|BUFFER_IN[235] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[119] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.584      ; 13.686     ;
; 27.636 ; A4299:I_4299|BUFFER_IN[235] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[118] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.584      ; 13.686     ;
; 27.636 ; A4299:I_4299|BUFFER_IN[235] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[117] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.584      ; 13.686     ;
; 27.636 ; A4299:I_4299|BUFFER_IN[235] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[116] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.584      ; 13.686     ;
; 27.636 ; A4299:I_4299|BUFFER_IN[235] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[115] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.584      ; 13.686     ;
; 27.636 ; A4299:I_4299|BUFFER_IN[235] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[114] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.584      ; 13.686     ;
; 27.636 ; A4299:I_4299|BUFFER_IN[235] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[113] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.584      ; 13.686     ;
; 27.636 ; A4299:I_4299|BUFFER_IN[235] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[112] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.584      ; 13.686     ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                  ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node           ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 38.199 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.901      ;
; 38.369 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.731      ;
; 38.369 ; SCLK_6M4          ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.731      ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'CLK_PLL1'                                                                                               ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 59.666 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.872      ;
; 59.666 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.872      ;
; 59.666 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.872      ;
; 59.666 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.872      ;
; 59.666 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.872      ;
; 59.830 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.708      ;
; 59.830 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.708      ;
; 59.830 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.708      ;
; 59.830 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.708      ;
; 59.830 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.708      ;
; 59.940 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 2.600      ;
; 59.943 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 2.597      ;
; 60.104 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 2.436      ;
; 60.107 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 2.433      ;
; 60.345 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.193      ;
; 60.345 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.193      ;
; 60.345 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.193      ;
; 60.345 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.193      ;
; 60.345 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.193      ;
; 60.581 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.957      ;
; 60.581 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.957      ;
; 60.581 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.957      ;
; 60.581 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.957      ;
; 60.581 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.957      ;
; 60.619 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 1.921      ;
; 60.622 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 1.918      ;
; 60.692 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.846      ;
; 60.692 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.846      ;
; 60.692 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.846      ;
; 60.692 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.846      ;
; 60.692 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.846      ;
; 60.855 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 1.685      ;
; 60.858 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 1.682      ;
; 60.966 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 1.574      ;
; 60.969 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 1.571      ;
; 61.349 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.189      ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 60.589 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.001      ; 1.950      ;
; 60.590 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.001      ; 1.949      ;
; 60.771 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.001      ; 1.768      ;
; 60.936 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.001      ; 1.603      ;
; 61.066 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.472      ;
; 61.254 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.284      ;
; 61.267 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.271      ;
; 61.268 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.270      ;
; 61.598 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.940      ;
; 61.601 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.937      ;
; 61.608 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.930      ;
; 61.630 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.908      ;
; 61.807 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; CLK_0M5              ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'CODEC_SCLK'                                                                                                                                                  ;
+--------+------------------------------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                      ; To Node                                        ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -0.086 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[190]  ; A4299:I_4299|BUFFER_IN[191]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.713      ; 0.913      ;
; -0.083 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[189]  ; A4299:I_4299|BUFFER_IN[190]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.713      ; 0.916      ;
; -0.079 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[192]  ; A4299:I_4299|BUFFER_IN[193]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.713      ; 0.920      ;
; 0.226  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[212]  ; A4299:I_4299|BUFFER_IN[213]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.545      ; 1.057      ;
; 0.234  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[241]  ; A4299:I_4299|BUFFER_IN[242]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.547      ; 1.067      ;
; 0.234  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[224]  ; A4299:I_4299|BUFFER_IN[225]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.547      ; 1.067      ;
; 0.234  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[214]  ; A4299:I_4299|BUFFER_IN[215]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.545      ; 1.065      ;
; 0.237  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[225]  ; A4299:I_4299|BUFFER_IN[226]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.547      ; 1.070      ;
; 0.416  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[227]  ; A4299:I_4299|BUFFER_IN[228]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.442      ; 1.144      ;
; 0.445  ; A4299:I_4299|INT                               ; A4299:I_4299|INT                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.731      ;
; 0.445  ; A4299:I_4299|SYNC                              ; A4299:I_4299|SYNC                              ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.731      ;
; 0.448  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[182]  ; A4299:I_4299|BUFFER_IN[183]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.689      ; 1.423      ;
; 0.449  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[210]  ; A4299:I_4299|BUFFER_IN[211]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.561      ; 1.296      ;
; 0.454  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[239]  ; A4299:I_4299|BUFFER_IN[240]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.547      ; 1.287      ;
; 0.455  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[242]  ; A4299:I_4299|BUFFER_IN[243]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.550      ; 1.291      ;
; 0.456  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[213]  ; A4299:I_4299|BUFFER_IN[214]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.545      ; 1.287      ;
; 0.457  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[240]  ; A4299:I_4299|BUFFER_IN[241]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.547      ; 1.290      ;
; 0.470  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[186]  ; A4299:I_4299|BUFFER_IN[187]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.298      ; 1.054      ;
; 0.470  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[243]  ; A4299:I_4299|BUFFER_IN[244]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.550      ; 1.306      ;
; 0.524  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[245]  ; A4299:I_4299|BUFFER_IN[246]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.252      ; 1.062      ;
; 0.584  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[226]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[227]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.271      ; 1.141      ;
; 0.603  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[207]  ; A4299:I_4299|BUFFER_IN[208]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.021      ; 0.910      ;
; 0.611  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[168]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[169]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.897      ;
; 0.612  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[146] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[147] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.898      ;
; 0.612  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[65]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[66]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.898      ;
; 0.612  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[176]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[177]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.898      ;
; 0.613  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[141] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[142] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.899      ;
; 0.613  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[114] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[115] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.899      ;
; 0.613  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[167]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[168]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.899      ;
; 0.614  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[117] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[118] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.900      ;
; 0.614  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[56]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[57]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.900      ;
; 0.614  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[46]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[47]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.900      ;
; 0.616  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[87]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[88]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.902      ;
; 0.616  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[164]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[165]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.902      ;
; 0.617  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[129] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[130] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.617  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[128] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[129] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.617  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[94]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[95]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.617  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[73]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[74]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.617  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[58]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[59]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.617  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[21]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[22]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.617  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[16]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[17]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.617  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[4]   ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[5]   ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.618  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[122] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[123] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.904      ;
; 0.618  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[100] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[101] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.904      ;
; 0.618  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[74]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[75]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.904      ;
; 0.618  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[51]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[52]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.904      ;
; 0.618  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[18]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[19]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.904      ;
; 0.619  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[169] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[170] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.905      ;
; 0.619  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[148] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[149] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.905      ;
; 0.619  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[145] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[146] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.905      ;
; 0.619  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[140] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[141] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.905      ;
; 0.619  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[110] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[111] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.905      ;
; 0.619  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[183]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[184]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.905      ;
; 0.619  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[177]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[178]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.905      ;
; 0.619  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[172]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[173]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.905      ;
; 0.620  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[162] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[163] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[107] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[108] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[98]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[99]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[25]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[26]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[1]   ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[2]   ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[175]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[176]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.621  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[165] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[166] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[161] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[162] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[155] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[156] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[149] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[150] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[137] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[138] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[125] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[126] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[120] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[121] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[113] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[114] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[93]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[94]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[91]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[92]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[82]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[83]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[77]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[78]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[68]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[69]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[9]   ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[10]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[208]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[209]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[163]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[164]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.622  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[163] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[164] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[157] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[158] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[124] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[125] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[115] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[116] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[80]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[81]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[79]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[80]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[49]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[50]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[47]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[48]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[45]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[46]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[36]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[37]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[161]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[162]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.623  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[164] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[165] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[160] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[161] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[116] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[117] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[112] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[113] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[57]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[58]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[44]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[45]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[39]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[40]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[29]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[30]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[7]   ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[8]   ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[229]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[230]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[211]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[212]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[171]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[172]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
+--------+------------------------------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                          ;
+-------+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                    ; To Node                                                                                      ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.224 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|ADR_EN_P                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.952      ; 3.462      ;
; 0.224 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|ADR_EN_P                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.952      ; 3.462      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                          ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_1                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_1                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                              ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                              ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                          ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|TAS_LOCK                                    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|TAS_LOCK                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.GET_VECTOR           ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.GET_VECTOR           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[1]                                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[1]                                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[2]                                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[2]                                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_RESET          ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_BUS_ERR        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_BUS_ERR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_ADR_ERR        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_ADR_ERR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_MISC           ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_MISC           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_HI  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_HI  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                              ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_LO  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_LO  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_INSTRUCTION    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_INSTRUCTION    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_STATUS         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_STATUS         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; RESET_CPUn                                                                                   ; RESET_CPUn                                                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[1]                        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[1]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[0]                        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[0]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP                            ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_INT            ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_INT            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[0]                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[0]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[1]                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[1]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:LOCK                                                    ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:LOCK                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[4]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[4]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_SP_HI                         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_SP_HI                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_HI                     ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_HI                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_LO                     ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_LO                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_P_RESET                    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_P_RESET                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_PC_HI          ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_PC_HI          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                                    ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_HI        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_HI        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_LO        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_LO        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_HI         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_HI         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_LO         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_LO         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[0]       ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_BIW_2                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_BIW_2                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \FLASH_WS:TMP[1]                                                                             ; \FLASH_WS:TMP[1]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \FLASH_WS:TMP[0]                                                                             ; \FLASH_WS:TMP[0]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \FLASH_WS:TMP[2]                                                                             ; \FLASH_WS:TMP[2]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[2]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[2]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[1]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[1]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[0]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[0]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\SHFT:LOCK                                                      ; FLASHBOOT_UMASPI:I_FLASHBOOT|\SHFT:LOCK                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_CLK_S                                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_CLK_S                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.IDLE                             ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.IDLE                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.WAIT_CTRL_RDY        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.WAIT_CTRL_RDY        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SRC_2_HI                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SRC_2_HI                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|RESET_CNT[0]                   ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|RESET_CNT[0]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|VMA_In                              ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|VMA_In                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                                ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_EXT                        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_EXT                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_LO                         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_LO                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.HALT                 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.HALT                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_HI                         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_HI                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[1]       ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_DIN_S                                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_DIN_S                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|OV_DIV_MUL                                       ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|OV_DIV_MUL                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[3] ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                             ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|E                                   ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|E                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA[3]                            ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA[3]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[3]                            ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[3]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[0]                                                                             ; \SLOW_CPU:TMP[0]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[2]                                                                             ; \SLOW_CPU:TMP[2]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[1]                                                                             ; \SLOW_CPU:TMP[1]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                           ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                           ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                            ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_CHK            ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_CHK            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:SPI_CLK_TMP[0]                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:SPI_CLK_TMP[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:SPI_CLK_TMP[1]                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:SPI_CLK_TMP[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_P_PRIV                     ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_P_PRIV                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
+-------+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                                                                                          ;
+-------+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                    ; To Node                                                                                      ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.224 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|ADR_EN_P                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.952      ; 3.462      ;
; 0.224 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|ADR_EN_P                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.952      ; 3.462      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                          ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_1                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_1                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                              ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                              ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                          ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|TAS_LOCK                                    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|TAS_LOCK                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.GET_VECTOR           ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.GET_VECTOR           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[1]                                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[1]                                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[2]                                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[2]                                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_RESET          ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_BUS_ERR        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_BUS_ERR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_ADR_ERR        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_ADR_ERR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_MISC           ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_MISC           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_HI  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_HI  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                              ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_LO  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_LO  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_INSTRUCTION    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_INSTRUCTION    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_STATUS         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_STATUS         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; RESET_CPUn                                                                                   ; RESET_CPUn                                                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[1]                        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[1]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[0]                        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[0]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP                            ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_INT            ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_INT            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[0]                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[0]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[1]                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[1]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:LOCK                                                    ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:LOCK                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[4]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[4]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_SP_HI                         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_SP_HI                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_HI                     ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_HI                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_LO                     ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_LO                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_P_RESET                    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_P_RESET                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_PC_HI          ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_PC_HI          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                                    ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_HI        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_HI        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_LO        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_LO        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_HI         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_HI         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_LO         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_LO         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[0]       ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_BIW_2                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_BIW_2                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \FLASH_WS:TMP[1]                                                                             ; \FLASH_WS:TMP[1]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \FLASH_WS:TMP[0]                                                                             ; \FLASH_WS:TMP[0]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \FLASH_WS:TMP[2]                                                                             ; \FLASH_WS:TMP[2]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[2]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[2]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[1]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[1]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[0]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[0]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\SHFT:LOCK                                                      ; FLASHBOOT_UMASPI:I_FLASHBOOT|\SHFT:LOCK                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_CLK_S                                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_CLK_S                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.IDLE                             ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.IDLE                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.WAIT_CTRL_RDY        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.WAIT_CTRL_RDY        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SRC_2_HI                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SRC_2_HI                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|RESET_CNT[0]                   ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|RESET_CNT[0]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|VMA_In                              ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|VMA_In                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                                ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_EXT                        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_EXT                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_LO                         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_LO                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.HALT                 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.HALT                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_HI                         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_HI                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[1]       ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_DIN_S                                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_DIN_S                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|OV_DIV_MUL                                       ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|OV_DIV_MUL                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[3] ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                             ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|E                                   ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|E                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA[3]                            ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA[3]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[3]                            ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[3]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[0]                                                                             ; \SLOW_CPU:TMP[0]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[2]                                                                             ; \SLOW_CPU:TMP[2]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[1]                                                                             ; \SLOW_CPU:TMP[1]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                           ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                           ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                            ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_CHK            ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_CHK            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:SPI_CLK_TMP[0]                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:SPI_CLK_TMP[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:SPI_CLK_TMP[1]                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:SPI_CLK_TMP[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_P_PRIV                     ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_P_PRIV                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
+-------+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.614 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[36]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[37]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[36]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[37]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.616 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[9]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[2][12]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[1][12]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[9]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[2][12]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[1][12]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.617 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[3]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.903      ;
; 0.617 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[3]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.903      ;
; 0.618 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22]    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[22]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.904      ;
; 0.618 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[20]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[21]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.904      ;
; 0.618 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22]    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[22]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.904      ;
; 0.618 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[20]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[21]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.904      ;
; 0.619 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[11]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.905      ;
; 0.619 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.905      ;
; 0.619 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.905      ;
; 0.619 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[11]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.905      ;
; 0.619 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.905      ;
; 0.619 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.905      ;
; 0.620 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[19]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[19]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.906      ;
; 0.621 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[56]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[57]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[54]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[55]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[49]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[50]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[33]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[34]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.907      ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.614 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[36]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[37]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[36]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[37]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.616 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[9]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[2][12]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[1][12]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[9]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[2][12]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[1][12]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.617 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[3]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.903      ;
; 0.617 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[3]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.903      ;
; 0.618 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22]    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[22]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.904      ;
; 0.618 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[20]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[21]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.904      ;
; 0.618 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22]    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[22]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.904      ;
; 0.618 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[20]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[21]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.904      ;
; 0.619 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[11]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.905      ;
; 0.619 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.905      ;
; 0.619 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.905      ;
; 0.619 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[11]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.905      ;
; 0.619 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.905      ;
; 0.619 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.905      ;
; 0.620 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[19]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[19]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.906      ;
; 0.621 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[56]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[57]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[54]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[55]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[49]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[50]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[33]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[34]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.907      ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                                                                                                        ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                     ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[5]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[9]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[9]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[6]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                                                                                                        ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                     ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[5]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[9]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[9]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[6]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                  ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node           ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; SCLK_6M4          ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.615 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.901      ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                          ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node             ; To Node               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.964 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.250      ;
; 1.003 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.289      ;
; 1.004 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.290      ;
; 1.396 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.682      ;
; 1.435 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.721      ;
; 1.483 ; CLK_24576             ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.769      ;
; 1.903 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 2.189      ;
; 1.943 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 2.229      ;
; 1.982 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 2.268      ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; CLK_0M5              ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.622 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.908      ;
; 0.644 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.930      ;
; 0.651 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.937      ;
; 0.654 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.940      ;
; 0.984 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.270      ;
; 0.985 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.271      ;
; 0.998 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.284      ;
; 1.186 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.472      ;
; 1.316 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.001      ; 1.603      ;
; 1.481 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.001      ; 1.768      ;
; 1.662 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.001      ; 1.949      ;
; 1.663 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.001      ; 1.950      ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'CLK_PLL1'                                                                                               ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 0.629 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.915      ;
; 0.903 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.189      ;
; 0.938 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.224      ;
; 0.946 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.232      ;
; 1.022 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.308      ;
; 1.022 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.308      ;
; 1.283 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 1.571      ;
; 1.286 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 1.574      ;
; 1.394 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 1.682      ;
; 1.397 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 1.685      ;
; 1.400 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.686      ;
; 1.408 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.694      ;
; 1.452 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.738      ;
; 1.452 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.738      ;
; 1.480 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.766      ;
; 1.532 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.818      ;
; 1.532 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.818      ;
; 1.560 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.846      ;
; 1.560 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.846      ;
; 1.560 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.846      ;
; 1.560 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.846      ;
; 1.612 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.898      ;
; 1.630 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 1.918      ;
; 1.633 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 1.921      ;
; 1.671 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.957      ;
; 1.671 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.957      ;
; 1.692 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.978      ;
; 1.907 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.193      ;
; 1.907 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.193      ;
; 1.907 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.193      ;
; 1.907 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.193      ;
; 2.145 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 2.433      ;
; 2.148 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 2.436      ;
; 2.309 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 2.597      ;
; 2.312 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 2.600      ;
; 2.422 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.708      ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                               ;
+--------+-------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                       ; To Node                                                           ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 8.865      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 8.865      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.002     ; 8.848      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.865      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.002     ; 8.848      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.865      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.865      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.027      ; 8.877      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.002     ; 8.848      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.865      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.002     ; 8.848      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.865      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.865      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.027      ; 8.877      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.018      ; 8.868      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 8.864      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.000      ; 8.831      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.000      ; 8.831      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.025      ; 8.856      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.025      ; 8.856      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.025      ; 8.856      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.000      ; 8.831      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.000      ; 8.831      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.025      ; 8.856      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.025      ; 8.856      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.025      ; 8.856      ;
+--------+-------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                               ;
+--------+-------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                       ; To Node                                                           ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 8.865      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 8.856      ;
; 22.437 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 8.865      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.002     ; 8.848      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.865      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.002     ; 8.848      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.865      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.865      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.027      ; 8.877      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.002     ; 8.848      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.865      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.002     ; 8.848      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.003      ; 8.853      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.865      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.865      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.027      ; 8.877      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.438 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.018      ; 8.868      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 8.862      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 8.864      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.000      ; 8.831      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.000      ; 8.831      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.025      ; 8.856      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.025      ; 8.856      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.025      ; 8.856      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.000      ; 8.831      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.000      ; 8.831      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.025      ; 8.856      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.025      ; 8.856      ;
; 22.457 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.025      ; 8.856      ;
+--------+-------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                 ;
+--------+-------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                       ; To Node                                                                             ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; MDAT_BUFFER[6]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.026      ; 8.875      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; MDAT_BUFFER[2]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.026      ; 8.875      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[3]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[3]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; MDAT_BUFFER[7]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.026      ; 8.875      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; MDAT_BUFFER[5]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.026      ; 8.875      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[2]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[6]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[2]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[63]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[15]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.005     ; 8.844      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[15]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.005     ; 8.844      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[1]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[7]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[62]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[14]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.005     ; 8.844      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[14]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.005     ; 8.844      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 8.837      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 8.837      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[61]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.015     ; 8.834      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[10]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[10]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 8.837      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 8.837      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 8.837      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[60]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[59]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[58]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[57]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[56]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[55]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[54]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[53]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[52]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[51]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[50]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[49]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[48]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.004      ; 8.853      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.007      ; 8.856      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.006      ; 8.855      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.007      ; 8.856      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[18]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[33]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[32]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[38]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[39]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[6]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.001     ; 8.848      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[18]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.001     ; 8.848      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[14]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[10]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.001     ; 8.848      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[37]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[35]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[36]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[34]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[19]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.001     ; 8.848      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.015     ; 8.834      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[15]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[27]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.006     ; 8.843      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[25]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.006     ; 8.843      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[24]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.006     ; 8.843      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[26]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.006     ; 8.843      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.006     ; 8.843      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[19]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.006     ; 8.843      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[16]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.006     ; 8.843      ;
+--------+-------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                 ;
+--------+-------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                       ; To Node                                                                             ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.015      ; 8.864      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; MDAT_BUFFER[6]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.026      ; 8.875      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; MDAT_BUFFER[2]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.026      ; 8.875      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[3]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[3]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; MDAT_BUFFER[7]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.026      ; 8.875      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; MDAT_BUFFER[5]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.026      ; 8.875      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[2]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[6]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[2]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[63]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[15]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.005     ; 8.844      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[15]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.005     ; 8.844      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[1]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[7]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.005      ; 8.854      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[62]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[14]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.005     ; 8.844      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[14]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.005     ; 8.844      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 8.837      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 8.837      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[61]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.015     ; 8.834      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[10]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[10]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 8.837      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 8.837      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 8.837      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.003     ; 8.846      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[60]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[59]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[58]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[57]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[56]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[55]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[54]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[53]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[52]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[51]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[50]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[49]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[48]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 8.860      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.004      ; 8.853      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.007      ; 8.856      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.006      ; 8.855      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.007      ; 8.856      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[18]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[33]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[32]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[38]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[39]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[6]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.001     ; 8.848      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[18]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.001     ; 8.848      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[14]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[10]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.001     ; 8.848      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[37]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[35]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[36]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[34]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.021     ; 8.828      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[19]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.001     ; 8.848      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.015     ; 8.834      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[15]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.009     ; 8.840      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[27]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.006     ; 8.843      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[25]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.006     ; 8.843      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[24]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.006     ; 8.843      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[26]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.006     ; 8.843      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.006     ; 8.843      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[19]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.006     ; 8.843      ;
; 22.439 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[16]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.006     ; 8.843      ;
+--------+-------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                           ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                           ; To Node                                                                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 78.982 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|dffe4 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0 ; CODEC_SCLK   ; CODEC_SCLK  ; 81.400       ; 0.758      ; 3.136      ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                           ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                           ; To Node                                                                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 2.128 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|dffe4 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.758      ; 3.136      ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                            ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                      ; To Node                                                                         ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.808 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 3.097      ;
; 2.808 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 3.097      ;
; 2.808 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 3.097      ;
; 2.808 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 3.097      ;
; 2.808 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 3.097      ;
; 2.808 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 3.097      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[3]                                                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[15]                                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.010     ; 5.872      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.010     ; 5.872      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.010     ; 5.872      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[1]                                                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[0]                                                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[14]                                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[10]                                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[9]                                                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[11]                                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[9] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[8] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][3]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][3]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][3]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][15]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.007     ; 5.875      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][6]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 5.848      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][3]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.006     ; 5.876      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][6]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.007     ; 5.875      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][6]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][6]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][8]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.021     ; 5.861      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][9]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.007     ; 5.875      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][15]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][15]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][15]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][2]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][2]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][2]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.006     ; 5.876      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][6]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.006     ; 5.876      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][0]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 5.848      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][15]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][2]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][0]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][0]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][14]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][10]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.021     ; 5.861      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][8]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 5.848      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][9]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.006     ; 5.876      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][9]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.006     ; 5.876      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][9]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][9]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][7]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][7]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][7]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][0]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.014     ; 5.868      ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                            ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                      ; To Node                                                                         ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.403 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.031      ; 2.720      ;
; 2.808 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 3.097      ;
; 2.808 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 3.097      ;
; 2.808 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 3.097      ;
; 2.808 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 3.097      ;
; 2.808 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 3.097      ;
; 2.808 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 3.097      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[3]                                                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[15]                                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.010     ; 5.872      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.010     ; 5.872      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.010     ; 5.872      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[1]                                                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[0]                                                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[14]                                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[10]                                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[9]                                                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[11]                                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.001      ; 5.883      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[9] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[8] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][3]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][3]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][3]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][15]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.007     ; 5.875      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][6]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 5.848      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][3]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.006     ; 5.876      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][6]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.007     ; 5.875      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][6]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][6]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][8]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.021     ; 5.861      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][9]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.007     ; 5.875      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][15]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][15]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][15]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][2]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][2]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][2]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.006     ; 5.876      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][6]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.006     ; 5.876      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][0]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 5.848      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][15]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][2]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][0]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][0]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.005     ; 5.877      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][14]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][10]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.021     ; 5.861      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.025     ; 5.857      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][8]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 5.848      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][9]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.006     ; 5.876      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][9]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.006     ; 5.876      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][9]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][9]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][7]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][7]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 5.870      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][7]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.014     ; 5.868      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.013     ; 5.869      ;
; 5.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][0]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.014     ; 5.868      ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                           ;
+-------+---------------+---------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                                                         ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+---------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[22]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[23]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[21]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[20]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[18]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[17]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[19]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[16]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[15]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[13]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[14]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[12]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[22]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[23]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[21]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[20]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[18]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[17]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[19]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[16]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[15]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[13]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[14]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[12]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.671      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[4]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[5]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[4]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[5]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 4.003      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 4.055      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.032      ; 4.109      ;
; 3.825 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[1]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.028      ; 4.139      ;
; 3.825 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[0]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.028      ; 4.139      ;
; 3.825 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[1]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.028      ; 4.139      ;
; 3.825 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[0]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.028      ; 4.139      ;
; 3.841 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|\P_STATUS_REG:SREG_MEM_TMP[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.019      ; 4.146      ;
; 3.841 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|\P_STATUS_REG:SREG_MEM_TMP[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.019      ; 4.146      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[26]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.024      ; 4.152      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[25]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.024      ; 4.152      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[24]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.024      ; 4.152      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[23]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.024      ; 4.152      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[26]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.024      ; 4.152      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[25]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.024      ; 4.152      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[24]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.024      ; 4.152      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[23]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.024      ; 4.152      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ADDRESS_REGISTERS:I_ADRREG|SSP[1]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 4.146      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SRC_1_LO         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.030      ; 4.160      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ADDRESS_REGISTERS:I_ADRREG|ADR_TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.015      ; 4.145      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ADDRESS_REGISTERS:I_ADRREG|ADR_TMP[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.015      ; 4.145      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ADDRESS_REGISTERS:I_ADRREG|ADR_TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.015      ; 4.145      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.VECT_NR ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 4.153      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ADDRESS_REGISTERS:I_ADRREG|ADR_TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.015      ; 4.145      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ADDRESS_REGISTERS:I_ADRREG|ADR_TMP[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.015      ; 4.145      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|OV_DIV_MUL                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 4.148      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ADDRESS_REGISTERS:I_ADRREG|ADR_TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.015      ; 4.145      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|\EXWORD_COUNTER:DEST_TMP[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.025      ; 4.155      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|\P_STATUS_REG:SREG_MEM[15]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.028      ; 4.158      ;
+-------+---------------+---------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                           ;
+-------+---------------+---------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                                                         ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+---------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[22]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[23]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[21]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[20]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[18]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[17]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[19]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[16]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[15]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[13]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[14]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[12]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[22]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[23]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[21]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[20]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[18]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[17]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[19]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[16]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[15]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[13]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[14]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[12]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.362 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.671      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[4]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[5]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[4]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.690 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[5]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 4.003      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 4.055      ;
; 3.769 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 4.055      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.032      ; 4.109      ;
; 3.791 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.032      ; 4.109      ;
; 3.825 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[1]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.028      ; 4.139      ;
; 3.825 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[0]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.028      ; 4.139      ;
; 3.825 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[1]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.028      ; 4.139      ;
; 3.825 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[0]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.028      ; 4.139      ;
; 3.841 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|\P_STATUS_REG:SREG_MEM_TMP[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.019      ; 4.146      ;
; 3.841 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|\P_STATUS_REG:SREG_MEM_TMP[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.019      ; 4.146      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[26]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.024      ; 4.152      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[25]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.024      ; 4.152      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[24]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.024      ; 4.152      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[23]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.024      ; 4.152      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[26]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.024      ; 4.152      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[25]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.024      ; 4.152      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[24]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.024      ; 4.152      ;
; 3.842 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|RESULT_I[23]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.024      ; 4.152      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ADDRESS_REGISTERS:I_ADRREG|SSP[1]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 4.146      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SRC_1_LO         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.030      ; 4.160      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ADDRESS_REGISTERS:I_ADRREG|ADR_TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.015      ; 4.145      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ADDRESS_REGISTERS:I_ADRREG|ADR_TMP[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.015      ; 4.145      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ADDRESS_REGISTERS:I_ADRREG|ADR_TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.015      ; 4.145      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.VECT_NR ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 4.153      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ADDRESS_REGISTERS:I_ADRREG|ADR_TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.015      ; 4.145      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ADDRESS_REGISTERS:I_ADRREG|ADR_TMP[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.015      ; 4.145      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|OV_DIV_MUL                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 4.148      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ADDRESS_REGISTERS:I_ADRREG|ADR_TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.015      ; 4.145      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|\EXWORD_COUNTER:DEST_TMP[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.025      ; 4.155      ;
; 3.844 ; RESET_CPUn    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|\P_STATUS_REG:SREG_MEM[15]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.028      ; 4.158      ;
+-------+---------------+---------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                     ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg7  ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                                                                                     ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg7  ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 11.584 ; 12.695       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576                                           ;
; 11.584 ; 12.695       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576                                           ;
; 11.584 ; 12.695       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]                               ;
; 11.584 ; 12.695       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]                               ;
; 11.584 ; 12.695       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]                               ;
; 11.584 ; 12.695       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]                               ;
; 11.584 ; 12.695       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]                               ;
; 11.584 ; 12.695       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]                               ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576|clk                                       ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576|clk                                       ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|inclk[0] ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|inclk[0] ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|outclk   ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|outclk   ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                                                 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4                                            ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4                                            ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]                                   ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]                                   ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|inclk[0] ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|inclk[0] ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|outclk   ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|outclk   ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4|clk                                        ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4|clk                                        ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]|clk                               ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]|clk                               ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CLK_PLL1'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 59.869 ; 62.500       ; 2.631          ; Port Rate        ; CLK_PLL1 ; Rise       ; CLK_PLL1                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                       ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                       ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------+
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[172] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[172] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[173] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[173] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[174] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[174] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[175] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[175] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[176] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[176] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[177] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[177] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[178] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[178] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[179] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[179] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[180] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[180] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[181] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[181] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[182] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[182] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[183] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[183] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[184] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[184] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[185] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[185] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[186] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[186] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[187] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[187] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[188] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[188] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[189] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[189] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[190] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[190] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[191] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[191] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[192] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[192] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[193] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[193] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[194] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[194] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[195] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[195] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[196] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[196] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[197] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[197] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[198] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[198] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[199] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[199] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[200] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[200] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[201] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[201] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[202] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[202] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[203] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[203] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[204] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[204] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[205] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[205] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[206] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[206] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[207] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[207] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[208] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[208] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[209] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[209] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[210] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[210] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[211] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[211] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[212] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[212] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[213] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[213] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[214] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[214] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[215] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[215] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[216] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[216] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[217] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[217] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[218] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[218] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[219] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[219] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[220] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[220] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[221] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[221] ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                       ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                       ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------+
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[172] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[172] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[173] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[173] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[174] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[174] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[175] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[175] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[176] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[176] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[177] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[177] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[178] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[178] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[179] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[179] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[180] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[180] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[181] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[181] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[182] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[182] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[183] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[183] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[184] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[184] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[185] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[185] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[186] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[186] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[187] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[187] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[188] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[188] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[189] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[189] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[190] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[190] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[191] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[191] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[192] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[192] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[193] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[193] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[194] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[194] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[195] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[195] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[196] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[196] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[197] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[197] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[198] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[198] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[199] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[199] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[200] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[200] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[201] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[201] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[202] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[202] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[203] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[203] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[204] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[204] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[205] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[205] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[206] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[206] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[207] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[207] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[208] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[208] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[209] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[209] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[210] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[210] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[211] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[211] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[212] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[212] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[213] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[213] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[214] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[214] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[215] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[215] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[216] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[216] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[217] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[217] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[218] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[218] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[219] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[219] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[220] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[220] ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[221] ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[221] ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5                                             ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5                                             ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CLK_PLL2'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 59.869 ; 62.500       ; 2.631          ; Port Rate        ; CLK_PLL2 ; Rise       ; CLK_PLL2                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CRT_PIN4_CLK1'                                                                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock         ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 59.869 ; 62.500       ; 2.631          ; Port Rate        ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1                             ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CODEC_SCLK'                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock      ; Clock Edge ; Target                                                                                                                                                    ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0                    ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0                    ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg0 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg0 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg6 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg6 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_datain_reg0  ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_datain_reg0  ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_memory_reg0  ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_memory_reg0  ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg0 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg0 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[180]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[180]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[181]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[181]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[182]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[182]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[183]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[183]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[184]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[184]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[185]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[185]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[186]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[186]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[187]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[187]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[188]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[188]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[189]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[189]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[190]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[190]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[191]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[191]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[192]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[192]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[193]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[193]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[194]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[194]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[195]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[195]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[196]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[196]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[197]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[197]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[198]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[198]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[199]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[199]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[200]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[200]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[201]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[201]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[202]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[202]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[203]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[203]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[204]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[204]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[205]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[205]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[206]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[206]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[207]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[207]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[208]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[208]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[209]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[209]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[210]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[210]                                                                                                                               ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; -0.876 ; -0.876 ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; 9.690  ; 9.690  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; -0.373 ; -0.373 ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; 12.212 ; 12.212 ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; 28.330 ; 28.330 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 12.525 ; 12.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 8.479  ; 8.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 10.036 ; 10.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 9.145  ; 9.145  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 10.036 ; 10.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 9.174  ; 9.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 8.946  ; 8.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 9.473  ; 9.473  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 9.213  ; 9.213  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 8.847  ; 8.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 8.614  ; 8.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 19.699 ; 19.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 20.630 ; 20.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 18.483 ; 18.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; 11.955 ; 11.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 20.934 ; 20.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 19.948 ; 19.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 19.812 ; 19.812 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 20.934 ; 20.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 16.614 ; 16.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 14.932 ; 14.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 19.045 ; 19.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 15.149 ; 15.149 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 15.039 ; 15.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 15.797 ; 15.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 16.028 ; 16.028 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 15.531 ; 15.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 16.926 ; 16.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 16.614 ; 16.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 16.502 ; 16.502 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 18.994 ; 18.994 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 19.025 ; 19.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 16.647 ; 16.647 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 17.407 ; 17.407 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 16.923 ; 16.923 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 17.419 ; 17.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 17.797 ; 17.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 19.045 ; 19.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 7.576  ; 7.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 11.848 ; 11.848 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 30.458 ; 30.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 30.458 ; 30.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 30.423 ; 30.423 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 30.363 ; 30.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; 13.335 ; 13.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; 8.072  ; 8.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; 10.798 ; 10.798 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; 15.200 ; 15.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; 9.231  ; 9.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 18.897 ; 18.897 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 9.610  ; 9.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 18.638 ; 18.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; 7.203  ; 7.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 29.678 ; 29.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 19.079 ; 19.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 19.044 ; 19.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 17.629 ; 17.629 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 17.251 ; 17.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 16.697 ; 16.697 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 16.182 ; 16.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 17.223 ; 17.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 17.845 ; 17.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 17.194 ; 17.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 19.044 ; 19.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; 5.970  ; 5.970  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; 5.069  ; 5.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; 4.715  ; 4.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; 4.459  ; 4.459  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; 4.186  ; 4.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; 3.799  ; 3.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 20.538 ; 20.538 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 16.890 ; 16.890 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 16.714 ; 16.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 16.725 ; 16.725 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 17.165 ; 17.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 16.418 ; 16.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 17.938 ; 17.938 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 19.801 ; 19.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 17.606 ; 17.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 18.666 ; 18.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 19.553 ; 19.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 17.749 ; 17.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 19.118 ; 19.118 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 17.510 ; 17.510 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 18.270 ; 18.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 19.153 ; 19.153 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 20.538 ; 20.538 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; 8.425  ; 8.425  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 7.657  ; 7.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 30.460 ; 30.460 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 11.123 ; 11.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 10.032 ; 10.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 10.589 ; 10.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 9.586  ; 9.586  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 9.835  ; 9.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 9.005  ; 9.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 9.215  ; 9.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 10.021 ; 10.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 9.589  ; 9.589  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 9.801  ; 9.801  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 10.589 ; 10.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 13.915 ; 13.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 13.833 ; 13.833 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 12.858 ; 12.858 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 13.229 ; 13.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 9.886  ; 9.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; 14.077 ; 14.077 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; 7.882  ; 7.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; 12.785 ; 12.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 23.589 ; 23.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; 9.268  ; 9.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; 8.399  ; 8.399  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; 9.182  ; 9.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; 8.365  ; 8.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; 9.182  ; 9.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; 8.658  ; 8.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; 7.967  ; 7.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; 8.435  ; 8.435  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; 7.800  ; 7.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 7.812  ; 7.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 28.361 ; 28.361 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 8.270  ; 8.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 26.622 ; 26.622 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 7.981  ; 7.981  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 7.164  ; 7.164  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 9.601  ; 9.601  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; 7.460  ; 7.460  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 18.763 ; 18.763 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 19.868 ; 19.868 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 17.762 ; 17.762 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 19.427 ; 19.427 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 19.387 ; 19.387 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 19.251 ; 19.251 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 19.427 ; 19.427 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 16.053 ; 16.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 14.371 ; 14.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 18.202 ; 18.202 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 14.331 ; 14.331 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 14.277 ; 14.277 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 14.861 ; 14.861 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 15.079 ; 15.079 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 15.097 ; 15.097 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 16.414 ; 16.414 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 15.893 ; 15.893 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 15.941 ; 15.941 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 17.811 ; 17.811 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 18.202 ; 18.202 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 15.655 ; 15.655 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 16.598 ; 16.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 15.215 ; 15.215 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 15.833 ; 15.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 16.222 ; 16.222 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 16.582 ; 16.582 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 9.367  ; 9.367  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; 6.861  ; 6.861  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; 7.211  ; 7.211  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; 7.284  ; 7.284  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 28.750 ; 28.750 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 28.750 ; 28.750 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 28.715 ; 28.715 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 28.655 ; 28.655 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; 7.677  ; 7.677  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 9.059  ; 9.059  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 18.385 ; 18.385 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; 8.748  ; 8.748  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 18.126 ; 18.126 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 27.727 ; 27.727 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 18.261 ; 18.261 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 16.581 ; 16.581 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 16.446 ; 16.446 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 16.428 ; 16.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 15.705 ; 15.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 15.373 ; 15.373 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 15.515 ; 15.515 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 16.259 ; 16.259 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 15.619 ; 15.619 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 16.581 ; 16.581 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 19.080 ; 19.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 16.072 ; 16.072 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 15.952 ; 15.952 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 15.789 ; 15.789 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 16.216 ; 16.216 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 15.984 ; 15.984 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 17.426 ; 17.426 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 19.080 ; 19.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 17.045 ; 17.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 17.483 ; 17.483 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 18.730 ; 18.730 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 16.757 ; 16.757 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 18.309 ; 18.309 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 15.802 ; 15.802 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 16.684 ; 16.684 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 17.578 ; 17.578 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 18.075 ; 18.075 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 28.752 ; 28.752 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 22.997 ; 22.997 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 6.951  ; 6.951  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; 6.402  ; 6.402  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 26.525 ; 26.525 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; 7.551  ; 7.551  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; 28.330 ; 28.330 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 12.525 ; 12.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 8.479  ; 8.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 10.036 ; 10.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 9.145  ; 9.145  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 10.036 ; 10.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 9.174  ; 9.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 8.946  ; 8.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 9.473  ; 9.473  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 9.213  ; 9.213  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 8.847  ; 8.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 8.614  ; 8.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 19.699 ; 19.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 20.630 ; 20.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 18.483 ; 18.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; 11.955 ; 11.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 20.934 ; 20.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 19.948 ; 19.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 19.812 ; 19.812 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 20.934 ; 20.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 16.614 ; 16.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 14.932 ; 14.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 19.045 ; 19.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 15.149 ; 15.149 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 15.039 ; 15.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 15.797 ; 15.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 16.028 ; 16.028 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 15.531 ; 15.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 16.926 ; 16.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 16.614 ; 16.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 16.502 ; 16.502 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 18.994 ; 18.994 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 19.025 ; 19.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 16.647 ; 16.647 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 17.407 ; 17.407 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 16.923 ; 16.923 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 17.419 ; 17.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 17.797 ; 17.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 19.045 ; 19.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 7.576  ; 7.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 11.848 ; 11.848 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 30.458 ; 30.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 30.458 ; 30.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 30.423 ; 30.423 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 30.363 ; 30.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; 13.335 ; 13.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; 8.072  ; 8.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; 10.798 ; 10.798 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; 15.200 ; 15.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; 9.231  ; 9.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 18.897 ; 18.897 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.610  ; 9.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 18.638 ; 18.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; 7.203  ; 7.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 29.678 ; 29.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 19.079 ; 19.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 19.044 ; 19.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 17.629 ; 17.629 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 17.251 ; 17.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 16.697 ; 16.697 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 16.182 ; 16.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 17.223 ; 17.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 17.845 ; 17.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 17.194 ; 17.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 19.044 ; 19.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; 5.970  ; 5.970  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; 5.069  ; 5.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; 4.715  ; 4.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; 4.459  ; 4.459  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; 4.186  ; 4.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; 3.799  ; 3.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 20.538 ; 20.538 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 16.890 ; 16.890 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 16.714 ; 16.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 16.725 ; 16.725 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 17.165 ; 17.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 16.418 ; 16.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 17.938 ; 17.938 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 19.801 ; 19.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 17.606 ; 17.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 18.666 ; 18.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 19.553 ; 19.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 17.749 ; 17.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 19.118 ; 19.118 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 17.510 ; 17.510 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 18.270 ; 18.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 19.153 ; 19.153 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 20.538 ; 20.538 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; 8.425  ; 8.425  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 7.657  ; 7.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 30.460 ; 30.460 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 11.123 ; 11.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 10.032 ; 10.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 10.589 ; 10.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 9.586  ; 9.586  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 9.835  ; 9.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 9.005  ; 9.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 9.215  ; 9.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 10.021 ; 10.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 9.589  ; 9.589  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 9.801  ; 9.801  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 10.589 ; 10.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 13.915 ; 13.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 13.833 ; 13.833 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 12.858 ; 12.858 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 13.229 ; 13.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 9.886  ; 9.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; 14.077 ; 14.077 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; 7.882  ; 7.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; 12.785 ; 12.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 23.589 ; 23.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; 9.268  ; 9.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; 8.399  ; 8.399  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; 9.182  ; 9.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; 8.365  ; 8.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; 9.182  ; 9.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; 8.658  ; 8.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; 7.967  ; 7.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; 8.435  ; 8.435  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; 7.800  ; 7.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 7.812  ; 7.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 28.361 ; 28.361 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 8.270  ; 8.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 26.622 ; 26.622 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 7.981  ; 7.981  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 7.164  ; 7.164  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 9.601  ; 9.601  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; 7.460  ; 7.460  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 18.763 ; 18.763 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 19.868 ; 19.868 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 17.762 ; 17.762 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 19.427 ; 19.427 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 19.387 ; 19.387 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 19.251 ; 19.251 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 19.427 ; 19.427 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 16.053 ; 16.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 14.371 ; 14.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 18.202 ; 18.202 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 14.331 ; 14.331 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 14.277 ; 14.277 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 14.861 ; 14.861 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 15.079 ; 15.079 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 15.097 ; 15.097 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 16.414 ; 16.414 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 15.893 ; 15.893 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 15.941 ; 15.941 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 17.811 ; 17.811 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 18.202 ; 18.202 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 15.655 ; 15.655 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 16.598 ; 16.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 15.215 ; 15.215 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 15.833 ; 15.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 16.222 ; 16.222 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 16.582 ; 16.582 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 9.367  ; 9.367  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; 6.861  ; 6.861  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; 7.211  ; 7.211  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; 7.284  ; 7.284  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 28.750 ; 28.750 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 28.750 ; 28.750 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 28.715 ; 28.715 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 28.655 ; 28.655 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; 7.677  ; 7.677  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 9.059  ; 9.059  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 18.385 ; 18.385 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; 8.748  ; 8.748  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 18.126 ; 18.126 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 27.727 ; 27.727 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 18.261 ; 18.261 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 16.581 ; 16.581 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 16.446 ; 16.446 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 16.428 ; 16.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 15.705 ; 15.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 15.373 ; 15.373 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 15.515 ; 15.515 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 16.259 ; 16.259 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 15.619 ; 15.619 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 16.581 ; 16.581 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 19.080 ; 19.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 16.072 ; 16.072 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 15.952 ; 15.952 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 15.789 ; 15.789 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 16.216 ; 16.216 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 15.984 ; 15.984 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 17.426 ; 17.426 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 19.080 ; 19.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 17.045 ; 17.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 17.483 ; 17.483 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 18.730 ; 18.730 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 16.757 ; 16.757 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 18.309 ; 18.309 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 15.802 ; 15.802 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 16.684 ; 16.684 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 17.578 ; 17.578 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 18.075 ; 18.075 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 28.752 ; 28.752 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 22.997 ; 22.997 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 6.951  ; 6.951  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; 6.402  ; 6.402  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 26.525 ; 26.525 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; 7.551  ; 7.551  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; 24.867 ; 24.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; 18.131 ; 18.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; 18.619 ; 18.619 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; 16.383 ; 16.383 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 18.615 ; 18.615 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; 18.615 ; 18.615 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; 18.479 ; 18.479 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; 12.840 ; 12.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; 18.429 ; 18.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; 15.281 ; 15.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 13.599 ; 13.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 16.346 ; 16.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 13.553 ; 13.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 13.028 ; 13.028 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 14.229 ; 14.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 14.119 ; 14.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 13.714 ; 13.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 15.045 ; 15.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 14.514 ; 14.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 15.169 ; 15.169 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 16.346 ; 16.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; 10.597 ; 10.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 26.995 ; 26.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 26.995 ; 26.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 26.960 ; 26.960 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 26.900 ; 26.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; 17.016 ; 17.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; 16.757 ; 16.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 26.262 ; 26.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; 17.483 ; 17.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; 14.981 ; 14.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; 14.981 ; 14.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 17.701 ; 17.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 15.294 ; 15.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 14.703 ; 14.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 15.157 ; 15.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 15.256 ; 15.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 14.601 ; 14.601 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 16.057 ; 16.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 17.701 ; 17.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 16.273 ; 16.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 16.018 ; 16.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 12.220 ; 12.220 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 12.271 ; 12.271 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 12.885 ; 12.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 12.380 ; 12.380 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 12.788 ; 12.788 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 12.778 ; 12.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 12.335 ; 12.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 26.997 ; 26.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 21.869 ; 21.869 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 24.945 ; 24.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 14.362 ; 14.362 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 14.232 ; 14.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 14.232 ; 14.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 14.196 ; 14.196 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 14.131 ; 14.131 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 11.487 ; 11.487 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 14.207 ; 14.207 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; 24.867 ; 24.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 18.131 ; 18.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 18.619 ; 18.619 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 16.383 ; 16.383 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 18.615 ; 18.615 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 18.615 ; 18.615 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 18.479 ; 18.479 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; 12.840 ; 12.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 18.429 ; 18.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 15.281 ; 15.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 13.599 ; 13.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 16.346 ; 16.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 13.553 ; 13.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 13.028 ; 13.028 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 14.229 ; 14.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 14.119 ; 14.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 13.714 ; 13.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 15.045 ; 15.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 14.514 ; 14.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 15.169 ; 15.169 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 16.346 ; 16.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 10.597 ; 10.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 26.995 ; 26.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 26.995 ; 26.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 26.960 ; 26.960 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 26.900 ; 26.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 17.016 ; 17.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 16.757 ; 16.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 26.262 ; 26.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 17.483 ; 17.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 14.981 ; 14.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 14.981 ; 14.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 17.701 ; 17.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 15.294 ; 15.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 14.703 ; 14.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 15.157 ; 15.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 15.256 ; 15.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 14.601 ; 14.601 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 16.057 ; 16.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 17.701 ; 17.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 16.273 ; 16.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 16.018 ; 16.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 12.220 ; 12.220 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 12.271 ; 12.271 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 12.885 ; 12.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 12.380 ; 12.380 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.788 ; 12.788 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.778 ; 12.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 12.335 ; 12.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 26.997 ; 26.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 21.869 ; 21.869 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 24.945 ; 24.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 14.362 ; 14.362 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 14.232 ; 14.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 14.232 ; 14.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 14.196 ; 14.196 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 14.131 ; 14.131 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 11.487 ; 11.487 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 14.207 ; 14.207 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; 24.527 ; 24.527 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; 16.132 ; 16.132 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; 16.855 ; 16.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; 14.688 ; 14.688 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; 17.262 ; 17.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; 16.711 ; 16.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; 16.575 ; 16.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; 17.262 ; 17.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; 13.377 ; 13.377 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 11.695 ; 11.695 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; 15.390 ; 15.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 11.763 ; 11.763 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 11.264 ; 11.264 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 12.230 ; 12.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 12.428 ; 12.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 12.107 ; 12.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 13.270 ; 13.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 12.819 ; 12.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 13.265 ; 13.265 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 15.308 ; 15.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 15.390 ; 15.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 13.279 ; 13.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 13.809 ; 13.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 12.730 ; 12.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 13.285 ; 13.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 13.726 ; 13.726 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 15.373 ; 15.373 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; 26.655 ; 26.655 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; 26.655 ; 26.655 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; 26.620 ; 26.620 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; 26.560 ; 26.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; 15.241 ; 15.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; 14.982 ; 14.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; 26.006 ; 26.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; 15.693 ; 15.693 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 15.553 ; 15.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; 13.943 ; 13.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; 13.616 ; 13.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; 13.329 ; 13.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 15.225 ; 15.225 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 15.420 ; 15.420 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 15.348 ; 15.348 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 15.553 ; 15.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; 15.372 ; 15.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 16.866 ; 16.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 13.504 ; 13.504 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 12.939 ; 12.939 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 13.158 ; 13.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 13.565 ; 13.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 12.994 ; 12.994 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 14.282 ; 14.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 16.006 ; 16.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 14.369 ; 14.369 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 14.980 ; 14.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 15.918 ; 15.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 14.381 ; 14.381 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 15.520 ; 15.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 13.317 ; 13.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 14.136 ; 14.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 15.082 ; 15.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 16.866 ; 16.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; 26.657 ; 26.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; 20.079 ; 20.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; 24.689 ; 24.689 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; 24.527 ; 24.527 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 16.132 ; 16.132 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 16.855 ; 16.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 14.688 ; 14.688 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 17.262 ; 17.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 16.711 ; 16.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 16.575 ; 16.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 17.262 ; 17.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 13.377 ; 13.377 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 11.695 ; 11.695 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 15.390 ; 15.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 11.763 ; 11.763 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 11.264 ; 11.264 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 12.230 ; 12.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 12.428 ; 12.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 12.107 ; 12.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 13.270 ; 13.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 12.819 ; 12.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 13.265 ; 13.265 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 15.308 ; 15.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 15.390 ; 15.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 13.279 ; 13.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 13.809 ; 13.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 12.730 ; 12.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 13.285 ; 13.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 13.726 ; 13.726 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 15.373 ; 15.373 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 26.655 ; 26.655 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 26.655 ; 26.655 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 26.620 ; 26.620 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 26.560 ; 26.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 15.241 ; 15.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 14.982 ; 14.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 26.006 ; 26.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 15.693 ; 15.693 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 15.553 ; 15.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 13.943 ; 13.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 13.616 ; 13.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 13.329 ; 13.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 15.225 ; 15.225 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 15.420 ; 15.420 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 15.348 ; 15.348 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 15.553 ; 15.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 15.372 ; 15.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 16.866 ; 16.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 13.504 ; 13.504 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 12.939 ; 12.939 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 13.158 ; 13.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 13.565 ; 13.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 12.994 ; 12.994 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 14.282 ; 14.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 16.006 ; 16.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 14.369 ; 14.369 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 14.980 ; 14.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 15.918 ; 15.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 14.381 ; 14.381 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 15.520 ; 15.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 13.317 ; 13.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 14.136 ; 14.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 15.082 ; 15.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 16.866 ; 16.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 26.657 ; 26.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 20.079 ; 20.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 24.689 ; 24.689 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                   ;
+----------------+---------------+---------+---------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+---------+---------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 1.129   ; 1.129   ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; -8.766  ; -8.766  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; 0.621   ; 0.621   ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; -9.169  ; -9.169  ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; -6.944  ; -6.944  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -6.728  ; -6.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -8.231  ; -8.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; -6.187  ; -6.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; -6.187  ; -6.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; -6.429  ; -6.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; -6.719  ; -6.719  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; -6.244  ; -6.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; -6.336  ; -6.336  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; -6.546  ; -6.546  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; -6.444  ; -6.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; -6.604  ; -6.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -8.386  ; -8.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -7.605  ; -7.605  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -7.300  ; -7.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; -8.760  ; -8.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -8.950  ; -8.950  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -8.950  ; -8.950  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -8.976  ; -8.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -9.418  ; -9.418  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -6.084  ; -6.084  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -5.062  ; -5.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -8.071  ; -8.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -8.662  ; -8.662  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -9.474  ; -9.474  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -9.001  ; -9.001  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -9.403  ; -9.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -9.075  ; -9.075  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -9.448  ; -9.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -8.925  ; -8.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -9.136  ; -9.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -9.268  ; -9.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -10.134 ; -10.134 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -9.236  ; -9.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -10.095 ; -10.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -9.425  ; -9.425  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -8.647  ; -8.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -8.871  ; -8.871  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -8.071  ; -8.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; -7.328  ; -7.328  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -7.080  ; -7.080  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -10.768 ; -10.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -11.146 ; -11.146 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -10.768 ; -10.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -11.119 ; -11.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; -7.475  ; -7.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; -3.461  ; -3.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; -7.437  ; -7.437  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; -8.736  ; -8.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; -7.665  ; -7.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -8.985  ; -8.985  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; -6.461  ; -6.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -8.726  ; -8.726  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; -6.955  ; -6.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -8.348  ; -8.348  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -7.301  ; -7.301  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -12.907 ; -12.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -14.318 ; -14.318 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -13.952 ; -13.952 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -13.387 ; -13.387 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -12.907 ; -12.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -13.376 ; -13.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -13.926 ; -13.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -13.434 ; -13.434 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -14.648 ; -14.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; -5.722  ; -5.722  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; -3.807  ; -3.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; -3.453  ; -3.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; -3.205  ; -3.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; -2.932  ; -2.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; -2.422  ; -2.422  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -6.699  ; -6.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -6.699  ; -6.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -7.337  ; -7.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -7.125  ; -7.125  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -7.699  ; -7.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -7.683  ; -7.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -7.882  ; -7.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -8.470  ; -8.470  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -7.766  ; -7.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -8.327  ; -8.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -6.852  ; -6.852  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -6.987  ; -6.987  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -7.380  ; -7.380  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -7.122  ; -7.122  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -7.206  ; -7.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -7.441  ; -7.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -7.176  ; -7.176  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; -2.490  ; -2.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; -7.409  ; -7.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -7.496  ; -7.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; -8.252  ; -8.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; -6.759  ; -6.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; -5.758  ; -5.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; -6.297  ; -6.297  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; -6.333  ; -6.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; -5.758  ; -5.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; -5.912  ; -5.912  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; -6.682  ; -6.682  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; -6.434  ; -6.434  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; -6.716  ; -6.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; -6.666  ; -6.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; -6.738  ; -6.738  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; -6.995  ; -6.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; -6.877  ; -6.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; -7.316  ; -7.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; -7.138  ; -7.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; -8.308  ; -8.308  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; -7.629  ; -7.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; -8.237  ; -8.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -7.984  ; -7.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; -9.016  ; -9.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; -8.149  ; -8.149  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; -6.718  ; -6.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; -6.718  ; -6.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; -7.332  ; -7.332  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; -7.262  ; -7.262  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; -7.714  ; -7.714  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; -8.183  ; -8.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; -7.550  ; -7.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -7.178  ; -7.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -8.754  ; -8.754  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; -6.951  ; -6.951  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; -11.147 ; -11.147 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -7.733  ; -7.733  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -6.916  ; -6.916  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -9.353  ; -9.353  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; -7.212  ; -7.212  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -16.985 ; -16.985 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -17.980 ; -17.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -15.644 ; -15.644 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -8.941  ; -8.941  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -16.940 ; -16.940 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -16.804 ; -16.804 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -8.941  ; -8.941  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -13.606 ; -13.606 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -11.924 ; -11.924 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -7.936  ; -7.936  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -7.936  ; -7.936  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -9.636  ; -9.636  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -9.352  ; -9.352  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -8.730  ; -8.730  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -8.532  ; -8.532  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -8.459  ; -8.459  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -9.654  ; -9.654  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -8.532  ; -8.532  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -9.255  ; -9.255  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -10.538 ; -10.538 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -9.598  ; -9.598  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -10.162 ; -10.162 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -9.657  ; -9.657  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -8.760  ; -8.760  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -8.916  ; -8.916  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -8.357  ; -8.357  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -8.412  ; -8.412  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; -5.075  ; -5.075  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; -5.332  ; -5.332  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; -5.405  ; -5.405  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -10.955 ; -10.955 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -11.056 ; -11.056 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -11.020 ; -11.020 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -10.955 ; -10.955 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; -7.429  ; -7.429  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -8.811  ; -8.811  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -15.466 ; -15.466 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; -8.500  ; -8.500  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -15.207 ; -15.207 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -8.990  ; -8.990  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -15.937 ; -15.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -12.974 ; -12.974 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -14.305 ; -14.305 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -14.356 ; -14.356 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -13.749 ; -13.749 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -12.974 ; -12.974 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -13.608 ; -13.608 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -14.039 ; -14.039 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -13.479 ; -13.479 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -14.330 ; -14.330 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -13.384 ; -13.384 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -13.748 ; -13.748 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -14.064 ; -14.064 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -14.011 ; -14.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -13.796 ; -13.796 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -13.384 ; -13.384 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -14.507 ; -14.507 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -16.962 ; -16.962 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -14.598 ; -14.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -15.342 ; -15.342 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -16.658 ; -16.658 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -14.801 ; -14.801 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -15.910 ; -15.910 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -13.895 ; -13.895 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -14.464 ; -14.464 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -15.438 ; -15.438 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -15.824 ; -15.824 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -10.486 ; -10.486 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -10.894 ; -10.894 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -6.703  ; -6.703  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; -6.154  ; -6.154  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -12.974 ; -12.974 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; -7.303  ; -7.303  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; -6.944  ; -6.944  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -6.728  ; -6.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -8.231  ; -8.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -6.187  ; -6.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -6.187  ; -6.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -6.429  ; -6.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -6.719  ; -6.719  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -6.244  ; -6.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -6.336  ; -6.336  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -6.546  ; -6.546  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -6.444  ; -6.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -6.604  ; -6.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -8.386  ; -8.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -7.605  ; -7.605  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -7.300  ; -7.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; -8.760  ; -8.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -8.950  ; -8.950  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -8.950  ; -8.950  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -8.976  ; -8.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -9.418  ; -9.418  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -6.084  ; -6.084  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -5.062  ; -5.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -8.071  ; -8.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -8.662  ; -8.662  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -9.474  ; -9.474  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -9.001  ; -9.001  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -9.403  ; -9.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -9.075  ; -9.075  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -9.448  ; -9.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -8.925  ; -8.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -9.136  ; -9.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -9.268  ; -9.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -10.134 ; -10.134 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -9.236  ; -9.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -10.095 ; -10.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -9.425  ; -9.425  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -8.647  ; -8.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -8.871  ; -8.871  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -8.071  ; -8.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; -7.328  ; -7.328  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -7.080  ; -7.080  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -10.768 ; -10.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -11.146 ; -11.146 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -10.768 ; -10.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -11.119 ; -11.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; -7.475  ; -7.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; -3.461  ; -3.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; -7.437  ; -7.437  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; -8.736  ; -8.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; -7.665  ; -7.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -8.985  ; -8.985  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; -6.461  ; -6.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -8.726  ; -8.726  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; -6.955  ; -6.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -8.348  ; -8.348  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.301  ; -7.301  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -12.907 ; -12.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -14.318 ; -14.318 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -13.952 ; -13.952 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -13.387 ; -13.387 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -12.907 ; -12.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -13.376 ; -13.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -13.926 ; -13.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -13.434 ; -13.434 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -14.648 ; -14.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; -5.722  ; -5.722  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; -3.807  ; -3.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; -3.453  ; -3.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; -3.205  ; -3.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; -2.932  ; -2.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; -2.422  ; -2.422  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -6.699  ; -6.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -6.699  ; -6.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -7.337  ; -7.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -7.125  ; -7.125  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -7.699  ; -7.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -7.683  ; -7.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -7.882  ; -7.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -8.470  ; -8.470  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -7.766  ; -7.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -8.327  ; -8.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -6.852  ; -6.852  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -6.987  ; -6.987  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -7.380  ; -7.380  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -7.122  ; -7.122  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -7.206  ; -7.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -7.441  ; -7.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -7.176  ; -7.176  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; -2.490  ; -2.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; -7.409  ; -7.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -7.496  ; -7.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; -8.252  ; -8.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; -6.759  ; -6.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; -5.758  ; -5.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; -6.297  ; -6.297  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; -6.333  ; -6.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; -5.758  ; -5.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; -5.912  ; -5.912  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; -6.682  ; -6.682  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; -6.434  ; -6.434  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; -6.716  ; -6.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; -6.666  ; -6.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; -6.738  ; -6.738  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; -6.995  ; -6.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; -6.877  ; -6.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; -7.316  ; -7.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; -7.138  ; -7.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; -8.308  ; -8.308  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; -7.629  ; -7.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; -8.237  ; -8.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -7.984  ; -7.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; -9.016  ; -9.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; -8.149  ; -8.149  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; -6.718  ; -6.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; -6.718  ; -6.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; -7.332  ; -7.332  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; -7.262  ; -7.262  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; -7.714  ; -7.714  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; -8.183  ; -8.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; -7.550  ; -7.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -7.178  ; -7.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -8.754  ; -8.754  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; -6.951  ; -6.951  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -11.147 ; -11.147 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -7.733  ; -7.733  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -6.916  ; -6.916  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -9.353  ; -9.353  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; -7.212  ; -7.212  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -16.985 ; -16.985 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -17.980 ; -17.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -15.644 ; -15.644 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -8.941  ; -8.941  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -16.940 ; -16.940 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -16.804 ; -16.804 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -8.941  ; -8.941  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -13.606 ; -13.606 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -11.924 ; -11.924 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -7.936  ; -7.936  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -7.936  ; -7.936  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -9.636  ; -9.636  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -9.352  ; -9.352  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -8.730  ; -8.730  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -8.532  ; -8.532  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -8.459  ; -8.459  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -9.654  ; -9.654  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -8.532  ; -8.532  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -9.255  ; -9.255  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -10.538 ; -10.538 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -9.598  ; -9.598  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -10.162 ; -10.162 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -9.657  ; -9.657  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -8.760  ; -8.760  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -8.916  ; -8.916  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -8.357  ; -8.357  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -8.412  ; -8.412  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; -5.075  ; -5.075  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; -5.332  ; -5.332  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; -5.405  ; -5.405  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -10.955 ; -10.955 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -11.056 ; -11.056 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -11.020 ; -11.020 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -10.955 ; -10.955 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; -7.429  ; -7.429  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -8.811  ; -8.811  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -15.466 ; -15.466 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; -8.500  ; -8.500  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -15.207 ; -15.207 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -8.990  ; -8.990  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -15.937 ; -15.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -12.974 ; -12.974 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -14.305 ; -14.305 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -14.356 ; -14.356 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -13.749 ; -13.749 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -12.974 ; -12.974 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -13.608 ; -13.608 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -14.039 ; -14.039 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -13.479 ; -13.479 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -14.330 ; -14.330 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -13.384 ; -13.384 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -13.748 ; -13.748 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -14.064 ; -14.064 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -14.011 ; -14.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -13.796 ; -13.796 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -13.384 ; -13.384 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -14.507 ; -14.507 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -16.962 ; -16.962 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -14.598 ; -14.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -15.342 ; -15.342 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -16.658 ; -16.658 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -14.801 ; -14.801 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -15.910 ; -15.910 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -13.895 ; -13.895 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -14.464 ; -14.464 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -15.438 ; -15.438 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -15.824 ; -15.824 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -10.486 ; -10.486 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -10.894 ; -10.894 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -6.703  ; -6.703  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; -6.154  ; -6.154  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -12.974 ; -12.974 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; -7.303  ; -7.303  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; -9.150  ; -9.150  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; -17.216 ; -17.216 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; -17.671 ; -17.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; -15.504 ; -15.504 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -7.930  ; -7.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; -8.295  ; -8.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; -7.930  ; -7.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; -11.111 ; -11.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; -10.394 ; -10.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; -5.038  ; -5.038  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -4.016  ; -4.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; -8.284  ; -8.284  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; -8.284  ; -8.284  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; -9.327  ; -9.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; -9.583  ; -9.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; -9.380  ; -9.380  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; -8.950  ; -8.950  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; -9.066  ; -9.066  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; -9.514  ; -9.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; -9.205  ; -9.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; -9.683  ; -9.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; -9.865  ; -9.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -10.684 ; -10.684 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -10.836 ; -10.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -10.684 ; -10.684 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -11.645 ; -11.645 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; -16.073 ; -16.073 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; -15.814 ; -15.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -11.082 ; -11.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; -16.285 ; -16.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; -14.733 ; -14.733 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; -14.733 ; -14.733 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -6.741  ; -6.741  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -6.776  ; -6.776  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -6.741  ; -6.741  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -6.821  ; -6.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -7.267  ; -7.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -7.319  ; -7.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -7.255  ; -7.255  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -7.359  ; -7.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -7.306  ; -7.306  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -7.012  ; -7.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -7.130  ; -7.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -7.118  ; -7.118  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -6.981  ; -6.981  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -7.128  ; -7.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -7.050  ; -7.050  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -6.784  ; -6.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -6.885  ; -6.885  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; -8.206  ; -8.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -11.584 ; -11.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; -11.520 ; -11.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; -11.012 ; -11.012 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -13.381 ; -13.381 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -13.482 ; -13.482 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -13.446 ; -13.446 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -13.381 ; -13.381 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -10.737 ; -10.737 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -12.905 ; -12.905 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; -9.150  ; -9.150  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -17.216 ; -17.216 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -17.671 ; -17.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -15.504 ; -15.504 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -7.930  ; -7.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -8.295  ; -8.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -7.930  ; -7.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; -11.111 ; -11.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -10.394 ; -10.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -5.038  ; -5.038  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -4.016  ; -4.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -8.284  ; -8.284  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -8.284  ; -8.284  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -9.327  ; -9.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -9.583  ; -9.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -9.380  ; -9.380  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -8.950  ; -8.950  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -9.066  ; -9.066  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -9.514  ; -9.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -9.205  ; -9.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -9.683  ; -9.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -9.865  ; -9.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -10.684 ; -10.684 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -10.836 ; -10.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -10.684 ; -10.684 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -11.645 ; -11.645 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -16.073 ; -16.073 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -15.814 ; -15.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -11.082 ; -11.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -16.285 ; -16.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -14.733 ; -14.733 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -14.733 ; -14.733 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -6.741  ; -6.741  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -6.776  ; -6.776  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -6.741  ; -6.741  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -6.821  ; -6.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -7.267  ; -7.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -7.319  ; -7.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -7.255  ; -7.255  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -7.359  ; -7.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -7.306  ; -7.306  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -7.012  ; -7.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -7.130  ; -7.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -7.118  ; -7.118  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -6.981  ; -6.981  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -7.128  ; -7.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -7.050  ; -7.050  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -6.784  ; -6.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -6.885  ; -6.885  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -8.206  ; -8.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -11.584 ; -11.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -11.520 ; -11.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -11.012 ; -11.012 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -13.381 ; -13.381 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -13.482 ; -13.482 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -13.446 ; -13.446 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -13.381 ; -13.381 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -10.737 ; -10.737 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -12.905 ; -12.905 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; -7.708  ; -7.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; -15.884 ; -15.884 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; -16.607 ; -16.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; -14.440 ; -14.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; -12.555 ; -12.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; -16.463 ; -16.463 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; -16.327 ; -16.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; -12.555 ; -12.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; -13.129 ; -13.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -11.447 ; -11.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; -7.444  ; -7.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; -7.444  ; -7.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; -8.263  ; -8.263  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; -8.251  ; -8.251  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; -8.251  ; -8.251  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; -7.894  ; -7.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; -7.986  ; -7.986  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; -8.450  ; -8.450  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; -8.055  ; -8.055  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; -8.161  ; -8.161  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; -9.069  ; -9.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; -8.331  ; -8.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; -9.049  ; -9.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; -8.351  ; -8.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; -7.591  ; -7.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; -7.829  ; -7.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; -7.717  ; -7.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; -12.646 ; -12.646 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; -12.730 ; -12.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; -12.702 ; -12.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; -12.646 ; -12.646 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; -14.993 ; -14.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; -14.734 ; -14.734 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; -11.984 ; -11.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; -15.445 ; -15.445 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; -6.286  ; -6.286  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; -13.211 ; -13.211 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; -12.887 ; -12.887 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; -12.482 ; -12.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.567  ; -6.567  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; -6.442  ; -6.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; -6.286  ; -6.286  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; -6.668  ; -6.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; -13.690 ; -13.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -12.589 ; -12.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -13.256 ; -13.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -12.691 ; -12.691 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -12.910 ; -12.910 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -13.317 ; -13.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -12.746 ; -12.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -14.034 ; -14.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -15.758 ; -15.758 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -14.121 ; -14.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -14.248 ; -14.248 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -15.189 ; -15.189 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -13.534 ; -13.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -14.797 ; -14.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -12.589 ; -12.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -13.295 ; -13.295 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -14.351 ; -14.351 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -15.184 ; -15.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; -8.576  ; -8.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; -11.724 ; -11.724 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; -11.707 ; -11.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; -7.708  ; -7.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -15.884 ; -15.884 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -16.607 ; -16.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -14.440 ; -14.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -12.555 ; -12.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -16.463 ; -16.463 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -16.327 ; -16.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -12.555 ; -12.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -13.129 ; -13.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -11.447 ; -11.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -7.444  ; -7.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -7.444  ; -7.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -8.263  ; -8.263  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -8.251  ; -8.251  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -8.251  ; -8.251  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -7.894  ; -7.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -7.986  ; -7.986  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -8.450  ; -8.450  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -8.055  ; -8.055  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -8.161  ; -8.161  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -9.069  ; -9.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -8.331  ; -8.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -9.049  ; -9.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -8.351  ; -8.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -7.591  ; -7.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -7.829  ; -7.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -7.717  ; -7.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -12.646 ; -12.646 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -12.730 ; -12.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -12.702 ; -12.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -12.646 ; -12.646 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -14.993 ; -14.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -14.734 ; -14.734 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -11.984 ; -11.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -15.445 ; -15.445 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -6.286  ; -6.286  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -13.211 ; -13.211 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -12.887 ; -12.887 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -12.482 ; -12.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.567  ; -6.567  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -6.442  ; -6.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -6.286  ; -6.286  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -6.668  ; -6.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -13.690 ; -13.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -12.589 ; -12.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -13.256 ; -13.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -12.691 ; -12.691 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -12.910 ; -12.910 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -13.317 ; -13.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -12.746 ; -12.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -14.034 ; -14.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -15.758 ; -15.758 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -14.121 ; -14.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -14.248 ; -14.248 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -15.189 ; -15.189 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -13.534 ; -13.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -14.797 ; -14.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -12.589 ; -12.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -13.295 ; -13.295 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -14.351 ; -14.351 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -15.184 ; -15.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -8.576  ; -8.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -11.724 ; -11.724 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -11.707 ; -11.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+---------+---------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                      ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 17.740 ; 17.740 ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 17.749 ; 17.749 ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 16.620 ; 16.620 ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 27.272 ; 27.272 ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 23.185 ; 23.185 ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 23.601 ; 23.601 ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 22.690 ; 22.690 ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 26.628 ; 26.628 ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 26.632 ; 26.632 ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 27.272 ; 27.272 ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 27.218 ; 27.218 ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 22.974 ; 22.974 ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 27.106 ; 27.106 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 25.614 ; 25.614 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 26.734 ; 26.734 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 25.529 ; 25.529 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 24.882 ; 24.882 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 25.164 ; 25.164 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 26.824 ; 26.824 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 26.561 ; 26.561 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 27.106 ; 27.106 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 23.803 ; 23.803 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 25.043 ; 25.043 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 22.290 ; 22.290 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 25.493 ; 25.493 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 24.923 ; 24.923 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 23.413 ; 23.413 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 22.084 ; 22.084 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 22.752 ; 22.752 ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 8.596  ; 8.596  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 28.328 ; 28.328 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 26.898 ; 26.898 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 27.661 ; 27.661 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 26.279 ; 26.279 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 27.181 ; 27.181 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 27.413 ; 27.413 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 28.328 ; 28.328 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 27.297 ; 27.297 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 27.275 ; 27.275 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 23.764 ; 23.764 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 25.054 ; 25.054 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 23.500 ; 23.500 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 24.175 ; 24.175 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 24.589 ; 24.589 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 25.199 ; 25.199 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 24.211 ; 24.211 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 24.266 ; 24.266 ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 13.526 ; 13.526 ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 11.306 ; 11.306 ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 9.613  ; 9.613  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 25.570 ; 25.570 ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 25.570 ; 25.570 ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 25.739 ; 25.739 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 25.739 ; 25.739 ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 22.250 ; 22.250 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 19.496 ; 19.496 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 21.786 ; 21.786 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 20.636 ; 20.636 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 19.012 ; 19.012 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 19.519 ; 19.519 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 22.004 ; 22.004 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 21.396 ; 21.396 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 22.250 ; 22.250 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 19.905 ; 19.905 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 21.980 ; 21.980 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 17.370 ; 17.370 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 22.128 ; 22.128 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 19.284 ; 19.284 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 20.365 ; 20.365 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 19.303 ; 19.303 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 20.815 ; 20.815 ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 23.508 ; 23.508 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 20.780 ; 20.780 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 22.713 ; 22.713 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 21.386 ; 21.386 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 21.311 ; 21.311 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 21.768 ; 21.768 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 23.508 ; 23.508 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 22.132 ; 22.132 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 22.419 ; 22.419 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 19.866 ; 19.866 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 21.991 ; 21.991 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 18.580 ; 18.580 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 20.810 ; 20.810 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 18.950 ; 18.950 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 22.151 ; 22.151 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 21.430 ; 21.430 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 22.329 ; 22.329 ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 21.639 ; 21.639 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 21.639 ; 21.639 ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 7.538  ; 7.538  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 21.808 ; 21.808 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 21.808 ; 21.808 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 11.397 ; 11.397 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.310 ; 12.310 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 11.662 ; 11.662 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 11.030 ; 11.030 ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 7.567  ; 7.567  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 21.639 ; 21.639 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 21.639 ; 21.639 ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 7.538  ; 7.538  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 21.808 ; 21.808 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 21.808 ; 21.808 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 11.397 ; 11.397 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.310 ; 12.310 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 11.662 ; 11.662 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 11.030 ; 11.030 ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 7.567  ; 7.567  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 39.292 ; 39.292 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 39.301 ; 39.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 35.272 ; 35.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 30.017 ; 30.017 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 32.176 ; 32.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 30.594 ; 30.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 30.901 ; 30.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 33.071 ; 33.071 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 30.016 ; 30.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 31.776 ; 31.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 30.654 ; 30.654 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 31.582 ; 31.582 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 31.764 ; 31.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 31.288 ; 31.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 32.256 ; 32.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 31.744 ; 31.744 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 32.109 ; 32.109 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 31.389 ; 31.389 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 30.418 ; 30.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 33.711 ; 33.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 31.137 ; 31.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 34.383 ; 34.383 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 34.748 ; 34.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 32.466 ; 32.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 32.169 ; 32.169 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 35.272 ; 35.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 14.990 ; 14.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 6.878  ; 6.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 10.673 ; 10.673 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 9.441  ; 9.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 7.875  ; 7.875  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 36.318 ; 36.318 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 38.172 ; 38.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 48.824 ; 48.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 44.737 ; 44.737 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 45.153 ; 45.153 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 44.242 ; 44.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 48.180 ; 48.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 48.184 ; 48.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 48.824 ; 48.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 48.770 ; 48.770 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 44.526 ; 44.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 7.739  ; 7.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 8.054  ; 8.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 6.663  ; 6.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 10.455 ; 10.455 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 5.228  ; 5.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 5.614  ; 5.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 5.107  ; 5.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 6.328  ; 6.328  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 49.741 ; 49.741 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 47.161 ; 47.161 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 49.098 ; 49.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 47.177 ; 47.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 47.280 ; 47.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 46.842 ; 46.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 48.714 ; 48.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 48.274 ; 48.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 49.741 ; 49.741 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 49.036 ; 49.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 49.102 ; 49.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 46.230 ; 46.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 49.150 ; 49.150 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 48.310 ; 48.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 47.181 ; 47.181 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 46.829 ; 46.829 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 47.668 ; 47.668 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 7.974  ; 7.974  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 6.591  ; 6.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 8.205  ; 8.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 6.806  ; 6.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 7.175  ; 7.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 15.497 ; 15.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 15.497 ; 15.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 15.158 ; 15.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 15.276 ; 15.276 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 7.544  ; 7.544  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 7.804  ; 7.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 6.860  ; 6.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 7.726  ; 7.726  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 7.409  ; 7.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 8.254  ; 8.254  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 7.385  ; 7.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 7.381  ; 7.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 31.319 ; 31.319 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 34.141 ; 34.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 38.965 ; 38.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 38.171 ; 38.171 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 7.033  ; 7.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 9.345  ; 9.345  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 5.178  ; 5.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 9.420  ; 9.420  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 8.173  ; 8.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 7.455  ; 7.455  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 37.135 ; 37.135 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 36.033 ; 36.033 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 36.370 ; 36.370 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 37.514 ; 37.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 37.159 ; 37.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 36.820 ; 36.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 36.001 ; 36.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 36.242 ; 36.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 35.884 ; 35.884 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 36.584 ; 36.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 7.588  ; 7.588  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 9.403  ; 9.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 8.866  ; 8.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 9.403  ; 9.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 9.185  ; 9.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 8.644  ; 8.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 30.577 ; 30.577 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 5.155  ; 5.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 5.742  ; 5.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 9.344  ; 9.344  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 6.304  ; 6.304  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 6.677  ; 6.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.717  ; 6.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 8.461  ; 8.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 7.972  ; 7.972  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 9.082  ; 9.082  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 9.344  ; 9.344  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 6.559  ; 6.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 7.062  ; 7.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 7.657  ; 7.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 6.102  ; 6.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 38.645 ; 38.645 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 36.001 ; 36.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 36.648 ; 36.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 36.193 ; 36.193 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 37.751 ; 37.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 37.279 ; 37.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 37.649 ; 37.649 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 37.857 ; 37.857 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 38.645 ; 38.645 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 37.428 ; 37.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 37.257 ; 37.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 36.658 ; 36.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 35.597 ; 35.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 35.472 ; 35.472 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 35.713 ; 35.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 35.713 ; 35.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 51.313 ; 51.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 48.445 ; 48.445 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 50.025 ; 50.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 48.293 ; 48.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 49.579 ; 49.579 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 49.143 ; 49.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 51.025 ; 51.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 50.768 ; 50.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 49.910 ; 49.910 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 51.313 ; 51.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 49.113 ; 49.113 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 50.004 ; 50.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 50.120 ; 50.120 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 48.813 ; 48.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 48.967 ; 48.967 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 48.956 ; 48.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 49.272 ; 49.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 11.571 ; 11.571 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 35.812 ; 35.812 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 35.527 ; 35.527 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 36.605 ; 36.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 35.539 ; 35.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 35.241 ; 35.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 37.095 ; 37.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 38.121 ; 38.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 13.928 ; 13.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 8.241  ; 8.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 9.716  ; 9.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 6.720  ; 6.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 13.650 ; 13.650 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 8.788  ; 8.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 7.458  ; 7.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 8.159  ; 8.159  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 7.730  ; 7.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 7.685  ; 7.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 7.826  ; 7.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 8.102  ; 8.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 8.788  ; 8.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 8.389  ; 8.389  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 5.645  ; 5.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 10.115 ; 10.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 4.759  ; 4.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 6.052  ; 6.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 10.513 ; 10.513 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 9.387  ; 9.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 8.370  ; 8.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 7.748  ; 7.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 10.111 ; 10.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 9.647  ; 9.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 10.864 ; 10.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 9.081  ; 9.081  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 8.747  ; 8.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 7.077  ; 7.077  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 8.992  ; 8.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 7.414  ; 7.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 8.992  ; 8.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 7.937  ; 7.937  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 8.220  ; 8.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 28.482 ; 28.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 5.068  ; 5.068  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 7.179  ; 7.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 7.140  ; 7.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 18.473 ; 18.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 15.606 ; 15.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 17.057 ; 17.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 45.091 ; 45.091 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 45.100 ; 45.100 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 41.071 ; 41.071 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 35.816 ; 35.816 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 37.975 ; 37.975 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 36.393 ; 36.393 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 36.700 ; 36.700 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 38.870 ; 38.870 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 35.815 ; 35.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 37.575 ; 37.575 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 36.453 ; 36.453 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 37.381 ; 37.381 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 37.563 ; 37.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 37.087 ; 37.087 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 38.055 ; 38.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 37.543 ; 37.543 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 37.908 ; 37.908 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 37.188 ; 37.188 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 36.217 ; 36.217 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 39.510 ; 39.510 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 36.936 ; 36.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 40.182 ; 40.182 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 40.547 ; 40.547 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 38.265 ; 38.265 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 37.968 ; 37.968 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 41.071 ; 41.071 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 12.720 ; 9.307  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 6.887  ; 6.887  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 42.117 ; 42.117 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 43.971 ; 43.971 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 54.623 ; 54.623 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 50.536 ; 50.536 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 50.952 ; 50.952 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 50.041 ; 50.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 53.979 ; 53.979 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 53.983 ; 53.983 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 54.623 ; 54.623 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 54.569 ; 54.569 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 50.325 ; 50.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 55.540 ; 55.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 52.960 ; 52.960 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 54.897 ; 54.897 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 52.976 ; 52.976 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 53.079 ; 53.079 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 52.641 ; 52.641 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 54.513 ; 54.513 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 54.073 ; 54.073 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 55.540 ; 55.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 54.835 ; 54.835 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 54.901 ; 54.901 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 52.029 ; 52.029 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 54.949 ; 54.949 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 54.109 ; 54.109 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 52.980 ; 52.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 52.628 ; 52.628 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 53.467 ; 53.467 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 9.853  ; 9.853  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 9.853  ; 9.853  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 9.514  ; 9.514  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 9.190  ; 9.190  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 37.118 ; 37.118 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 39.940 ; 39.940 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 44.764 ; 44.764 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 43.970 ; 43.970 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 42.934 ; 42.934 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 41.832 ; 41.832 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 42.169 ; 42.169 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 43.313 ; 43.313 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 42.958 ; 42.958 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 42.619 ; 42.619 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 41.800 ; 41.800 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 42.041 ; 42.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 41.683 ; 41.683 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 42.383 ; 42.383 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 36.376 ; 36.376 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 44.444 ; 44.444 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 41.800 ; 41.800 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 42.447 ; 42.447 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 41.992 ; 41.992 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 43.550 ; 43.550 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 43.078 ; 43.078 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 43.448 ; 43.448 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 43.656 ; 43.656 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 44.444 ; 44.444 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 43.227 ; 43.227 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 43.056 ; 43.056 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 42.457 ; 42.457 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 41.396 ; 41.396 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 41.271 ; 41.271 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 41.512 ; 41.512 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 41.512 ; 41.512 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 57.112 ; 57.112 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 54.244 ; 54.244 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 55.824 ; 55.824 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 54.092 ; 54.092 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 55.378 ; 55.378 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 54.942 ; 54.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 56.824 ; 56.824 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 56.567 ; 56.567 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 55.709 ; 55.709 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 57.112 ; 57.112 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 54.912 ; 54.912 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 55.803 ; 55.803 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 55.919 ; 55.919 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 54.612 ; 54.612 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 54.766 ; 54.766 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 54.755 ; 54.755 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 55.071 ; 55.071 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 41.611 ; 41.611 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 41.326 ; 41.326 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 42.404 ; 42.404 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 41.338 ; 41.338 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 41.040 ; 41.040 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 42.894 ; 42.894 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 43.920 ; 43.920 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 8.245  ; 8.245  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 34.281 ; 34.281 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 39.292 ; 39.292 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 39.301 ; 39.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 35.272 ; 35.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 30.017 ; 30.017 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 32.176 ; 32.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 30.594 ; 30.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 30.901 ; 30.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 33.071 ; 33.071 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 30.016 ; 30.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 31.776 ; 31.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 30.654 ; 30.654 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 31.582 ; 31.582 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 31.764 ; 31.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 31.288 ; 31.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 32.256 ; 32.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 31.744 ; 31.744 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 32.109 ; 32.109 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 31.389 ; 31.389 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 30.418 ; 30.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 33.711 ; 33.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 31.137 ; 31.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 34.383 ; 34.383 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 34.748 ; 34.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 32.466 ; 32.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 32.169 ; 32.169 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 35.272 ; 35.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 14.990 ; 14.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 6.878  ; 6.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 10.673 ; 10.673 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 9.441  ; 9.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 7.875  ; 7.875  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 36.318 ; 36.318 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 38.172 ; 38.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 48.824 ; 48.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 44.737 ; 44.737 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 45.153 ; 45.153 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 44.242 ; 44.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 48.180 ; 48.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 48.184 ; 48.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 48.824 ; 48.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 48.770 ; 48.770 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 44.526 ; 44.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 7.739  ; 7.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 8.054  ; 8.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 6.663  ; 6.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 10.455 ; 10.455 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 5.228  ; 5.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 5.614  ; 5.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 5.107  ; 5.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 6.328  ; 6.328  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 49.741 ; 49.741 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 47.161 ; 47.161 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 49.098 ; 49.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 47.177 ; 47.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 47.280 ; 47.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 46.842 ; 46.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 48.714 ; 48.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 48.274 ; 48.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 49.741 ; 49.741 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 49.036 ; 49.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 49.102 ; 49.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 46.230 ; 46.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 49.150 ; 49.150 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 48.310 ; 48.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 47.181 ; 47.181 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 46.829 ; 46.829 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 47.668 ; 47.668 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 7.974  ; 7.974  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 6.591  ; 6.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 8.205  ; 8.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 6.806  ; 6.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 7.175  ; 7.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 15.497 ; 15.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 15.497 ; 15.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 15.158 ; 15.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 15.276 ; 15.276 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 7.544  ; 7.544  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 7.804  ; 7.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 6.860  ; 6.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 7.726  ; 7.726  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 7.409  ; 7.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 8.254  ; 8.254  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 7.385  ; 7.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 7.381  ; 7.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 31.319 ; 31.319 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 34.141 ; 34.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 38.965 ; 38.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 38.171 ; 38.171 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 7.033  ; 7.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 9.345  ; 9.345  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 5.178  ; 5.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 9.420  ; 9.420  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 8.173  ; 8.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 7.455  ; 7.455  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 37.135 ; 37.135 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 36.033 ; 36.033 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 36.370 ; 36.370 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 37.514 ; 37.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 37.159 ; 37.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 36.820 ; 36.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 36.001 ; 36.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 36.242 ; 36.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 35.884 ; 35.884 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 36.584 ; 36.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 7.588  ; 7.588  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 9.403  ; 9.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 8.866  ; 8.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 9.403  ; 9.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 9.185  ; 9.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 8.644  ; 8.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 30.577 ; 30.577 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 5.155  ; 5.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 5.742  ; 5.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 9.344  ; 9.344  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 6.304  ; 6.304  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 6.677  ; 6.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.717  ; 6.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 8.461  ; 8.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 7.972  ; 7.972  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 9.082  ; 9.082  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 9.344  ; 9.344  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 6.559  ; 6.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 7.062  ; 7.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 7.657  ; 7.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 6.102  ; 6.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 38.645 ; 38.645 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 36.001 ; 36.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 36.648 ; 36.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 36.193 ; 36.193 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 37.751 ; 37.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 37.279 ; 37.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 37.649 ; 37.649 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 37.857 ; 37.857 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 38.645 ; 38.645 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 37.428 ; 37.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 37.257 ; 37.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 36.658 ; 36.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 35.597 ; 35.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 35.472 ; 35.472 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 35.713 ; 35.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 35.713 ; 35.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 51.313 ; 51.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 48.445 ; 48.445 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 50.025 ; 50.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 48.293 ; 48.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 49.579 ; 49.579 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 49.143 ; 49.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 51.025 ; 51.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 50.768 ; 50.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 49.910 ; 49.910 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 51.313 ; 51.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 49.113 ; 49.113 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 50.004 ; 50.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 50.120 ; 50.120 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 48.813 ; 48.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 48.967 ; 48.967 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 48.956 ; 48.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 49.272 ; 49.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 11.571 ; 11.571 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 35.812 ; 35.812 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 35.527 ; 35.527 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 36.605 ; 36.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 35.539 ; 35.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 35.241 ; 35.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 37.095 ; 37.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 38.121 ; 38.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 13.928 ; 13.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 8.241  ; 8.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 9.716  ; 9.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 6.720  ; 6.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 13.650 ; 13.650 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 8.788  ; 8.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 7.458  ; 7.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 8.159  ; 8.159  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 7.730  ; 7.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 7.685  ; 7.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 7.826  ; 7.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 8.102  ; 8.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 8.788  ; 8.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 8.389  ; 8.389  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 5.645  ; 5.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 10.115 ; 10.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 4.759  ; 4.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 6.052  ; 6.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 10.513 ; 10.513 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 9.387  ; 9.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 8.370  ; 8.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 7.748  ; 7.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 10.111 ; 10.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 9.647  ; 9.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 10.864 ; 10.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 9.081  ; 9.081  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 8.747  ; 8.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 7.077  ; 7.077  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 8.992  ; 8.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 7.414  ; 7.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 8.992  ; 8.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 7.937  ; 7.937  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 8.220  ; 8.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 28.482 ; 28.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 5.068  ; 5.068  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 7.179  ; 7.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 7.140  ; 7.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 18.473 ; 18.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 15.606 ; 15.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 17.057 ; 17.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 45.091 ; 45.091 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 45.100 ; 45.100 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 41.071 ; 41.071 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 35.816 ; 35.816 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 37.975 ; 37.975 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 36.393 ; 36.393 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 36.700 ; 36.700 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 38.870 ; 38.870 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 35.815 ; 35.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 37.575 ; 37.575 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 36.453 ; 36.453 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 37.381 ; 37.381 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 37.563 ; 37.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 37.087 ; 37.087 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 38.055 ; 38.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 37.543 ; 37.543 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 37.908 ; 37.908 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 37.188 ; 37.188 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 36.217 ; 36.217 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 39.510 ; 39.510 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 36.936 ; 36.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 40.182 ; 40.182 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 40.547 ; 40.547 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 38.265 ; 38.265 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 37.968 ; 37.968 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 41.071 ; 41.071 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 12.720 ; 9.307  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 6.887  ; 6.887  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 42.117 ; 42.117 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 43.971 ; 43.971 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 54.623 ; 54.623 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 50.536 ; 50.536 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 50.952 ; 50.952 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 50.041 ; 50.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 53.979 ; 53.979 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 53.983 ; 53.983 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 54.623 ; 54.623 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 54.569 ; 54.569 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 50.325 ; 50.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 55.540 ; 55.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 52.960 ; 52.960 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 54.897 ; 54.897 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 52.976 ; 52.976 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 53.079 ; 53.079 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 52.641 ; 52.641 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 54.513 ; 54.513 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 54.073 ; 54.073 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 55.540 ; 55.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 54.835 ; 54.835 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 54.901 ; 54.901 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 52.029 ; 52.029 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 54.949 ; 54.949 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 54.109 ; 54.109 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 52.980 ; 52.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 52.628 ; 52.628 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 53.467 ; 53.467 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 9.853  ; 9.853  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 9.853  ; 9.853  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 9.514  ; 9.514  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 9.190  ; 9.190  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 37.118 ; 37.118 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 39.940 ; 39.940 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 44.764 ; 44.764 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 43.970 ; 43.970 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 42.934 ; 42.934 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 41.832 ; 41.832 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 42.169 ; 42.169 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 43.313 ; 43.313 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 42.958 ; 42.958 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 42.619 ; 42.619 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 41.800 ; 41.800 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 42.041 ; 42.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 41.683 ; 41.683 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 42.383 ; 42.383 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 36.376 ; 36.376 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 44.444 ; 44.444 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 41.800 ; 41.800 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 42.447 ; 42.447 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 41.992 ; 41.992 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 43.550 ; 43.550 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 43.078 ; 43.078 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 43.448 ; 43.448 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 43.656 ; 43.656 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 44.444 ; 44.444 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 43.227 ; 43.227 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 43.056 ; 43.056 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 42.457 ; 42.457 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 41.396 ; 41.396 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 41.271 ; 41.271 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 41.512 ; 41.512 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 41.512 ; 41.512 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 57.112 ; 57.112 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 54.244 ; 54.244 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 55.824 ; 55.824 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 54.092 ; 54.092 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 55.378 ; 55.378 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 54.942 ; 54.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 56.824 ; 56.824 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 56.567 ; 56.567 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 55.709 ; 55.709 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 57.112 ; 57.112 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 54.912 ; 54.912 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 55.803 ; 55.803 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 55.919 ; 55.919 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 54.612 ; 54.612 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 54.766 ; 54.766 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 54.755 ; 54.755 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 55.071 ; 55.071 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 41.611 ; 41.611 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 41.326 ; 41.326 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 42.404 ; 42.404 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 41.338 ; 41.338 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 41.040 ; 41.040 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 42.894 ; 42.894 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 43.920 ; 43.920 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 8.245  ; 8.245  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 34.281 ; 34.281 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 13.331 ; 13.331 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 13.340 ; 13.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 11.879 ; 11.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 9.608  ; 9.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 8.630  ; 8.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 12.211 ; 12.211 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 22.863 ; 22.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 18.776 ; 18.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 19.192 ; 19.192 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 18.281 ; 18.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 22.219 ; 22.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 22.223 ; 22.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 22.863 ; 22.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 22.809 ; 22.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 18.565 ; 18.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 8.079  ; 8.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 8.099  ; 8.099  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 7.315  ; 7.315  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 8.430  ; 8.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 8.430  ; 8.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 7.766  ; 7.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 8.408  ; 8.408  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 7.694  ; 7.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 14.403 ; 14.403 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 7.735  ; 7.735  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 7.735  ; 7.735  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 7.421  ; 7.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 7.390  ; 7.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 7.398  ; 7.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 22.697 ; 22.697 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 21.205 ; 21.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 22.325 ; 22.325 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 21.120 ; 21.120 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 20.473 ; 20.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 20.755 ; 20.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 22.415 ; 22.415 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 22.152 ; 22.152 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 22.697 ; 22.697 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 19.681 ; 19.681 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 20.634 ; 20.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 17.881 ; 17.881 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 21.084 ; 21.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 20.514 ; 20.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 19.004 ; 19.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 17.675 ; 17.675 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 18.343 ; 18.343 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 7.351  ; 7.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 11.610 ; 11.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 4.880  ; 4.880  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 5.172  ; 5.172  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 6.162  ; 6.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 15.227 ; 15.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 13.439 ; 13.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 13.014 ; 13.014 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 13.199 ; 13.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 13.841 ; 13.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 13.345 ; 13.345 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 13.993 ; 13.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 13.818 ; 13.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 15.227 ; 15.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 14.995 ; 14.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 14.162 ; 14.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 13.533 ; 13.533 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 13.180 ; 13.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 13.387 ; 13.387 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 11.761 ; 11.761 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 11.761 ; 11.761 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 11.840 ; 11.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 11.556 ; 11.556 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 26.855 ; 26.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 23.954 ; 23.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 23.252 ; 23.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 23.835 ; 23.835 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 23.914 ; 23.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 24.685 ; 24.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 26.567 ; 26.567 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 26.310 ; 26.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 23.167 ; 23.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 26.855 ; 26.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 23.365 ; 23.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 25.546 ; 25.546 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 25.662 ; 25.662 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 24.355 ; 24.355 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 23.798 ; 23.798 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 23.954 ; 23.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 24.814 ; 24.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 11.198 ; 11.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 10.990 ; 10.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 10.255 ; 10.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 12.461 ; 12.461 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 12.830 ; 12.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 10.786 ; 10.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 9.581  ; 9.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 10.030 ; 10.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 9.884  ; 9.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]      ; CLK_PLL1      ; 10.322 ; 10.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 9.621  ; 9.621  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 10.322 ; 10.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 9.323  ; 9.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 9.324  ; 9.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 9.662  ; 9.662  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 9.889  ; 9.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 9.925  ; 9.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 10.154 ; 10.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP        ; CLK_PLL1      ; 9.592  ; 9.592  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 13.060 ; 13.060 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 9.952  ; 9.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 10.335 ; 10.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 12.658 ; 12.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 11.119 ; 11.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 5.271  ; 5.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 4.936  ; 4.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 5.271  ; 5.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 4.932  ; 4.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 4.573  ; 4.573  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 4.554  ; 4.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 13.331 ; 13.331 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 13.340 ; 13.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 11.879 ; 11.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 9.608  ; 9.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 8.630  ; 8.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 12.211 ; 12.211 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 22.863 ; 22.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 18.776 ; 18.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 19.192 ; 19.192 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 18.281 ; 18.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 22.219 ; 22.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 22.223 ; 22.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 22.863 ; 22.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 22.809 ; 22.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 18.565 ; 18.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 8.079  ; 8.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 8.099  ; 8.099  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 7.315  ; 7.315  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 8.430  ; 8.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 8.430  ; 8.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 7.766  ; 7.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 8.408  ; 8.408  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 7.694  ; 7.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 14.403 ; 14.403 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 7.735  ; 7.735  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 7.735  ; 7.735  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 7.421  ; 7.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 7.390  ; 7.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 7.398  ; 7.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 22.697 ; 22.697 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 21.205 ; 21.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 22.325 ; 22.325 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 21.120 ; 21.120 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 20.473 ; 20.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 20.755 ; 20.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 22.415 ; 22.415 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 22.152 ; 22.152 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 22.697 ; 22.697 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 19.681 ; 19.681 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 20.634 ; 20.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 17.881 ; 17.881 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 21.084 ; 21.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 20.514 ; 20.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 19.004 ; 19.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 17.675 ; 17.675 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 18.343 ; 18.343 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 7.351  ; 7.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 11.610 ; 11.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 4.880  ; 4.880  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 5.172  ; 5.172  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 6.162  ; 6.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 15.227 ; 15.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 13.439 ; 13.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 13.014 ; 13.014 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 13.199 ; 13.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 13.841 ; 13.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 13.345 ; 13.345 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 13.993 ; 13.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 13.818 ; 13.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 15.227 ; 15.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 14.995 ; 14.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 14.162 ; 14.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 13.533 ; 13.533 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 13.180 ; 13.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 13.387 ; 13.387 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 11.761 ; 11.761 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 11.761 ; 11.761 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 11.840 ; 11.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 11.556 ; 11.556 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 26.855 ; 26.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 23.954 ; 23.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 23.252 ; 23.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 23.835 ; 23.835 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 23.914 ; 23.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 24.685 ; 24.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 26.567 ; 26.567 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 26.310 ; 26.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 23.167 ; 23.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 26.855 ; 26.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 23.365 ; 23.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 25.546 ; 25.546 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 25.662 ; 25.662 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 24.355 ; 24.355 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 23.798 ; 23.798 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 23.954 ; 23.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 24.814 ; 24.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 11.198 ; 11.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 10.990 ; 10.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 10.255 ; 10.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 12.461 ; 12.461 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 12.830 ; 12.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 10.786 ; 10.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 9.581  ; 9.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 10.030 ; 10.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 9.884  ; 9.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 10.322 ; 10.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 9.621  ; 9.621  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 10.322 ; 10.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 9.323  ; 9.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 9.324  ; 9.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 9.662  ; 9.662  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 9.889  ; 9.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 9.925  ; 9.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 10.154 ; 10.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 9.592  ; 9.592  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 13.060 ; 13.060 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 9.952  ; 9.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 10.335 ; 10.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 12.658 ; 12.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 11.119 ; 11.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 5.271  ; 5.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 4.936  ; 4.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 5.271  ; 5.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 4.932  ; 4.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 4.573  ; 4.573  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 4.554  ; 4.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 32.101 ; 32.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 29.838 ; 29.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 31.198 ; 31.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 29.501 ; 29.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 29.419 ; 29.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 30.049 ; 30.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 32.101 ; 32.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 31.181 ; 31.181 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 31.955 ; 31.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 30.540 ; 30.540 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 31.444 ; 31.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 28.004 ; 28.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 30.466 ; 30.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 29.233 ; 29.233 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 27.502 ; 27.502 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 27.654 ; 27.654 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 28.004 ; 28.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 10.428 ; 10.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 10.102 ; 10.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 10.115 ; 10.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 10.428 ; 10.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 10.411 ; 10.411 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 33.605 ; 33.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 31.122 ; 31.122 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 32.125 ; 32.125 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 30.251 ; 30.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 31.718 ; 31.718 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 32.298 ; 32.298 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 33.605 ; 33.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 31.917 ; 31.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 32.124 ; 32.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 30.501 ; 30.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 31.455 ; 31.455 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 29.214 ; 29.214 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 29.148 ; 29.148 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 28.899 ; 28.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 29.288 ; 29.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 29.781 ; 29.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 29.518 ; 29.518 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 32.101 ; 32.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 29.838 ; 29.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 31.198 ; 31.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 29.501 ; 29.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 29.419 ; 29.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 30.049 ; 30.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 32.101 ; 32.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 31.181 ; 31.181 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 31.955 ; 31.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 30.540 ; 30.540 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 31.444 ; 31.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 28.004 ; 28.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 30.466 ; 30.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 29.233 ; 29.233 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 27.502 ; 27.502 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 27.654 ; 27.654 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 28.004 ; 28.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 10.428 ; 10.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 10.102 ; 10.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 10.115 ; 10.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 10.428 ; 10.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 10.411 ; 10.411 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 33.605 ; 33.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 31.122 ; 31.122 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 32.125 ; 32.125 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 30.251 ; 30.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 31.718 ; 31.718 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 32.298 ; 32.298 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 33.605 ; 33.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 31.917 ; 31.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 32.124 ; 32.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 30.501 ; 30.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 31.455 ; 31.455 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 29.214 ; 29.214 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 29.148 ; 29.148 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 28.899 ; 28.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 29.288 ; 29.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 29.781 ; 29.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 29.518 ; 29.518 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.821  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.821  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 17.620 ; 17.620 ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 17.585 ; 17.585 ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 16.620 ; 16.620 ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 17.005 ; 17.005 ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 19.062 ; 19.062 ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 18.923 ; 18.923 ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 17.005 ; 17.005 ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 19.197 ; 19.197 ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 17.860 ; 17.860 ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 17.839 ; 17.839 ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 18.211 ; 18.211 ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 17.363 ; 17.363 ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 19.236 ; 19.236 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 21.276 ; 21.276 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 22.704 ; 22.704 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 22.065 ; 22.065 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 21.347 ; 21.347 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 21.054 ; 21.054 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 23.392 ; 23.392 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 23.104 ; 23.104 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 23.670 ; 23.670 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 22.228 ; 22.228 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 23.953 ; 23.953 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 19.236 ; 19.236 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 23.663 ; 23.663 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 21.975 ; 21.975 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 21.295 ; 21.295 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 20.285 ; 20.285 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 21.123 ; 21.123 ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 8.596  ; 8.596  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 20.446 ; 20.446 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 22.560 ; 22.560 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 23.631 ; 23.631 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 22.815 ; 22.815 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 23.646 ; 23.646 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 23.303 ; 23.303 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 24.896 ; 24.896 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 23.840 ; 23.840 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 23.839 ; 23.839 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 22.189 ; 22.189 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 23.964 ; 23.964 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 20.446 ; 20.446 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 22.345 ; 22.345 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 21.641 ; 21.641 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 23.081 ; 23.081 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 22.412 ; 22.412 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 22.637 ; 22.637 ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 13.526 ; 13.526 ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 11.306 ; 11.306 ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 9.613  ; 9.613  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 25.570 ; 25.570 ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 25.570 ; 25.570 ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 25.739 ; 25.739 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 25.739 ; 25.739 ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 15.951 ; 15.951 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 16.520 ; 16.520 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 18.889 ; 18.889 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 17.780 ; 17.780 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 16.605 ; 16.605 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 17.581 ; 17.581 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 18.582 ; 18.582 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 18.957 ; 18.957 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 19.380 ; 19.380 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 18.106 ; 18.106 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 18.820 ; 18.820 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 15.951 ; 15.951 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 19.875 ; 19.875 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 17.665 ; 17.665 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 18.004 ; 18.004 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 16.984 ; 16.984 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 17.416 ; 17.416 ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 17.161 ; 17.161 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 17.804 ; 17.804 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 19.816 ; 19.816 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 18.530 ; 18.530 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 18.904 ; 18.904 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 19.830 ; 19.830 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 20.086 ; 20.086 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 19.693 ; 19.693 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 19.549 ; 19.549 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 18.067 ; 18.067 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 18.831 ; 18.831 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 17.161 ; 17.161 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 18.557 ; 18.557 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 17.331 ; 17.331 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 19.790 ; 19.790 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 19.111 ; 19.111 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 18.930 ; 18.930 ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 21.639 ; 21.639 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 21.639 ; 21.639 ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 7.538  ; 7.538  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 10.756 ; 10.756 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 21.808 ; 21.808 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 11.043 ; 11.043 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.069 ; 12.069 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 11.429 ; 11.429 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 10.756 ; 10.756 ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 7.567  ; 7.567  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 21.639 ; 21.639 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 21.639 ; 21.639 ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 7.538  ; 7.538  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 10.756 ; 10.756 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 21.808 ; 21.808 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 11.043 ; 11.043 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.069 ; 12.069 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 11.429 ; 11.429 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 10.756 ; 10.756 ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 7.567  ; 7.567  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 7.720  ; 7.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 7.729  ; 7.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 6.779  ; 6.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 8.446  ; 8.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 8.846  ; 8.846  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 10.371 ; 10.371 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 8.804  ; 8.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 10.051 ; 10.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 8.498  ; 8.498  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 9.045  ; 9.045  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 7.272  ; 7.272  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 8.191  ; 8.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 9.063  ; 9.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 8.731  ; 8.731  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 7.799  ; 7.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 6.779  ; 6.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 7.404  ; 7.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 7.010  ; 7.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 6.915  ; 6.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 7.128  ; 7.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 6.846  ; 6.846  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 7.321  ; 7.321  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 8.798  ; 8.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 8.835  ; 8.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 9.331  ; 9.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 9.426  ; 9.426  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 8.442  ; 8.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 6.878  ; 6.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 7.366  ; 7.366  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 9.441  ; 9.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 7.875  ; 7.875  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 12.168 ; 12.168 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 7.518  ; 7.518  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 6.804  ; 6.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 6.804  ; 6.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 6.889  ; 6.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 7.118  ; 7.118  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 7.071  ; 7.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 7.129  ; 7.129  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 7.113  ; 7.113  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 7.276  ; 7.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 7.283  ; 7.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 7.739  ; 7.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 8.054  ; 8.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 6.663  ; 6.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 7.236  ; 7.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 5.228  ; 5.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 5.614  ; 5.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 5.107  ; 5.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 6.243  ; 6.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 6.433  ; 6.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 8.162  ; 8.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 8.271  ; 8.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 8.003  ; 8.003  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 7.901  ; 7.901  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 7.736  ; 7.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 8.927  ; 8.927  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 8.289  ; 8.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 9.112  ; 9.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 8.380  ; 8.380  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 8.496  ; 8.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 7.140  ; 7.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 7.691  ; 7.691  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 8.373  ; 8.373  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 6.949  ; 6.949  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 6.433  ; 6.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 7.009  ; 7.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 7.823  ; 7.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 6.591  ; 6.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 7.994  ; 7.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 6.806  ; 6.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 7.175  ; 7.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 7.873  ; 7.873  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 8.532  ; 8.532  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 9.555  ; 8.649  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 7.873  ; 7.873  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 7.544  ; 7.544  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 7.804  ; 7.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 6.860  ; 6.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 7.726  ; 7.726  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 7.409  ; 7.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 8.254  ; 8.254  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 7.385  ; 7.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 7.381  ; 7.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 7.801  ; 7.801  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 8.057  ; 8.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 7.666  ; 7.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 7.259  ; 7.259  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 6.512  ; 6.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 9.345  ; 9.345  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 5.178  ; 5.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 8.083  ; 8.083  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 7.132  ; 7.132  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 7.455  ; 7.455  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 12.381 ; 12.381 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 11.757 ; 11.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 12.159 ; 12.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 13.303 ; 13.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 12.948 ; 12.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 12.609 ; 12.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 11.851 ; 11.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 12.092 ; 12.092 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 11.734 ; 11.734 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 12.434 ; 12.434 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 6.994  ; 6.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 7.078  ; 7.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 7.469  ; 7.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 7.850  ; 7.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 7.612  ; 7.612  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 7.078  ; 7.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 8.558  ; 8.949  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 5.155  ; 5.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 5.742  ; 5.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 6.304  ; 6.304  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 6.304  ; 6.304  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 6.677  ; 6.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.717  ; 6.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 7.731  ; 7.731  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 7.905  ; 7.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 8.311  ; 8.311  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 8.240  ; 8.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 6.559  ; 6.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 7.062  ; 7.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 6.299  ; 6.299  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 5.597  ; 5.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 13.794 ; 13.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 14.654 ; 14.654 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 13.794 ; 13.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 15.190 ; 15.190 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 15.563 ; 15.563 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 15.748 ; 15.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 16.013 ; 16.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 16.118 ; 16.118 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 16.875 ; 16.875 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 15.552 ; 15.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 16.290 ; 16.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 15.095 ; 15.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 14.625 ; 14.625 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 14.474 ; 14.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 15.199 ; 15.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 15.199 ; 15.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 11.707 ; 11.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 12.826 ; 12.826 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 13.748 ; 13.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 12.640 ; 12.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 13.962 ; 13.962 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 14.145 ; 14.145 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 15.083 ; 15.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 14.019 ; 14.019 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 14.166 ; 14.166 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 12.542 ; 12.542 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 12.803 ; 12.803 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 11.707 ; 11.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 11.928 ; 11.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 12.170 ; 12.170 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 13.343 ; 13.343 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 12.456 ; 12.456 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 13.439 ; 13.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 8.693  ; 8.693  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 12.432 ; 12.432 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 9.783  ; 9.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 10.884 ; 10.884 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 11.896 ; 11.896 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 11.598 ; 11.598 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 11.733 ; 11.733 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 13.911 ; 13.911 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 6.584  ; 6.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 6.016  ; 6.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 9.716  ; 9.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 6.572  ; 6.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 6.852  ; 6.852  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 4.828  ; 4.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 5.371  ; 5.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 6.382  ; 6.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 4.828  ; 4.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 4.832  ; 4.832  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 5.690  ; 5.690  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 5.394  ; 5.394  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 5.670  ; 5.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 5.807  ; 5.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 5.645  ; 5.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 6.059  ; 6.059  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 4.759  ; 4.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 6.052  ; 6.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 9.063  ; 9.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 6.229  ; 6.229  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 8.248  ; 8.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 6.535  ; 6.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 8.660  ; 8.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 8.221  ; 8.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 10.864 ; 10.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 7.650  ; 7.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 8.747  ; 8.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 6.917  ; 6.917  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 6.932  ; 6.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 6.932  ; 6.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 7.705  ; 7.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 7.419  ; 7.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 7.727  ; 7.727  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 8.067  ; 7.199  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 5.068  ; 5.068  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 7.179  ; 7.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 7.140  ; 7.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 8.385  ; 8.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 8.923  ; 8.923  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 9.128  ; 9.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 15.211 ; 15.211 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 15.176 ; 15.176 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 7.673  ; 7.673  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 8.238  ; 8.238  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 8.638  ; 8.638  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 10.844 ; 10.844 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 8.596  ; 8.596  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 9.843  ; 9.843  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 8.290  ; 8.290  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 8.837  ; 8.837  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 7.673  ; 7.673  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 8.242  ; 8.242  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 9.178  ; 9.178  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 8.846  ; 8.846  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 9.480  ; 9.480  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 9.581  ; 9.581  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 9.824  ; 9.824  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 9.947  ; 9.947  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 8.479  ; 8.479  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 10.654 ; 10.654 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 8.620  ; 8.620  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 9.336  ; 9.336  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 11.405 ; 11.405 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 8.819  ; 8.819  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 9.482  ; 9.482  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 9.402  ; 9.402  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 8.442  ; 8.442  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 6.887  ; 6.887  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 11.960 ; 11.960 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 14.211 ; 14.211 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 14.596 ; 14.596 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 16.653 ; 16.653 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 16.514 ; 16.514 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 14.596 ; 14.596 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 16.788 ; 16.788 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 15.451 ; 15.451 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 15.430 ; 15.430 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 15.802 ; 15.802 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 14.954 ; 14.954 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 13.160 ; 13.160 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 13.400 ; 13.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 15.014 ; 15.014 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 14.305 ; 14.305 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 14.621 ; 14.621 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 13.160 ; 13.160 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 15.482 ; 15.482 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 14.285 ; 14.285 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 16.544 ; 16.544 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 14.932 ; 14.932 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 16.768 ; 16.768 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 14.091 ; 14.091 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 16.376 ; 16.376 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 14.661 ; 14.661 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 15.326 ; 15.326 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 14.300 ; 14.300 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 14.771 ; 14.771 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 7.539  ; 7.539  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 8.202  ; 8.202  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 7.863  ; 7.863  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 7.539  ; 7.539  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 9.385  ; 9.385  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 9.435  ; 9.435  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 13.036 ; 13.036 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 12.242 ; 12.242 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 12.173 ; 12.173 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 11.549 ; 11.549 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 11.951 ; 11.951 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 13.095 ; 13.095 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 12.740 ; 12.740 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 12.401 ; 12.401 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 11.643 ; 11.643 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 11.884 ; 11.884 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 11.526 ; 11.526 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 12.226 ; 12.226 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 8.684  ; 8.558  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 13.586 ; 13.586 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 14.446 ; 14.446 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 13.586 ; 13.586 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 14.982 ; 14.982 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 16.018 ; 16.018 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 15.540 ; 15.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 15.805 ; 15.805 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 15.910 ; 15.910 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 16.667 ; 16.667 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 15.344 ; 15.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 16.082 ; 16.082 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 15.315 ; 15.315 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 14.417 ; 14.417 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 14.266 ; 14.266 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 14.991 ; 14.991 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 14.991 ; 14.991 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 14.327 ; 14.327 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 14.684 ; 14.684 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 15.941 ; 15.941 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 15.055 ; 15.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 16.920 ; 16.920 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 15.409 ; 15.409 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 16.986 ; 16.986 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 15.021 ; 15.021 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 16.075 ; 16.075 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 14.893 ; 14.893 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 14.738 ; 14.738 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 15.184 ; 15.184 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 15.058 ; 15.058 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 14.327 ; 14.327 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 16.071 ; 16.071 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 15.196 ; 15.196 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 14.791 ; 14.791 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 12.762 ; 12.762 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 9.575  ; 9.575  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 10.676 ; 10.676 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 11.688 ; 11.688 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 11.390 ; 11.390 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 11.525 ; 11.525 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 13.974 ; 13.974 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 7.380  ; 7.380  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 7.199  ; 7.325  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 7.720  ; 7.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 7.729  ; 7.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 6.779  ; 6.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 8.446  ; 8.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 8.846  ; 8.846  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 10.371 ; 10.371 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 8.804  ; 8.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 10.051 ; 10.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 8.498  ; 8.498  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 9.045  ; 9.045  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 7.272  ; 7.272  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 8.191  ; 8.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 9.063  ; 9.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 8.731  ; 8.731  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 7.799  ; 7.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 6.779  ; 6.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 7.404  ; 7.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 7.010  ; 7.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 6.915  ; 6.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 7.128  ; 7.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 6.846  ; 6.846  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 7.321  ; 7.321  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 8.798  ; 8.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 8.835  ; 8.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 9.331  ; 9.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 9.426  ; 9.426  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 8.442  ; 8.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 6.878  ; 6.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 7.366  ; 7.366  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 9.441  ; 9.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 7.875  ; 7.875  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 12.168 ; 12.168 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 7.518  ; 7.518  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 6.804  ; 6.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 6.804  ; 6.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 6.889  ; 6.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 7.118  ; 7.118  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 7.071  ; 7.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 7.129  ; 7.129  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 7.113  ; 7.113  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 7.276  ; 7.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 7.283  ; 7.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 7.739  ; 7.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 8.054  ; 8.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 6.663  ; 6.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 7.236  ; 7.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 5.228  ; 5.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 5.614  ; 5.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 5.107  ; 5.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 6.243  ; 6.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 6.433  ; 6.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 8.162  ; 8.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 8.271  ; 8.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 8.003  ; 8.003  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 7.901  ; 7.901  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 7.736  ; 7.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 8.927  ; 8.927  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 8.289  ; 8.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 9.112  ; 9.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 8.380  ; 8.380  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 8.496  ; 8.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 7.140  ; 7.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 7.691  ; 7.691  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 8.373  ; 8.373  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.949  ; 6.949  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 6.433  ; 6.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 7.009  ; 7.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 7.823  ; 7.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 6.591  ; 6.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 7.994  ; 7.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 6.806  ; 6.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 7.175  ; 7.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 7.873  ; 7.873  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 8.532  ; 8.532  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 9.555  ; 8.649  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 7.873  ; 7.873  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 7.544  ; 7.544  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 7.804  ; 7.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 6.860  ; 6.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 7.726  ; 7.726  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 7.409  ; 7.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 8.254  ; 8.254  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 7.385  ; 7.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 7.381  ; 7.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 7.801  ; 7.801  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 8.057  ; 8.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 7.666  ; 7.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 7.259  ; 7.259  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 6.512  ; 6.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 9.345  ; 9.345  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 5.178  ; 5.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 8.083  ; 8.083  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 7.132  ; 7.132  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 7.455  ; 7.455  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 12.381 ; 12.381 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 11.757 ; 11.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 12.159 ; 12.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 13.303 ; 13.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 12.948 ; 12.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 12.609 ; 12.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 11.851 ; 11.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 12.092 ; 12.092 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 11.734 ; 11.734 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 12.434 ; 12.434 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 6.994  ; 6.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 7.078  ; 7.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 7.469  ; 7.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 7.850  ; 7.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 7.612  ; 7.612  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 7.078  ; 7.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 8.558  ; 8.949  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 5.155  ; 5.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 5.742  ; 5.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 6.304  ; 6.304  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 6.304  ; 6.304  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 6.677  ; 6.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.717  ; 6.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 7.731  ; 7.731  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 7.905  ; 7.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 8.311  ; 8.311  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 8.240  ; 8.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 6.559  ; 6.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 7.062  ; 7.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 6.299  ; 6.299  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 5.597  ; 5.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 13.794 ; 13.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 14.654 ; 14.654 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 13.794 ; 13.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 15.190 ; 15.190 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 15.563 ; 15.563 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 15.748 ; 15.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 16.013 ; 16.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 16.118 ; 16.118 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 16.875 ; 16.875 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 15.552 ; 15.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 16.290 ; 16.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 15.095 ; 15.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 14.625 ; 14.625 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 14.474 ; 14.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 15.199 ; 15.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 15.199 ; 15.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 11.707 ; 11.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 12.826 ; 12.826 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 13.748 ; 13.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 12.640 ; 12.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 13.962 ; 13.962 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 14.145 ; 14.145 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 15.083 ; 15.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 14.019 ; 14.019 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 14.166 ; 14.166 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 12.542 ; 12.542 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 12.803 ; 12.803 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 11.707 ; 11.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 11.928 ; 11.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 12.170 ; 12.170 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 13.343 ; 13.343 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.456 ; 12.456 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 13.439 ; 13.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 8.693  ; 8.693  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 12.432 ; 12.432 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 9.783  ; 9.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 10.884 ; 10.884 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 11.896 ; 11.896 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 11.598 ; 11.598 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 11.733 ; 11.733 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 13.911 ; 13.911 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 6.584  ; 6.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 6.016  ; 6.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 9.716  ; 9.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 6.572  ; 6.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 6.852  ; 6.852  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 4.828  ; 4.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 5.371  ; 5.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 6.382  ; 6.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 4.828  ; 4.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 4.832  ; 4.832  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 5.690  ; 5.690  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 5.394  ; 5.394  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 5.670  ; 5.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 5.807  ; 5.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 5.645  ; 5.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 6.059  ; 6.059  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 4.759  ; 4.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 6.052  ; 6.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 9.063  ; 9.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 6.229  ; 6.229  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 8.248  ; 8.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 6.535  ; 6.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 8.660  ; 8.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 8.221  ; 8.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 10.864 ; 10.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 7.650  ; 7.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 8.747  ; 8.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 6.917  ; 6.917  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 6.932  ; 6.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 6.932  ; 6.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 7.705  ; 7.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 7.419  ; 7.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 7.727  ; 7.727  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 8.067  ; 7.199  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 5.068  ; 5.068  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 7.179  ; 7.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 7.140  ; 7.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 8.385  ; 8.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 8.923  ; 8.923  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 9.128  ; 9.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 15.211 ; 15.211 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 15.176 ; 15.176 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 7.673  ; 7.673  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 8.238  ; 8.238  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 8.638  ; 8.638  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 10.844 ; 10.844 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 8.596  ; 8.596  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 9.843  ; 9.843  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 8.290  ; 8.290  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 8.837  ; 8.837  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 7.673  ; 7.673  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 8.242  ; 8.242  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 9.178  ; 9.178  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 8.846  ; 8.846  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 9.480  ; 9.480  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 9.581  ; 9.581  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 9.824  ; 9.824  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 9.947  ; 9.947  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 8.479  ; 8.479  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 10.654 ; 10.654 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 8.620  ; 8.620  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 9.336  ; 9.336  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 11.405 ; 11.405 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 8.819  ; 8.819  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 9.482  ; 9.482  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 9.402  ; 9.402  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 8.442  ; 8.442  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 6.887  ; 6.887  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 11.960 ; 11.960 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 14.211 ; 14.211 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 14.596 ; 14.596 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 16.653 ; 16.653 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 16.514 ; 16.514 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 14.596 ; 14.596 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 16.788 ; 16.788 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 15.451 ; 15.451 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 15.430 ; 15.430 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 15.802 ; 15.802 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 14.954 ; 14.954 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 13.160 ; 13.160 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 13.400 ; 13.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 15.014 ; 15.014 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 14.305 ; 14.305 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 14.621 ; 14.621 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 13.160 ; 13.160 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 15.482 ; 15.482 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 14.285 ; 14.285 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 16.544 ; 16.544 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 14.932 ; 14.932 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 16.768 ; 16.768 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 14.091 ; 14.091 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 16.376 ; 16.376 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 14.661 ; 14.661 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 15.326 ; 15.326 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 14.300 ; 14.300 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 14.771 ; 14.771 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 7.539  ; 7.539  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 8.202  ; 8.202  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 7.863  ; 7.863  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 7.539  ; 7.539  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 9.385  ; 9.385  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 9.435  ; 9.435  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 13.036 ; 13.036 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 12.242 ; 12.242 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 12.173 ; 12.173 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 11.549 ; 11.549 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 11.951 ; 11.951 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 13.095 ; 13.095 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 12.740 ; 12.740 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 12.401 ; 12.401 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 11.643 ; 11.643 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 11.884 ; 11.884 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 11.526 ; 11.526 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 12.226 ; 12.226 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 8.684  ; 8.558  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 13.586 ; 13.586 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 14.446 ; 14.446 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 13.586 ; 13.586 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 14.982 ; 14.982 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 16.018 ; 16.018 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 15.540 ; 15.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 15.805 ; 15.805 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 15.910 ; 15.910 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 16.667 ; 16.667 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 15.344 ; 15.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 16.082 ; 16.082 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 15.315 ; 15.315 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 14.417 ; 14.417 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 14.266 ; 14.266 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 14.991 ; 14.991 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 14.991 ; 14.991 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 14.327 ; 14.327 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 14.684 ; 14.684 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 15.941 ; 15.941 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 15.055 ; 15.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 16.920 ; 16.920 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 15.409 ; 15.409 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 16.986 ; 16.986 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 15.021 ; 15.021 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 16.075 ; 16.075 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 14.893 ; 14.893 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 14.738 ; 14.738 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 15.184 ; 15.184 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 15.058 ; 15.058 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 14.327 ; 14.327 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 16.071 ; 16.071 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 15.196 ; 15.196 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 14.791 ; 14.791 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 12.762 ; 12.762 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 9.575  ; 9.575  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 10.676 ; 10.676 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 11.688 ; 11.688 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 11.390 ; 11.390 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 11.525 ; 11.525 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 13.974 ; 13.974 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 7.380  ; 7.380  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 7.199  ; 7.325  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 11.671 ; 11.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 11.636 ; 11.636 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 11.373 ; 11.373 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 9.608  ; 9.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 8.630  ; 8.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 10.671 ; 10.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 10.549 ; 10.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 10.696 ; 10.696 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 10.549 ; 10.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 11.056 ; 11.056 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 11.315 ; 11.315 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 11.911 ; 11.911 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 11.890 ; 11.890 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 12.262 ; 12.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 11.414 ; 11.414 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 5.618  ; 5.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 6.508  ; 6.508  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 6.388  ; 6.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 6.751  ; 6.751  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 5.618  ; 5.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 5.946  ; 5.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 6.692  ; 6.692  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 6.069  ; 6.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 6.657  ; 6.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 5.946  ; 5.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 6.845  ; 6.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 5.702  ; 5.702  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 6.887  ; 6.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 6.106  ; 6.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 5.702  ; 5.702  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 5.726  ; 5.726  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 11.712 ; 11.712 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 13.412 ; 13.412 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 14.107 ; 14.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 12.587 ; 12.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 12.550 ; 12.550 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 11.712 ; 11.712 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 13.989 ; 13.989 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 13.951 ; 13.951 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 14.702 ; 14.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 15.996 ; 15.996 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 17.784 ; 17.784 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 13.287 ; 13.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 16.758 ; 16.758 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 14.434 ; 14.434 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 14.497 ; 14.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 13.821 ; 13.821 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 15.174 ; 15.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 5.018  ; 5.018  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 10.264 ; 10.264 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 4.880  ; 4.880  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 5.172  ; 5.172  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 4.876  ; 4.876  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 8.500  ; 8.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 9.789  ; 9.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 9.672  ; 9.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 9.644  ; 9.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 10.435 ; 10.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 10.143 ; 10.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 8.812  ; 8.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 10.153 ; 10.153 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 11.597 ; 11.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 11.066 ; 11.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 10.037 ; 10.037 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 10.189 ; 10.189 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 9.095  ; 9.095  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 8.500  ; 8.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 9.485  ; 9.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 9.485  ; 9.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 9.090  ; 9.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 8.803  ; 8.803  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 7.615  ; 7.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 8.657  ; 8.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 10.009 ; 10.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 9.699  ; 9.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 11.041 ; 11.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 7.615  ; 7.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 10.451 ; 10.451 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 9.670  ; 9.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 7.988  ; 7.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 8.980  ; 8.980  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 8.500  ; 8.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 8.245  ; 8.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 8.714  ; 8.714  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 8.881  ; 8.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 9.349  ; 9.349  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 8.543  ; 8.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 8.271  ; 8.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 8.615  ; 8.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 8.474  ; 8.474  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 7.674  ; 7.674  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 8.749  ; 8.749  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 9.587  ; 9.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 9.246  ; 9.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 9.581  ; 9.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 8.861  ; 8.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 9.681  ; 9.681  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]      ; CLK_PLL1      ; 9.181  ; 9.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 9.479  ; 9.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 10.180 ; 10.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 9.181  ; 9.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 9.182  ; 9.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 9.520  ; 9.520  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 9.747  ; 9.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 9.783  ; 9.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 10.012 ; 10.012 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP        ; CLK_PLL1      ; 9.450  ; 9.450  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 12.891 ; 12.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 9.721  ; 9.721  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 10.123 ; 10.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 12.489 ; 12.489 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 9.773  ; 9.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 2.964  ; 4.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 4.936  ; 4.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 5.271  ; 5.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 4.932  ; 4.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 4.573  ; 4.573  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 4.554  ; 4.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 11.671 ; 11.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 11.636 ; 11.636 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 11.373 ; 11.373 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 9.608  ; 9.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 8.630  ; 8.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 10.671 ; 10.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 10.549 ; 10.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 10.696 ; 10.696 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 10.549 ; 10.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 11.056 ; 11.056 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 11.315 ; 11.315 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 11.911 ; 11.911 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 11.890 ; 11.890 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 12.262 ; 12.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 11.414 ; 11.414 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 5.618  ; 5.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 6.508  ; 6.508  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 6.388  ; 6.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 6.751  ; 6.751  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 5.618  ; 5.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 5.946  ; 5.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 6.692  ; 6.692  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 6.069  ; 6.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 6.657  ; 6.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 5.946  ; 5.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 6.845  ; 6.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 5.702  ; 5.702  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 6.887  ; 6.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 6.106  ; 6.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 5.702  ; 5.702  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 5.726  ; 5.726  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 11.712 ; 11.712 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 13.412 ; 13.412 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 14.107 ; 14.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 12.587 ; 12.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 12.550 ; 12.550 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 11.712 ; 11.712 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 13.989 ; 13.989 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 13.951 ; 13.951 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 14.702 ; 14.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 15.996 ; 15.996 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 17.784 ; 17.784 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 13.287 ; 13.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 16.758 ; 16.758 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 14.434 ; 14.434 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 14.497 ; 14.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 13.821 ; 13.821 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 15.174 ; 15.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 5.018  ; 5.018  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 10.264 ; 10.264 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 4.880  ; 4.880  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 5.172  ; 5.172  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 4.876  ; 4.876  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 8.500  ; 8.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 9.789  ; 9.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 9.672  ; 9.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 9.644  ; 9.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 10.435 ; 10.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 10.143 ; 10.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 8.812  ; 8.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 10.153 ; 10.153 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 11.597 ; 11.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 11.066 ; 11.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 10.037 ; 10.037 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 10.189 ; 10.189 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 9.095  ; 9.095  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 8.500  ; 8.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 9.485  ; 9.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 9.485  ; 9.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 9.090  ; 9.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 8.803  ; 8.803  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 7.615  ; 7.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 8.657  ; 8.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 10.009 ; 10.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 9.699  ; 9.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 11.041 ; 11.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 7.615  ; 7.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 10.451 ; 10.451 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 9.670  ; 9.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 7.988  ; 7.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 8.980  ; 8.980  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 8.500  ; 8.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 8.245  ; 8.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 8.714  ; 8.714  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 8.881  ; 8.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 9.349  ; 9.349  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 8.543  ; 8.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 8.271  ; 8.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 8.615  ; 8.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 8.474  ; 8.474  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 7.674  ; 7.674  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 8.749  ; 8.749  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 9.587  ; 9.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 9.246  ; 9.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 9.581  ; 9.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 8.861  ; 8.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 9.681  ; 9.681  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 9.181  ; 9.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 9.479  ; 9.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 10.180 ; 10.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 9.181  ; 9.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 9.182  ; 9.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 9.520  ; 9.520  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 9.747  ; 9.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 9.783  ; 9.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 10.012 ; 10.012 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 9.450  ; 9.450  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 12.891 ; 12.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 9.721  ; 9.721  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 10.123 ; 10.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 12.489 ; 12.489 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 9.773  ; 9.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 2.964  ; 4.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 4.936  ; 4.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 5.271  ; 5.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 4.932  ; 4.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 4.573  ; 4.573  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 4.554  ; 4.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 13.522 ; 13.522 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 14.998 ; 14.998 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 16.255 ; 16.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 15.712 ; 15.712 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 14.335 ; 14.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 14.666 ; 14.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 16.646 ; 16.646 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 17.214 ; 17.214 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 17.394 ; 17.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 15.808 ; 15.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 17.821 ; 17.821 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 13.522 ; 13.522 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 16.832 ; 16.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 14.912 ; 14.912 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 13.749 ; 13.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 13.819 ; 13.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 14.037 ; 14.037 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 5.967  ; 5.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 5.967  ; 5.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 6.392  ; 6.392  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 6.874  ; 6.874  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 6.857  ; 6.857  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 14.578 ; 14.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 16.282 ; 16.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 17.182 ; 17.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 16.462 ; 16.462 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 16.634 ; 16.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 16.915 ; 16.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 18.150 ; 18.150 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 17.950 ; 17.950 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 17.563 ; 17.563 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 15.769 ; 15.769 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 17.832 ; 17.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 14.732 ; 14.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 15.514 ; 15.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 14.578 ; 14.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 15.535 ; 15.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 15.946 ; 15.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 15.551 ; 15.551 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 13.522 ; 13.522 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 14.998 ; 14.998 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 16.255 ; 16.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 15.712 ; 15.712 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 14.335 ; 14.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 14.666 ; 14.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 16.646 ; 16.646 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 17.214 ; 17.214 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.394 ; 17.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 15.808 ; 15.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 17.821 ; 17.821 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 13.522 ; 13.522 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 16.832 ; 16.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 14.912 ; 14.912 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 13.749 ; 13.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 13.819 ; 13.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 14.037 ; 14.037 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 5.967  ; 5.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 5.967  ; 5.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 6.392  ; 6.392  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 6.874  ; 6.874  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 6.857  ; 6.857  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 14.578 ; 14.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 16.282 ; 16.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 17.182 ; 17.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 16.462 ; 16.462 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 16.634 ; 16.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 16.915 ; 16.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 18.150 ; 18.150 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 17.950 ; 17.950 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 17.563 ; 17.563 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 15.769 ; 15.769 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 17.832 ; 17.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 14.732 ; 14.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 15.514 ; 15.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 14.578 ; 14.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 15.535 ; 15.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 15.946 ; 15.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 15.551 ; 15.551 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.821  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.821  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------+
; Propagation Delay                                                ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 23.083 ; 23.083 ; 23.083 ; 23.083 ;
; ASn          ; ACSI_WRn      ; 23.092 ; 23.092 ; 23.092 ; 23.092 ;
; ASn          ; BUTTONn       ; 20.989 ;        ;        ; 20.989 ;
; ASn          ; CA1_OUT       ; 21.963 ;        ;        ; 21.963 ;
; ASn          ; CD[0]         ; 28.528 ; 28.528 ; 28.528 ; 28.528 ;
; ASn          ; CD[1]         ; 28.944 ; 28.944 ; 28.944 ; 28.944 ;
; ASn          ; CD[2]         ; 28.033 ; 28.033 ; 28.033 ; 28.033 ;
; ASn          ; CD[3]         ; 31.971 ; 31.971 ; 31.971 ; 31.971 ;
; ASn          ; CD[4]         ; 31.975 ; 31.975 ; 31.975 ; 31.975 ;
; ASn          ; CD[5]         ; 32.615 ; 32.615 ; 32.615 ; 32.615 ;
; ASn          ; CD[6]         ; 32.561 ; 32.561 ; 32.561 ; 32.561 ;
; ASn          ; CD[7]         ; 28.317 ; 28.317 ; 28.317 ; 28.317 ;
; ASn          ; DATA[0]       ; 29.974 ; 30.430 ; 30.430 ; 29.974 ;
; ASn          ; DATA[1]       ; 32.262 ; 32.063 ; 32.063 ; 32.262 ;
; ASn          ; DATA[2]       ; 30.185 ; 30.998 ; 30.998 ; 30.185 ;
; ASn          ; DATA[3]       ; 29.658 ; 29.601 ; 29.601 ; 29.658 ;
; ASn          ; DATA[4]       ; 29.681 ; 30.134 ; 30.134 ; 29.681 ;
; ASn          ; DATA[5]       ; 31.401 ; 31.670 ; 31.670 ; 31.401 ;
; ASn          ; DATA[6]       ; 31.775 ; 31.809 ; 31.809 ; 31.775 ;
; ASn          ; DATA[7]       ; 31.875 ; 32.468 ; 32.468 ; 31.875 ;
; ASn          ; DATA[8]       ; 32.345 ; 32.345 ; 32.345 ; 32.345 ;
; ASn          ; DATA[9]       ; 32.988 ; 32.988 ; 32.988 ; 32.988 ;
; ASn          ; DATA[10]      ; 30.316 ; 30.316 ; 30.316 ; 30.316 ;
; ASn          ; DATA[11]      ; 32.749 ; 32.847 ; 32.847 ; 32.749 ;
; ASn          ; DATA[12]      ; 32.920 ; 32.920 ; 32.920 ; 32.920 ;
; ASn          ; DATA[13]      ; 30.778 ; 30.656 ; 30.656 ; 30.778 ;
; ASn          ; DATA[14]      ; 29.905 ; 29.905 ; 29.905 ; 29.905 ;
; ASn          ; DATA[15]      ; 30.940 ; 30.803 ; 30.803 ; 30.940 ;
; ASn          ; DTACKn        ; 24.836 ; 24.836 ; 24.836 ; 24.836 ;
; ASn          ; FLASH_CEn     ; 20.413 ;        ;        ; 20.413 ;
; ASn          ; FLASH_OEn     ; 19.619 ;        ;        ; 19.619 ;
; ASn          ; IDE_CS0n      ; 13.851 ;        ;        ; 13.851 ;
; ASn          ; IDE_CS1n      ; 12.631 ;        ;        ; 12.631 ;
; ASn          ; IDE_D_EN_INn  ; 14.492 ;        ;        ; 14.492 ;
; ASn          ; IDE_D_EN_OUTn ; 16.088 ;        ;        ; 16.088 ;
; ASn          ; IDE_IORDn     ; 15.733 ;        ;        ; 15.733 ;
; ASn          ; IDE_IOWRn     ; 15.394 ;        ;        ; 15.394 ;
; ASn          ; JOY_RHn       ; 14.716 ;        ;        ; 14.716 ;
; ASn          ; JOY_RLn       ; 14.957 ;        ;        ; 14.957 ;
; ASn          ; JOY_WEn       ;        ; 14.599 ; 14.599 ;        ;
; ASn          ; JOY_WL        ;        ; 14.871 ; 14.871 ;        ;
; ASn          ; RAM_DATA[0]   ; 31.258 ; 31.714 ; 31.714 ; 31.258 ;
; ASn          ; RAM_DATA[1]   ; 33.189 ; 32.990 ; 32.990 ; 33.189 ;
; ASn          ; RAM_DATA[2]   ; 30.935 ; 31.748 ; 31.748 ; 30.935 ;
; ASn          ; RAM_DATA[3]   ; 31.957 ; 31.900 ; 31.900 ; 31.957 ;
; ASn          ; RAM_DATA[4]   ; 31.930 ; 32.383 ; 32.383 ; 31.930 ;
; ASn          ; RAM_DATA[5]   ; 32.905 ; 33.174 ; 33.174 ; 32.905 ;
; ASn          ; RAM_DATA[6]   ; 32.511 ; 32.545 ; 32.545 ; 32.511 ;
; ASn          ; RAM_DATA[7]   ; 32.044 ; 32.637 ; 32.637 ; 32.044 ;
; ASn          ; RAM_DATA[8]   ; 32.306 ; 32.306 ; 32.306 ; 32.306 ;
; ASn          ; RAM_DATA[9]   ; 32.999 ; 32.999 ; 32.999 ; 32.999 ;
; ASn          ; RAM_DATA[10]  ; 31.526 ; 31.526 ; 31.526 ; 31.526 ;
; ASn          ; RAM_DATA[11]  ; 31.431 ; 31.529 ; 31.529 ; 31.431 ;
; ASn          ; RAM_DATA[12]  ; 32.586 ; 32.586 ; 32.586 ; 32.586 ;
; ASn          ; RAM_DATA[13]  ; 32.564 ; 32.442 ; 32.442 ; 32.564 ;
; ASn          ; RAM_DATA[14]  ; 32.032 ; 32.032 ; 32.032 ; 32.032 ;
; ASn          ; RAM_DATA[15]  ; 32.454 ; 32.317 ; 32.317 ; 32.454 ;
; ASn          ; ROM0n         ; 16.366 ;        ;        ; 16.366 ;
; ASn          ; ROM1n         ; 16.094 ;        ;        ; 16.094 ;
; ASn          ; ROM2n         ; 18.053 ;        ;        ; 18.053 ;
; ASn          ; ROM3n         ; 15.611 ;        ;        ; 15.611 ;
; ASn          ; ROM4n         ; 15.766 ;        ;        ; 15.766 ;
; ASn          ; ROM5n         ; 18.044 ;        ;        ; 18.044 ;
; ASn          ; ROM6n         ; 17.579 ;        ;        ; 17.579 ;
; COM_CTS      ; DATA[2]       ;        ; 24.709 ; 24.709 ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 25.459 ; 25.459 ;        ;
; COM_DCD      ; DATA[1]       ;        ; 26.470 ; 26.470 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 27.397 ; 27.397 ;        ;
; COM_RI       ; DATA[6]       ;        ; 24.094 ; 24.094 ;        ;
; COM_RI       ; RAM_DATA[6]   ;        ; 24.830 ; 24.830 ;        ;
; CONFIG[1]    ; DATA[7]       ; 26.655 ; 26.655 ; 26.655 ; 26.655 ;
; CONFIG[1]    ; HSYNC         ; 12.714 ; 12.714 ; 12.714 ; 12.714 ;
; CONFIG[1]    ; RAM_DATA[7]   ; 26.824 ; 26.824 ; 26.824 ; 26.824 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 15.729 ; 15.375 ; 15.375 ; 15.729 ;
; CONFIG[1]    ; RAM_DATA[13]  ; 16.401 ; 16.642 ; 16.642 ; 16.401 ;
; CONFIG[1]    ; RAM_DATA[14]  ; 15.994 ; 15.761 ; 15.761 ; 15.994 ;
; CONFIG[1]    ; RAM_DATA[15]  ; 15.088 ; 15.362 ; 15.362 ; 15.088 ;
; CONFIG[1]    ; VSYNC         ; 12.351 ; 12.351 ; 12.351 ; 12.351 ;
; CONFIG[2]    ; DATA[7]       ; 26.519 ; 26.519 ; 26.519 ; 26.519 ;
; CONFIG[2]    ; HSYNC         ; 12.442 ; 12.442 ; 12.442 ; 12.442 ;
; CONFIG[2]    ; RAM_DATA[7]   ; 26.688 ; 26.688 ; 26.688 ; 26.688 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 14.767 ; 15.121 ; 15.121 ; 14.767 ;
; CONFIG[2]    ; RAM_DATA[13]  ; 16.034 ; 15.793 ; 15.793 ; 16.034 ;
; CONFIG[2]    ; RAM_DATA[14]  ; 15.153 ; 15.386 ; 15.386 ; 15.153 ;
; CONFIG[2]    ; RAM_DATA[15]  ; 14.754 ; 14.480 ; 14.480 ; 14.754 ;
; CONFIG[2]    ; VSYNC         ; 12.094 ; 12.094 ; 12.094 ; 12.094 ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 17.486 ; 17.486 ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 14.935 ; 14.935 ;        ;
; CONFIG[6]    ; DATA[0]       ; 21.623 ; 21.623 ; 21.623 ; 21.623 ;
; CONFIG[6]    ; DATA[1]       ; 22.767 ; 22.767 ; 22.767 ; 22.767 ;
; CONFIG[6]    ; DATA[2]       ; 22.271 ; 22.271 ; 22.271 ; 22.271 ;
; CONFIG[6]    ; DATA[3]       ; 23.180 ; 22.831 ; 22.831 ; 23.180 ;
; CONFIG[6]    ; DATA[4]       ; 23.211 ; 23.560 ; 23.560 ; 23.211 ;
; CONFIG[6]    ; DATA[5]       ; 25.278 ; 25.627 ; 25.627 ; 25.278 ;
; CONFIG[6]    ; DATA[6]       ; 25.410 ; 25.759 ; 25.759 ; 25.410 ;
; CONFIG[6]    ; DATA[7]       ; 26.120 ; 26.469 ; 26.469 ; 26.120 ;
; CONFIG[6]    ; DATA[8]       ; 24.753 ; 24.404 ; 24.404 ; 24.753 ;
; CONFIG[6]    ; DATA[9]       ; 25.935 ; 25.923 ; 25.923 ; 25.935 ;
; CONFIG[6]    ; DATA[10]      ; 23.316 ; 23.665 ; 23.665 ; 23.316 ;
; CONFIG[6]    ; DATA[11]      ; 25.711 ; 25.885 ; 25.885 ; 25.711 ;
; CONFIG[6]    ; DATA[12]      ; 24.623 ; 24.972 ; 24.972 ; 24.623 ;
; CONFIG[6]    ; DATA[13]      ; 23.798 ; 24.147 ; 24.147 ; 23.798 ;
; CONFIG[6]    ; DATA[14]      ; 22.454 ; 22.480 ; 22.480 ; 22.454 ;
; CONFIG[6]    ; DATA[15]      ; 23.326 ; 23.675 ; 23.675 ; 23.326 ;
; CONFIG[6]    ; DTACKn        ; 19.020 ; 19.020 ; 19.020 ; 19.020 ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 16.100 ; 16.100 ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 16.489 ; 16.489 ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 18.429 ; 18.080 ; 18.080 ; 18.429 ;
; CONFIG[6]    ; FLASH_OEn     ; 17.635 ; 17.286 ; 17.286 ; 17.635 ;
; CONFIG[6]    ; RAM_DATA[0]   ; 22.907 ; 22.907 ; 22.907 ; 22.907 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 23.694 ; 23.694 ; 23.694 ; 23.694 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 23.021 ; 23.021 ; 23.021 ; 23.021 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 25.479 ; 25.130 ; 25.130 ; 25.479 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 25.460 ; 25.809 ; 25.809 ; 25.460 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 26.782 ; 27.131 ; 27.131 ; 26.782 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 26.146 ; 26.495 ; 26.495 ; 26.146 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 26.289 ; 26.638 ; 26.638 ; 26.289 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 24.714 ; 24.365 ; 24.365 ; 24.714 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 25.946 ; 25.934 ; 25.934 ; 25.946 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 24.526 ; 24.875 ; 24.875 ; 24.526 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 24.393 ; 24.567 ; 24.567 ; 24.393 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 24.289 ; 24.638 ; 24.638 ; 24.289 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 25.584 ; 25.933 ; 25.933 ; 25.584 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 24.581 ; 24.607 ; 24.607 ; 24.581 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 24.840 ; 25.189 ; 25.189 ; 24.840 ;
; CONFIG[6]    ; ROM2n         ; 16.069 ; 15.720 ; 15.720 ; 16.069 ;
; CRT_PIN3     ; DATA[7]       ; 23.321 ; 23.321 ; 23.321 ; 23.321 ;
; CRT_PIN3     ; RAM_DATA[7]   ; 23.490 ; 23.490 ; 23.490 ; 23.490 ;
; CRT_PIN3     ; RAM_DATA[12]  ; 12.419 ; 12.065 ; 12.065 ; 12.419 ;
; CRT_PIN3     ; RAM_DATA[13]  ; 13.091 ; 13.332 ; 13.332 ; 13.091 ;
; CRT_PIN3     ; RAM_DATA[14]  ; 12.684 ; 12.451 ; 12.451 ; 12.684 ;
; CRT_PIN3     ; RAM_DATA[15]  ; 11.778 ; 12.052 ; 12.052 ; 11.778 ;
; DATA[0]      ; DATA[0]       ; 19.937 ;        ;        ; 19.937 ;
; DATA[0]      ; RAM_DATA[0]   ; 21.221 ;        ;        ; 21.221 ;
; DATA[1]      ; DATA[1]       ; 20.879 ;        ;        ; 20.879 ;
; DATA[1]      ; RAM_DATA[1]   ; 21.806 ;        ;        ; 21.806 ;
; DATA[2]      ; DATA[2]       ; 20.807 ;        ;        ; 20.807 ;
; DATA[2]      ; RAM_DATA[2]   ; 21.557 ;        ;        ; 21.557 ;
; DATA[3]      ; DATA[3]       ; 20.099 ;        ;        ; 20.099 ;
; DATA[3]      ; RAM_DATA[3]   ; 22.398 ;        ;        ; 22.398 ;
; DATA[4]      ; DATA[4]       ; 20.034 ;        ;        ; 20.034 ;
; DATA[4]      ; RAM_DATA[4]   ; 22.283 ;        ;        ; 22.283 ;
; DATA[5]      ; DATA[5]       ; 22.880 ;        ;        ; 22.880 ;
; DATA[5]      ; RAM_DATA[5]   ; 24.384 ;        ;        ; 24.384 ;
; DATA[6]      ; DATA[6]       ; 22.225 ;        ;        ; 22.225 ;
; DATA[6]      ; RAM_DATA[6]   ; 22.961 ;        ;        ; 22.961 ;
; DATA[7]      ; DATA[7]       ; 23.209 ;        ;        ; 23.209 ;
; DATA[7]      ; RAM_DATA[7]   ; 23.378 ;        ;        ; 23.378 ;
; DATA[8]      ; DATA[8]       ; 23.824 ;        ;        ; 23.824 ;
; DATA[8]      ; RAM_DATA[8]   ; 23.785 ;        ;        ; 23.785 ;
; DATA[9]      ; DATA[9]       ; 24.810 ;        ;        ; 24.810 ;
; DATA[9]      ; RAM_DATA[9]   ; 24.821 ;        ;        ; 24.821 ;
; DATA[10]     ; DATA[10]      ; 20.286 ;        ;        ; 20.286 ;
; DATA[10]     ; RAM_DATA[10]  ; 21.496 ;        ;        ; 21.496 ;
; DATA[11]     ; DATA[11]      ; 23.334 ;        ;        ; 23.334 ;
; DATA[11]     ; RAM_DATA[11]  ; 22.016 ;        ;        ; 22.016 ;
; DATA[12]     ; DATA[12]      ; 21.513 ;        ;        ; 21.513 ;
; DATA[12]     ; RAM_DATA[12]  ; 21.179 ;        ;        ; 21.179 ;
; DATA[13]     ; DATA[13]      ; 20.805 ;        ;        ; 20.805 ;
; DATA[13]     ; RAM_DATA[13]  ; 22.591 ;        ;        ; 22.591 ;
; DATA[14]     ; DATA[14]      ; 20.326 ;        ;        ; 20.326 ;
; DATA[14]     ; RAM_DATA[14]  ; 22.453 ;        ;        ; 22.453 ;
; DATA[15]     ; DATA[15]      ; 21.786 ;        ;        ; 21.786 ;
; DATA[15]     ; RAM_DATA[15]  ; 23.300 ;        ;        ; 23.300 ;
; FC[0]        ; ACSI_RDn      ; 20.164 ; 20.164 ; 20.164 ; 20.164 ;
; FC[0]        ; ACSI_WRn      ; 20.173 ; 20.173 ; 20.173 ; 20.173 ;
; FC[0]        ; BUTTONn       ; 16.891 ; 16.891 ; 16.891 ; 16.891 ;
; FC[0]        ; CA1_OUT       ; 19.044 ; 19.044 ; 19.044 ; 19.044 ;
; FC[0]        ; CD[0]         ; 25.609 ; 25.609 ; 25.609 ; 25.609 ;
; FC[0]        ; CD[1]         ; 26.025 ; 26.025 ; 26.025 ; 26.025 ;
; FC[0]        ; CD[2]         ; 25.114 ; 25.114 ; 25.114 ; 25.114 ;
; FC[0]        ; CD[3]         ; 29.052 ; 29.052 ; 29.052 ; 29.052 ;
; FC[0]        ; CD[4]         ; 29.056 ; 29.056 ; 29.056 ; 29.056 ;
; FC[0]        ; CD[5]         ; 29.696 ; 29.696 ; 29.696 ; 29.696 ;
; FC[0]        ; CD[6]         ; 29.642 ; 29.642 ; 29.642 ; 29.642 ;
; FC[0]        ; CD[7]         ; 25.398 ; 25.398 ; 25.398 ; 25.398 ;
; FC[0]        ; DATA[0]       ; 32.558 ; 32.558 ; 32.558 ; 32.558 ;
; FC[0]        ; DATA[1]       ; 34.191 ; 34.191 ; 34.191 ; 34.191 ;
; FC[0]        ; DATA[2]       ; 33.126 ; 33.126 ; 33.126 ; 33.126 ;
; FC[0]        ; DATA[3]       ; 31.424 ; 31.424 ; 31.424 ; 31.424 ;
; FC[0]        ; DATA[4]       ; 32.262 ; 32.262 ; 32.262 ; 32.262 ;
; FC[0]        ; DATA[5]       ; 33.798 ; 33.798 ; 33.798 ; 33.798 ;
; FC[0]        ; DATA[6]       ; 33.937 ; 33.937 ; 33.937 ; 33.937 ;
; FC[0]        ; DATA[7]       ; 34.596 ; 34.596 ; 34.596 ; 34.596 ;
; FC[0]        ; DATA[8]       ; 34.473 ; 34.473 ; 34.473 ; 34.473 ;
; FC[0]        ; DATA[9]       ; 35.116 ; 35.116 ; 35.116 ; 35.116 ;
; FC[0]        ; DATA[10]      ; 32.444 ; 32.444 ; 32.444 ; 32.444 ;
; FC[0]        ; DATA[11]      ; 34.975 ; 34.975 ; 34.975 ; 34.975 ;
; FC[0]        ; DATA[12]      ; 35.048 ; 35.048 ; 35.048 ; 35.048 ;
; FC[0]        ; DATA[13]      ; 32.906 ; 32.906 ; 32.906 ; 32.906 ;
; FC[0]        ; DATA[14]      ; 32.033 ; 32.033 ; 32.033 ; 32.033 ;
; FC[0]        ; DATA[15]      ; 33.068 ; 33.068 ; 33.068 ; 33.068 ;
; FC[0]        ; DTACKn        ; 24.095 ; 24.095 ; 24.095 ; 24.095 ;
; FC[0]        ; FLASH_CEn     ; 20.033 ; 20.033 ; 20.033 ; 20.033 ;
; FC[0]        ; FLASH_OEn     ; 19.239 ; 19.239 ; 19.239 ; 19.239 ;
; FC[0]        ; JOY_RHn       ; 17.488 ; 17.488 ; 17.488 ; 17.488 ;
; FC[0]        ; JOY_RLn       ; 17.729 ; 17.729 ; 17.729 ; 17.729 ;
; FC[0]        ; JOY_WEn       ; 17.371 ; 17.371 ; 17.371 ; 17.371 ;
; FC[0]        ; JOY_WL        ; 17.643 ; 17.643 ; 17.643 ; 17.643 ;
; FC[0]        ; RAM_DATA[0]   ; 33.842 ; 33.842 ; 33.842 ; 33.842 ;
; FC[0]        ; RAM_DATA[1]   ; 35.118 ; 35.118 ; 35.118 ; 35.118 ;
; FC[0]        ; RAM_DATA[2]   ; 33.876 ; 33.876 ; 33.876 ; 33.876 ;
; FC[0]        ; RAM_DATA[3]   ; 33.723 ; 33.723 ; 33.723 ; 33.723 ;
; FC[0]        ; RAM_DATA[4]   ; 34.511 ; 34.511 ; 34.511 ; 34.511 ;
; FC[0]        ; RAM_DATA[5]   ; 35.302 ; 35.302 ; 35.302 ; 35.302 ;
; FC[0]        ; RAM_DATA[6]   ; 34.673 ; 34.673 ; 34.673 ; 34.673 ;
; FC[0]        ; RAM_DATA[7]   ; 34.765 ; 34.765 ; 34.765 ; 34.765 ;
; FC[0]        ; RAM_DATA[8]   ; 34.434 ; 34.434 ; 34.434 ; 34.434 ;
; FC[0]        ; RAM_DATA[9]   ; 35.127 ; 35.127 ; 35.127 ; 35.127 ;
; FC[0]        ; RAM_DATA[10]  ; 33.654 ; 33.654 ; 33.654 ; 33.654 ;
; FC[0]        ; RAM_DATA[11]  ; 33.657 ; 33.657 ; 33.657 ; 33.657 ;
; FC[0]        ; RAM_DATA[12]  ; 34.714 ; 34.714 ; 34.714 ; 34.714 ;
; FC[0]        ; RAM_DATA[13]  ; 34.692 ; 34.692 ; 34.692 ; 34.692 ;
; FC[0]        ; RAM_DATA[14]  ; 34.160 ; 34.160 ; 34.160 ; 34.160 ;
; FC[0]        ; RAM_DATA[15]  ; 34.582 ; 34.582 ; 34.582 ; 34.582 ;
; FC[0]        ; ROM0n         ; 15.986 ; 15.986 ; 15.986 ; 15.986 ;
; FC[0]        ; ROM1n         ; 15.714 ; 15.714 ; 15.714 ; 15.714 ;
; FC[0]        ; ROM2n         ; 17.673 ; 17.673 ; 17.673 ; 17.673 ;
; FC[0]        ; ROM3n         ; 15.231 ; 15.231 ; 15.231 ; 15.231 ;
; FC[0]        ; ROM4n         ; 15.386 ; 15.386 ; 15.386 ; 15.386 ;
; FC[0]        ; ROM5n         ; 17.664 ; 17.664 ; 17.664 ; 17.664 ;
; FC[0]        ; ROM6n         ; 17.199 ; 17.199 ; 17.199 ; 17.199 ;
; FC[1]        ; ACSI_RDn      ; 20.136 ; 20.136 ; 20.136 ; 20.136 ;
; FC[1]        ; ACSI_WRn      ; 20.145 ; 20.145 ; 20.145 ; 20.145 ;
; FC[1]        ; BUTTONn       ; 16.619 ; 16.619 ; 16.619 ; 16.619 ;
; FC[1]        ; CA1_OUT       ; 19.016 ; 19.016 ; 19.016 ; 19.016 ;
; FC[1]        ; CD[0]         ; 25.581 ; 25.581 ; 25.581 ; 25.581 ;
; FC[1]        ; CD[1]         ; 25.997 ; 25.997 ; 25.997 ; 25.997 ;
; FC[1]        ; CD[2]         ; 25.086 ; 25.086 ; 25.086 ; 25.086 ;
; FC[1]        ; CD[3]         ; 29.024 ; 29.024 ; 29.024 ; 29.024 ;
; FC[1]        ; CD[4]         ; 29.028 ; 29.028 ; 29.028 ; 29.028 ;
; FC[1]        ; CD[5]         ; 29.668 ; 29.668 ; 29.668 ; 29.668 ;
; FC[1]        ; CD[6]         ; 29.614 ; 29.614 ; 29.614 ; 29.614 ;
; FC[1]        ; CD[7]         ; 25.370 ; 25.370 ; 25.370 ; 25.370 ;
; FC[1]        ; DATA[0]       ; 32.523 ; 32.523 ; 32.523 ; 32.523 ;
; FC[1]        ; DATA[1]       ; 34.156 ; 34.156 ; 34.156 ; 34.156 ;
; FC[1]        ; DATA[2]       ; 33.091 ; 33.091 ; 33.091 ; 33.091 ;
; FC[1]        ; DATA[3]       ; 31.389 ; 31.389 ; 31.389 ; 31.389 ;
; FC[1]        ; DATA[4]       ; 32.227 ; 32.227 ; 32.227 ; 32.227 ;
; FC[1]        ; DATA[5]       ; 33.763 ; 33.763 ; 33.763 ; 33.763 ;
; FC[1]        ; DATA[6]       ; 33.902 ; 33.902 ; 33.902 ; 33.902 ;
; FC[1]        ; DATA[7]       ; 34.561 ; 34.561 ; 34.561 ; 34.561 ;
; FC[1]        ; DATA[8]       ; 34.438 ; 34.438 ; 34.438 ; 34.438 ;
; FC[1]        ; DATA[9]       ; 35.081 ; 35.081 ; 35.081 ; 35.081 ;
; FC[1]        ; DATA[10]      ; 32.409 ; 32.409 ; 32.409 ; 32.409 ;
; FC[1]        ; DATA[11]      ; 34.940 ; 34.940 ; 34.940 ; 34.940 ;
; FC[1]        ; DATA[12]      ; 35.013 ; 35.013 ; 35.013 ; 35.013 ;
; FC[1]        ; DATA[13]      ; 32.871 ; 32.871 ; 32.871 ; 32.871 ;
; FC[1]        ; DATA[14]      ; 31.998 ; 31.998 ; 31.998 ; 31.998 ;
; FC[1]        ; DATA[15]      ; 33.033 ; 33.033 ; 33.033 ; 33.033 ;
; FC[1]        ; DTACKn        ; 24.060 ; 24.060 ; 24.060 ; 24.060 ;
; FC[1]        ; FLASH_CEn     ; 20.293 ; 20.293 ; 20.293 ; 20.293 ;
; FC[1]        ; FLASH_OEn     ; 19.499 ; 19.499 ; 19.499 ; 19.499 ;
; FC[1]        ; JOY_RHn       ; 17.460 ; 17.460 ; 17.460 ; 17.460 ;
; FC[1]        ; JOY_RLn       ; 17.701 ; 17.701 ; 17.701 ; 17.701 ;
; FC[1]        ; JOY_WEn       ; 17.343 ; 17.343 ; 17.343 ; 17.343 ;
; FC[1]        ; JOY_WL        ; 17.615 ; 17.615 ; 17.615 ; 17.615 ;
; FC[1]        ; RAM_DATA[0]   ; 33.807 ; 33.807 ; 33.807 ; 33.807 ;
; FC[1]        ; RAM_DATA[1]   ; 35.083 ; 35.083 ; 35.083 ; 35.083 ;
; FC[1]        ; RAM_DATA[2]   ; 33.841 ; 33.841 ; 33.841 ; 33.841 ;
; FC[1]        ; RAM_DATA[3]   ; 33.688 ; 33.688 ; 33.688 ; 33.688 ;
; FC[1]        ; RAM_DATA[4]   ; 34.476 ; 34.476 ; 34.476 ; 34.476 ;
; FC[1]        ; RAM_DATA[5]   ; 35.267 ; 35.267 ; 35.267 ; 35.267 ;
; FC[1]        ; RAM_DATA[6]   ; 34.638 ; 34.638 ; 34.638 ; 34.638 ;
; FC[1]        ; RAM_DATA[7]   ; 34.730 ; 34.730 ; 34.730 ; 34.730 ;
; FC[1]        ; RAM_DATA[8]   ; 34.399 ; 34.399 ; 34.399 ; 34.399 ;
; FC[1]        ; RAM_DATA[9]   ; 35.092 ; 35.092 ; 35.092 ; 35.092 ;
; FC[1]        ; RAM_DATA[10]  ; 33.619 ; 33.619 ; 33.619 ; 33.619 ;
; FC[1]        ; RAM_DATA[11]  ; 33.622 ; 33.622 ; 33.622 ; 33.622 ;
; FC[1]        ; RAM_DATA[12]  ; 34.679 ; 34.679 ; 34.679 ; 34.679 ;
; FC[1]        ; RAM_DATA[13]  ; 34.657 ; 34.657 ; 34.657 ; 34.657 ;
; FC[1]        ; RAM_DATA[14]  ; 34.125 ; 34.125 ; 34.125 ; 34.125 ;
; FC[1]        ; RAM_DATA[15]  ; 34.547 ; 34.547 ; 34.547 ; 34.547 ;
; FC[1]        ; ROM0n         ; 16.246 ; 16.246 ; 16.246 ; 16.246 ;
; FC[1]        ; ROM1n         ; 15.974 ; 15.974 ; 15.974 ; 15.974 ;
; FC[1]        ; ROM2n         ; 17.933 ; 17.933 ; 17.933 ; 17.933 ;
; FC[1]        ; ROM3n         ; 15.491 ; 15.491 ; 15.491 ; 15.491 ;
; FC[1]        ; ROM4n         ; 15.646 ; 15.646 ; 15.646 ; 15.646 ;
; FC[1]        ; ROM5n         ; 17.924 ; 17.924 ; 17.924 ; 17.924 ;
; FC[1]        ; ROM6n         ; 17.459 ; 17.459 ; 17.459 ; 17.459 ;
; FC[2]        ; ACSI_RDn      ; 20.080 ; 20.080 ; 20.080 ; 20.080 ;
; FC[2]        ; ACSI_WRn      ; 20.089 ; 20.089 ; 20.089 ; 20.089 ;
; FC[2]        ; CA1_OUT       ;        ; 18.960 ; 18.960 ;        ;
; FC[2]        ; CD[0]         ; 25.525 ; 25.525 ; 25.525 ; 25.525 ;
; FC[2]        ; CD[1]         ; 25.941 ; 25.941 ; 25.941 ; 25.941 ;
; FC[2]        ; CD[2]         ; 25.030 ; 25.030 ; 25.030 ; 25.030 ;
; FC[2]        ; CD[3]         ; 28.968 ; 28.968 ; 28.968 ; 28.968 ;
; FC[2]        ; CD[4]         ; 28.972 ; 28.972 ; 28.972 ; 28.972 ;
; FC[2]        ; CD[5]         ; 29.612 ; 29.612 ; 29.612 ; 29.612 ;
; FC[2]        ; CD[6]         ; 29.558 ; 29.558 ; 29.558 ; 29.558 ;
; FC[2]        ; CD[7]         ; 25.314 ; 25.314 ; 25.314 ; 25.314 ;
; FC[2]        ; DATA[0]       ; 32.463 ; 30.199 ; 30.199 ; 32.463 ;
; FC[2]        ; DATA[1]       ; 34.096 ; 31.570 ; 31.570 ; 34.096 ;
; FC[2]        ; DATA[2]       ; 33.031 ; 30.041 ; 30.041 ; 33.031 ;
; FC[2]        ; DATA[3]       ; 31.329 ; 29.507 ; 29.507 ; 31.329 ;
; FC[2]        ; DATA[4]       ; 32.167 ; 29.854 ; 29.854 ; 32.167 ;
; FC[2]        ; DATA[5]       ; 33.703 ; 31.475 ; 31.475 ; 33.703 ;
; FC[2]        ; DATA[6]       ; 33.842 ; 30.971 ; 30.971 ; 33.842 ;
; FC[2]        ; DATA[7]       ; 34.501 ; 31.330 ; 31.330 ; 34.501 ;
; FC[2]        ; DATA[8]       ; 34.378 ; 34.378 ; 34.378 ; 34.378 ;
; FC[2]        ; DATA[9]       ; 35.021 ; 35.021 ; 35.021 ; 35.021 ;
; FC[2]        ; DATA[10]      ; 32.349 ; 32.349 ; 32.349 ; 32.349 ;
; FC[2]        ; DATA[11]      ; 34.880 ; 34.782 ; 34.782 ; 34.880 ;
; FC[2]        ; DATA[12]      ; 34.953 ; 34.953 ; 34.953 ; 34.953 ;
; FC[2]        ; DATA[13]      ; 32.689 ; 32.811 ; 32.811 ; 32.689 ;
; FC[2]        ; DATA[14]      ; 31.938 ; 31.938 ; 31.938 ; 31.938 ;
; FC[2]        ; DATA[15]      ; 32.836 ; 32.973 ; 32.973 ; 32.836 ;
; FC[2]        ; DTACKn        ; 24.000 ; 24.000 ; 24.000 ; 24.000 ;
; FC[2]        ; JOY_RHn       ;        ; 17.404 ; 17.404 ;        ;
; FC[2]        ; JOY_RLn       ;        ; 17.645 ; 17.645 ;        ;
; FC[2]        ; JOY_WEn       ; 17.287 ;        ;        ; 17.287 ;
; FC[2]        ; JOY_WL        ; 17.559 ;        ;        ; 17.559 ;
; FC[2]        ; RAM_DATA[0]   ; 33.747 ; 31.483 ; 31.483 ; 33.747 ;
; FC[2]        ; RAM_DATA[1]   ; 35.023 ; 32.497 ; 32.497 ; 35.023 ;
; FC[2]        ; RAM_DATA[2]   ; 33.781 ; 30.791 ; 30.791 ; 33.781 ;
; FC[2]        ; RAM_DATA[3]   ; 33.628 ; 31.806 ; 31.806 ; 33.628 ;
; FC[2]        ; RAM_DATA[4]   ; 34.416 ; 32.103 ; 32.103 ; 34.416 ;
; FC[2]        ; RAM_DATA[5]   ; 35.207 ; 32.979 ; 32.979 ; 35.207 ;
; FC[2]        ; RAM_DATA[6]   ; 34.578 ; 31.707 ; 31.707 ; 34.578 ;
; FC[2]        ; RAM_DATA[7]   ; 34.670 ; 31.499 ; 31.499 ; 34.670 ;
; FC[2]        ; RAM_DATA[8]   ; 34.339 ; 34.339 ; 34.339 ; 34.339 ;
; FC[2]        ; RAM_DATA[9]   ; 35.032 ; 35.032 ; 35.032 ; 35.032 ;
; FC[2]        ; RAM_DATA[10]  ; 33.559 ; 33.559 ; 33.559 ; 33.559 ;
; FC[2]        ; RAM_DATA[11]  ; 33.562 ; 33.464 ; 33.464 ; 33.562 ;
; FC[2]        ; RAM_DATA[12]  ; 34.619 ; 34.619 ; 34.619 ; 34.619 ;
; FC[2]        ; RAM_DATA[13]  ; 34.475 ; 34.597 ; 34.597 ; 34.475 ;
; FC[2]        ; RAM_DATA[14]  ; 34.065 ; 34.065 ; 34.065 ; 34.065 ;
; FC[2]        ; RAM_DATA[15]  ; 34.350 ; 34.487 ; 34.487 ; 34.350 ;
; HDINTn       ; DATA[5]       ; 24.851 ;        ;        ; 24.851 ;
; HDINTn       ; RAM_DATA[5]   ; 26.355 ;        ;        ; 26.355 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 24.592 ; 24.592 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 26.096 ; 26.096 ;        ;
; IDE_IORDY    ; DTACKn        ; 17.181 ; 17.181 ; 17.181 ; 17.181 ;
; LDSn         ; ACSI_RDn      ; 22.710 ; 22.710 ; 22.710 ; 22.710 ;
; LDSn         ; ACSI_WRn      ; 22.719 ; 22.719 ; 22.719 ; 22.719 ;
; LDSn         ; BUTTONn       ; 20.616 ;        ;        ; 20.616 ;
; LDSn         ; CA1_OUT       ; 21.590 ;        ;        ; 21.590 ;
; LDSn         ; CD[0]         ; 28.155 ; 28.155 ; 28.155 ; 28.155 ;
; LDSn         ; CD[1]         ; 28.571 ; 28.571 ; 28.571 ; 28.571 ;
; LDSn         ; CD[2]         ; 27.660 ; 27.660 ; 27.660 ; 27.660 ;
; LDSn         ; CD[3]         ; 31.598 ; 31.598 ; 31.598 ; 31.598 ;
; LDSn         ; CD[4]         ; 31.602 ; 31.602 ; 31.602 ; 31.602 ;
; LDSn         ; CD[5]         ; 32.242 ; 32.242 ; 32.242 ; 32.242 ;
; LDSn         ; CD[6]         ; 32.188 ; 32.188 ; 32.188 ; 32.188 ;
; LDSn         ; CD[7]         ; 27.944 ; 27.944 ; 27.944 ; 27.944 ;
; LDSn         ; DATA[0]       ; 30.598 ; 29.758 ; 29.758 ; 30.598 ;
; LDSn         ; DATA[1]       ; 33.460 ; 32.094 ; 32.094 ; 33.460 ;
; LDSn         ; DATA[2]       ; 30.929 ; 29.812 ; 29.812 ; 30.929 ;
; LDSn         ; DATA[3]       ; 31.018 ; 30.511 ; 30.511 ; 31.018 ;
; LDSn         ; DATA[4]       ; 29.889 ; 29.461 ; 29.461 ; 29.889 ;
; LDSn         ; DATA[5]       ; 32.606 ; 31.839 ; 31.839 ; 32.606 ;
; LDSn         ; DATA[6]       ; 31.812 ; 31.168 ; 31.168 ; 31.812 ;
; LDSn         ; DATA[7]       ; 33.689 ; 33.073 ; 33.073 ; 33.689 ;
; LDSn         ; DATA[8]       ; 33.740 ; 31.914 ; 31.914 ; 33.740 ;
; LDSn         ; DATA[9]       ; 33.770 ; 32.139 ; 32.139 ; 33.770 ;
; LDSn         ; DATA[10]      ; 31.042 ; 29.694 ; 29.694 ; 31.042 ;
; LDSn         ; DATA[11]      ; 34.308 ; 32.348 ; 32.348 ; 34.308 ;
; LDSn         ; DATA[12]      ; 31.358 ; 31.145 ; 31.145 ; 31.358 ;
; LDSn         ; DATA[13]      ; 31.986 ; 30.531 ; 30.531 ; 31.986 ;
; LDSn         ; DATA[14]      ; 31.557 ; 29.662 ; 29.662 ; 31.557 ;
; LDSn         ; DATA[15]      ; 32.419 ; 30.659 ; 30.659 ; 32.419 ;
; LDSn         ; DTACKn        ; 24.463 ; 24.463 ; 24.463 ; 24.463 ;
; LDSn         ; IDE_IORDn     ; 15.551 ;        ;        ; 15.551 ;
; LDSn         ; IDE_IOWRn     ; 15.211 ;        ;        ; 15.211 ;
; LDSn         ; JOY_RLn       ; 13.301 ;        ;        ; 13.301 ;
; LDSn         ; JOY_WEn       ;        ; 12.943 ; 12.943 ;        ;
; LDSn         ; JOY_WL        ;        ; 12.687 ; 12.687 ;        ;
; LDSn         ; RAM_CAS0n     ; 17.071 ;        ;        ; 17.071 ;
; LDSn         ; RAM_DATA[0]   ; 31.882 ; 31.042 ; 31.042 ; 31.882 ;
; LDSn         ; RAM_DATA[1]   ; 34.387 ; 33.021 ; 33.021 ; 34.387 ;
; LDSn         ; RAM_DATA[2]   ; 31.679 ; 30.562 ; 30.562 ; 31.679 ;
; LDSn         ; RAM_DATA[3]   ; 33.317 ; 32.810 ; 32.810 ; 33.317 ;
; LDSn         ; RAM_DATA[4]   ; 32.138 ; 31.710 ; 31.710 ; 32.138 ;
; LDSn         ; RAM_DATA[5]   ; 34.110 ; 33.343 ; 33.343 ; 34.110 ;
; LDSn         ; RAM_DATA[6]   ; 32.548 ; 31.904 ; 31.904 ; 32.548 ;
; LDSn         ; RAM_DATA[7]   ; 33.858 ; 33.242 ; 33.242 ; 33.858 ;
; LDSn         ; RAM_DATA[8]   ; 33.701 ; 31.875 ; 31.875 ; 33.701 ;
; LDSn         ; RAM_DATA[9]   ; 33.781 ; 32.150 ; 32.150 ; 33.781 ;
; LDSn         ; RAM_DATA[10]  ; 32.252 ; 30.904 ; 30.904 ; 32.252 ;
; LDSn         ; RAM_DATA[11]  ; 32.990 ; 31.030 ; 31.030 ; 32.990 ;
; LDSn         ; RAM_DATA[12]  ; 31.024 ; 30.811 ; 30.811 ; 31.024 ;
; LDSn         ; RAM_DATA[13]  ; 33.772 ; 32.317 ; 32.317 ; 33.772 ;
; LDSn         ; RAM_DATA[14]  ; 33.684 ; 31.789 ; 31.789 ; 33.684 ;
; LDSn         ; RAM_DATA[15]  ; 33.933 ; 32.173 ; 32.173 ; 33.933 ;
; LDSn         ; RAM_DQM0L     ; 14.828 ;        ;        ; 14.828 ;
; LPT_BSY      ; DATA[0]       ; 23.867 ;        ;        ; 23.867 ;
; LPT_BSY      ; RAM_DATA[0]   ; 25.151 ;        ;        ; 25.151 ;
; LPT_D[0]     ; DATA[8]       ; 22.459 ;        ;        ; 22.459 ;
; LPT_D[0]     ; RAM_DATA[8]   ; 22.420 ;        ;        ; 22.420 ;
; LPT_D[1]     ; DATA[9]       ; 23.036 ;        ;        ; 23.036 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 23.047 ;        ;        ; 23.047 ;
; LPT_D[2]     ; DATA[10]      ; 20.336 ;        ;        ; 20.336 ;
; LPT_D[2]     ; RAM_DATA[10]  ; 21.546 ;        ;        ; 21.546 ;
; LPT_D[3]     ; DATA[11]      ; 22.109 ;        ;        ; 22.109 ;
; LPT_D[3]     ; RAM_DATA[11]  ; 20.791 ;        ;        ; 20.791 ;
; LPT_D[4]     ; DATA[12]      ; 21.813 ;        ;        ; 21.813 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 21.479 ;        ;        ; 21.479 ;
; LPT_D[5]     ; DATA[13]      ; 21.231 ;        ;        ; 21.231 ;
; LPT_D[5]     ; RAM_DATA[13]  ; 23.017 ;        ;        ; 23.017 ;
; LPT_D[6]     ; DATA[14]      ; 19.723 ;        ;        ; 19.723 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 21.850 ;        ;        ; 21.850 ;
; LPT_D[7]     ; DATA[15]      ; 21.785 ;        ;        ; 21.785 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 23.299 ;        ;        ; 23.299 ;
; MIDI_IN      ; MIDI_TLR      ; 8.873  ;        ;        ; 8.873  ;
; RAM_DATA[0]  ; DATA[0]       ; 21.678 ;        ;        ; 21.678 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 22.962 ;        ;        ; 22.962 ;
; RAM_DATA[1]  ; DATA[1]       ; 22.554 ;        ;        ; 22.554 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 23.481 ;        ;        ; 23.481 ;
; RAM_DATA[2]  ; DATA[2]       ; 21.735 ;        ;        ; 21.735 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 22.485 ;        ;        ; 22.485 ;
; RAM_DATA[3]  ; DATA[3]       ; 21.236 ;        ;        ; 21.236 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 23.535 ;        ;        ; 23.535 ;
; RAM_DATA[4]  ; DATA[4]       ; 20.921 ;        ;        ; 20.921 ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 23.170 ;        ;        ; 23.170 ;
; RAM_DATA[5]  ; DATA[5]       ; 23.892 ;        ;        ; 23.892 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 25.396 ;        ;        ; 25.396 ;
; RAM_DATA[6]  ; DATA[6]       ; 25.412 ;        ;        ; 25.412 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 26.148 ;        ;        ; 26.148 ;
; RAM_DATA[7]  ; DATA[7]       ; 24.313 ;        ;        ; 24.313 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 24.482 ;        ;        ; 24.482 ;
; RAM_DATA[8]  ; DATA[8]       ; 23.496 ;        ;        ; 23.496 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 23.457 ;        ;        ; 23.457 ;
; RAM_DATA[9]  ; DATA[9]       ; 25.338 ;        ;        ; 25.338 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 25.349 ;        ;        ; 25.349 ;
; RAM_DATA[10] ; DATA[10]      ; 21.388 ;        ;        ; 21.388 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 22.598 ;        ;        ; 22.598 ;
; RAM_DATA[11] ; DATA[11]      ; 25.045 ;        ;        ; 25.045 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 23.727 ;        ;        ; 23.727 ;
; RAM_DATA[12] ; DATA[12]      ; 22.100 ;        ;        ; 22.100 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 21.766 ;        ;        ; 21.766 ;
; RAM_DATA[13] ; DATA[13]      ; 21.656 ;        ;        ; 21.656 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 23.442 ;        ;        ; 23.442 ;
; RAM_DATA[14] ; DATA[14]      ; 21.682 ;        ;        ; 21.682 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 23.809 ;        ;        ; 23.809 ;
; RAM_DATA[15] ; DATA[15]      ; 23.279 ;        ;        ; 23.279 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 24.793 ;        ;        ; 24.793 ;
; RWn          ; ACSI_RDn      ; 20.173 ; 20.173 ; 20.173 ; 20.173 ;
; RWn          ; ACSI_WRn      ; 20.182 ; 20.182 ; 20.182 ; 20.182 ;
; RWn          ; BUTTONn       ;        ; 16.692 ; 16.692 ;        ;
; RWn          ; CA1_OUT       ;        ; 19.053 ; 19.053 ;        ;
; RWn          ; CD[0]         ; 25.618 ; 25.618 ; 25.618 ; 25.618 ;
; RWn          ; CD[1]         ; 26.034 ; 26.034 ; 26.034 ; 26.034 ;
; RWn          ; CD[2]         ; 25.123 ; 25.123 ; 25.123 ; 25.123 ;
; RWn          ; CD[3]         ; 29.061 ; 29.061 ; 29.061 ; 29.061 ;
; RWn          ; CD[4]         ; 29.065 ; 29.065 ; 29.065 ; 29.065 ;
; RWn          ; CD[5]         ; 29.705 ; 29.705 ; 29.705 ; 29.705 ;
; RWn          ; CD[6]         ; 29.651 ; 29.651 ; 29.651 ; 29.651 ;
; RWn          ; CD[7]         ; 25.407 ; 25.407 ; 25.407 ; 25.407 ;
; RWn          ; DATA[0]       ; 30.304 ; 32.560 ; 32.560 ; 30.304 ;
; RWn          ; DATA[1]       ; 31.951 ; 34.193 ; 34.193 ; 31.951 ;
; RWn          ; DATA[2]       ; 30.035 ; 33.128 ; 33.128 ; 30.035 ;
; RWn          ; DATA[3]       ; 30.368 ; 31.426 ; 31.426 ; 30.368 ;
; RWn          ; DATA[4]       ; 29.947 ; 32.264 ; 32.264 ; 29.947 ;
; RWn          ; DATA[5]       ; 31.696 ; 33.800 ; 33.800 ; 31.696 ;
; RWn          ; DATA[6]       ; 31.135 ; 33.939 ; 33.939 ; 31.135 ;
; RWn          ; DATA[7]       ; 32.930 ; 34.598 ; 34.598 ; 32.930 ;
; RWn          ; DATA[8]       ; 34.475 ; 34.475 ; 34.475 ; 34.475 ;
; RWn          ; DATA[9]       ; 35.118 ; 35.118 ; 35.118 ; 35.118 ;
; RWn          ; DATA[10]      ; 32.446 ; 32.446 ; 32.446 ; 32.446 ;
; RWn          ; DATA[11]      ; 34.879 ; 34.977 ; 34.977 ; 34.879 ;
; RWn          ; DATA[12]      ; 35.050 ; 35.050 ; 35.050 ; 35.050 ;
; RWn          ; DATA[13]      ; 32.908 ; 32.786 ; 32.786 ; 32.908 ;
; RWn          ; DATA[14]      ; 32.035 ; 32.035 ; 32.035 ; 32.035 ;
; RWn          ; DATA[15]      ; 33.070 ; 32.933 ; 32.933 ; 33.070 ;
; RWn          ; DTACKn        ; 24.097 ; 24.097 ; 24.097 ; 24.097 ;
; RWn          ; FLASH_CEn     ;        ; 20.033 ; 20.033 ;        ;
; RWn          ; FLASH_OEn     ;        ; 19.239 ; 19.239 ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 14.460 ; 14.460 ;        ;
; RWn          ; IDE_D_EN_OUTn ; 15.046 ;        ;        ; 15.046 ;
; RWn          ; IDE_IORDn     ;        ; 14.732 ; 14.732 ;        ;
; RWn          ; IDE_IOWRn     ; 14.352 ;        ;        ; 14.352 ;
; RWn          ; JOY_RHn       ;        ; 17.497 ; 17.497 ;        ;
; RWn          ; JOY_RLn       ;        ; 17.738 ; 17.738 ;        ;
; RWn          ; JOY_WEn       ; 17.380 ;        ;        ; 17.380 ;
; RWn          ; JOY_WL        ; 17.652 ; 12.211 ; 12.211 ; 17.652 ;
; RWn          ; RAM_DATA[0]   ; 31.588 ; 33.844 ; 33.844 ; 31.588 ;
; RWn          ; RAM_DATA[1]   ; 32.878 ; 35.120 ; 35.120 ; 32.878 ;
; RWn          ; RAM_DATA[2]   ; 30.785 ; 33.878 ; 33.878 ; 30.785 ;
; RWn          ; RAM_DATA[3]   ; 32.667 ; 33.725 ; 33.725 ; 32.667 ;
; RWn          ; RAM_DATA[4]   ; 32.196 ; 34.513 ; 34.513 ; 32.196 ;
; RWn          ; RAM_DATA[5]   ; 33.200 ; 35.304 ; 35.304 ; 33.200 ;
; RWn          ; RAM_DATA[6]   ; 31.871 ; 34.675 ; 34.675 ; 31.871 ;
; RWn          ; RAM_DATA[7]   ; 33.099 ; 34.767 ; 34.767 ; 33.099 ;
; RWn          ; RAM_DATA[8]   ; 34.436 ; 34.436 ; 34.436 ; 34.436 ;
; RWn          ; RAM_DATA[9]   ; 35.129 ; 35.129 ; 35.129 ; 35.129 ;
; RWn          ; RAM_DATA[10]  ; 33.656 ; 33.656 ; 33.656 ; 33.656 ;
; RWn          ; RAM_DATA[11]  ; 33.561 ; 33.659 ; 33.659 ; 33.561 ;
; RWn          ; RAM_DATA[12]  ; 34.716 ; 34.716 ; 34.716 ; 34.716 ;
; RWn          ; RAM_DATA[13]  ; 34.694 ; 34.572 ; 34.572 ; 34.694 ;
; RWn          ; RAM_DATA[14]  ; 34.162 ; 34.162 ; 34.162 ; 34.162 ;
; RWn          ; RAM_DATA[15]  ; 34.584 ; 34.447 ; 34.447 ; 34.584 ;
; RWn          ; RAM_WEn       ; 16.091 ;        ;        ; 16.091 ;
; RWn          ; ROM0n         ;        ; 15.986 ; 15.986 ;        ;
; RWn          ; ROM1n         ;        ; 15.714 ; 15.714 ;        ;
; RWn          ; ROM2n         ;        ; 17.673 ; 17.673 ;        ;
; RWn          ; ROM3n         ;        ; 15.231 ; 15.231 ;        ;
; RWn          ; ROM4n         ;        ; 15.386 ; 15.386 ;        ;
; RWn          ; ROM5n         ;        ; 17.664 ; 17.664 ;        ;
; RWn          ; ROM6n         ;        ; 17.199 ; 17.199 ;        ;
; SCSI_ACKn    ; CD[0]         ; 14.204 ; 14.204 ; 14.204 ; 14.204 ;
; SCSI_ATNn    ; CD[1]         ; 16.332 ; 16.332 ; 16.332 ; 16.332 ;
; SCSI_BSYn    ; CD[6]         ; 17.707 ; 17.707 ; 17.707 ; 17.707 ;
; SCSI_D[0]    ; CD[0]         ; 14.770 ; 14.770 ; 14.770 ; 14.770 ;
; SCSI_D[1]    ; CD[1]         ; 15.008 ; 15.008 ; 15.008 ; 15.008 ;
; SCSI_D[2]    ; CD[2]         ;        ; 13.276 ; 13.276 ;        ;
; SCSI_D[3]    ; CD[3]         ; 15.444 ; 15.444 ; 15.444 ; 15.444 ;
; SCSI_D[4]    ; CD[4]         ; 17.943 ; 17.943 ; 17.943 ; 17.943 ;
; SCSI_D[5]    ; CD[5]         ; 16.747 ; 16.747 ; 16.747 ; 16.747 ;
; SCSI_D[6]    ; CD[6]         ; 17.645 ; 17.645 ; 17.645 ; 17.645 ;
; SCSI_D[7]    ; CD[7]         ; 16.361 ; 16.361 ; 16.361 ; 16.361 ;
; SCSI_DCn     ; CD[3]         ; 19.285 ; 19.285 ; 19.285 ; 19.285 ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 18.454 ; 18.454 ; 18.454 ; 18.454 ;
; SCSI_DCn     ; SCSI_D[0]     ; 17.103 ; 17.103 ; 17.103 ; 17.103 ;
; SCSI_DCn     ; SCSI_D[1]     ; 17.103 ; 17.103 ; 17.103 ; 17.103 ;
; SCSI_DCn     ; SCSI_D[2]     ; 17.096 ; 17.096 ; 17.096 ; 17.096 ;
; SCSI_DCn     ; SCSI_D[3]     ; 17.096 ; 17.096 ; 17.096 ; 17.096 ;
; SCSI_DCn     ; SCSI_D[4]     ; 17.430 ; 17.430 ; 17.430 ; 17.430 ;
; SCSI_DCn     ; SCSI_D[5]     ; 17.430 ; 17.430 ; 17.430 ; 17.430 ;
; SCSI_DCn     ; SCSI_D[6]     ; 17.705 ; 17.705 ; 17.705 ; 17.705 ;
; SCSI_DCn     ; SCSI_D[7]     ; 17.705 ; 17.705 ; 17.705 ; 17.705 ;
; SCSI_DCn     ; SCSI_DP       ; 17.113 ; 17.113 ; 17.113 ; 17.113 ;
; SCSI_DP      ; CD[0]         ; 14.407 ; 14.407 ; 14.407 ; 14.407 ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 12.296 ; 12.296 ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 12.292 ;        ;        ; 12.292 ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 12.274 ; 12.274 ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 12.643 ;        ;        ; 12.643 ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 13.212 ; 13.212 ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 13.208 ;        ;        ; 13.208 ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 13.616 ; 13.616 ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 12.942 ;        ;        ; 12.942 ;
; SCSI_IDn[1]  ; SCSI_DP       ; 15.073 ; 15.073 ; 15.073 ; 15.073 ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 11.936 ; 11.936 ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 11.936 ; 11.936 ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 11.905 ;        ;        ; 11.905 ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 12.277 ;        ;        ; 12.277 ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 12.863 ; 12.863 ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 12.856 ; 12.856 ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 13.266 ;        ;        ; 13.266 ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 12.578 ;        ;        ; 12.578 ;
; SCSI_IDn[2]  ; SCSI_DP       ; 14.707 ; 14.707 ; 14.707 ; 14.707 ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 12.483 ; 12.483 ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 12.477 ; 12.477 ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 12.495 ; 12.495 ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 12.865 ; 12.865 ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 13.339 ;        ;        ; 13.339 ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 13.332 ;        ;        ; 13.332 ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 13.775 ;        ;        ; 13.775 ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 13.101 ;        ;        ; 13.101 ;
; SCSI_IDn[3]  ; SCSI_DP       ; 15.295 ; 15.295 ; 15.295 ; 15.295 ;
; SCSI_IOn     ; CD[2]         ;        ; 15.779 ; 15.779 ;        ;
; SCSI_IOn     ; CD[3]         ; 19.203 ; 19.203 ; 19.203 ; 19.203 ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 18.372 ; 18.372 ; 18.372 ; 18.372 ;
; SCSI_IOn     ; SCSI_D[0]     ; 17.021 ; 17.021 ; 17.021 ; 17.021 ;
; SCSI_IOn     ; SCSI_D[1]     ; 17.021 ; 17.021 ; 17.021 ; 17.021 ;
; SCSI_IOn     ; SCSI_D[2]     ; 17.014 ; 17.014 ; 17.014 ; 17.014 ;
; SCSI_IOn     ; SCSI_D[3]     ; 17.014 ; 17.014 ; 17.014 ; 17.014 ;
; SCSI_IOn     ; SCSI_D[4]     ; 17.348 ; 17.348 ; 17.348 ; 17.348 ;
; SCSI_IOn     ; SCSI_D[5]     ; 17.348 ; 17.348 ; 17.348 ; 17.348 ;
; SCSI_IOn     ; SCSI_D[6]     ; 17.623 ; 17.623 ; 17.623 ; 17.623 ;
; SCSI_IOn     ; SCSI_D[7]     ; 17.623 ; 17.623 ; 17.623 ; 17.623 ;
; SCSI_IOn     ; SCSI_DP       ; 17.031 ; 17.031 ; 17.031 ; 17.031 ;
; SCSI_IOn     ; SCSI_RDn      ; 14.482 ;        ;        ; 14.482 ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 14.079 ; 14.079 ;        ;
; SCSI_MSGn    ; CD[3]         ; 18.228 ; 18.228 ; 18.228 ; 18.228 ;
; SCSI_MSGn    ; CD[4]         ; 17.647 ; 17.647 ; 17.647 ; 17.647 ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 17.397 ; 17.397 ; 17.397 ; 17.397 ;
; SCSI_MSGn    ; SCSI_D[0]     ; 16.046 ; 16.046 ; 16.046 ; 16.046 ;
; SCSI_MSGn    ; SCSI_D[1]     ; 16.046 ; 16.046 ; 16.046 ; 16.046 ;
; SCSI_MSGn    ; SCSI_D[2]     ; 16.039 ; 16.039 ; 16.039 ; 16.039 ;
; SCSI_MSGn    ; SCSI_D[3]     ; 16.039 ; 16.039 ; 16.039 ; 16.039 ;
; SCSI_MSGn    ; SCSI_D[4]     ; 16.373 ; 16.373 ; 16.373 ; 16.373 ;
; SCSI_MSGn    ; SCSI_D[5]     ; 16.373 ; 16.373 ; 16.373 ; 16.373 ;
; SCSI_MSGn    ; SCSI_D[6]     ; 16.648 ; 16.648 ; 16.648 ; 16.648 ;
; SCSI_MSGn    ; SCSI_D[7]     ; 16.648 ; 16.648 ; 16.648 ; 16.648 ;
; SCSI_MSGn    ; SCSI_DP       ; 16.056 ; 16.056 ; 16.056 ; 16.056 ;
; SCSI_REQn    ; CD[3]         ; 18.599 ; 18.599 ; 18.599 ; 18.599 ;
; SCSI_REQn    ; CD[5]         ; 17.150 ; 17.150 ; 17.150 ; 17.150 ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 17.768 ;        ;        ; 17.768 ;
; SCSI_REQn    ; SCSI_D[0]     ; 16.417 ; 16.417 ; 16.417 ; 16.417 ;
; SCSI_REQn    ; SCSI_D[1]     ; 16.417 ; 16.417 ; 16.417 ; 16.417 ;
; SCSI_REQn    ; SCSI_D[2]     ; 16.410 ; 16.410 ; 16.410 ; 16.410 ;
; SCSI_REQn    ; SCSI_D[3]     ; 16.410 ; 16.410 ; 16.410 ; 16.410 ;
; SCSI_REQn    ; SCSI_D[4]     ; 16.744 ; 16.744 ; 16.744 ; 16.744 ;
; SCSI_REQn    ; SCSI_D[5]     ; 16.744 ; 16.744 ; 16.744 ; 16.744 ;
; SCSI_REQn    ; SCSI_D[6]     ; 17.019 ; 17.019 ; 17.019 ; 17.019 ;
; SCSI_REQn    ; SCSI_D[7]     ; 17.019 ; 17.019 ; 17.019 ; 17.019 ;
; SCSI_REQn    ; SCSI_DP       ; 16.427 ; 16.427 ; 16.427 ; 16.427 ;
; SCSI_RSTn    ; CD[7]         ;        ; 16.793 ; 16.793 ;        ;
; SCSI_SELn    ; CD[1]         ; 15.091 ; 15.091 ; 15.091 ; 15.091 ;
; SD_AVR_ENn   ; RESETn        ;        ; 16.134 ; 16.134 ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 13.868 ; 13.868 ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 15.607 ; 15.607 ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 13.293 ;        ;        ; 13.293 ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 13.484 ;        ;        ; 13.484 ;
; SD_RESETn    ; ACSI_RDn      ; 20.379 ; 20.379 ; 20.379 ; 20.379 ;
; SD_RESETn    ; ACSI_WRn      ; 20.388 ; 20.388 ; 20.388 ; 20.388 ;
; SD_RESETn    ; CA1_OUT       ; 19.259 ;        ;        ; 19.259 ;
; SD_RESETn    ; CD[0]         ; 25.824 ; 25.824 ; 25.824 ; 25.824 ;
; SD_RESETn    ; CD[1]         ; 26.240 ; 26.240 ; 26.240 ; 26.240 ;
; SD_RESETn    ; CD[2]         ; 25.329 ; 25.329 ; 25.329 ; 25.329 ;
; SD_RESETn    ; CD[3]         ; 29.267 ; 29.267 ; 29.267 ; 29.267 ;
; SD_RESETn    ; CD[4]         ; 29.271 ; 29.271 ; 29.271 ; 29.271 ;
; SD_RESETn    ; CD[5]         ; 29.911 ; 29.911 ; 29.911 ; 29.911 ;
; SD_RESETn    ; CD[6]         ; 29.857 ; 29.857 ; 29.857 ; 29.857 ;
; SD_RESETn    ; CD[7]         ; 25.613 ; 25.613 ; 25.613 ; 25.613 ;
; SD_RESETn    ; COM_TxD       ; 21.253 ; 21.253 ; 21.253 ; 21.253 ;
; SD_RESETn    ; DATA[0]       ; 27.921 ; 28.253 ; 28.253 ; 27.921 ;
; SD_RESETn    ; DATA[1]       ; 29.373 ; 29.373 ; 29.373 ; 29.373 ;
; SD_RESETn    ; DATA[2]       ; 28.168 ; 28.168 ; 28.168 ; 28.168 ;
; SD_RESETn    ; DATA[3]       ; 27.521 ; 27.521 ; 27.521 ; 27.521 ;
; SD_RESETn    ; DATA[4]       ; 27.461 ; 27.803 ; 27.803 ; 27.461 ;
; SD_RESETn    ; DATA[5]       ; 29.463 ; 29.463 ; 29.463 ; 29.463 ;
; SD_RESETn    ; DATA[6]       ; 29.200 ; 29.105 ; 29.105 ; 29.200 ;
; SD_RESETn    ; DATA[7]       ; 29.677 ; 29.745 ; 29.745 ; 29.677 ;
; SD_RESETn    ; DATA[8]       ; 24.867 ; 26.442 ; 26.442 ; 24.867 ;
; SD_RESETn    ; DATA[9]       ; 27.506 ; 27.682 ; 27.682 ; 27.506 ;
; SD_RESETn    ; DATA[10]      ; 21.875 ; 24.929 ; 24.929 ; 21.875 ;
; SD_RESETn    ; DATA[11]      ; 27.416 ; 28.132 ; 28.132 ; 27.416 ;
; SD_RESETn    ; DATA[12]      ; 26.478 ; 27.562 ; 27.562 ; 26.478 ;
; SD_RESETn    ; DATA[13]      ; 23.934 ; 26.052 ; 26.052 ; 23.934 ;
; SD_RESETn    ; DATA[14]      ; 22.924 ; 24.723 ; 24.723 ; 22.924 ;
; SD_RESETn    ; DATA[15]      ; 23.762 ; 25.391 ; 25.391 ; 23.762 ;
; SD_RESETn    ; DTACKn        ; 22.132 ; 22.132 ; 22.132 ; 22.132 ;
; SD_RESETn    ; RAM_DATA[0]   ; 29.205 ; 29.537 ; 29.537 ; 29.205 ;
; SD_RESETn    ; RAM_DATA[1]   ; 30.300 ; 30.300 ; 30.300 ; 30.300 ;
; SD_RESETn    ; RAM_DATA[2]   ; 28.918 ; 28.918 ; 28.918 ; 28.918 ;
; SD_RESETn    ; RAM_DATA[3]   ; 29.820 ; 29.820 ; 29.820 ; 29.820 ;
; SD_RESETn    ; RAM_DATA[4]   ; 29.710 ; 30.052 ; 30.052 ; 29.710 ;
; SD_RESETn    ; RAM_DATA[5]   ; 30.967 ; 30.967 ; 30.967 ; 30.967 ;
; SD_RESETn    ; RAM_DATA[6]   ; 29.936 ; 29.841 ; 29.841 ; 29.936 ;
; SD_RESETn    ; RAM_DATA[7]   ; 29.846 ; 29.914 ; 29.914 ; 29.846 ;
; SD_RESETn    ; RAM_DATA[8]   ; 24.828 ; 26.403 ; 26.403 ; 24.828 ;
; SD_RESETn    ; RAM_DATA[9]   ; 27.517 ; 27.693 ; 27.693 ; 27.517 ;
; SD_RESETn    ; RAM_DATA[10]  ; 23.085 ; 26.139 ; 26.139 ; 23.085 ;
; SD_RESETn    ; RAM_DATA[11]  ; 26.098 ; 26.814 ; 26.814 ; 26.098 ;
; SD_RESETn    ; RAM_DATA[12]  ; 26.144 ; 27.228 ; 27.228 ; 26.144 ;
; SD_RESETn    ; RAM_DATA[13]  ; 25.720 ; 27.838 ; 27.838 ; 25.720 ;
; SD_RESETn    ; RAM_DATA[14]  ; 25.051 ; 26.850 ; 26.850 ; 25.051 ;
; SD_RESETn    ; RAM_DATA[15]  ; 25.276 ; 26.905 ; 26.905 ; 25.276 ;
; UDSn         ; ACSI_RDn      ; 20.215 ; 20.215 ; 20.215 ; 20.215 ;
; UDSn         ; ACSI_WRn      ; 20.224 ; 20.224 ; 20.224 ; 20.224 ;
; UDSn         ; CA1_OUT       ; 19.095 ;        ;        ; 19.095 ;
; UDSn         ; CD[0]         ; 25.660 ; 25.660 ; 25.660 ; 25.660 ;
; UDSn         ; CD[1]         ; 26.076 ; 26.076 ; 26.076 ; 26.076 ;
; UDSn         ; CD[2]         ; 25.165 ; 25.165 ; 25.165 ; 25.165 ;
; UDSn         ; CD[3]         ; 29.103 ; 29.103 ; 29.103 ; 29.103 ;
; UDSn         ; CD[4]         ; 29.107 ; 29.107 ; 29.107 ; 29.107 ;
; UDSn         ; CD[5]         ; 29.747 ; 29.747 ; 29.747 ; 29.747 ;
; UDSn         ; CD[6]         ; 29.693 ; 29.693 ; 29.693 ; 29.693 ;
; UDSn         ; CD[7]         ; 25.449 ; 25.449 ; 25.449 ; 25.449 ;
; UDSn         ; DATA[0]       ; 29.281 ; 30.333 ; 30.333 ; 29.281 ;
; UDSn         ; DATA[1]       ; 32.143 ; 31.966 ; 31.966 ; 32.143 ;
; UDSn         ; DATA[2]       ; 29.612 ; 30.901 ; 30.901 ; 29.612 ;
; UDSn         ; DATA[3]       ; 29.701 ; 29.199 ; 29.199 ; 29.701 ;
; UDSn         ; DATA[4]       ; 28.572 ; 30.037 ; 30.037 ; 28.572 ;
; UDSn         ; DATA[5]       ; 31.289 ; 31.573 ; 31.573 ; 31.289 ;
; UDSn         ; DATA[6]       ; 30.495 ; 31.712 ; 31.712 ; 30.495 ;
; UDSn         ; DATA[7]       ; 32.372 ; 32.371 ; 32.371 ; 32.372 ;
; UDSn         ; DATA[8]       ; 32.423 ; 32.248 ; 32.248 ; 32.423 ;
; UDSn         ; DATA[9]       ; 32.891 ; 32.891 ; 32.891 ; 32.891 ;
; UDSn         ; DATA[10]      ; 30.219 ; 30.219 ; 30.219 ; 30.219 ;
; UDSn         ; DATA[11]      ; 32.991 ; 32.750 ; 32.750 ; 32.991 ;
; UDSn         ; DATA[12]      ; 32.823 ; 32.823 ; 32.823 ; 32.823 ;
; UDSn         ; DATA[13]      ; 30.681 ; 30.559 ; 30.559 ; 30.681 ;
; UDSn         ; DATA[14]      ; 30.240 ; 29.808 ; 29.808 ; 30.240 ;
; UDSn         ; DATA[15]      ; 31.102 ; 30.706 ; 30.706 ; 31.102 ;
; UDSn         ; DTACKn        ; 21.968 ; 21.968 ; 21.968 ; 21.968 ;
; UDSn         ; JOY_RHn       ; 14.783 ;        ;        ; 14.783 ;
; UDSn         ; RAM_CAS0n     ; 16.464 ;        ;        ; 16.464 ;
; UDSn         ; RAM_DATA[0]   ; 30.565 ; 31.617 ; 31.617 ; 30.565 ;
; UDSn         ; RAM_DATA[1]   ; 33.070 ; 32.893 ; 32.893 ; 33.070 ;
; UDSn         ; RAM_DATA[2]   ; 30.362 ; 31.651 ; 31.651 ; 30.362 ;
; UDSn         ; RAM_DATA[3]   ; 32.000 ; 31.498 ; 31.498 ; 32.000 ;
; UDSn         ; RAM_DATA[4]   ; 30.821 ; 32.286 ; 32.286 ; 30.821 ;
; UDSn         ; RAM_DATA[5]   ; 32.793 ; 33.077 ; 33.077 ; 32.793 ;
; UDSn         ; RAM_DATA[6]   ; 31.231 ; 32.448 ; 32.448 ; 31.231 ;
; UDSn         ; RAM_DATA[7]   ; 32.541 ; 32.540 ; 32.540 ; 32.541 ;
; UDSn         ; RAM_DATA[8]   ; 32.384 ; 32.209 ; 32.209 ; 32.384 ;
; UDSn         ; RAM_DATA[9]   ; 32.902 ; 32.902 ; 32.902 ; 32.902 ;
; UDSn         ; RAM_DATA[10]  ; 31.429 ; 31.429 ; 31.429 ; 31.429 ;
; UDSn         ; RAM_DATA[11]  ; 31.673 ; 31.432 ; 31.432 ; 31.673 ;
; UDSn         ; RAM_DATA[12]  ; 32.489 ; 32.489 ; 32.489 ; 32.489 ;
; UDSn         ; RAM_DATA[13]  ; 32.467 ; 32.345 ; 32.345 ; 32.467 ;
; UDSn         ; RAM_DATA[14]  ; 32.367 ; 31.935 ; 31.935 ; 32.367 ;
; UDSn         ; RAM_DATA[15]  ; 32.616 ; 32.220 ; 32.220 ; 32.616 ;
; UDSn         ; RAM_DQM0H     ; 14.860 ;        ;        ; 14.860 ;
+--------------+---------------+--------+--------+--------+--------+


+------------------------------------------------------------------+
; Minimum Propagation Delay                                        ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 20.839 ; 20.839 ; 20.839 ; 20.839 ;
; ASn          ; ACSI_WRn      ; 20.804 ; 20.804 ; 20.804 ; 20.804 ;
; ASn          ; BUTTONn       ; 20.989 ;        ;        ; 20.989 ;
; ASn          ; CA1_OUT       ; 19.839 ;        ;        ; 19.839 ;
; ASn          ; CD[0]         ; 22.417 ; 22.281 ; 22.281 ; 22.417 ;
; ASn          ; CD[1]         ; 22.319 ; 22.142 ; 22.142 ; 22.319 ;
; ASn          ; CD[2]         ; 20.224 ; 20.224 ; 20.224 ; 20.224 ;
; ASn          ; CD[3]         ; 22.769 ; 22.416 ; 22.416 ; 22.769 ;
; ASn          ; CD[4]         ; 21.079 ; 21.079 ; 21.079 ; 21.079 ;
; ASn          ; CD[5]         ; 21.058 ; 21.058 ; 21.058 ; 21.058 ;
; ASn          ; CD[6]         ; 21.430 ; 21.430 ; 21.430 ; 21.430 ;
; ASn          ; CD[7]         ; 20.582 ; 20.582 ; 20.582 ; 20.582 ;
; ASn          ; DATA[0]       ; 19.757 ; 19.757 ; 19.757 ; 19.757 ;
; ASn          ; DATA[1]       ; 19.757 ; 19.757 ; 19.757 ; 19.757 ;
; ASn          ; DATA[2]       ; 19.391 ; 19.391 ; 19.391 ; 19.391 ;
; ASn          ; DATA[3]       ; 19.391 ; 19.391 ; 19.391 ; 19.391 ;
; ASn          ; DATA[4]       ; 19.429 ; 19.429 ; 19.429 ; 19.429 ;
; ASn          ; DATA[5]       ; 19.429 ; 19.429 ; 19.429 ; 19.429 ;
; ASn          ; DATA[6]       ; 19.044 ; 19.044 ; 19.044 ; 19.044 ;
; ASn          ; DATA[7]       ; 19.034 ; 19.034 ; 19.034 ; 19.034 ;
; ASn          ; DATA[8]       ; 19.370 ; 19.370 ; 19.370 ; 19.370 ;
; ASn          ; DATA[9]       ; 19.370 ; 19.370 ; 19.370 ; 19.370 ;
; ASn          ; DATA[10]      ; 19.706 ; 19.706 ; 19.706 ; 19.706 ;
; ASn          ; DATA[11]      ; 19.706 ; 19.706 ; 19.706 ; 19.706 ;
; ASn          ; DATA[12]      ; 19.767 ; 19.767 ; 19.767 ; 19.767 ;
; ASn          ; DATA[13]      ; 19.767 ; 19.767 ; 19.767 ; 19.767 ;
; ASn          ; DATA[14]      ; 19.725 ; 19.725 ; 19.725 ; 19.725 ;
; ASn          ; DATA[15]      ; 19.715 ; 19.715 ; 19.715 ; 19.715 ;
; ASn          ; DTACKn        ; 16.368 ; 16.368 ; 16.368 ; 16.368 ;
; ASn          ; FLASH_CEn     ; 20.413 ;        ;        ; 20.413 ;
; ASn          ; FLASH_OEn     ; 19.619 ;        ;        ; 19.619 ;
; ASn          ; IDE_CS0n      ; 13.851 ;        ;        ; 13.851 ;
; ASn          ; IDE_CS1n      ; 12.631 ;        ;        ; 12.631 ;
; ASn          ; IDE_D_EN_INn  ; 14.492 ;        ;        ; 14.492 ;
; ASn          ; IDE_D_EN_OUTn ; 16.088 ;        ;        ; 16.088 ;
; ASn          ; IDE_IORDn     ; 15.733 ;        ;        ; 15.733 ;
; ASn          ; IDE_IOWRn     ; 15.394 ;        ;        ; 15.394 ;
; ASn          ; JOY_RHn       ; 14.716 ;        ;        ; 14.716 ;
; ASn          ; JOY_RLn       ; 14.957 ;        ;        ; 14.957 ;
; ASn          ; JOY_WEn       ;        ; 14.599 ; 14.599 ;        ;
; ASn          ; JOY_WL        ;        ; 14.871 ; 14.871 ;        ;
; ASn          ; RAM_DATA[0]   ; 23.233 ; 23.545 ; 23.545 ; 23.233 ;
; ASn          ; RAM_DATA[1]   ; 24.525 ; 24.335 ; 24.335 ; 24.525 ;
; ASn          ; RAM_DATA[2]   ; 22.974 ; 23.159 ; 23.159 ; 22.974 ;
; ASn          ; RAM_DATA[3]   ; 23.995 ; 24.317 ; 24.317 ; 23.995 ;
; ASn          ; RAM_DATA[4]   ; 23.988 ; 24.540 ; 24.540 ; 23.988 ;
; ASn          ; RAM_DATA[5]   ; 25.186 ; 24.950 ; 24.950 ; 25.186 ;
; ASn          ; RAM_DATA[6]   ; 23.441 ; 24.771 ; 24.771 ; 23.441 ;
; ASn          ; RAM_DATA[7]   ; 24.311 ; 25.086 ; 25.086 ; 24.311 ;
; ASn          ; RAM_DATA[8]   ; 22.612 ; 23.520 ; 23.520 ; 22.612 ;
; ASn          ; RAM_DATA[9]   ; 23.699 ; 24.281 ; 24.281 ; 23.699 ;
; ASn          ; RAM_DATA[10]  ; 22.424 ; 22.720 ; 22.720 ; 22.424 ;
; ASn          ; RAM_DATA[11]  ; 22.065 ; 22.680 ; 22.680 ; 22.065 ;
; ASn          ; RAM_DATA[12]  ; 22.192 ; 22.192 ; 22.192 ; 22.192 ;
; ASn          ; RAM_DATA[13]  ; 24.248 ; 24.680 ; 24.680 ; 24.248 ;
; ASn          ; RAM_DATA[14]  ; 23.658 ; 23.658 ; 23.658 ; 23.658 ;
; ASn          ; RAM_DATA[15]  ; 23.878 ; 23.657 ; 23.657 ; 23.878 ;
; ASn          ; ROM0n         ; 16.366 ;        ;        ; 16.366 ;
; ASn          ; ROM1n         ; 16.094 ;        ;        ; 16.094 ;
; ASn          ; ROM2n         ; 18.053 ;        ;        ; 18.053 ;
; ASn          ; ROM3n         ; 15.611 ;        ;        ; 15.611 ;
; ASn          ; ROM4n         ; 15.766 ;        ;        ; 15.766 ;
; ASn          ; ROM5n         ; 18.044 ;        ;        ; 18.044 ;
; ASn          ; ROM6n         ; 17.579 ;        ;        ; 17.579 ;
; COM_CTS      ; DATA[2]       ;        ; 24.709 ; 24.709 ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 25.459 ; 25.459 ;        ;
; COM_DCD      ; DATA[1]       ;        ; 26.470 ; 26.470 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 27.397 ; 27.397 ;        ;
; COM_RI       ; DATA[6]       ;        ; 24.094 ; 24.094 ;        ;
; COM_RI       ; RAM_DATA[6]   ;        ; 24.830 ; 24.830 ;        ;
; CONFIG[1]    ; DATA[7]       ; 26.655 ; 26.655 ; 26.655 ; 26.655 ;
; CONFIG[1]    ; HSYNC         ; 12.714 ; 12.714 ; 12.714 ; 12.714 ;
; CONFIG[1]    ; RAM_DATA[7]   ; 26.824 ; 26.824 ; 26.824 ; 26.824 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 15.729 ; 15.375 ; 15.375 ; 15.729 ;
; CONFIG[1]    ; RAM_DATA[13]  ; 16.401 ; 16.642 ; 16.642 ; 16.401 ;
; CONFIG[1]    ; RAM_DATA[14]  ; 15.994 ; 15.761 ; 15.761 ; 15.994 ;
; CONFIG[1]    ; RAM_DATA[15]  ; 15.088 ; 15.362 ; 15.362 ; 15.088 ;
; CONFIG[1]    ; VSYNC         ; 12.351 ; 12.351 ; 12.351 ; 12.351 ;
; CONFIG[2]    ; DATA[7]       ; 26.519 ; 26.519 ; 26.519 ; 26.519 ;
; CONFIG[2]    ; HSYNC         ; 12.442 ; 12.442 ; 12.442 ; 12.442 ;
; CONFIG[2]    ; RAM_DATA[7]   ; 26.688 ; 26.688 ; 26.688 ; 26.688 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 14.767 ; 15.121 ; 15.121 ; 14.767 ;
; CONFIG[2]    ; RAM_DATA[13]  ; 16.034 ; 15.793 ; 15.793 ; 16.034 ;
; CONFIG[2]    ; RAM_DATA[14]  ; 15.153 ; 15.386 ; 15.386 ; 15.153 ;
; CONFIG[2]    ; RAM_DATA[15]  ; 14.754 ; 14.480 ; 14.480 ; 14.754 ;
; CONFIG[2]    ; VSYNC         ; 12.094 ; 12.094 ; 12.094 ; 12.094 ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 17.486 ; 17.486 ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 14.935 ; 14.935 ;        ;
; CONFIG[6]    ; DATA[0]       ; 21.274 ; 21.274 ; 21.274 ; 21.274 ;
; CONFIG[6]    ; DATA[1]       ; 22.418 ; 22.418 ; 22.418 ; 22.418 ;
; CONFIG[6]    ; DATA[2]       ; 21.922 ; 21.922 ; 21.922 ; 21.922 ;
; CONFIG[6]    ; DATA[3]       ; 22.002 ; 22.351 ; 22.351 ; 22.002 ;
; CONFIG[6]    ; DATA[4]       ; 22.922 ; 22.573 ; 22.573 ; 22.922 ;
; CONFIG[6]    ; DATA[5]       ; 24.513 ; 24.164 ; 24.164 ; 24.513 ;
; CONFIG[6]    ; DATA[6]       ; 24.655 ; 24.306 ; 24.306 ; 24.655 ;
; CONFIG[6]    ; DATA[7]       ; 24.849 ; 24.500 ; 24.500 ; 24.849 ;
; CONFIG[6]    ; DATA[8]       ; 24.046 ; 24.395 ; 24.395 ; 24.046 ;
; CONFIG[6]    ; DATA[9]       ; 25.574 ; 25.586 ; 25.586 ; 25.574 ;
; CONFIG[6]    ; DATA[10]      ; 22.825 ; 22.476 ; 22.476 ; 22.825 ;
; CONFIG[6]    ; DATA[11]      ; 25.536 ; 25.362 ; 25.362 ; 25.536 ;
; CONFIG[6]    ; DATA[12]      ; 24.520 ; 24.171 ; 24.171 ; 24.520 ;
; CONFIG[6]    ; DATA[13]      ; 22.910 ; 22.561 ; 22.561 ; 22.910 ;
; CONFIG[6]    ; DATA[14]      ; 22.131 ; 22.105 ; 22.105 ; 22.131 ;
; CONFIG[6]    ; DATA[15]      ; 22.870 ; 22.521 ; 22.521 ; 22.870 ;
; CONFIG[6]    ; DTACKn        ; 18.671 ; 18.671 ; 18.671 ; 18.671 ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 16.100 ; 16.100 ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 16.489 ; 16.489 ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 18.429 ; 18.080 ; 18.080 ; 18.429 ;
; CONFIG[6]    ; FLASH_OEn     ; 17.635 ; 17.286 ; 17.286 ; 17.635 ;
; CONFIG[6]    ; RAM_DATA[0]   ; 22.558 ; 22.558 ; 22.558 ; 22.558 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 23.345 ; 23.345 ; 23.345 ; 23.345 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 22.672 ; 22.672 ; 22.672 ; 22.672 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 24.301 ; 24.650 ; 24.650 ; 24.301 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 25.171 ; 24.822 ; 24.822 ; 25.171 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 26.017 ; 25.668 ; 25.668 ; 26.017 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 25.391 ; 25.042 ; 25.042 ; 25.391 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 25.018 ; 24.669 ; 24.669 ; 25.018 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 24.007 ; 24.356 ; 24.356 ; 24.007 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 25.585 ; 25.597 ; 25.597 ; 25.585 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 24.035 ; 23.686 ; 23.686 ; 24.035 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 24.218 ; 24.044 ; 24.044 ; 24.218 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 24.186 ; 23.837 ; 23.837 ; 24.186 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 24.696 ; 24.347 ; 24.347 ; 24.696 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 24.258 ; 24.232 ; 24.232 ; 24.258 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 24.384 ; 24.035 ; 24.035 ; 24.384 ;
; CONFIG[6]    ; ROM2n         ; 16.069 ; 15.720 ; 15.720 ; 16.069 ;
; CRT_PIN3     ; DATA[7]       ; 23.321 ; 23.321 ; 23.321 ; 23.321 ;
; CRT_PIN3     ; RAM_DATA[7]   ; 23.490 ; 23.490 ; 23.490 ; 23.490 ;
; CRT_PIN3     ; RAM_DATA[12]  ; 12.419 ; 12.065 ; 12.065 ; 12.419 ;
; CRT_PIN3     ; RAM_DATA[13]  ; 13.091 ; 13.332 ; 13.332 ; 13.091 ;
; CRT_PIN3     ; RAM_DATA[14]  ; 12.684 ; 12.451 ; 12.451 ; 12.684 ;
; CRT_PIN3     ; RAM_DATA[15]  ; 11.778 ; 12.052 ; 12.052 ; 11.778 ;
; DATA[0]      ; DATA[0]       ; 15.866 ;        ;        ; 15.866 ;
; DATA[0]      ; RAM_DATA[0]   ; 17.150 ;        ;        ; 17.150 ;
; DATA[1]      ; DATA[1]       ; 18.126 ;        ;        ; 18.126 ;
; DATA[1]      ; RAM_DATA[1]   ; 19.053 ;        ;        ; 19.053 ;
; DATA[2]      ; DATA[2]       ; 17.076 ;        ;        ; 17.076 ;
; DATA[2]      ; RAM_DATA[2]   ; 17.826 ;        ;        ; 17.826 ;
; DATA[3]      ; DATA[3]       ; 16.170 ;        ;        ; 16.170 ;
; DATA[3]      ; RAM_DATA[3]   ; 18.469 ;        ;        ; 18.469 ;
; DATA[4]      ; DATA[4]       ; 16.069 ;        ;        ; 16.069 ;
; DATA[4]      ; RAM_DATA[4]   ; 18.318 ;        ;        ; 18.318 ;
; DATA[5]      ; DATA[5]       ; 17.844 ;        ;        ; 17.844 ;
; DATA[5]      ; RAM_DATA[5]   ; 19.348 ;        ;        ; 19.348 ;
; DATA[6]      ; DATA[6]       ; 18.104 ;        ;        ; 18.104 ;
; DATA[6]      ; RAM_DATA[6]   ; 18.840 ;        ;        ; 18.840 ;
; DATA[7]      ; DATA[7]       ; 18.247 ;        ;        ; 18.247 ;
; DATA[7]      ; RAM_DATA[7]   ; 18.416 ;        ;        ; 18.416 ;
; DATA[8]      ; DATA[8]       ; 17.409 ;        ;        ; 17.409 ;
; DATA[8]      ; RAM_DATA[8]   ; 17.370 ;        ;        ; 17.370 ;
; DATA[9]      ; DATA[9]       ; 19.218 ;        ;        ; 19.218 ;
; DATA[9]      ; RAM_DATA[9]   ; 19.229 ;        ;        ; 19.229 ;
; DATA[10]     ; DATA[10]      ; 16.185 ;        ;        ; 16.185 ;
; DATA[10]     ; RAM_DATA[10]  ; 17.395 ;        ;        ; 17.395 ;
; DATA[11]     ; DATA[11]      ; 19.297 ;        ;        ; 19.297 ;
; DATA[11]     ; RAM_DATA[11]  ; 17.979 ;        ;        ; 17.979 ;
; DATA[12]     ; DATA[12]      ; 17.862 ;        ;        ; 17.862 ;
; DATA[12]     ; RAM_DATA[12]  ; 17.528 ;        ;        ; 17.528 ;
; DATA[13]     ; DATA[13]      ; 15.952 ;        ;        ; 15.952 ;
; DATA[13]     ; RAM_DATA[13]  ; 17.738 ;        ;        ; 17.738 ;
; DATA[14]     ; DATA[14]      ; 15.160 ;        ;        ; 15.160 ;
; DATA[14]     ; RAM_DATA[14]  ; 17.287 ;        ;        ; 17.287 ;
; DATA[15]     ; DATA[15]      ; 15.812 ;        ;        ; 15.812 ;
; DATA[15]     ; RAM_DATA[15]  ; 17.326 ;        ;        ; 17.326 ;
; FC[0]        ; ACSI_RDn      ; 20.044 ; 20.044 ; 20.044 ; 20.044 ;
; FC[0]        ; ACSI_WRn      ; 20.009 ; 20.009 ; 20.009 ; 20.009 ;
; FC[0]        ; BUTTONn       ; 16.891 ; 16.891 ; 16.891 ; 16.891 ;
; FC[0]        ; CA1_OUT       ; 19.044 ; 19.044 ; 19.044 ; 19.044 ;
; FC[0]        ; CD[0]         ; 21.486 ; 21.486 ; 21.486 ; 21.486 ;
; FC[0]        ; CD[1]         ; 21.347 ; 21.347 ; 21.347 ; 21.347 ;
; FC[0]        ; CD[2]         ; 19.429 ; 19.429 ; 19.429 ; 19.429 ;
; FC[0]        ; CD[3]         ; 21.621 ; 21.621 ; 21.621 ; 21.621 ;
; FC[0]        ; CD[4]         ; 20.284 ; 20.284 ; 20.284 ; 20.284 ;
; FC[0]        ; CD[5]         ; 20.263 ; 20.263 ; 20.263 ; 20.263 ;
; FC[0]        ; CD[6]         ; 20.635 ; 20.635 ; 20.635 ; 20.635 ;
; FC[0]        ; CD[7]         ; 19.787 ; 19.787 ; 19.787 ; 19.787 ;
; FC[0]        ; DATA[0]       ; 21.152 ; 21.152 ; 21.152 ; 21.152 ;
; FC[0]        ; DATA[1]       ; 22.873 ; 22.873 ; 22.873 ; 22.873 ;
; FC[0]        ; DATA[2]       ; 21.720 ; 21.720 ; 21.720 ; 21.720 ;
; FC[0]        ; DATA[3]       ; 21.115 ; 21.115 ; 21.115 ; 21.115 ;
; FC[0]        ; DATA[4]       ; 21.158 ; 21.158 ; 21.158 ; 21.158 ;
; FC[0]        ; DATA[5]       ; 23.101 ; 23.101 ; 23.101 ; 23.101 ;
; FC[0]        ; DATA[6]       ; 22.863 ; 22.863 ; 22.863 ; 22.863 ;
; FC[0]        ; DATA[7]       ; 24.035 ; 24.035 ; 24.035 ; 24.035 ;
; FC[0]        ; DATA[8]       ; 23.066 ; 23.066 ; 23.066 ; 23.066 ;
; FC[0]        ; DATA[9]       ; 24.173 ; 24.173 ; 24.173 ; 24.173 ;
; FC[0]        ; DATA[10]      ; 20.990 ; 20.990 ; 20.990 ; 20.990 ;
; FC[0]        ; DATA[11]      ; 24.244 ; 24.244 ; 24.244 ; 24.244 ;
; FC[0]        ; DATA[12]      ; 22.480 ; 22.480 ; 22.480 ; 22.480 ;
; FC[0]        ; DATA[13]      ; 21.881 ; 21.881 ; 21.881 ; 21.881 ;
; FC[0]        ; DATA[14]      ; 21.095 ; 21.095 ; 21.095 ; 21.095 ;
; FC[0]        ; DATA[15]      ; 21.783 ; 21.783 ; 21.783 ; 21.783 ;
; FC[0]        ; DTACKn        ; 18.415 ; 18.415 ; 18.415 ; 18.415 ;
; FC[0]        ; FLASH_CEn     ; 20.033 ; 20.033 ; 20.033 ; 20.033 ;
; FC[0]        ; FLASH_OEn     ; 19.239 ; 19.239 ; 19.239 ; 19.239 ;
; FC[0]        ; JOY_RHn       ; 17.488 ; 17.488 ; 17.488 ; 17.488 ;
; FC[0]        ; JOY_RLn       ; 17.729 ; 17.729 ; 17.729 ; 17.729 ;
; FC[0]        ; JOY_WEn       ; 17.371 ; 17.371 ; 17.371 ; 17.371 ;
; FC[0]        ; JOY_WL        ; 17.643 ; 17.643 ; 17.643 ; 17.643 ;
; FC[0]        ; RAM_DATA[0]   ; 22.436 ; 22.436 ; 22.436 ; 22.436 ;
; FC[0]        ; RAM_DATA[1]   ; 23.800 ; 23.800 ; 23.800 ; 23.800 ;
; FC[0]        ; RAM_DATA[2]   ; 22.470 ; 22.470 ; 22.470 ; 22.470 ;
; FC[0]        ; RAM_DATA[3]   ; 23.414 ; 23.414 ; 23.414 ; 23.414 ;
; FC[0]        ; RAM_DATA[4]   ; 23.407 ; 23.407 ; 23.407 ; 23.407 ;
; FC[0]        ; RAM_DATA[5]   ; 24.605 ; 24.605 ; 24.605 ; 24.605 ;
; FC[0]        ; RAM_DATA[6]   ; 23.599 ; 23.599 ; 23.599 ; 23.599 ;
; FC[0]        ; RAM_DATA[7]   ; 24.204 ; 24.204 ; 24.204 ; 24.204 ;
; FC[0]        ; RAM_DATA[8]   ; 23.027 ; 23.027 ; 23.027 ; 23.027 ;
; FC[0]        ; RAM_DATA[9]   ; 24.184 ; 24.184 ; 24.184 ; 24.184 ;
; FC[0]        ; RAM_DATA[10]  ; 22.200 ; 22.200 ; 22.200 ; 22.200 ;
; FC[0]        ; RAM_DATA[11]  ; 22.926 ; 22.926 ; 22.926 ; 22.926 ;
; FC[0]        ; RAM_DATA[12]  ; 22.146 ; 22.146 ; 22.146 ; 22.146 ;
; FC[0]        ; RAM_DATA[13]  ; 23.667 ; 23.667 ; 23.667 ; 23.667 ;
; FC[0]        ; RAM_DATA[14]  ; 23.222 ; 23.222 ; 23.222 ; 23.222 ;
; FC[0]        ; RAM_DATA[15]  ; 23.297 ; 23.297 ; 23.297 ; 23.297 ;
; FC[0]        ; ROM0n         ; 15.986 ; 15.986 ; 15.986 ; 15.986 ;
; FC[0]        ; ROM1n         ; 15.714 ; 15.714 ; 15.714 ; 15.714 ;
; FC[0]        ; ROM2n         ; 17.673 ; 17.673 ; 17.673 ; 17.673 ;
; FC[0]        ; ROM3n         ; 15.231 ; 15.231 ; 15.231 ; 15.231 ;
; FC[0]        ; ROM4n         ; 15.386 ; 15.386 ; 15.386 ; 15.386 ;
; FC[0]        ; ROM5n         ; 17.664 ; 17.664 ; 17.664 ; 17.664 ;
; FC[0]        ; ROM6n         ; 17.199 ; 17.199 ; 17.199 ; 17.199 ;
; FC[1]        ; ACSI_RDn      ; 20.016 ; 20.016 ; 20.016 ; 20.016 ;
; FC[1]        ; ACSI_WRn      ; 19.981 ; 19.981 ; 19.981 ; 19.981 ;
; FC[1]        ; BUTTONn       ; 16.619 ; 16.619 ; 16.619 ; 16.619 ;
; FC[1]        ; CA1_OUT       ; 19.016 ; 19.016 ; 19.016 ; 19.016 ;
; FC[1]        ; CD[0]         ; 21.458 ; 21.458 ; 21.458 ; 21.458 ;
; FC[1]        ; CD[1]         ; 21.319 ; 21.319 ; 21.319 ; 21.319 ;
; FC[1]        ; CD[2]         ; 19.401 ; 19.401 ; 19.401 ; 19.401 ;
; FC[1]        ; CD[3]         ; 21.593 ; 21.593 ; 21.593 ; 21.593 ;
; FC[1]        ; CD[4]         ; 20.256 ; 20.256 ; 20.256 ; 20.256 ;
; FC[1]        ; CD[5]         ; 20.235 ; 20.235 ; 20.235 ; 20.235 ;
; FC[1]        ; CD[6]         ; 20.607 ; 20.607 ; 20.607 ; 20.607 ;
; FC[1]        ; CD[7]         ; 19.759 ; 19.759 ; 19.759 ; 19.759 ;
; FC[1]        ; DATA[0]       ; 21.124 ; 21.124 ; 21.124 ; 21.124 ;
; FC[1]        ; DATA[1]       ; 22.845 ; 22.845 ; 22.845 ; 22.845 ;
; FC[1]        ; DATA[2]       ; 21.692 ; 21.692 ; 21.692 ; 21.692 ;
; FC[1]        ; DATA[3]       ; 21.087 ; 21.087 ; 21.087 ; 21.087 ;
; FC[1]        ; DATA[4]       ; 21.130 ; 21.130 ; 21.130 ; 21.130 ;
; FC[1]        ; DATA[5]       ; 23.073 ; 23.073 ; 23.073 ; 23.073 ;
; FC[1]        ; DATA[6]       ; 22.835 ; 22.835 ; 22.835 ; 22.835 ;
; FC[1]        ; DATA[7]       ; 24.007 ; 24.007 ; 24.007 ; 24.007 ;
; FC[1]        ; DATA[8]       ; 23.027 ; 23.027 ; 23.027 ; 23.027 ;
; FC[1]        ; DATA[9]       ; 24.134 ; 24.134 ; 24.134 ; 24.134 ;
; FC[1]        ; DATA[10]      ; 20.962 ; 20.962 ; 20.962 ; 20.962 ;
; FC[1]        ; DATA[11]      ; 23.999 ; 23.999 ; 23.999 ; 23.999 ;
; FC[1]        ; DATA[12]      ; 22.452 ; 22.452 ; 22.452 ; 22.452 ;
; FC[1]        ; DATA[13]      ; 21.853 ; 21.853 ; 21.853 ; 21.853 ;
; FC[1]        ; DATA[14]      ; 21.067 ; 21.067 ; 21.067 ; 21.067 ;
; FC[1]        ; DATA[15]      ; 21.755 ; 21.755 ; 21.755 ; 21.755 ;
; FC[1]        ; DTACKn        ; 18.547 ; 18.547 ; 18.547 ; 18.547 ;
; FC[1]        ; FLASH_CEn     ; 20.293 ; 20.293 ; 20.293 ; 20.293 ;
; FC[1]        ; FLASH_OEn     ; 19.499 ; 19.499 ; 19.499 ; 19.499 ;
; FC[1]        ; JOY_RHn       ; 17.460 ; 17.460 ; 17.460 ; 17.460 ;
; FC[1]        ; JOY_RLn       ; 17.701 ; 17.701 ; 17.701 ; 17.701 ;
; FC[1]        ; JOY_WEn       ; 17.343 ; 17.343 ; 17.343 ; 17.343 ;
; FC[1]        ; JOY_WL        ; 17.615 ; 17.615 ; 17.615 ; 17.615 ;
; FC[1]        ; RAM_DATA[0]   ; 22.408 ; 22.408 ; 22.408 ; 22.408 ;
; FC[1]        ; RAM_DATA[1]   ; 23.772 ; 23.772 ; 23.772 ; 23.772 ;
; FC[1]        ; RAM_DATA[2]   ; 22.442 ; 22.442 ; 22.442 ; 22.442 ;
; FC[1]        ; RAM_DATA[3]   ; 23.386 ; 23.386 ; 23.386 ; 23.386 ;
; FC[1]        ; RAM_DATA[4]   ; 23.379 ; 23.379 ; 23.379 ; 23.379 ;
; FC[1]        ; RAM_DATA[5]   ; 24.577 ; 24.577 ; 24.577 ; 24.577 ;
; FC[1]        ; RAM_DATA[6]   ; 23.571 ; 23.571 ; 23.571 ; 23.571 ;
; FC[1]        ; RAM_DATA[7]   ; 24.176 ; 24.176 ; 24.176 ; 24.176 ;
; FC[1]        ; RAM_DATA[8]   ; 22.988 ; 22.988 ; 22.988 ; 22.988 ;
; FC[1]        ; RAM_DATA[9]   ; 24.145 ; 24.145 ; 24.145 ; 24.145 ;
; FC[1]        ; RAM_DATA[10]  ; 22.172 ; 22.172 ; 22.172 ; 22.172 ;
; FC[1]        ; RAM_DATA[11]  ; 22.681 ; 22.681 ; 22.681 ; 22.681 ;
; FC[1]        ; RAM_DATA[12]  ; 22.118 ; 22.118 ; 22.118 ; 22.118 ;
; FC[1]        ; RAM_DATA[13]  ; 23.639 ; 23.639 ; 23.639 ; 23.639 ;
; FC[1]        ; RAM_DATA[14]  ; 23.194 ; 23.194 ; 23.194 ; 23.194 ;
; FC[1]        ; RAM_DATA[15]  ; 23.269 ; 23.269 ; 23.269 ; 23.269 ;
; FC[1]        ; ROM0n         ; 16.246 ; 16.246 ; 16.246 ; 16.246 ;
; FC[1]        ; ROM1n         ; 15.974 ; 15.974 ; 15.974 ; 15.974 ;
; FC[1]        ; ROM2n         ; 17.933 ; 17.933 ; 17.933 ; 17.933 ;
; FC[1]        ; ROM3n         ; 15.491 ; 15.491 ; 15.491 ; 15.491 ;
; FC[1]        ; ROM4n         ; 15.646 ; 15.646 ; 15.646 ; 15.646 ;
; FC[1]        ; ROM5n         ; 17.924 ; 17.924 ; 17.924 ; 17.924 ;
; FC[1]        ; ROM6n         ; 17.459 ; 17.459 ; 17.459 ; 17.459 ;
; FC[2]        ; ACSI_RDn      ; 19.960 ; 19.960 ; 19.960 ; 19.960 ;
; FC[2]        ; ACSI_WRn      ; 19.925 ; 19.925 ; 19.925 ; 19.925 ;
; FC[2]        ; CA1_OUT       ;        ; 18.960 ; 18.960 ;        ;
; FC[2]        ; CD[0]         ; 21.402 ; 21.538 ; 21.538 ; 21.402 ;
; FC[2]        ; CD[1]         ; 21.263 ; 21.440 ; 21.440 ; 21.263 ;
; FC[2]        ; CD[2]         ; 19.345 ; 19.345 ; 19.345 ; 19.345 ;
; FC[2]        ; CD[3]         ; 21.537 ; 21.890 ; 21.890 ; 21.537 ;
; FC[2]        ; CD[4]         ; 20.200 ; 20.200 ; 20.200 ; 20.200 ;
; FC[2]        ; CD[5]         ; 20.179 ; 20.179 ; 20.179 ; 20.179 ;
; FC[2]        ; CD[6]         ; 20.551 ; 20.551 ; 20.551 ; 20.551 ;
; FC[2]        ; CD[7]         ; 19.703 ; 19.703 ; 19.703 ; 19.703 ;
; FC[2]        ; DATA[0]       ; 22.085 ; 21.068 ; 21.068 ; 22.085 ;
; FC[2]        ; DATA[1]       ; 23.295 ; 22.789 ; 22.789 ; 23.295 ;
; FC[2]        ; DATA[2]       ; 26.031 ; 21.636 ; 21.636 ; 26.031 ;
; FC[2]        ; DATA[3]       ; 25.031 ; 21.031 ; 21.031 ; 25.031 ;
; FC[2]        ; DATA[4]       ; 24.870 ; 21.074 ; 21.074 ; 24.870 ;
; FC[2]        ; DATA[5]       ; 26.732 ; 23.017 ; 23.017 ; 26.732 ;
; FC[2]        ; DATA[6]       ; 26.163 ; 22.779 ; 22.779 ; 26.163 ;
; FC[2]        ; DATA[7]       ; 27.277 ; 23.951 ; 23.951 ; 27.277 ;
; FC[2]        ; DATA[8]       ; 26.321 ; 23.400 ; 23.400 ; 26.321 ;
; FC[2]        ; DATA[9]       ; 27.561 ; 24.507 ; 24.507 ; 27.561 ;
; FC[2]        ; DATA[10]      ; 24.739 ; 20.906 ; 20.906 ; 24.739 ;
; FC[2]        ; DATA[11]      ; 27.195 ; 24.160 ; 24.160 ; 27.195 ;
; FC[2]        ; DATA[12]      ; 25.931 ; 22.396 ; 22.396 ; 25.931 ;
; FC[2]        ; DATA[13]      ; 25.759 ; 21.797 ; 21.797 ; 25.759 ;
; FC[2]        ; DATA[14]      ; 24.250 ; 21.011 ; 21.011 ; 24.250 ;
; FC[2]        ; DATA[15]      ; 25.270 ; 21.699 ; 21.699 ; 25.270 ;
; FC[2]        ; DTACKn        ; 19.054 ; 19.054 ; 19.054 ; 19.054 ;
; FC[2]        ; JOY_RHn       ;        ; 17.404 ; 17.404 ;        ;
; FC[2]        ; JOY_RLn       ;        ; 17.645 ; 17.645 ;        ;
; FC[2]        ; JOY_WEn       ; 17.287 ;        ;        ; 17.287 ;
; FC[2]        ; JOY_WL        ; 17.559 ;        ;        ; 17.559 ;
; FC[2]        ; RAM_DATA[0]   ; 23.369 ; 22.352 ; 22.352 ; 23.369 ;
; FC[2]        ; RAM_DATA[1]   ; 24.222 ; 23.716 ; 23.716 ; 24.222 ;
; FC[2]        ; RAM_DATA[2]   ; 26.781 ; 22.386 ; 22.386 ; 26.781 ;
; FC[2]        ; RAM_DATA[3]   ; 27.330 ; 23.330 ; 23.330 ; 27.330 ;
; FC[2]        ; RAM_DATA[4]   ; 27.119 ; 23.323 ; 23.323 ; 27.119 ;
; FC[2]        ; RAM_DATA[5]   ; 28.236 ; 24.521 ; 24.521 ; 28.236 ;
; FC[2]        ; RAM_DATA[6]   ; 26.899 ; 23.515 ; 23.515 ; 26.899 ;
; FC[2]        ; RAM_DATA[7]   ; 27.446 ; 24.120 ; 24.120 ; 27.446 ;
; FC[2]        ; RAM_DATA[8]   ; 26.282 ; 23.361 ; 23.361 ; 26.282 ;
; FC[2]        ; RAM_DATA[9]   ; 27.572 ; 24.518 ; 24.518 ; 27.572 ;
; FC[2]        ; RAM_DATA[10]  ; 25.949 ; 22.116 ; 22.116 ; 25.949 ;
; FC[2]        ; RAM_DATA[11]  ; 25.877 ; 22.842 ; 22.842 ; 25.877 ;
; FC[2]        ; RAM_DATA[12]  ; 25.597 ; 22.062 ; 22.062 ; 25.597 ;
; FC[2]        ; RAM_DATA[13]  ; 27.545 ; 23.583 ; 23.583 ; 27.545 ;
; FC[2]        ; RAM_DATA[14]  ; 26.377 ; 23.138 ; 23.138 ; 26.377 ;
; FC[2]        ; RAM_DATA[15]  ; 26.784 ; 23.213 ; 23.213 ; 26.784 ;
; HDINTn       ; DATA[5]       ; 24.851 ;        ;        ; 24.851 ;
; HDINTn       ; RAM_DATA[5]   ; 26.355 ;        ;        ; 26.355 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 24.592 ; 24.592 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 26.096 ; 26.096 ;        ;
; IDE_IORDY    ; DTACKn        ; 17.181 ; 17.181 ; 17.181 ; 17.181 ;
; LDSn         ; ACSI_RDn      ; 18.222 ; 18.222 ; 18.222 ; 18.222 ;
; LDSn         ; ACSI_WRn      ; 18.187 ; 18.187 ; 18.187 ; 18.187 ;
; LDSn         ; BUTTONn       ; 20.616 ;        ;        ; 20.616 ;
; LDSn         ; CA1_OUT       ; 17.222 ;        ;        ; 17.222 ;
; LDSn         ; CD[0]         ; 19.800 ; 19.664 ; 19.664 ; 19.800 ;
; LDSn         ; CD[1]         ; 19.702 ; 19.525 ; 19.525 ; 19.702 ;
; LDSn         ; CD[2]         ; 17.607 ; 17.607 ; 17.607 ; 17.607 ;
; LDSn         ; CD[3]         ; 20.152 ; 19.799 ; 19.799 ; 20.152 ;
; LDSn         ; CD[4]         ; 18.462 ; 18.462 ; 18.462 ; 18.462 ;
; LDSn         ; CD[5]         ; 18.441 ; 18.441 ; 18.441 ; 18.441 ;
; LDSn         ; CD[6]         ; 18.813 ; 18.813 ; 18.813 ; 18.813 ;
; LDSn         ; CD[7]         ; 17.965 ; 17.965 ; 17.965 ; 17.965 ;
; LDSn         ; DATA[0]       ; 21.779 ; 21.361 ; 21.361 ; 21.779 ;
; LDSn         ; DATA[1]       ; 22.189 ; 22.189 ; 22.189 ; 22.189 ;
; LDSn         ; DATA[2]       ; 21.823 ; 21.687 ; 21.687 ; 21.823 ;
; LDSn         ; DATA[3]       ; 20.609 ; 20.687 ; 20.687 ; 20.609 ;
; LDSn         ; DATA[4]       ; 20.876 ; 21.067 ; 21.067 ; 20.876 ;
; LDSn         ; DATA[5]       ; 21.861 ; 21.861 ; 21.861 ; 21.861 ;
; LDSn         ; DATA[6]       ; 21.476 ; 21.476 ; 21.476 ; 21.476 ;
; LDSn         ; DATA[7]       ; 21.466 ; 21.466 ; 21.466 ; 21.466 ;
; LDSn         ; DATA[8]       ; 21.802 ; 21.802 ; 21.802 ; 21.802 ;
; LDSn         ; DATA[9]       ; 21.802 ; 21.802 ; 21.802 ; 21.802 ;
; LDSn         ; DATA[10]      ; 19.838 ; 20.395 ; 20.395 ; 19.838 ;
; LDSn         ; DATA[11]      ; 22.138 ; 22.138 ; 22.138 ; 22.138 ;
; LDSn         ; DATA[12]      ; 22.199 ; 21.905 ; 21.905 ; 22.199 ;
; LDSn         ; DATA[13]      ; 21.897 ; 21.415 ; 21.415 ; 21.897 ;
; LDSn         ; DATA[14]      ; 20.887 ; 19.993 ; 19.993 ; 20.887 ;
; LDSn         ; DATA[15]      ; 21.725 ; 22.147 ; 22.147 ; 21.725 ;
; LDSn         ; DTACKn        ; 18.529 ; 18.529 ; 18.529 ; 18.529 ;
; LDSn         ; IDE_IORDn     ; 15.551 ;        ;        ; 15.551 ;
; LDSn         ; IDE_IOWRn     ; 15.211 ;        ;        ; 15.211 ;
; LDSn         ; JOY_RLn       ; 13.301 ;        ;        ; 13.301 ;
; LDSn         ; JOY_WEn       ;        ; 12.943 ; 12.943 ;        ;
; LDSn         ; JOY_WL        ;        ; 12.687 ; 12.687 ;        ;
; LDSn         ; RAM_CAS0n     ; 17.071 ;        ;        ; 17.071 ;
; LDSn         ; RAM_DATA[0]   ; 23.063 ; 22.645 ; 22.645 ; 23.063 ;
; LDSn         ; RAM_DATA[1]   ; 23.389 ; 23.138 ; 23.138 ; 23.389 ;
; LDSn         ; RAM_DATA[2]   ; 22.580 ; 22.437 ; 22.437 ; 22.580 ;
; LDSn         ; RAM_DATA[3]   ; 22.908 ; 22.986 ; 22.986 ; 22.908 ;
; LDSn         ; RAM_DATA[4]   ; 23.125 ; 23.316 ; 23.316 ; 23.125 ;
; LDSn         ; RAM_DATA[5]   ; 24.533 ; 25.066 ; 25.066 ; 24.533 ;
; LDSn         ; RAM_DATA[6]   ; 23.136 ; 23.783 ; 23.783 ; 23.136 ;
; LDSn         ; RAM_DATA[7]   ; 23.543 ; 24.077 ; 24.077 ; 23.543 ;
; LDSn         ; RAM_DATA[8]   ; 22.791 ; 22.873 ; 22.873 ; 22.791 ;
; LDSn         ; RAM_DATA[9]   ; 24.487 ; 24.030 ; 24.030 ; 24.487 ;
; LDSn         ; RAM_DATA[10]  ; 21.048 ; 21.605 ; 21.605 ; 21.048 ;
; LDSn         ; RAM_DATA[11]  ; 22.583 ; 21.620 ; 21.620 ; 22.583 ;
; LDSn         ; RAM_DATA[12]  ; 22.243 ; 21.571 ; 21.571 ; 22.243 ;
; LDSn         ; RAM_DATA[13]  ; 23.683 ; 23.201 ; 23.201 ; 23.683 ;
; LDSn         ; RAM_DATA[14]  ; 23.014 ; 22.120 ; 22.120 ; 23.014 ;
; LDSn         ; RAM_DATA[15]  ; 23.239 ; 24.069 ; 24.069 ; 23.239 ;
; LDSn         ; RAM_DQM0L     ; 14.828 ;        ;        ; 14.828 ;
; LPT_BSY      ; DATA[0]       ; 23.867 ;        ;        ; 23.867 ;
; LPT_BSY      ; RAM_DATA[0]   ; 25.151 ;        ;        ; 25.151 ;
; LPT_D[0]     ; DATA[8]       ; 22.459 ;        ;        ; 22.459 ;
; LPT_D[0]     ; RAM_DATA[8]   ; 22.420 ;        ;        ; 22.420 ;
; LPT_D[1]     ; DATA[9]       ; 23.036 ;        ;        ; 23.036 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 23.047 ;        ;        ; 23.047 ;
; LPT_D[2]     ; DATA[10]      ; 20.336 ;        ;        ; 20.336 ;
; LPT_D[2]     ; RAM_DATA[10]  ; 21.546 ;        ;        ; 21.546 ;
; LPT_D[3]     ; DATA[11]      ; 22.109 ;        ;        ; 22.109 ;
; LPT_D[3]     ; RAM_DATA[11]  ; 20.791 ;        ;        ; 20.791 ;
; LPT_D[4]     ; DATA[12]      ; 21.813 ;        ;        ; 21.813 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 21.479 ;        ;        ; 21.479 ;
; LPT_D[5]     ; DATA[13]      ; 21.231 ;        ;        ; 21.231 ;
; LPT_D[5]     ; RAM_DATA[13]  ; 23.017 ;        ;        ; 23.017 ;
; LPT_D[6]     ; DATA[14]      ; 19.723 ;        ;        ; 19.723 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 21.850 ;        ;        ; 21.850 ;
; LPT_D[7]     ; DATA[15]      ; 21.785 ;        ;        ; 21.785 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 23.299 ;        ;        ; 23.299 ;
; MIDI_IN      ; MIDI_TLR      ; 8.873  ;        ;        ; 8.873  ;
; RAM_DATA[0]  ; DATA[0]       ; 21.678 ;        ;        ; 21.678 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 22.962 ;        ;        ; 22.962 ;
; RAM_DATA[1]  ; DATA[1]       ; 22.554 ;        ;        ; 22.554 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 23.481 ;        ;        ; 23.481 ;
; RAM_DATA[2]  ; DATA[2]       ; 21.735 ;        ;        ; 21.735 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 22.485 ;        ;        ; 22.485 ;
; RAM_DATA[3]  ; DATA[3]       ; 21.236 ;        ;        ; 21.236 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 23.535 ;        ;        ; 23.535 ;
; RAM_DATA[4]  ; DATA[4]       ; 20.921 ;        ;        ; 20.921 ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 23.170 ;        ;        ; 23.170 ;
; RAM_DATA[5]  ; DATA[5]       ; 23.892 ;        ;        ; 23.892 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 25.396 ;        ;        ; 25.396 ;
; RAM_DATA[6]  ; DATA[6]       ; 25.412 ;        ;        ; 25.412 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 26.148 ;        ;        ; 26.148 ;
; RAM_DATA[7]  ; DATA[7]       ; 24.313 ;        ;        ; 24.313 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 24.482 ;        ;        ; 24.482 ;
; RAM_DATA[8]  ; DATA[8]       ; 23.496 ;        ;        ; 23.496 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 23.457 ;        ;        ; 23.457 ;
; RAM_DATA[9]  ; DATA[9]       ; 25.338 ;        ;        ; 25.338 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 25.349 ;        ;        ; 25.349 ;
; RAM_DATA[10] ; DATA[10]      ; 21.388 ;        ;        ; 21.388 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 22.598 ;        ;        ; 22.598 ;
; RAM_DATA[11] ; DATA[11]      ; 25.045 ;        ;        ; 25.045 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 23.727 ;        ;        ; 23.727 ;
; RAM_DATA[12] ; DATA[12]      ; 22.100 ;        ;        ; 22.100 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 21.766 ;        ;        ; 21.766 ;
; RAM_DATA[13] ; DATA[13]      ; 21.656 ;        ;        ; 21.656 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 23.442 ;        ;        ; 23.442 ;
; RAM_DATA[14] ; DATA[14]      ; 21.682 ;        ;        ; 21.682 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 23.809 ;        ;        ; 23.809 ;
; RAM_DATA[15] ; DATA[15]      ; 23.279 ;        ;        ; 23.279 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 24.793 ;        ;        ; 24.793 ;
; RWn          ; ACSI_RDn      ; 20.053 ; 14.669 ; 14.669 ; 20.053 ;
; RWn          ; ACSI_WRn      ; 14.634 ; 20.018 ; 20.018 ; 14.634 ;
; RWn          ; BUTTONn       ;        ; 16.692 ; 16.692 ;        ;
; RWn          ; CA1_OUT       ;        ; 19.053 ; 19.053 ;        ;
; RWn          ; CD[0]         ; 15.940 ; 15.633 ; 15.633 ; 15.940 ;
; RWn          ; CD[1]         ; 15.793 ; 15.494 ; 15.494 ; 15.793 ;
; RWn          ; CD[2]         ; 13.576 ; 13.576 ; 13.576 ; 13.576 ;
; RWn          ; CD[3]         ; 16.121 ; 15.768 ; 15.768 ; 16.121 ;
; RWn          ; CD[4]         ; 14.431 ; 14.431 ; 14.431 ; 14.431 ;
; RWn          ; CD[5]         ; 14.410 ; 14.410 ; 14.410 ; 14.410 ;
; RWn          ; CD[6]         ; 14.782 ; 14.782 ; 14.782 ; 14.782 ;
; RWn          ; CD[7]         ; 13.934 ; 13.934 ; 13.934 ; 13.934 ;
; RWn          ; DATA[0]       ; 18.844 ; 18.416 ; 18.416 ; 18.844 ;
; RWn          ; DATA[1]       ; 20.053 ; 20.053 ; 20.053 ; 20.053 ;
; RWn          ; DATA[2]       ; 19.351 ; 18.721 ; 18.721 ; 19.351 ;
; RWn          ; DATA[3]       ; 19.760 ; 17.997 ; 17.997 ; 19.760 ;
; RWn          ; DATA[4]       ; 19.597 ; 18.166 ; 18.166 ; 19.597 ;
; RWn          ; DATA[5]       ; 20.388 ; 20.109 ; 20.109 ; 20.388 ;
; RWn          ; DATA[6]       ; 20.977 ; 19.871 ; 19.871 ; 20.977 ;
; RWn          ; DATA[7]       ; 21.323 ; 20.909 ; 20.909 ; 21.323 ;
; RWn          ; DATA[8]       ; 20.586 ; 20.138 ; 20.138 ; 20.586 ;
; RWn          ; DATA[9]       ; 21.614 ; 20.751 ; 20.751 ; 21.614 ;
; RWn          ; DATA[10]      ; 17.346 ; 17.346 ; 17.346 ; 17.346 ;
; RWn          ; DATA[11]      ; 21.596 ; 20.769 ; 20.769 ; 21.596 ;
; RWn          ; DATA[12]      ; 20.477 ; 19.488 ; 19.488 ; 20.477 ;
; RWn          ; DATA[13]      ; 19.952 ; 18.692 ; 18.692 ; 19.952 ;
; RWn          ; DATA[14]      ; 18.637 ; 17.393 ; 17.393 ; 18.637 ;
; RWn          ; DATA[15]      ; 19.877 ; 18.791 ; 18.791 ; 19.877 ;
; RWn          ; DTACKn        ; 18.415 ; 18.415 ; 18.415 ; 18.415 ;
; RWn          ; FLASH_CEn     ;        ; 20.033 ; 20.033 ;        ;
; RWn          ; FLASH_OEn     ;        ; 19.239 ; 19.239 ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 14.460 ; 14.460 ;        ;
; RWn          ; IDE_D_EN_OUTn ; 15.046 ;        ;        ; 15.046 ;
; RWn          ; IDE_IORDn     ;        ; 14.732 ; 14.732 ;        ;
; RWn          ; IDE_IOWRn     ; 14.352 ;        ;        ; 14.352 ;
; RWn          ; JOY_RHn       ;        ; 14.159 ; 14.159 ;        ;
; RWn          ; JOY_RLn       ;        ; 14.400 ; 14.400 ;        ;
; RWn          ; JOY_WEn       ; 14.042 ;        ;        ; 14.042 ;
; RWn          ; JOY_WL        ; 17.652 ; 12.211 ; 12.211 ; 17.652 ;
; RWn          ; RAM_DATA[0]   ; 15.263 ; 15.263 ; 15.263 ; 15.263 ;
; RWn          ; RAM_DATA[1]   ; 15.272 ; 15.272 ; 15.272 ; 15.272 ;
; RWn          ; RAM_DATA[2]   ; 15.272 ; 15.272 ; 15.272 ; 15.272 ;
; RWn          ; RAM_DATA[3]   ; 16.132 ; 16.132 ; 16.132 ; 16.132 ;
; RWn          ; RAM_DATA[4]   ; 16.132 ; 16.132 ; 16.132 ; 16.132 ;
; RWn          ; RAM_DATA[5]   ; 16.961 ; 16.961 ; 16.961 ; 16.961 ;
; RWn          ; RAM_DATA[6]   ; 16.710 ; 16.710 ; 16.710 ; 16.710 ;
; RWn          ; RAM_DATA[7]   ; 16.820 ; 16.820 ; 16.820 ; 16.820 ;
; RWn          ; RAM_DATA[8]   ; 15.839 ; 15.839 ; 15.839 ; 15.839 ;
; RWn          ; RAM_DATA[9]   ; 15.839 ; 15.839 ; 15.839 ; 15.839 ;
; RWn          ; RAM_DATA[10]  ; 15.593 ; 15.593 ; 15.593 ; 15.593 ;
; RWn          ; RAM_DATA[11]  ; 15.583 ; 15.583 ; 15.583 ; 15.583 ;
; RWn          ; RAM_DATA[12]  ; 15.583 ; 15.583 ; 15.583 ; 15.583 ;
; RWn          ; RAM_DATA[13]  ; 15.583 ; 15.583 ; 15.583 ; 15.583 ;
; RWn          ; RAM_DATA[14]  ; 15.267 ; 15.267 ; 15.267 ; 15.267 ;
; RWn          ; RAM_DATA[15]  ; 15.267 ; 15.267 ; 15.267 ; 15.267 ;
; RWn          ; RAM_WEn       ; 16.091 ;        ;        ; 16.091 ;
; RWn          ; ROM0n         ;        ; 15.986 ; 15.986 ;        ;
; RWn          ; ROM1n         ;        ; 15.714 ; 15.714 ;        ;
; RWn          ; ROM2n         ;        ; 17.673 ; 17.673 ;        ;
; RWn          ; ROM3n         ;        ; 15.231 ; 15.231 ;        ;
; RWn          ; ROM4n         ;        ; 15.386 ; 15.386 ;        ;
; RWn          ; ROM5n         ;        ; 17.664 ; 17.664 ;        ;
; RWn          ; ROM6n         ;        ; 17.199 ; 17.199 ;        ;
; SCSI_ACKn    ; CD[0]         ; 14.204 ; 14.204 ; 14.204 ; 14.204 ;
; SCSI_ATNn    ; CD[1]         ; 16.332 ; 16.332 ; 16.332 ; 16.332 ;
; SCSI_BSYn    ; CD[6]         ; 17.707 ; 17.707 ; 17.707 ; 17.707 ;
; SCSI_D[0]    ; CD[0]         ; 14.770 ; 14.770 ; 14.770 ; 14.770 ;
; SCSI_D[1]    ; CD[1]         ; 15.008 ; 15.008 ; 15.008 ; 15.008 ;
; SCSI_D[2]    ; CD[2]         ;        ; 13.276 ; 13.276 ;        ;
; SCSI_D[3]    ; CD[3]         ; 15.444 ; 15.444 ; 15.444 ; 15.444 ;
; SCSI_D[4]    ; CD[4]         ; 17.943 ; 17.943 ; 17.943 ; 17.943 ;
; SCSI_D[5]    ; CD[5]         ; 16.747 ; 16.747 ; 16.747 ; 16.747 ;
; SCSI_D[6]    ; CD[6]         ; 17.645 ; 17.645 ; 17.645 ; 17.645 ;
; SCSI_D[7]    ; CD[7]         ; 16.361 ; 16.361 ; 16.361 ; 16.361 ;
; SCSI_DCn     ; CD[3]         ; 15.935 ; 15.935 ; 15.935 ; 15.935 ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 18.454 ; 18.454 ; 18.454 ; 18.454 ;
; SCSI_DCn     ; SCSI_D[0]     ; 17.103 ; 17.103 ; 17.103 ; 17.103 ;
; SCSI_DCn     ; SCSI_D[1]     ; 17.103 ; 17.103 ; 17.103 ; 17.103 ;
; SCSI_DCn     ; SCSI_D[2]     ; 17.096 ; 17.096 ; 17.096 ; 17.096 ;
; SCSI_DCn     ; SCSI_D[3]     ; 17.096 ; 17.096 ; 17.096 ; 17.096 ;
; SCSI_DCn     ; SCSI_D[4]     ; 17.430 ; 17.430 ; 17.430 ; 17.430 ;
; SCSI_DCn     ; SCSI_D[5]     ; 17.430 ; 17.430 ; 17.430 ; 17.430 ;
; SCSI_DCn     ; SCSI_D[6]     ; 17.705 ; 17.705 ; 17.705 ; 17.705 ;
; SCSI_DCn     ; SCSI_D[7]     ; 17.705 ; 17.705 ; 17.705 ; 17.705 ;
; SCSI_DCn     ; SCSI_DP       ; 17.113 ; 17.113 ; 17.113 ; 17.113 ;
; SCSI_DP      ; CD[0]         ; 14.407 ; 14.407 ; 14.407 ; 14.407 ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 12.296 ; 12.296 ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 12.292 ;        ;        ; 12.292 ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 12.274 ; 12.274 ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 12.643 ;        ;        ; 12.643 ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 13.212 ; 13.212 ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 13.208 ;        ;        ; 13.208 ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 13.616 ; 13.616 ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 12.942 ;        ;        ; 12.942 ;
; SCSI_IDn[1]  ; SCSI_DP       ; 13.345 ; 13.345 ; 13.345 ; 13.345 ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 11.936 ; 11.936 ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 11.936 ; 11.936 ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 11.905 ;        ;        ; 11.905 ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 12.277 ;        ;        ; 12.277 ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 12.863 ; 12.863 ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 12.856 ; 12.856 ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 13.266 ;        ;        ; 13.266 ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 12.578 ;        ;        ; 12.578 ;
; SCSI_IDn[2]  ; SCSI_DP       ; 12.996 ; 12.996 ; 12.996 ; 12.996 ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 12.483 ; 12.483 ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 12.477 ; 12.477 ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 12.495 ; 12.495 ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 12.865 ; 12.865 ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 13.339 ;        ;        ; 13.339 ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 13.332 ;        ;        ; 13.332 ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 13.775 ;        ;        ; 13.775 ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 13.101 ;        ;        ; 13.101 ;
; SCSI_IDn[3]  ; SCSI_DP       ; 13.472 ; 13.472 ; 13.472 ; 13.472 ;
; SCSI_IOn     ; CD[2]         ;        ; 15.779 ; 15.779 ;        ;
; SCSI_IOn     ; CD[3]         ; 19.203 ; 19.203 ; 19.203 ; 19.203 ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 14.852 ; 18.372 ; 18.372 ; 14.852 ;
; SCSI_IOn     ; SCSI_D[0]     ; 13.501 ; 13.501 ; 13.501 ; 13.501 ;
; SCSI_IOn     ; SCSI_D[1]     ; 13.501 ; 13.501 ; 13.501 ; 13.501 ;
; SCSI_IOn     ; SCSI_D[2]     ; 13.494 ; 13.494 ; 13.494 ; 13.494 ;
; SCSI_IOn     ; SCSI_D[3]     ; 13.494 ; 13.494 ; 13.494 ; 13.494 ;
; SCSI_IOn     ; SCSI_D[4]     ; 13.828 ; 13.828 ; 13.828 ; 13.828 ;
; SCSI_IOn     ; SCSI_D[5]     ; 13.828 ; 13.828 ; 13.828 ; 13.828 ;
; SCSI_IOn     ; SCSI_D[6]     ; 14.103 ; 14.103 ; 14.103 ; 14.103 ;
; SCSI_IOn     ; SCSI_D[7]     ; 14.103 ; 14.103 ; 14.103 ; 14.103 ;
; SCSI_IOn     ; SCSI_DP       ; 13.511 ; 13.511 ; 13.511 ; 13.511 ;
; SCSI_IOn     ; SCSI_RDn      ; 14.482 ;        ;        ; 14.482 ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 14.079 ; 14.079 ;        ;
; SCSI_MSGn    ; CD[3]         ; 18.228 ; 18.228 ; 18.228 ; 18.228 ;
; SCSI_MSGn    ; CD[4]         ; 17.647 ; 17.647 ; 17.647 ; 17.647 ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 17.397 ; 17.397 ; 17.397 ; 17.397 ;
; SCSI_MSGn    ; SCSI_D[0]     ; 16.046 ; 16.046 ; 16.046 ; 16.046 ;
; SCSI_MSGn    ; SCSI_D[1]     ; 16.046 ; 16.046 ; 16.046 ; 16.046 ;
; SCSI_MSGn    ; SCSI_D[2]     ; 16.039 ; 16.039 ; 16.039 ; 16.039 ;
; SCSI_MSGn    ; SCSI_D[3]     ; 16.039 ; 16.039 ; 16.039 ; 16.039 ;
; SCSI_MSGn    ; SCSI_D[4]     ; 16.373 ; 16.373 ; 16.373 ; 16.373 ;
; SCSI_MSGn    ; SCSI_D[5]     ; 16.373 ; 16.373 ; 16.373 ; 16.373 ;
; SCSI_MSGn    ; SCSI_D[6]     ; 16.648 ; 16.648 ; 16.648 ; 16.648 ;
; SCSI_MSGn    ; SCSI_D[7]     ; 16.648 ; 16.648 ; 16.648 ; 16.648 ;
; SCSI_MSGn    ; SCSI_DP       ; 16.056 ; 16.056 ; 16.056 ; 16.056 ;
; SCSI_REQn    ; CD[3]         ; 18.599 ; 18.599 ; 18.599 ; 18.599 ;
; SCSI_REQn    ; CD[5]         ; 17.150 ; 17.150 ; 17.150 ; 17.150 ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 17.768 ;        ;        ; 17.768 ;
; SCSI_REQn    ; SCSI_D[0]     ; 16.417 ; 16.417 ; 16.417 ; 16.417 ;
; SCSI_REQn    ; SCSI_D[1]     ; 16.417 ; 16.417 ; 16.417 ; 16.417 ;
; SCSI_REQn    ; SCSI_D[2]     ; 16.410 ; 16.410 ; 16.410 ; 16.410 ;
; SCSI_REQn    ; SCSI_D[3]     ; 16.410 ; 16.410 ; 16.410 ; 16.410 ;
; SCSI_REQn    ; SCSI_D[4]     ; 16.744 ; 16.744 ; 16.744 ; 16.744 ;
; SCSI_REQn    ; SCSI_D[5]     ; 16.744 ; 16.744 ; 16.744 ; 16.744 ;
; SCSI_REQn    ; SCSI_D[6]     ; 17.019 ; 17.019 ; 17.019 ; 17.019 ;
; SCSI_REQn    ; SCSI_D[7]     ; 17.019 ; 17.019 ; 17.019 ; 17.019 ;
; SCSI_REQn    ; SCSI_DP       ; 16.427 ; 16.427 ; 16.427 ; 16.427 ;
; SCSI_RSTn    ; CD[7]         ;        ; 16.793 ; 16.793 ;        ;
; SCSI_SELn    ; CD[1]         ; 15.091 ; 15.091 ; 15.091 ; 15.091 ;
; SD_AVR_ENn   ; RESETn        ;        ; 16.134 ; 16.134 ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 13.868 ; 13.868 ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 15.607 ; 15.607 ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 13.293 ;        ;        ; 13.293 ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 13.484 ;        ;        ; 13.484 ;
; SD_RESETn    ; ACSI_RDn      ; 20.259 ; 20.259 ; 20.259 ; 20.259 ;
; SD_RESETn    ; ACSI_WRn      ; 20.224 ; 20.224 ; 20.224 ; 20.224 ;
; SD_RESETn    ; CA1_OUT       ; 19.259 ;        ;        ; 19.259 ;
; SD_RESETn    ; CD[0]         ; 21.837 ; 21.701 ; 21.701 ; 21.837 ;
; SD_RESETn    ; CD[1]         ; 21.739 ; 21.562 ; 21.562 ; 21.739 ;
; SD_RESETn    ; CD[2]         ; 19.644 ; 19.644 ; 19.644 ; 19.644 ;
; SD_RESETn    ; CD[3]         ; 22.189 ; 21.836 ; 21.836 ; 22.189 ;
; SD_RESETn    ; CD[4]         ; 20.499 ; 20.499 ; 20.499 ; 20.499 ;
; SD_RESETn    ; CD[5]         ; 20.478 ; 20.478 ; 20.478 ; 20.478 ;
; SD_RESETn    ; CD[6]         ; 20.850 ; 20.850 ; 20.850 ; 20.850 ;
; SD_RESETn    ; CD[7]         ; 20.002 ; 20.002 ; 20.002 ; 20.002 ;
; SD_RESETn    ; COM_TxD       ; 21.253 ; 21.253 ; 21.253 ; 21.253 ;
; SD_RESETn    ; DATA[0]       ; 23.915 ; 25.909 ; 25.909 ; 23.915 ;
; SD_RESETn    ; DATA[1]       ; 25.343 ; 26.344 ; 26.344 ; 25.343 ;
; SD_RESETn    ; DATA[2]       ; 24.704 ; 26.432 ; 26.432 ; 24.704 ;
; SD_RESETn    ; DATA[3]       ; 23.986 ; 25.350 ; 25.350 ; 23.986 ;
; SD_RESETn    ; DATA[4]       ; 23.693 ; 25.169 ; 25.169 ; 23.693 ;
; SD_RESETn    ; DATA[5]       ; 26.031 ; 27.031 ; 27.031 ; 26.031 ;
; SD_RESETn    ; DATA[6]       ; 25.743 ; 26.462 ; 26.462 ; 25.743 ;
; SD_RESETn    ; DATA[7]       ; 26.309 ; 27.533 ; 27.533 ; 26.309 ;
; SD_RESETn    ; DATA[8]       ; 24.867 ; 26.442 ; 26.442 ; 24.867 ;
; SD_RESETn    ; DATA[9]       ; 26.592 ; 27.682 ; 27.682 ; 26.592 ;
; SD_RESETn    ; DATA[10]      ; 21.875 ; 24.929 ; 24.929 ; 21.875 ;
; SD_RESETn    ; DATA[11]      ; 26.302 ; 28.132 ; 28.132 ; 26.302 ;
; SD_RESETn    ; DATA[12]      ; 24.614 ; 27.562 ; 27.562 ; 24.614 ;
; SD_RESETn    ; DATA[13]      ; 23.934 ; 26.052 ; 26.052 ; 23.934 ;
; SD_RESETn    ; DATA[14]      ; 22.924 ; 24.723 ; 24.723 ; 22.924 ;
; SD_RESETn    ; DATA[15]      ; 23.762 ; 25.391 ; 25.391 ; 23.762 ;
; SD_RESETn    ; DTACKn        ; 21.735 ; 21.735 ; 21.735 ; 21.735 ;
; SD_RESETn    ; RAM_DATA[0]   ; 25.199 ; 27.193 ; 27.193 ; 25.199 ;
; SD_RESETn    ; RAM_DATA[1]   ; 26.270 ; 27.271 ; 27.271 ; 26.270 ;
; SD_RESETn    ; RAM_DATA[2]   ; 25.454 ; 27.182 ; 27.182 ; 25.454 ;
; SD_RESETn    ; RAM_DATA[3]   ; 26.285 ; 27.649 ; 27.649 ; 26.285 ;
; SD_RESETn    ; RAM_DATA[4]   ; 25.942 ; 27.418 ; 27.418 ; 25.942 ;
; SD_RESETn    ; RAM_DATA[5]   ; 27.535 ; 28.535 ; 28.535 ; 27.535 ;
; SD_RESETn    ; RAM_DATA[6]   ; 26.479 ; 27.198 ; 27.198 ; 26.479 ;
; SD_RESETn    ; RAM_DATA[7]   ; 26.478 ; 27.702 ; 27.702 ; 26.478 ;
; SD_RESETn    ; RAM_DATA[8]   ; 24.828 ; 26.403 ; 26.403 ; 24.828 ;
; SD_RESETn    ; RAM_DATA[9]   ; 26.603 ; 27.693 ; 27.693 ; 26.603 ;
; SD_RESETn    ; RAM_DATA[10]  ; 23.085 ; 26.139 ; 26.139 ; 23.085 ;
; SD_RESETn    ; RAM_DATA[11]  ; 24.984 ; 26.814 ; 26.814 ; 24.984 ;
; SD_RESETn    ; RAM_DATA[12]  ; 24.280 ; 27.228 ; 27.228 ; 24.280 ;
; SD_RESETn    ; RAM_DATA[13]  ; 25.720 ; 27.838 ; 27.838 ; 25.720 ;
; SD_RESETn    ; RAM_DATA[14]  ; 25.051 ; 26.850 ; 26.850 ; 25.051 ;
; SD_RESETn    ; RAM_DATA[15]  ; 25.276 ; 26.905 ; 26.905 ; 25.276 ;
; UDSn         ; ACSI_RDn      ; 17.945 ; 17.945 ; 17.945 ; 17.945 ;
; UDSn         ; ACSI_WRn      ; 17.910 ; 17.910 ; 17.910 ; 17.910 ;
; UDSn         ; CA1_OUT       ; 16.945 ;        ;        ; 16.945 ;
; UDSn         ; CD[0]         ; 19.523 ; 19.387 ; 19.387 ; 19.523 ;
; UDSn         ; CD[1]         ; 19.425 ; 19.248 ; 19.248 ; 19.425 ;
; UDSn         ; CD[2]         ; 17.330 ; 17.330 ; 17.330 ; 17.330 ;
; UDSn         ; CD[3]         ; 19.875 ; 19.522 ; 19.522 ; 19.875 ;
; UDSn         ; CD[4]         ; 18.185 ; 18.185 ; 18.185 ; 18.185 ;
; UDSn         ; CD[5]         ; 18.164 ; 18.164 ; 18.164 ; 18.164 ;
; UDSn         ; CD[6]         ; 18.536 ; 18.536 ; 18.536 ; 18.536 ;
; UDSn         ; CD[7]         ; 17.688 ; 17.688 ; 17.688 ; 17.688 ;
; UDSn         ; DATA[0]       ; 20.872 ; 20.872 ; 20.872 ; 20.872 ;
; UDSn         ; DATA[1]       ; 20.872 ; 20.872 ; 20.872 ; 20.872 ;
; UDSn         ; DATA[2]       ; 20.506 ; 20.506 ; 20.506 ; 20.506 ;
; UDSn         ; DATA[3]       ; 20.506 ; 20.506 ; 20.506 ; 20.506 ;
; UDSn         ; DATA[4]       ; 20.544 ; 20.544 ; 20.544 ; 20.544 ;
; UDSn         ; DATA[5]       ; 20.544 ; 20.544 ; 20.544 ; 20.544 ;
; UDSn         ; DATA[6]       ; 20.159 ; 20.159 ; 20.159 ; 20.159 ;
; UDSn         ; DATA[7]       ; 20.149 ; 20.149 ; 20.149 ; 20.149 ;
; UDSn         ; DATA[8]       ; 20.485 ; 20.485 ; 20.485 ; 20.485 ;
; UDSn         ; DATA[9]       ; 20.485 ; 20.485 ; 20.485 ; 20.485 ;
; UDSn         ; DATA[10]      ; 19.561 ; 20.821 ; 20.821 ; 19.561 ;
; UDSn         ; DATA[11]      ; 20.821 ; 20.821 ; 20.821 ; 20.821 ;
; UDSn         ; DATA[12]      ; 20.882 ; 20.882 ; 20.882 ; 20.882 ;
; UDSn         ; DATA[13]      ; 20.882 ; 20.882 ; 20.882 ; 20.882 ;
; UDSn         ; DATA[14]      ; 20.610 ; 20.840 ; 20.840 ; 20.610 ;
; UDSn         ; DATA[15]      ; 20.830 ; 20.830 ; 20.830 ; 20.830 ;
; UDSn         ; DTACKn        ; 19.421 ; 19.421 ; 19.421 ; 19.421 ;
; UDSn         ; JOY_RHn       ; 14.783 ;        ;        ; 14.783 ;
; UDSn         ; RAM_CAS0n     ; 16.464 ;        ;        ; 16.464 ;
; UDSn         ; RAM_DATA[0]   ; 22.885 ; 24.461 ; 24.461 ; 22.885 ;
; UDSn         ; RAM_DATA[1]   ; 23.956 ; 24.790 ; 24.790 ; 23.956 ;
; UDSn         ; RAM_DATA[2]   ; 23.140 ; 24.709 ; 24.709 ; 23.140 ;
; UDSn         ; RAM_DATA[3]   ; 23.971 ; 24.712 ; 24.712 ; 23.971 ;
; UDSn         ; RAM_DATA[4]   ; 23.628 ; 25.104 ; 25.104 ; 23.628 ;
; UDSn         ; RAM_DATA[5]   ; 25.221 ; 26.221 ; 26.221 ; 25.221 ;
; UDSn         ; RAM_DATA[6]   ; 24.165 ; 24.884 ; 24.884 ; 24.165 ;
; UDSn         ; RAM_DATA[7]   ; 24.164 ; 25.431 ; 25.431 ; 24.164 ;
; UDSn         ; RAM_DATA[8]   ; 22.514 ; 24.635 ; 24.635 ; 22.514 ;
; UDSn         ; RAM_DATA[9]   ; 24.289 ; 25.396 ; 25.396 ; 24.289 ;
; UDSn         ; RAM_DATA[10]  ; 20.771 ; 23.407 ; 23.407 ; 20.771 ;
; UDSn         ; RAM_DATA[11]  ; 22.670 ; 23.256 ; 23.256 ; 22.670 ;
; UDSn         ; RAM_DATA[12]  ; 21.966 ; 22.976 ; 22.976 ; 21.966 ;
; UDSn         ; RAM_DATA[13]  ; 23.406 ; 25.102 ; 25.102 ; 23.406 ;
; UDSn         ; RAM_DATA[14]  ; 22.737 ; 23.756 ; 23.756 ; 22.737 ;
; UDSn         ; RAM_DATA[15]  ; 22.962 ; 24.772 ; 24.772 ; 22.962 ;
; UDSn         ; RAM_DQM0H     ; 14.860 ;        ;        ; 14.860 ;
+--------------+---------------+--------+--------+--------+--------+


+-------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                     ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise   ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 22.290 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 22.336 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 22.329 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 22.301 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 22.329 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 22.290 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 22.290 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 22.308 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 22.308 ;      ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 18.614 ;      ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 19.493 ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 14.936 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 16.594 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 16.594 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 16.584 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 16.584 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 16.594 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 16.584 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 16.614 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 16.614 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 16.342 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 16.342 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 15.798 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 15.788 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 15.212 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 15.202 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 14.936 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 14.936 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 15.778 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 16.456 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 16.456 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 16.545 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 16.564 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 16.574 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 16.545 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 14.956 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 43.842 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 43.888 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 43.881 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 43.853 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 43.881 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 43.842 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 43.842 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 43.860 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 43.860 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 15.610 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 38.716 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 39.439 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 39.439 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 39.073 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 39.073 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 39.111 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 39.111 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 38.726 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 38.716 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 39.052 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 39.052 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 39.388 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 39.388 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 39.449 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 39.449 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 39.407 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 39.397 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 8.469  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 41.274 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 15.015 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 15.425 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 15.015 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 15.015 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 7.576  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 13.423 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 5.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 6.163  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 5.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 5.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 7.068  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 7.068  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 7.380  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 7.380  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 6.156  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 40.212 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 40.212 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 40.221 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 40.221 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 41.081 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 41.081 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 41.910 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 41.659 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 41.910 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 40.788 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 40.788 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 40.542 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 40.532 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 40.532 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 40.532 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 40.216 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 40.216 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 13.308 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 6.903  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.209  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.084  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 12.292 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 12.299 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 12.299 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 12.292 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 12.292 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 12.626 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 12.626 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 12.901 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 12.901 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 7.095  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 12.309 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.249  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 7.085  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 7.095  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 8.027  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 7.699  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 13.423 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 7.564  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 10.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 12.496 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 12.496 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 12.486 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 12.486 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 12.496 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 12.486 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 12.516 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 12.516 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 12.244 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 12.244 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 11.700 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 11.690 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 11.114 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 11.104 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 10.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 10.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 11.680 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 12.358 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 12.358 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 12.447 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 12.466 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 12.476 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 12.447 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 9.273  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 49.641 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 49.687 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 49.680 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 49.652 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 49.680 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 49.641 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 49.641 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 49.659 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 49.659 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 44.515 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 45.238 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 45.238 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 44.872 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 44.872 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 44.910 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 44.910 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 44.525 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 44.515 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 44.851 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 44.851 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 45.187 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 45.187 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 45.248 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 45.248 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 45.206 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 45.196 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 47.073 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 9.371  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 9.781  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 9.371  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 9.371  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 7.740  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 46.011 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 46.011 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 46.020 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 46.020 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 46.880 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 46.880 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 47.709 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 47.458 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 47.709 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 46.587 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 46.587 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 46.341 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 46.331 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 46.331 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 46.331 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 46.015 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 46.015 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 7.625  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 7.740  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 6.389  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 14.936 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 16.594 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 16.594 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 16.584 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 16.584 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 16.594 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 16.584 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 16.614 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 16.614 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 16.342 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 16.342 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 15.798 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 15.788 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 15.212 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 15.202 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 14.936 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 14.936 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 15.778 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 16.456 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 16.456 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 16.545 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 16.564 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 16.574 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 16.545 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 14.956 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 43.842 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 43.888 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 43.881 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 43.853 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 43.881 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 43.842 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 43.842 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 43.860 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 43.860 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 15.610 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 38.716 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 39.439 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 39.439 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 39.073 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 39.073 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 39.111 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 39.111 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 38.726 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 38.716 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 39.052 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 39.052 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 39.388 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 39.388 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 39.449 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 39.449 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 39.407 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 39.397 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 8.469  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 41.274 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 15.015 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 15.425 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 15.015 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 15.015 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 7.576  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 13.423 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 5.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 6.163  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 5.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 5.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 7.068  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 7.068  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 7.380  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 7.380  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 6.156  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 40.212 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 40.212 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 40.221 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 40.221 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 41.081 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 41.081 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 41.910 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 41.659 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 41.910 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 40.788 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 40.788 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 40.542 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 40.532 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 40.532 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 40.532 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 40.216 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 40.216 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 13.308 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 6.903  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.209  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.084  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 12.292 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 12.299 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 12.299 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 12.292 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 12.292 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 12.626 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 12.626 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 12.901 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 12.901 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 7.095  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 12.309 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.249  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 7.085  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 7.095  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 8.027  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 7.699  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 13.423 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.564  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 10.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 12.496 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 12.496 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 12.486 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 12.486 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 12.496 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 12.486 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 12.516 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 12.516 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 12.244 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 12.244 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 11.700 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 11.690 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 11.114 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 11.104 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 10.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 10.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 11.680 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 12.358 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 12.358 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 12.447 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 12.466 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 12.476 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 12.447 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 9.273  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 49.641 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 49.687 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 49.680 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 49.652 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 49.680 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 49.641 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 49.641 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 49.659 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 49.659 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 44.515 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 45.238 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 45.238 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 44.872 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 44.872 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 44.910 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 44.910 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 44.525 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 44.515 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 44.851 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 44.851 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 45.187 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 45.187 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 45.248 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 45.248 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 45.206 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 45.196 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 47.073 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 9.371  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 9.781  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 9.371  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 9.371  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 7.740  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 46.011 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 46.011 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 46.020 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 46.020 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 46.880 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 46.880 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 47.709 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 47.458 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 47.709 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 46.587 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 46.587 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 46.341 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 46.331 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 46.331 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 46.331 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 46.015 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 46.015 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 7.625  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 7.740  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 6.389  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 9.982  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 17.881 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 17.927 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 17.920 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 17.892 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 17.920 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 17.881 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 17.881 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 17.899 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 17.899 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 14.205 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 15.084 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 9.032  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 9.442  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 9.032  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 9.032  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 8.447  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 14.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 14.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 14.030 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 14.030 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 14.890 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 14.890 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 15.719 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 15.468 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 15.719 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 14.597 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 14.597 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 14.351 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 14.341 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 14.341 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 14.341 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 14.025 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 14.025 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 8.332  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 9.211  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 11.796 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 9.671  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 8.958  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 8.965  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 8.965  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 8.958  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 8.958  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 9.292  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 9.292  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 9.567  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 9.567  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 9.642  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 8.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 8.796  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 9.632  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 9.642  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 10.333 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 10.007 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 8.447  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 15.088 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 9.982  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 17.881 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 17.927 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 17.920 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 17.892 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 17.920 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 17.881 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 17.881 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 17.899 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 17.899 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 14.205 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 15.084 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 9.032  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 9.442  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 9.032  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 9.032  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.447  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 14.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 14.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 14.030 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 14.030 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 14.890 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 14.890 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 15.719 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 15.468 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 15.719 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 14.597 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 14.597 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 14.351 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 14.341 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 14.341 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 14.341 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 14.025 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 14.025 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 8.332  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 9.211  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 11.796 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 9.671  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 8.958  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 8.965  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 8.965  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 8.958  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 8.958  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 9.292  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 9.292  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 9.567  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 9.567  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 9.642  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 8.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 8.796  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 9.632  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 9.642  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 10.333 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 10.007 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.447  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 15.088 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 9.827  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 9.827  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 9.827  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 10.372 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 10.372 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 9.827  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 9.827  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 9.827  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 10.372 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 10.372 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                             ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise   ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 19.511 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 19.557 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 19.550 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 19.522 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 19.550 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 19.511 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 19.511 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 19.529 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 19.529 ;      ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 18.614 ;      ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 19.096 ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 7.453  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 9.111  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 9.111  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 9.101  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 9.101  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 9.111  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 9.101  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 9.131  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 9.131  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 8.859  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 8.859  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 8.315  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 8.305  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 7.729  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 7.719  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 7.453  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 7.453  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 8.295  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 8.973  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 8.973  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 9.062  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 9.081  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 9.091  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 9.062  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 8.408  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 8.143  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 8.189  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 8.182  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 8.154  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 8.182  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 8.143  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 8.143  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 8.161  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 8.161  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 8.661  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 9.126  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 9.849  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 9.849  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 9.483  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 9.483  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 9.521  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 9.521  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 9.136  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 9.126  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 9.462  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 9.462  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 9.798  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 9.798  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 9.859  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 9.859  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 9.817  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 9.807  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 7.508  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 10.314 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 8.139  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 8.549  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 8.139  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 8.139  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 7.576  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 6.875  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 5.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 6.163  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 5.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 5.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 7.068  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 7.068  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 7.380  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 7.380  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 6.156  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 13.326 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 13.326 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 13.335 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 13.335 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 14.195 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 14.195 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 15.024 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 14.773 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 15.024 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 13.902 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 13.902 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 13.656 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 13.646 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 13.646 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 13.646 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 13.330 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 13.330 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 6.760  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 5.974  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.209  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.084  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 6.121  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 6.128  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 6.128  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 6.121  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 6.121  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 6.455  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 6.455  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 6.730  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 6.730  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 7.095  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 6.138  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.249  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 7.085  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 7.095  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 7.096  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 6.770  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 6.875  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 7.564  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 7.873  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 9.531  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 9.531  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 9.521  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 9.521  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 9.531  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 9.521  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 9.551  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 9.551  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 9.279  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 9.279  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 8.735  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 8.725  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.149  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.139  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 7.873  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 7.873  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 8.715  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 9.393  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 9.393  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 9.482  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 9.501  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 9.511  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 9.482  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 8.408  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 17.102 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 17.148 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 17.141 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 17.113 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 17.141 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 17.102 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 17.102 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 17.120 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 17.120 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 11.294 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 12.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 12.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 11.651 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 11.651 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 11.689 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 11.689 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 11.304 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 11.294 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 11.630 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 11.630 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 11.966 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 11.966 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 12.027 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 12.027 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 11.985 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 11.975 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 12.514 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 7.720  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 8.130  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 7.720  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 7.720  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 6.875  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 13.260 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 13.260 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 13.269 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 13.269 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 14.129 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 14.129 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 14.958 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 14.707 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 14.958 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 13.836 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 13.836 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 13.590 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 13.580 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 13.580 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 13.580 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 13.264 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 13.264 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 6.760  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 6.875  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 6.389  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 7.453  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 9.111  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 9.111  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 9.101  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 9.101  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 9.111  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 9.101  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 9.131  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 9.131  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 8.859  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 8.859  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 8.315  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 8.305  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 7.729  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 7.719  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 7.453  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 7.453  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 8.295  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 8.973  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 8.973  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 9.062  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 9.081  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 9.091  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 9.062  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 8.408  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 8.143  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 8.189  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 8.182  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 8.154  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 8.182  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 8.143  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 8.143  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 8.161  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 8.161  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 8.661  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 9.126  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 9.849  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 9.849  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 9.483  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 9.483  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 9.521  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 9.521  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 9.136  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 9.126  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 9.462  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 9.462  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 9.798  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 9.798  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 9.859  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 9.859  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 9.817  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 9.807  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 7.508  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 10.314 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 8.139  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 8.549  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 8.139  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 8.139  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 7.576  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 6.875  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 5.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 6.163  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 5.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 5.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 7.068  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 7.068  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 7.380  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 7.380  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 6.156  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 13.326 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 13.326 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 13.335 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 13.335 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 14.195 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 14.195 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 15.024 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 14.773 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 15.024 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 13.902 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 13.902 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 13.656 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 13.646 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 13.646 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 13.646 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 13.330 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 13.330 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 6.760  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 5.974  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.209  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.084  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 6.121  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 6.128  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 6.128  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 6.121  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 6.121  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 6.455  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 6.455  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 6.730  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 6.730  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 7.095  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 6.138  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.249  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 7.085  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 7.095  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 7.096  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 6.770  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 6.875  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.564  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 7.873  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 9.531  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 9.531  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 9.521  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 9.521  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 9.531  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 9.521  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 9.551  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 9.551  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 9.279  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 9.279  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 8.735  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 8.725  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.149  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.139  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 7.873  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 7.873  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 8.715  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 9.393  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 9.393  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 9.482  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 9.501  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 9.511  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 9.482  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 8.408  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 17.102 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 17.148 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 17.141 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 17.113 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 17.141 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 17.102 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 17.102 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 17.120 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 17.120 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 11.294 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 12.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 12.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 11.651 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 11.651 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 11.689 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 11.689 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 11.304 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 11.294 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 11.630 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 11.630 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 11.966 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 11.966 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 12.027 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 12.027 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 11.985 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 11.975 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 12.514 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 7.720  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 8.130  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 7.720  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 7.720  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 6.875  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 13.260 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 13.260 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 13.269 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 13.269 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 14.129 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 14.129 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 14.958 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 14.707 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 14.958 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 13.836 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 13.836 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 13.590 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 13.580 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 13.580 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 13.580 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 13.264 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 13.264 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 6.760  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 6.875  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 6.389  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 9.982  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 10.838 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 10.884 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 10.877 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 10.849 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 10.877 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 10.838 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 10.838 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 10.856 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 10.856 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 12.665 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 11.457 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 9.032  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 9.442  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 9.032  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 9.032  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 8.447  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 10.249 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 10.249 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 10.258 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 10.258 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.118 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.118 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 11.947 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 11.696 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 11.947 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 10.825 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 10.825 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 10.579 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 10.569 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 10.569 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 10.569 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 10.253 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 10.253 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 8.332  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 8.827  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 11.584 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 9.459  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 8.314  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 8.321  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 8.321  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 8.314  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 8.314  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 8.648  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 8.648  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 8.923  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 8.923  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 9.473  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 8.331  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 8.627  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 9.463  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 9.473  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 9.919  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 9.623  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 8.447  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 15.088 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 9.982  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 10.838 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 10.884 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 10.877 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 10.849 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 10.877 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 10.838 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 10.838 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 10.856 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 10.856 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 12.665 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 11.457 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 9.032  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 9.442  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 9.032  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 9.032  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.447  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 10.249 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 10.249 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 10.258 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 10.258 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.118 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.118 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 11.947 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 11.696 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 11.947 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 10.825 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 10.825 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 10.579 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 10.569 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 10.569 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 10.569 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 10.253 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 10.253 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 8.332  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 8.827  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 11.584 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 9.459  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 8.314  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 8.321  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 8.321  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 8.314  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 8.314  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 8.648  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 8.648  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 8.923  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 8.923  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 9.473  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 8.331  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 8.627  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 9.463  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 9.473  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 9.919  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 9.623  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.447  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 15.088 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 6.472  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 6.472  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 6.472  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 6.818  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 6.818  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 6.472  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 6.472  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 6.472  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 6.818  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 6.818  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 22.290    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 22.336    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 22.329    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 22.301    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 22.329    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 22.290    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 22.290    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 22.308    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 22.308    ;           ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 18.614    ;           ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 19.493    ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 14.936    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 16.594    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 16.594    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 16.584    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 16.584    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 16.594    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 16.584    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 16.614    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 16.614    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 16.342    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 16.342    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 15.798    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 15.788    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 15.212    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 15.202    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 14.936    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 14.936    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 15.778    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 16.456    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 16.456    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 16.545    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 16.564    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 16.574    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 16.545    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 14.956    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 43.842    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 43.888    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 43.881    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 43.853    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 43.881    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 43.842    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 43.842    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 43.860    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 43.860    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 15.610    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 38.716    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 39.439    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 39.439    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 39.073    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 39.073    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 39.111    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 39.111    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 38.726    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 38.716    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 39.052    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 39.052    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 39.388    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 39.388    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 39.449    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 39.449    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 39.407    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 39.397    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 8.469     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 41.274    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 15.015    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 15.425    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 15.015    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 15.015    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 7.576     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 13.423    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 5.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 6.163     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 5.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 5.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 7.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 7.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 7.380     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 7.380     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 6.156     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 40.212    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 40.212    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 40.221    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 40.221    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 41.081    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 41.081    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 41.910    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 41.659    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 41.910    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 40.788    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 40.788    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 40.542    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 40.532    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 40.532    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 40.532    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 40.216    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 40.216    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 13.308    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 6.903     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.209     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.084     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 12.292    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 12.299    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 12.299    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 12.292    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 12.292    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 12.626    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 12.626    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 12.901    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 12.901    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 7.095     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 12.309    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.249     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 7.085     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 7.095     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 8.027     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 7.699     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 13.423    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 7.564     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 10.838    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 12.496    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 12.496    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 12.486    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 12.486    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 12.496    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 12.486    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 12.516    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 12.516    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 12.244    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 12.244    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 11.700    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 11.690    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 11.114    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 11.104    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 10.838    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 10.838    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 11.680    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 12.358    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 12.358    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 12.447    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 12.466    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 12.476    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 12.447    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 9.273     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 49.641    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 49.687    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 49.680    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 49.652    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 49.680    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 49.641    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 49.641    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 49.659    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 49.659    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 44.515    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 45.238    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 45.238    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 44.872    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 44.872    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 44.910    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 44.910    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 44.525    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 44.515    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 44.851    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 44.851    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 45.187    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 45.187    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 45.248    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 45.248    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 45.206    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 45.196    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 47.073    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 9.371     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 9.781     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 9.371     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 9.371     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 7.740     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 46.011    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 46.011    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 46.020    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 46.020    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 46.880    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 46.880    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 47.709    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 47.458    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 47.709    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 46.587    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 46.587    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 46.341    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 46.331    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 46.331    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 46.331    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 46.015    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 46.015    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 7.625     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 7.740     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 6.389     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 14.936    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 16.594    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 16.594    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 16.584    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 16.584    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 16.594    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 16.584    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 16.614    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 16.614    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 16.342    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 16.342    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 15.798    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 15.788    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 15.212    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 15.202    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 14.936    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 14.936    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 15.778    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 16.456    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 16.456    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 16.545    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 16.564    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 16.574    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 16.545    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 14.956    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 43.842    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 43.888    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 43.881    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 43.853    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 43.881    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 43.842    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 43.842    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 43.860    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 43.860    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 15.610    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 38.716    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 39.439    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 39.439    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 39.073    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 39.073    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 39.111    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 39.111    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 38.726    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 38.716    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 39.052    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 39.052    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 39.388    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 39.388    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 39.449    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 39.449    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 39.407    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 39.397    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 8.469     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 41.274    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 15.015    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 15.425    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 15.015    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 15.015    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 7.576     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 13.423    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 5.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 6.163     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 5.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 5.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 7.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 7.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 7.380     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 7.380     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 6.156     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 40.212    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 40.212    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 40.221    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 40.221    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 41.081    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 41.081    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 41.910    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 41.659    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 41.910    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 40.788    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 40.788    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 40.542    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 40.532    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 40.532    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 40.532    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 40.216    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 40.216    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 13.308    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 6.903     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.209     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.084     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 12.292    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 12.299    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 12.299    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 12.292    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 12.292    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 12.626    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 12.626    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 12.901    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 12.901    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 7.095     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 12.309    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.249     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 7.085     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 7.095     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 8.027     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 7.699     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 13.423    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.564     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 10.838    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 12.496    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 12.496    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 12.486    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 12.486    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 12.496    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 12.486    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 12.516    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 12.516    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 12.244    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 12.244    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 11.700    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 11.690    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 11.114    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 11.104    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 10.838    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 10.838    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 11.680    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 12.358    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 12.358    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 12.447    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 12.466    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 12.476    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 12.447    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 9.273     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 49.641    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 49.687    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 49.680    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 49.652    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 49.680    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 49.641    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 49.641    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 49.659    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 49.659    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 44.515    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 45.238    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 45.238    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 44.872    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 44.872    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 44.910    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 44.910    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 44.525    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 44.515    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 44.851    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 44.851    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 45.187    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 45.187    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 45.248    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 45.248    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 45.206    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 45.196    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 47.073    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 9.371     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 9.781     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 9.371     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 9.371     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 7.740     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 46.011    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 46.011    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 46.020    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 46.020    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 46.880    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 46.880    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 47.709    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 47.458    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 47.709    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 46.587    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 46.587    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 46.341    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 46.331    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 46.331    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 46.331    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 46.015    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 46.015    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 7.625     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 7.740     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 6.389     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 9.982     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 17.881    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 17.927    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 17.920    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 17.892    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 17.920    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 17.881    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 17.881    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 17.899    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 17.899    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 14.205    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 15.084    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 9.032     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 9.442     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 9.032     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 9.032     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 8.447     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 14.021    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 14.021    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 14.030    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 14.030    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 14.890    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 14.890    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 15.719    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 15.468    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 15.719    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 14.597    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 14.597    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 14.351    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 14.341    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 14.341    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 14.341    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 14.025    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 14.025    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 8.332     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 9.211     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 11.796    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 9.671     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 8.958     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 8.965     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 8.965     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 8.958     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 8.958     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 9.292     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 9.292     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 9.567     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 9.567     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 9.642     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 8.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 8.796     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 9.632     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 9.642     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 10.333    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 10.007    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 8.447     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 15.088    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 9.982     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 17.881    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 17.927    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 17.920    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 17.892    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 17.920    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 17.881    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 17.881    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 17.899    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 17.899    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 14.205    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 15.084    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 9.032     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 9.442     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 9.032     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 9.032     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.447     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 14.021    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 14.021    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 14.030    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 14.030    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 14.890    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 14.890    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 15.719    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 15.468    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 15.719    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 14.597    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 14.597    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 14.351    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 14.341    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 14.341    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 14.341    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 14.025    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 14.025    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 8.332     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 9.211     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 11.796    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 9.671     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 8.958     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 8.965     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 8.965     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 8.958     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 8.958     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 9.292     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 9.292     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 9.567     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 9.567     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 9.642     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 8.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 8.796     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 9.632     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 9.642     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 10.333    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 10.007    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.447     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 15.088    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 9.827     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 9.827     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 9.827     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 10.372    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 10.372    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 9.827     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 9.827     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 9.827     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 10.372    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 10.372    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                    ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 19.511    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 19.557    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 19.550    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 19.522    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 19.550    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 19.511    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 19.511    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 19.529    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 19.529    ;           ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 18.614    ;           ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 19.096    ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 7.453     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 9.111     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 9.111     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 9.101     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 9.101     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 9.111     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 9.101     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 9.131     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 9.131     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 8.859     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 8.859     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 8.315     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 8.305     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 7.729     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 7.719     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 7.453     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 7.453     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 8.295     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 8.973     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 8.973     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 9.062     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 9.081     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 9.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 9.062     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 8.408     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 8.143     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 8.189     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 8.182     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 8.154     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 8.182     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 8.143     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 8.143     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 8.161     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 8.161     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 8.661     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 9.126     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 9.849     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 9.849     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 9.483     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 9.483     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 9.521     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 9.521     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 9.136     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 9.126     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 9.462     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 9.462     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 9.798     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 9.798     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 9.859     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 9.859     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 9.817     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 9.807     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 7.508     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 10.314    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 8.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 8.549     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 8.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 8.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 7.576     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 6.875     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 5.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 6.163     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 5.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 5.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 7.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 7.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 7.380     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 7.380     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 6.156     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 13.326    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 13.326    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 13.335    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 13.335    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 14.195    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 14.195    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 15.024    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 14.773    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 15.024    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 13.902    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 13.902    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 13.656    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 13.646    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 13.646    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 13.646    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 13.330    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 13.330    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 6.760     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 5.974     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.209     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.084     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 6.121     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 6.128     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 6.128     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 6.121     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 6.121     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 6.455     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 6.455     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 6.730     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 6.730     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 7.095     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 6.138     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.249     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 7.085     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 7.095     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 7.096     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 6.770     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 6.875     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 7.564     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 7.873     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 9.531     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 9.531     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 9.521     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 9.521     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 9.531     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 9.521     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 9.551     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 9.551     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 9.279     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 9.279     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 8.735     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 8.725     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.149     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.139     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 7.873     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 7.873     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 8.715     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 9.393     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 9.393     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 9.482     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 9.501     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 9.511     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 9.482     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 8.408     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 17.102    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 17.148    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 17.141    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 17.113    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 17.141    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 17.102    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 17.102    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 17.120    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 17.120    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 11.294    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 12.017    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 12.017    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 11.651    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 11.651    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 11.689    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 11.689    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 11.304    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 11.294    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 11.630    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 11.630    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 11.966    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 11.966    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 12.027    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 12.027    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 11.985    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 11.975    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 12.514    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 7.720     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 8.130     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 7.720     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 7.720     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 6.875     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 13.260    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 13.260    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 13.269    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 13.269    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 14.129    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 14.129    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 14.958    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 14.707    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 14.958    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 13.836    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 13.836    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 13.590    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 13.580    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 13.580    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 13.580    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 13.264    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 13.264    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 6.760     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 6.875     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 6.389     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 7.453     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 9.111     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 9.111     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 9.101     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 9.101     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 9.111     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 9.101     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 9.131     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 9.131     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 8.859     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 8.859     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 8.315     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 8.305     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 7.729     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 7.719     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 7.453     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 7.453     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 8.295     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 8.973     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 8.973     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 9.062     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 9.081     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 9.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 9.062     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 8.408     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 8.143     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 8.189     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 8.182     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 8.154     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 8.182     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 8.143     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 8.143     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 8.161     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 8.161     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 8.661     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 9.126     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 9.849     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 9.849     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 9.483     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 9.483     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 9.521     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 9.521     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 9.136     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 9.126     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 9.462     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 9.462     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 9.798     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 9.798     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 9.859     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 9.859     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 9.817     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 9.807     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 7.508     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 10.314    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 8.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 8.549     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 8.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 8.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 7.576     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 6.875     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 5.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 6.163     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 5.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 5.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 7.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 7.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 7.380     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 7.380     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 6.156     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 13.326    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 13.326    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 13.335    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 13.335    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 14.195    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 14.195    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 15.024    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 14.773    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 15.024    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 13.902    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 13.902    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 13.656    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 13.646    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 13.646    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 13.646    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 13.330    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 13.330    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 6.760     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 5.974     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.209     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.084     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 6.121     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 6.128     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 6.128     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 6.121     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 6.121     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 6.455     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 6.455     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 6.730     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 6.730     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 7.095     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 6.138     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.249     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 7.085     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 7.095     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 7.096     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 6.770     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 6.875     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.564     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 7.873     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 9.531     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 9.531     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 9.521     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 9.521     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 9.531     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 9.521     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 9.551     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 9.551     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 9.279     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 9.279     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 8.735     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 8.725     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.149     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.139     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 7.873     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 7.873     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 8.715     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 9.393     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 9.393     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 9.482     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 9.501     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 9.511     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 9.482     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 8.408     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 17.102    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 17.148    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 17.141    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 17.113    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 17.141    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 17.102    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 17.102    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 17.120    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 17.120    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 11.294    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 12.017    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 12.017    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 11.651    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 11.651    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 11.689    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 11.689    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 11.304    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 11.294    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 11.630    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 11.630    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 11.966    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 11.966    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 12.027    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 12.027    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 11.985    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 11.975    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 12.514    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 7.720     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 8.130     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 7.720     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 7.720     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 6.875     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 13.260    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 13.260    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 13.269    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 13.269    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 14.129    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 14.129    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 14.958    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 14.707    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 14.958    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 13.836    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 13.836    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 13.590    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 13.580    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 13.580    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 13.580    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 13.264    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 13.264    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 6.760     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 6.875     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 6.389     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 9.982     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 10.838    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 10.884    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 10.877    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 10.849    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 10.877    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 10.838    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 10.838    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 10.856    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 10.856    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 12.665    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 11.457    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 9.032     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 9.442     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 9.032     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 9.032     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 8.447     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 10.249    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 10.249    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 10.258    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 10.258    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.118    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.118    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 11.947    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 11.696    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 11.947    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 10.825    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 10.825    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 10.579    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 10.569    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 10.569    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 10.569    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 10.253    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 10.253    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 8.332     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 8.827     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 11.584    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 9.459     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 8.314     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 8.321     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 8.321     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 8.314     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 8.314     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 8.648     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 8.648     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 8.923     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 8.923     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 9.473     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 8.331     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 8.627     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 9.463     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 9.473     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 9.919     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 9.623     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 8.447     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 15.088    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 9.982     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 10.838    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 10.884    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 10.877    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 10.849    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 10.877    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 10.838    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 10.838    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 10.856    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 10.856    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 12.665    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 11.457    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 9.032     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 9.442     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 9.032     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 9.032     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.447     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 10.249    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 10.249    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 10.258    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 10.258    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.118    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.118    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 11.947    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 11.696    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 11.947    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 10.825    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 10.825    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 10.579    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 10.569    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 10.569    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 10.569    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 10.253    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 10.253    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 8.332     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 8.827     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 11.584    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 9.459     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 8.314     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 8.321     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 8.321     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 8.314     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 8.314     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 8.648     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 8.648     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 8.923     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 8.923     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 9.473     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 8.331     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 8.627     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 9.463     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 9.473     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 9.919     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 9.623     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.447     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 15.088    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 6.472     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 6.472     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 6.472     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 6.818     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 6.818     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 6.472     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 6.472     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 6.472     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 6.818     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 6.818     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------+
; Fast Model Setup Summary                                                            ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; -7.016 ; -270.683      ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; -7.016 ; -270.683      ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 0.800  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.800  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 1.373  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 1.373  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 24.565 ; 0.000         ;
; CODEC_SCLK                                                 ; 35.364 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 38.703 ; 0.000         ;
; CLK_PLL1                                                   ; 61.345 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 61.755 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------+
; Fast Model Hold Summary                                                             ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -0.065 ; -0.065        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -0.065 ; -0.065        ;
; CODEC_SCLK                                                 ; -0.046 ; -0.133        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 0.215  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.215  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 0.215  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.215  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 0.215  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 0.215  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 0.215  ; 0.000         ;
; CLK_PLL1                                                   ; 0.245  ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------+
; Fast Model Recovery Summary                                                         ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 27.346 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 27.346 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 27.347 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 27.347 ; 0.000         ;
; CODEC_SCLK                                                 ; 80.246 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------+
; Fast Model Removal Summary                                                         ;
+------------------------------------------------------------+-------+---------------+
; Clock                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------+-------+---------------+
; CODEC_SCLK                                                 ; 1.015 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 1.054 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 1.054 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1.433 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1.433 ; 0.000         ;
+------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width Summary                                              ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 8.289  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 8.289  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 11.695 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 13.498 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 13.498 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 18.531 ; 0.000         ;
; CLK_PLL1                                                   ; 30.250 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 30.250 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 30.250 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 30.250 ; 0.000         ;
; CLK_PLL2                                                   ; 31.250 ; 0.000         ;
; CRT_PIN4_CLK1                                              ; 31.250 ; 0.000         ;
; CODEC_SCLK                                                 ; 38.573 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                                                                       ;
+--------+----------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                            ; To Node                                           ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -7.016 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.472     ;
; -7.016 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.472     ;
; -7.008 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.464     ;
; -7.008 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.464     ;
; -6.974 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.430     ;
; -6.974 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.430     ;
; -6.934 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.390     ;
; -6.934 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.390     ;
; -6.933 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.389     ;
; -6.933 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.389     ;
; -6.926 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.382     ;
; -6.926 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.382     ;
; -6.880 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.336     ;
; -6.880 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.336     ;
; -6.866 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.322     ;
; -6.866 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.322     ;
; -6.852 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.308     ;
; -6.852 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.308     ;
; -6.831 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.287     ;
; -6.831 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.287     ;
; -6.828 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.284     ;
; -6.828 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.284     ;
; -6.787 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.243     ;
; -6.787 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.008      ; 17.243     ;
; -6.688 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 17.140     ;
; -6.688 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 17.140     ;
; -6.680 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 17.132     ;
; -6.680 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 17.132     ;
; -6.646 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 17.098     ;
; -6.646 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 17.098     ;
; -6.645 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 17.100     ;
; -6.645 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 17.100     ;
; -6.637 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 17.092     ;
; -6.637 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 17.092     ;
; -6.612 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.001      ; 17.061     ;
; -6.612 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.001      ; 17.061     ;
; -6.606 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 17.058     ;
; -6.606 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 17.058     ;
; -6.605 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 17.057     ;
; -6.605 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 17.057     ;
; -6.603 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 17.058     ;
; -6.603 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 17.058     ;
; -6.598 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 17.050     ;
; -6.598 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 17.050     ;
; -6.563 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 17.018     ;
; -6.563 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 17.018     ;
; -6.562 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 17.017     ;
; -6.562 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 17.017     ;
; -6.555 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 17.010     ;
; -6.555 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 17.010     ;
; -6.552 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 17.004     ;
; -6.552 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 17.004     ;
; -6.538 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.990     ;
; -6.538 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.990     ;
; -6.524 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.976     ;
; -6.524 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.976     ;
; -6.518 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.970     ;
; -6.518 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.970     ;
; -6.510 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.962     ;
; -6.510 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.962     ;
; -6.509 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 16.964     ;
; -6.509 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 16.964     ;
; -6.503 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.955     ;
; -6.503 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.955     ;
; -6.500 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.952     ;
; -6.500 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.952     ;
; -6.495 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 16.950     ;
; -6.495 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 16.950     ;
; -6.487 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.004     ; 16.931     ;
; -6.487 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.004     ; 16.931     ;
; -6.481 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 16.936     ;
; -6.481 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 16.936     ;
; -6.480 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.001      ; 16.929     ;
; -6.480 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.001      ; 16.929     ;
; -6.479 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.004     ; 16.923     ;
; -6.479 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.004     ; 16.923     ;
; -6.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.928     ;
; -6.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.928     ;
; -6.475 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 16.930     ;
; -6.475 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 16.930     ;
; -6.467 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.004     ; 16.911     ;
; -6.467 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 16.922     ;
; -6.467 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.004     ; 16.911     ;
; -6.467 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 16.922     ;
; -6.460 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 16.915     ;
; -6.460 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 16.915     ;
; -6.459 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.911     ;
; -6.459 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.004     ; 16.903     ;
; -6.459 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.911     ;
; -6.459 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.004     ; 16.903     ;
; -6.457 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 16.912     ;
; -6.457 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.007      ; 16.912     ;
; -6.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.004     ; 16.889     ;
; -6.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.004     ; 16.889     ;
; -6.436 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.888     ;
; -6.436 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.888     ;
; -6.435 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.887     ;
; -6.435 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.004      ; 16.887     ;
; -6.434 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][14] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.002      ; 16.884     ;
; -6.434 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][14] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.002      ; 16.884     ;
+--------+----------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                                                                       ;
+--------+----------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                            ; To Node                                           ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -7.016 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.472     ;
; -7.016 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.472     ;
; -7.008 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.464     ;
; -7.008 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.464     ;
; -6.974 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.430     ;
; -6.974 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.430     ;
; -6.934 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.390     ;
; -6.934 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.390     ;
; -6.933 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.389     ;
; -6.933 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.389     ;
; -6.926 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.382     ;
; -6.926 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.382     ;
; -6.880 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.336     ;
; -6.880 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.336     ;
; -6.866 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.322     ;
; -6.866 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.322     ;
; -6.852 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.308     ;
; -6.852 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.308     ;
; -6.831 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.287     ;
; -6.831 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.287     ;
; -6.828 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.284     ;
; -6.828 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.284     ;
; -6.787 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.243     ;
; -6.787 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.008      ; 17.243     ;
; -6.688 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 17.140     ;
; -6.688 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 17.140     ;
; -6.680 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 17.132     ;
; -6.680 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 17.132     ;
; -6.646 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 17.098     ;
; -6.646 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 17.098     ;
; -6.645 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 17.100     ;
; -6.645 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 17.100     ;
; -6.637 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 17.092     ;
; -6.637 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 17.092     ;
; -6.612 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.001      ; 17.061     ;
; -6.612 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.001      ; 17.061     ;
; -6.606 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 17.058     ;
; -6.606 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 17.058     ;
; -6.605 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 17.057     ;
; -6.605 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 17.057     ;
; -6.603 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 17.058     ;
; -6.603 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 17.058     ;
; -6.598 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 17.050     ;
; -6.598 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 17.050     ;
; -6.563 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 17.018     ;
; -6.563 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 17.018     ;
; -6.562 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 17.017     ;
; -6.562 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 17.017     ;
; -6.555 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 17.010     ;
; -6.555 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 17.010     ;
; -6.552 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 17.004     ;
; -6.552 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 17.004     ;
; -6.538 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.990     ;
; -6.538 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.990     ;
; -6.524 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.976     ;
; -6.524 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.976     ;
; -6.518 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.970     ;
; -6.518 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.970     ;
; -6.510 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.962     ;
; -6.510 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.962     ;
; -6.509 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 16.964     ;
; -6.509 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 16.964     ;
; -6.503 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.955     ;
; -6.503 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.955     ;
; -6.500 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.952     ;
; -6.500 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.952     ;
; -6.495 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 16.950     ;
; -6.495 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 16.950     ;
; -6.487 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.004     ; 16.931     ;
; -6.487 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.004     ; 16.931     ;
; -6.481 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 16.936     ;
; -6.481 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 16.936     ;
; -6.480 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.001      ; 16.929     ;
; -6.480 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][15] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.001      ; 16.929     ;
; -6.479 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.004     ; 16.923     ;
; -6.479 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.004     ; 16.923     ;
; -6.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.928     ;
; -6.476 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.928     ;
; -6.475 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 16.930     ;
; -6.475 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 16.930     ;
; -6.467 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.004     ; 16.911     ;
; -6.467 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 16.922     ;
; -6.467 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.004     ; 16.911     ;
; -6.467 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 16.922     ;
; -6.460 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 16.915     ;
; -6.460 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][0]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 16.915     ;
; -6.459 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.911     ;
; -6.459 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.004     ; 16.903     ;
; -6.459 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.911     ;
; -6.459 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.004     ; 16.903     ;
; -6.457 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 16.912     ;
; -6.457 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.007      ; 16.912     ;
; -6.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.004     ; 16.889     ;
; -6.445 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.004     ; 16.889     ;
; -6.436 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.888     ;
; -6.436 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.888     ;
; -6.435 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.887     ;
; -6.435 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.004      ; 16.887     ;
; -6.434 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][14] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.002      ; 16.884     ;
; -6.434 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][14] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.002      ; 16.884     ;
+--------+----------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                 ;
+-------+---------------------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                         ; To Node                                                                         ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.800 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.642      ;
; 0.800 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.642      ;
; 0.880 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.561      ;
; 0.880 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.561      ;
; 0.912 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.530      ;
; 0.912 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.530      ;
; 0.921 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.521      ;
; 0.921 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.521      ;
; 0.938 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.004     ; 9.507      ;
; 0.938 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.004     ; 9.507      ;
; 0.944 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.497      ;
; 0.944 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.497      ;
; 0.957 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.484      ;
; 0.957 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.484      ;
; 0.966 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.011     ; 9.472      ;
; 0.966 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.011     ; 9.472      ;
; 0.980 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.012     ; 9.457      ;
; 0.980 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.012     ; 9.457      ;
; 0.992 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.449      ;
; 0.992 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.449      ;
; 0.999 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.443      ;
; 0.999 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.443      ;
; 1.012 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.430      ;
; 1.012 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.430      ;
; 1.033 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.409      ;
; 1.033 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.409      ;
; 1.036 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.406      ;
; 1.036 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.406      ;
; 1.046 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.012     ; 9.391      ;
; 1.046 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.012     ; 9.391      ;
; 1.050 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.004     ; 9.395      ;
; 1.050 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.004     ; 9.395      ;
; 1.054 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.388      ;
; 1.054 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.388      ;
; 1.056 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.385      ;
; 1.056 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.385      ;
; 1.060 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.013     ; 9.376      ;
; 1.060 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.013     ; 9.376      ;
; 1.063 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[0][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.006     ; 9.380      ;
; 1.063 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[0][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.006     ; 9.380      ;
; 1.066 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[1][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.006     ; 9.377      ;
; 1.066 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[1][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.006     ; 9.377      ;
; 1.069 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.372      ;
; 1.069 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.372      ;
; 1.077 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.365      ;
; 1.077 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.365      ;
; 1.086 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[0][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.005     ; 9.358      ;
; 1.086 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[0][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.005     ; 9.358      ;
; 1.087 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.011     ; 9.351      ;
; 1.087 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.011     ; 9.351      ;
; 1.091 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.350      ;
; 1.091 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.350      ;
; 1.092 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.349      ;
; 1.092 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.349      ;
; 1.095 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.346      ;
; 1.095 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.346      ;
; 1.101 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.012     ; 9.336      ;
; 1.101 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.012     ; 9.336      ;
; 1.104 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.337      ;
; 1.104 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.337      ;
; 1.107 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.335      ;
; 1.107 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.335      ;
; 1.110 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.012     ; 9.327      ;
; 1.110 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.012     ; 9.327      ;
; 1.111 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.331      ;
; 1.111 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.331      ;
; 1.116 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.325      ;
; 1.116 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.325      ;
; 1.118 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.009     ; 9.322      ;
; 1.118 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.009     ; 9.322      ;
; 1.123 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.012     ; 9.314      ;
; 1.123 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.012     ; 9.314      ;
; 1.124 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.013     ; 9.312      ;
; 1.124 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.317      ;
; 1.124 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.013     ; 9.312      ;
; 1.124 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.317      ;
; 1.127 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|BUFFER_B[9]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.015     ; 9.307      ;
; 1.127 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.315      ;
; 1.127 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|BUFFER_B[9]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.015     ; 9.307      ;
; 1.127 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.315      ;
; 1.137 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.013     ; 9.299      ;
; 1.137 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.013     ; 9.299      ;
; 1.141 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|BUFFER_B[9]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.016     ; 9.292      ;
; 1.141 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|BUFFER_B[9]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.016     ; 9.292      ;
; 1.143 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[0][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.299      ;
; 1.143 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[0][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.299      ;
; 1.144 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.004     ; 9.301      ;
; 1.144 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.004     ; 9.301      ;
; 1.145 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|BUFFER_B[21]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.001     ; 9.303      ;
; 1.145 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|BUFFER_B[21]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.001     ; 9.303      ;
; 1.146 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[1][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.296      ;
; 1.146 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[1][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.296      ;
; 1.158 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.283      ;
; 1.158 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.283      ;
; 1.163 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.278      ;
; 1.163 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.278      ;
; 1.165 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.011     ; 9.273      ;
; 1.165 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.011     ; 9.273      ;
; 1.166 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.007     ; 9.276      ;
; 1.166 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[0][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.006     ; 9.277      ;
+-------+---------------------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                                 ;
+-------+---------------------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                         ; To Node                                                                         ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.800 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.642      ;
; 0.800 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.642      ;
; 0.880 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.561      ;
; 0.880 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.561      ;
; 0.912 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.530      ;
; 0.912 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.530      ;
; 0.921 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.521      ;
; 0.921 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.521      ;
; 0.938 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.004     ; 9.507      ;
; 0.938 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.004     ; 9.507      ;
; 0.944 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.497      ;
; 0.944 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.497      ;
; 0.957 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.484      ;
; 0.957 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.484      ;
; 0.966 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.011     ; 9.472      ;
; 0.966 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.011     ; 9.472      ;
; 0.980 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.012     ; 9.457      ;
; 0.980 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.012     ; 9.457      ;
; 0.992 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.449      ;
; 0.992 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.449      ;
; 0.999 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.443      ;
; 0.999 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.443      ;
; 1.012 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.430      ;
; 1.012 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.430      ;
; 1.033 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.409      ;
; 1.033 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.409      ;
; 1.036 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.406      ;
; 1.036 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.406      ;
; 1.046 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.012     ; 9.391      ;
; 1.046 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.012     ; 9.391      ;
; 1.050 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.004     ; 9.395      ;
; 1.050 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.004     ; 9.395      ;
; 1.054 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.388      ;
; 1.054 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.388      ;
; 1.056 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.385      ;
; 1.056 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.385      ;
; 1.060 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.013     ; 9.376      ;
; 1.060 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.013     ; 9.376      ;
; 1.063 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[0][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.006     ; 9.380      ;
; 1.063 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[0][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.006     ; 9.380      ;
; 1.066 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[1][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.006     ; 9.377      ;
; 1.066 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[1][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.006     ; 9.377      ;
; 1.069 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.372      ;
; 1.069 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.372      ;
; 1.077 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.365      ;
; 1.077 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.365      ;
; 1.086 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[0][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.005     ; 9.358      ;
; 1.086 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[0][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.005     ; 9.358      ;
; 1.087 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.011     ; 9.351      ;
; 1.087 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.011     ; 9.351      ;
; 1.091 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.350      ;
; 1.091 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.350      ;
; 1.092 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.349      ;
; 1.092 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.349      ;
; 1.095 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.346      ;
; 1.095 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.346      ;
; 1.101 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.012     ; 9.336      ;
; 1.101 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.012     ; 9.336      ;
; 1.104 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.337      ;
; 1.104 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.337      ;
; 1.107 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.335      ;
; 1.107 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.335      ;
; 1.110 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.012     ; 9.327      ;
; 1.110 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.012     ; 9.327      ;
; 1.111 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.331      ;
; 1.111 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.331      ;
; 1.116 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.325      ;
; 1.116 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.325      ;
; 1.118 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.009     ; 9.322      ;
; 1.118 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.009     ; 9.322      ;
; 1.123 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.012     ; 9.314      ;
; 1.123 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.012     ; 9.314      ;
; 1.124 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.013     ; 9.312      ;
; 1.124 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.317      ;
; 1.124 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.013     ; 9.312      ;
; 1.124 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.317      ;
; 1.127 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|BUFFER_B[9]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.015     ; 9.307      ;
; 1.127 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.315      ;
; 1.127 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|BUFFER_B[9]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.015     ; 9.307      ;
; 1.127 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.315      ;
; 1.137 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.013     ; 9.299      ;
; 1.137 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[1][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.013     ; 9.299      ;
; 1.141 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|BUFFER_B[9]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.016     ; 9.292      ;
; 1.141 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|BUFFER_B[9]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.016     ; 9.292      ;
; 1.143 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[0][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.299      ;
; 1.143 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[0][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.299      ;
; 1.144 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.004     ; 9.301      ;
; 1.144 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.004     ; 9.301      ;
; 1.145 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|BUFFER_B[21]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.001     ; 9.303      ;
; 1.145 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|BUFFER_B[21]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.001     ; 9.303      ;
; 1.146 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[1][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.296      ;
; 1.146 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|EXWORD_REG[1][5]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.296      ;
; 1.158 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.283      ;
; 1.158 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.283      ;
; 1.163 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.278      ;
; 1.163 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[0][4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.278      ;
; 1.165 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.011     ; 9.273      ;
; 1.165 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[1][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.011     ; 9.273      ;
; 1.166 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|BIW[2][5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.007     ; 9.276      ;
; 1.166 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_OPCODE_DECODER:I_OPCODE|DEST_EXWORD_REG[0][5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.006     ; 9.277      ;
+-------+---------------------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                          ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                         ; To Node                                                                                  ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 1.373 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.028     ; 9.048      ;
; 1.373 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.028     ; 9.048      ;
; 1.409 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.034     ; 9.006      ;
; 1.409 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.034     ; 9.006      ;
; 1.431 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.031     ; 8.987      ;
; 1.431 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.031     ; 8.987      ;
; 1.441 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.024     ; 8.984      ;
; 1.441 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.024     ; 8.984      ;
; 1.448 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.033     ; 8.968      ;
; 1.448 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.033     ; 8.968      ;
; 1.449 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.039     ; 8.961      ;
; 1.449 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.039     ; 8.961      ;
; 1.453 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.029     ; 8.967      ;
; 1.453 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.029     ; 8.967      ;
; 1.467 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.025     ; 8.957      ;
; 1.467 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.025     ; 8.957      ;
; 1.475 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.018     ; 8.956      ;
; 1.475 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.018     ; 8.956      ;
; 1.489 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.035     ; 8.925      ;
; 1.489 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.035     ; 8.925      ;
; 1.494 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.028     ; 8.927      ;
; 1.494 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.028     ; 8.927      ;
; 1.511 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.032     ; 8.906      ;
; 1.511 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.025     ; 8.913      ;
; 1.511 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.032     ; 8.906      ;
; 1.511 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.025     ; 8.913      ;
; 1.516 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.036     ; 8.897      ;
; 1.516 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.036     ; 8.897      ;
; 1.517 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.029     ; 8.903      ;
; 1.517 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.029     ; 8.903      ;
; 1.519 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.029     ; 8.901      ;
; 1.519 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.029     ; 8.901      ;
; 1.521 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.025     ; 8.903      ;
; 1.521 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.025     ; 8.903      ;
; 1.528 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.034     ; 8.887      ;
; 1.528 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.034     ; 8.887      ;
; 1.529 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.040     ; 8.880      ;
; 1.529 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.040     ; 8.880      ;
; 1.530 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.034     ; 8.885      ;
; 1.530 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.029     ; 8.890      ;
; 1.530 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.034     ; 8.885      ;
; 1.530 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.029     ; 8.890      ;
; 1.533 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[21]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.027     ; 8.889      ;
; 1.533 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.013     ; 8.903      ;
; 1.533 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[21]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.027     ; 8.889      ;
; 1.533 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.013     ; 8.903      ;
; 1.539 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.039     ; 8.871      ;
; 1.539 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.039     ; 8.871      ;
; 1.541 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.023     ; 8.885      ;
; 1.541 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.023     ; 8.885      ;
; 1.543 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.039     ; 8.867      ;
; 1.543 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.039     ; 8.867      ;
; 1.544 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[5]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.021     ; 8.884      ;
; 1.544 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[5]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.021     ; 8.884      ;
; 1.547 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.026     ; 8.876      ;
; 1.547 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.031     ; 8.871      ;
; 1.547 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.026     ; 8.876      ;
; 1.547 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.031     ; 8.871      ;
; 1.552 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.031     ; 8.866      ;
; 1.552 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.031     ; 8.866      ;
; 1.553 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.035     ; 8.861      ;
; 1.553 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.035     ; 8.861      ;
; 1.555 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[21]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.029     ; 8.865      ;
; 1.555 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.019     ; 8.875      ;
; 1.555 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[21]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.029     ; 8.865      ;
; 1.555 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.019     ; 8.875      ;
; 1.562 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.018     ; 8.869      ;
; 1.562 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.024     ; 8.863      ;
; 1.562 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.018     ; 8.869      ;
; 1.562 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.024     ; 8.863      ;
; 1.566 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.035     ; 8.848      ;
; 1.566 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.035     ; 8.848      ;
; 1.569 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.033     ; 8.847      ;
; 1.569 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.028     ; 8.852      ;
; 1.569 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.033     ; 8.847      ;
; 1.569 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.028     ; 8.852      ;
; 1.570 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.039     ; 8.840      ;
; 1.570 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.039     ; 8.840      ;
; 1.572 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.028     ; 8.849      ;
; 1.572 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.028     ; 8.849      ;
; 1.575 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.032     ; 8.842      ;
; 1.575 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.032     ; 8.842      ;
; 1.579 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.023     ; 8.847      ;
; 1.579 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.021     ; 8.849      ;
; 1.579 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.023     ; 8.847      ;
; 1.579 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.021     ; 8.849      ;
; 1.580 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.018     ; 8.851      ;
; 1.580 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.018     ; 8.851      ;
; 1.585 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.025     ; 8.839      ;
; 1.585 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.025     ; 8.839      ;
; 1.586 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.030     ; 8.833      ;
; 1.586 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.030     ; 8.833      ;
; 1.587 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.036     ; 8.826      ;
; 1.587 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.036     ; 8.826      ;
; 1.588 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.025     ; 8.836      ;
; 1.588 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.032     ; 8.829      ;
; 1.588 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.025     ; 8.836      ;
; 1.588 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.032     ; 8.829      ;
; 1.592 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.034     ; 8.823      ;
; 1.592 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.034     ; 8.823      ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                          ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                         ; To Node                                                                                  ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 1.373 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.028     ; 9.048      ;
; 1.373 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.028     ; 9.048      ;
; 1.409 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.034     ; 9.006      ;
; 1.409 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.034     ; 9.006      ;
; 1.431 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.031     ; 8.987      ;
; 1.431 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.031     ; 8.987      ;
; 1.441 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.024     ; 8.984      ;
; 1.441 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.024     ; 8.984      ;
; 1.448 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.033     ; 8.968      ;
; 1.448 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.033     ; 8.968      ;
; 1.449 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.039     ; 8.961      ;
; 1.449 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.039     ; 8.961      ;
; 1.453 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.029     ; 8.967      ;
; 1.453 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.029     ; 8.967      ;
; 1.467 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.025     ; 8.957      ;
; 1.467 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.025     ; 8.957      ;
; 1.475 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.018     ; 8.956      ;
; 1.475 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.018     ; 8.956      ;
; 1.489 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.035     ; 8.925      ;
; 1.489 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.035     ; 8.925      ;
; 1.494 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.028     ; 8.927      ;
; 1.494 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.028     ; 8.927      ;
; 1.511 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.032     ; 8.906      ;
; 1.511 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.025     ; 8.913      ;
; 1.511 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.032     ; 8.906      ;
; 1.511 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.025     ; 8.913      ;
; 1.516 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.036     ; 8.897      ;
; 1.516 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.036     ; 8.897      ;
; 1.517 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.029     ; 8.903      ;
; 1.517 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.029     ; 8.903      ;
; 1.519 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.029     ; 8.901      ;
; 1.519 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.029     ; 8.901      ;
; 1.521 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.025     ; 8.903      ;
; 1.521 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.025     ; 8.903      ;
; 1.528 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.034     ; 8.887      ;
; 1.528 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.034     ; 8.887      ;
; 1.529 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.040     ; 8.880      ;
; 1.529 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.040     ; 8.880      ;
; 1.530 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.034     ; 8.885      ;
; 1.530 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.029     ; 8.890      ;
; 1.530 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.034     ; 8.885      ;
; 1.530 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.029     ; 8.890      ;
; 1.533 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[21]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.027     ; 8.889      ;
; 1.533 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.013     ; 8.903      ;
; 1.533 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[21]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.027     ; 8.889      ;
; 1.533 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.013     ; 8.903      ;
; 1.539 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.039     ; 8.871      ;
; 1.539 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.039     ; 8.871      ;
; 1.541 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.023     ; 8.885      ;
; 1.541 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.023     ; 8.885      ;
; 1.543 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.039     ; 8.867      ;
; 1.543 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.039     ; 8.867      ;
; 1.544 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[5]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.021     ; 8.884      ;
; 1.544 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[5]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.021     ; 8.884      ;
; 1.547 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.026     ; 8.876      ;
; 1.547 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.031     ; 8.871      ;
; 1.547 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.026     ; 8.876      ;
; 1.547 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.031     ; 8.871      ;
; 1.552 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.031     ; 8.866      ;
; 1.552 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.031     ; 8.866      ;
; 1.553 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.035     ; 8.861      ;
; 1.553 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.035     ; 8.861      ;
; 1.555 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[21]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.029     ; 8.865      ;
; 1.555 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.019     ; 8.875      ;
; 1.555 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[21]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.029     ; 8.865      ;
; 1.555 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.019     ; 8.875      ;
; 1.562 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.018     ; 8.869      ;
; 1.562 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.024     ; 8.863      ;
; 1.562 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.018     ; 8.869      ;
; 1.562 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.024     ; 8.863      ;
; 1.566 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.035     ; 8.848      ;
; 1.566 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.035     ; 8.848      ;
; 1.569 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.033     ; 8.847      ;
; 1.569 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.028     ; 8.852      ;
; 1.569 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.033     ; 8.847      ;
; 1.569 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.028     ; 8.852      ;
; 1.570 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.039     ; 8.840      ;
; 1.570 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.039     ; 8.840      ;
; 1.572 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.028     ; 8.849      ;
; 1.572 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.028     ; 8.849      ;
; 1.575 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.032     ; 8.842      ;
; 1.575 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.032     ; 8.842      ;
; 1.579 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.023     ; 8.847      ;
; 1.579 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.021     ; 8.849      ;
; 1.579 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.023     ; 8.847      ;
; 1.579 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.021     ; 8.849      ;
; 1.580 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.018     ; 8.851      ;
; 1.580 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.018     ; 8.851      ;
; 1.585 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.025     ; 8.839      ;
; 1.585 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.025     ; 8.839      ;
; 1.586 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.030     ; 8.833      ;
; 1.586 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.030     ; 8.833      ;
; 1.587 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.036     ; 8.826      ;
; 1.587 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.036     ; 8.826      ;
; 1.588 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.025     ; 8.836      ;
; 1.588 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.032     ; 8.829      ;
; 1.588 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.025     ; 8.836      ;
; 1.588 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.032     ; 8.829      ;
; 1.592 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.034     ; 8.823      ;
; 1.592 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.034     ; 8.823      ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                          ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node             ; To Node               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 24.565 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.857      ;
; 24.578 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.844      ;
; 24.600 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.822      ;
; 24.737 ; CLK_24576             ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.685      ;
; 24.763 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.659      ;
; 24.776 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.646      ;
; 24.903 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.519      ;
; 24.903 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.519      ;
; 24.911 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.511      ;
; 25.055 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.367      ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'CODEC_SCLK'                                                                                                                              ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                   ; To Node                                        ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 35.364 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[119] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.144      ; 5.512      ;
; 35.364 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[118] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.144      ; 5.512      ;
; 35.364 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[117] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.144      ; 5.512      ;
; 35.364 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[116] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.144      ; 5.512      ;
; 35.364 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[115] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.144      ; 5.512      ;
; 35.364 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[114] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.144      ; 5.512      ;
; 35.364 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[113] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.144      ; 5.512      ;
; 35.364 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[112] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.144      ; 5.512      ;
; 35.364 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[11]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.144      ; 5.512      ;
; 35.364 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[10]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.144      ; 5.512      ;
; 35.364 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[9]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.144      ; 5.512      ;
; 35.364 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[8]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.144      ; 5.512      ;
; 35.364 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[7]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.144      ; 5.512      ;
; 35.364 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[6]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.144      ; 5.512      ;
; 35.364 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[3]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.144      ; 5.512      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[97]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[96]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[95]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[94]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[93]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[92]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[91]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[90]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[89]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[61]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[60]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[59]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[58]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[57]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[56]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.408 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[0]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.148      ; 5.472      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[142] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[141] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[140] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[139] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[138] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[137] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[136] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[135] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[134] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[130] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[129] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[128] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[104] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[103] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[27]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[26]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[25]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[19]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[18]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[17]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[16]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.411 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[15]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.218      ; 5.539      ;
; 35.468 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[126] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.151      ; 5.415      ;
; 35.468 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[125] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.151      ; 5.415      ;
; 35.468 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[124] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.151      ; 5.415      ;
; 35.468 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[123] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.151      ; 5.415      ;
; 35.468 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[122] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.151      ; 5.415      ;
; 35.468 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[121] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.151      ; 5.415      ;
; 35.468 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[120] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.151      ; 5.415      ;
; 35.468 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[5]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.151      ; 5.415      ;
; 35.468 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[4]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.151      ; 5.415      ;
; 35.468 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[2]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.151      ; 5.415      ;
; 35.468 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[1]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.151      ; 5.415      ;
; 35.476 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[127] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.155      ; 5.411      ;
; 35.476 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[102] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.155      ; 5.411      ;
; 35.476 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[101] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.155      ; 5.411      ;
; 35.476 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[100] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.155      ; 5.411      ;
; 35.476 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[99]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.155      ; 5.411      ;
; 35.476 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[98]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.155      ; 5.411      ;
; 35.476 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[62]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.155      ; 5.411      ;
; 35.476 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[55]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.155      ; 5.411      ;
; 35.476 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[54]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.155      ; 5.411      ;
; 35.476 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[53]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.155      ; 5.411      ;
; 35.476 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[52]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.155      ; 5.411      ;
; 35.476 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[51]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.155      ; 5.411      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[75]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[74]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[73]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[72]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[71]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[70]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[69]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[68]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[67]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[66]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[65]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[64]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[63]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[50]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[49]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.478 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[12]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.152      ; 5.406      ;
; 35.490 ; A4299:I_4299|BUFFER_IN[237] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[119] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.156      ; 5.398      ;
; 35.490 ; A4299:I_4299|BUFFER_IN[237] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[118] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.156      ; 5.398      ;
; 35.490 ; A4299:I_4299|BUFFER_IN[237] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[117] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.156      ; 5.398      ;
; 35.490 ; A4299:I_4299|BUFFER_IN[237] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[116] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.156      ; 5.398      ;
; 35.490 ; A4299:I_4299|BUFFER_IN[237] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[115] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.156      ; 5.398      ;
; 35.490 ; A4299:I_4299|BUFFER_IN[237] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[114] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.156      ; 5.398      ;
; 35.490 ; A4299:I_4299|BUFFER_IN[237] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[113] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.156      ; 5.398      ;
; 35.490 ; A4299:I_4299|BUFFER_IN[237] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[112] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.156      ; 5.398      ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                  ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node           ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 38.703 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.391      ;
; 38.727 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.367      ;
; 38.727 ; SCLK_6M4          ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.367      ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'CLK_PLL1'                                                                                               ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 61.345 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.187      ;
; 61.345 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.187      ;
; 61.345 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.187      ;
; 61.345 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.187      ;
; 61.345 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.187      ;
; 61.404 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.128      ;
; 61.404 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.128      ;
; 61.404 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.128      ;
; 61.404 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.128      ;
; 61.404 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.128      ;
; 61.520 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 1.014      ;
; 61.539 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 0.995      ;
; 61.579 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 0.955      ;
; 61.583 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.949      ;
; 61.583 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.949      ;
; 61.583 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.949      ;
; 61.583 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.949      ;
; 61.583 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.949      ;
; 61.598 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 0.936      ;
; 61.648 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.884      ;
; 61.648 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.884      ;
; 61.648 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.884      ;
; 61.648 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.884      ;
; 61.648 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.884      ;
; 61.701 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.831      ;
; 61.701 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.831      ;
; 61.701 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.831      ;
; 61.701 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.831      ;
; 61.701 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.831      ;
; 61.758 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 0.776      ;
; 61.777 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 0.757      ;
; 61.823 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 0.711      ;
; 61.842 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 0.692      ;
; 61.876 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 0.658      ;
; 61.895 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.002      ; 0.639      ;
; 62.018 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.514      ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 61.755 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.777      ;
; 61.765 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.767      ;
; 61.814 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.718      ;
; 61.894 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.638      ;
; 61.940 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.592      ;
; 62.004 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.528      ;
; 62.014 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.518      ;
; 62.014 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.518      ;
; 62.120 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.412      ;
; 62.122 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.410      ;
; 62.128 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.404      ;
; 62.138 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.394      ;
; 62.165 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; CLK_0M5              ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                           ;
+--------+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                    ; To Node                                                                                      ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -0.065 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|ADR_EN_P                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.725      ; 1.812      ;
; -0.065 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|ADR_EN_P                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.725      ; 1.812      ;
; 0.041  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|LDS_RD_EN_P                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.713      ; 1.906      ;
; 0.041  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|LDS_RD_EN_P                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.713      ; 1.906      ;
; 0.164  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|ADR_EN_N                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.725      ; 2.041      ;
; 0.164  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|ADR_EN_N                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.725      ; 2.041      ;
; 0.193  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|LDS_WR_EN_P                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.713      ; 2.058      ;
; 0.193  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|LDS_WR_EN_P                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.713      ; 2.058      ;
; 0.194  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|WAITSTATES                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.722      ; 2.068      ;
; 0.194  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|WAITSTATES                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.722      ; 2.068      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                          ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_1                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_1                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                              ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                              ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                          ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|TAS_LOCK                                    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|TAS_LOCK                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.GET_VECTOR           ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.GET_VECTOR           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[1]                                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[1]                                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[2]                                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[2]                                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_RESET          ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_BUS_ERR        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_BUS_ERR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_ADR_ERR        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_ADR_ERR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_MISC           ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_MISC           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_HI  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_HI  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                              ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_LO  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_LO  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_INSTRUCTION    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_INSTRUCTION    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_STATUS         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_STATUS         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; RESET_CPUn                                                                                   ; RESET_CPUn                                                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[1]                        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[1]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[0]                        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[0]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP                            ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_INT            ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_INT            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[0]                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[0]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[1]                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[1]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:LOCK                                                    ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:LOCK                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[4]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[4]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_SP_HI                         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_SP_HI                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_HI                     ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_HI                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_LO                     ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_LO                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_P_RESET                    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_P_RESET                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_PC_HI          ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_PC_HI          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                                    ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_HI        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_HI        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_LO        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_LO        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_HI         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_HI         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_LO         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_LO         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[0]       ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_BIW_2                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_BIW_2                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; \FLASH_WS:TMP[1]                                                                             ; \FLASH_WS:TMP[1]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; \FLASH_WS:TMP[0]                                                                             ; \FLASH_WS:TMP[0]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; \FLASH_WS:TMP[2]                                                                             ; \FLASH_WS:TMP[2]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[2]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[2]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[1]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[1]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[0]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[0]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\SHFT:LOCK                                                      ; FLASHBOOT_UMASPI:I_FLASHBOOT|\SHFT:LOCK                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_CLK_S                                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_CLK_S                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.IDLE                             ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.IDLE                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.WAIT_CTRL_RDY        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.WAIT_CTRL_RDY        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SRC_2_HI                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SRC_2_HI                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|RESET_CNT[0]                   ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|RESET_CNT[0]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|VMA_In                              ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|VMA_In                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                                ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_EXT                        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_EXT                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_LO                         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_LO                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.HALT                 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.HALT                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_HI                         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_HI                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[1]       ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_DIN_S                                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_DIN_S                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|OV_DIV_MUL                                       ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|OV_DIV_MUL                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[3] ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                             ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|E                                   ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|E                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA[3]                            ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA[3]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[3]                            ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[3]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; \SLOW_CPU:TMP[0]                                                                             ; \SLOW_CPU:TMP[0]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; \SLOW_CPU:TMP[2]                                                                             ; \SLOW_CPU:TMP[2]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; \SLOW_CPU:TMP[1]                                                                             ; \SLOW_CPU:TMP[1]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                           ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                           ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                            ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
+--------+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                                                                                           ;
+--------+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                    ; To Node                                                                                      ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -0.065 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|ADR_EN_P                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.725      ; 1.812      ;
; -0.065 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|ADR_EN_P                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.725      ; 1.812      ;
; 0.041  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|LDS_RD_EN_P                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.713      ; 1.906      ;
; 0.041  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|LDS_RD_EN_P                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.713      ; 1.906      ;
; 0.164  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|ADR_EN_N                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.725      ; 2.041      ;
; 0.164  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|ADR_EN_N                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.725      ; 2.041      ;
; 0.193  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|LDS_WR_EN_P                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.713      ; 2.058      ;
; 0.193  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|LDS_WR_EN_P                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.713      ; 2.058      ;
; 0.194  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|WAITSTATES                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.722      ; 2.068      ;
; 0.194  ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|WAITSTATES                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.722      ; 2.068      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                          ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_1                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_1                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                              ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                              ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                          ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|TAS_LOCK                                    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|TAS_LOCK                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.GET_VECTOR           ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.GET_VECTOR           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[1]                                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[1]                                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[2]                                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|CMD_PNTR[2]                                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_RESET          ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_BUS_ERR        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_BUS_ERR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_ADR_ERR        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_ADR_ERR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_MISC           ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_MISC           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_HI  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_HI  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                              ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_LO  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_ACCESS_ADR_LO  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_INSTRUCTION    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_INSTRUCTION    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_STATUS         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_STATUS         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; RESET_CPUn                                                                                   ; RESET_CPUn                                                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[1]                        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[1]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[0]                        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|SLICE_CNT[0]                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP                            ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_INT            ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EXCEPTION_Q.EX_INT            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[0]                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[0]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[1]                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:BOOT_ACK_TMP[1]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:LOCK                                                    ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:LOCK                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[4]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[4]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_SP_HI                         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_SP_HI                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_HI                     ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_HI                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_LO                     ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.WR_DEST_2_LO                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_P_RESET                    ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_P_RESET                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_PC_HI          ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.STACK_PC_HI          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                                    ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_HI        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_HI        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_LO        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_SSP_LO        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_HI         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_HI         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_LO         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.UPDATE_PC_LO         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[0]       ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_BIW_2                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_BIW_2                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; \FLASH_WS:TMP[1]                                                                             ; \FLASH_WS:TMP[1]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; \FLASH_WS:TMP[0]                                                                             ; \FLASH_WS:TMP[0]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; \FLASH_WS:TMP[2]                                                                             ; \FLASH_WS:TMP[2]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[2]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[2]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[1]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[1]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[0]                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_MC_WAIT:TMP[0]                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\SHFT:LOCK                                                      ; FLASHBOOT_UMASPI:I_FLASHBOOT|\SHFT:LOCK                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_CLK_S                                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_CLK_S                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.IDLE                             ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.IDLE                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.WAIT_CTRL_RDY        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.WAIT_CTRL_RDY        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SRC_2_HI                      ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SRC_2_HI                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|RESET_CNT[0]                   ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|RESET_CNT[0]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|VMA_In                              ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|VMA_In                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                                ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_EXT                        ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.FETCH_EXT                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_LO                         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_LO                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.HALT                 ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|EX_STATE.HALT                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_HI                         ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_CONTROL:I_CTRL|EXEC_STATE.RD_SP_HI                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[1]       ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_INTERRUPT_CONTROL:I_IRQ_CTRL|\INT_VECTOR:VECT_TMP[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_DIN_S                                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_DIN_S                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|OV_DIV_MUL                                       ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_ALU:I_ALU|OV_DIV_MUL                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[3] ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                             ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|E                                   ; WF68K00IP_TOP_SOC:I_CPU|WF68K00IP_BUS_INTERFACE:I_BUS_IF|E                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA[3]                            ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA[3]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[3]                            ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[3]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; \SLOW_CPU:TMP[0]                                                                             ; \SLOW_CPU:TMP[0]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; \SLOW_CPU:TMP[2]                                                                             ; \SLOW_CPU:TMP[2]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; \SLOW_CPU:TMP[1]                                                                             ; \SLOW_CPU:TMP[1]                                                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                           ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                           ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                            ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
+--------+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'CODEC_SCLK'                                                                                                                                                  ;
+--------+------------------------------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                      ; To Node                                        ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -0.046 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[190]  ; A4299:I_4299|BUFFER_IN[191]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.291      ; 0.397      ;
; -0.045 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[189]  ; A4299:I_4299|BUFFER_IN[190]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.291      ; 0.398      ;
; -0.042 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[192]  ; A4299:I_4299|BUFFER_IN[193]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.291      ; 0.401      ;
; 0.127  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[227]  ; A4299:I_4299|BUFFER_IN[228]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.199      ; 0.478      ;
; 0.130  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[212]  ; A4299:I_4299|BUFFER_IN[213]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.200      ; 0.482      ;
; 0.132  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[214]  ; A4299:I_4299|BUFFER_IN[215]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.200      ; 0.484      ;
; 0.142  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[225]  ; A4299:I_4299|BUFFER_IN[226]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.192      ; 0.486      ;
; 0.144  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[241]  ; A4299:I_4299|BUFFER_IN[242]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.192      ; 0.488      ;
; 0.144  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[224]  ; A4299:I_4299|BUFFER_IN[225]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.192      ; 0.488      ;
; 0.145  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[182]  ; A4299:I_4299|BUFFER_IN[183]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.285      ; 0.582      ;
; 0.202  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[210]  ; A4299:I_4299|BUFFER_IN[211]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.211      ; 0.565      ;
; 0.209  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[213]  ; A4299:I_4299|BUFFER_IN[214]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.200      ; 0.561      ;
; 0.213  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[186]  ; A4299:I_4299|BUFFER_IN[187]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.112      ; 0.477      ;
; 0.215  ; A4299:I_4299|INT                               ; A4299:I_4299|INT                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.367      ;
; 0.215  ; A4299:I_4299|SYNC                              ; A4299:I_4299|SYNC                              ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.367      ;
; 0.218  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[242]  ; A4299:I_4299|BUFFER_IN[243]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.193      ; 0.563      ;
; 0.220  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[239]  ; A4299:I_4299|BUFFER_IN[240]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.192      ; 0.564      ;
; 0.221  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[240]  ; A4299:I_4299|BUFFER_IN[241]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.192      ; 0.565      ;
; 0.226  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[243]  ; A4299:I_4299|BUFFER_IN[244]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.193      ; 0.571      ;
; 0.230  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[207]  ; A4299:I_4299|BUFFER_IN[208]                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.012      ; 0.394      ;
; 0.231  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[12]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[13]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.076      ; 0.459      ;
; 0.233  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[226]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[227]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.092      ; 0.477      ;
; 0.235  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[168]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[169]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.387      ;
; 0.236  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[65]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[66]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.388      ;
; 0.236  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[176]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[177]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.388      ;
; 0.237  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[146] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[147] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.389      ;
; 0.237  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[141] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[142] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.389      ;
; 0.237  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[114] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[115] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.389      ;
; 0.237  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[56]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[57]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.389      ;
; 0.237  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[183]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[184]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.389      ;
; 0.237  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[167]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[168]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.389      ;
; 0.238  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[128] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[129] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.238  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[117] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[118] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.238  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[87]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[88]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.238  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[73]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[74]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.238  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[46]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[47]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.238  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[21]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[22]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.238  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[16]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[17]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.238  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[4]   ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[5]   ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.239  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[129] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[130] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[100] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[101] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[94]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[95]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[74]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[75]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[58]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[59]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[208]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[209]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[164]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[165]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.240  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[148] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[149] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[145] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[146] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[122] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[123] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[113] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[114] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[110] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[111] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[107] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[108] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[91]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[92]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[51]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[52]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[18]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[19]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[1]   ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[2]   ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[229]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[230]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[217]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[218]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[172]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[173]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[169] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[170] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[165] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[166] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[163] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[164] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[162] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[163] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[161] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[162] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[157] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[158] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[155] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[156] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[149] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[150] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[140] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[141] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[125] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[126] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[124] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[125] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[120] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[121] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[115] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[116] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[98]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[99]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[93]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[94]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[82]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[83]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[79]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[80]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[68]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[69]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[49]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[50]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[45]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[46]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[9]   ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[10]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[184]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[185]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[228]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[229]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[243]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[244]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[248]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[249]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[220]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[221]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[211]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[212]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[191]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[192]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[177]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[178]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[163]  ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[164]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.242  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[164] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[165] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[137] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[138] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[116] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[117] ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[80]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[81]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[75]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[76]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.076      ; 0.470      ;
; 0.242  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[57]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[58]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[47]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[48]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[44]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[45]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[36]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[37]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[29]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[30]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[25]  ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[26]  ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
+--------+------------------------------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[36]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[37]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[36]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[37]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.238 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[9]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[9]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22]    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[22]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[2][12]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[1][12]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[3]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22]    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[22]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[2][12]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[1][12]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[3]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[12]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[13]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[19]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[11]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[20]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[21]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[12]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[13]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[19]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[11]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[20]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[21]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.241 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[62]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[63]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[56]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[57]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.393      ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[36]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[37]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[36]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[37]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.238 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[9]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[9]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22]    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[22]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[2][12]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[1][12]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[3]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22]    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[22]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[2][12]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[1][12]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[3]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[12]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[13]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[19]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[11]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[20]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[21]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[12]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[13]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[19]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[11]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[20]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[21]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.241 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[62]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[63]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[56]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[57]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.393      ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                                                                                                        ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                     ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[5]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[9]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[9]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[6]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                                                                                                        ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                     ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[5]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[9]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[9]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[6]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                  ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node           ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; SCLK_6M4          ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.239 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.391      ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                          ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node             ; To Node               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.359 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.511      ;
; 0.367 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.519      ;
; 0.367 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.519      ;
; 0.494 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.646      ;
; 0.507 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.659      ;
; 0.533 ; CLK_24576             ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.685      ;
; 0.670 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.822      ;
; 0.692 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.844      ;
; 0.705 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.857      ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; CLK_0M5              ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.242 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.394      ;
; 0.252 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.404      ;
; 0.258 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.410      ;
; 0.260 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.412      ;
; 0.366 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.518      ;
; 0.366 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.518      ;
; 0.376 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.528      ;
; 0.440 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.592      ;
; 0.486 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.638      ;
; 0.566 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.718      ;
; 0.615 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.767      ;
; 0.625 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.777      ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'CLK_PLL1'                                                                                               ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 0.245 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.397      ;
; 0.358 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.510      ;
; 0.362 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.514      ;
; 0.363 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.515      ;
; 0.376 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.528      ;
; 0.376 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.528      ;
; 0.485 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 0.639      ;
; 0.496 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.648      ;
; 0.501 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.653      ;
; 0.504 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 0.658      ;
; 0.516 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.668      ;
; 0.516 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.668      ;
; 0.531 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.683      ;
; 0.538 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 0.692      ;
; 0.551 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.703      ;
; 0.551 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.703      ;
; 0.557 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 0.711      ;
; 0.566 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.718      ;
; 0.586 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.738      ;
; 0.603 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 0.757      ;
; 0.621 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.773      ;
; 0.622 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 0.776      ;
; 0.679 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.831      ;
; 0.679 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.831      ;
; 0.679 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.831      ;
; 0.732 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.884      ;
; 0.732 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.884      ;
; 0.782 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 0.936      ;
; 0.797 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.949      ;
; 0.797 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.949      ;
; 0.797 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.949      ;
; 0.797 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.949      ;
; 0.801 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 0.955      ;
; 0.841 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 0.995      ;
; 0.860 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.002      ; 1.014      ;
; 0.976 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.128      ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                          ;
+--------+-------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                       ; To Node                                                                      ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.019     ; 3.917      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[23]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[21]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[19]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[8]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[22]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[20]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[27]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[25]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[16]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[29]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[31]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[18]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[14]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[10]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[8]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[12]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[24]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[26]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[28]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[30]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[19]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[7]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[12]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.019     ; 3.917      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[15]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[11]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[13]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[9]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[11]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.019     ; 3.917      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[15]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.019     ; 3.917      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[13]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.019     ; 3.917      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[7]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.019     ; 3.917      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.019     ; 3.917      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[23]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[21]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[19]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[8]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[22]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[20]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[27]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[25]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[16]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.023     ; 3.913      ;
+--------+-------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                          ;
+--------+-------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                       ; To Node                                                                      ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.019     ; 3.917      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[23]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[21]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[19]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[8]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[22]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[20]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[27]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[25]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[16]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[29]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[31]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[18]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[14]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[10]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[8]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[12]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[24]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[26]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[28]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[30]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[19]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[7]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[12]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.019     ; 3.917      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[15]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[11]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[13]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[9]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[11]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.019     ; 3.917      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[15]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.019     ; 3.917      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[13]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.019     ; 3.917      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[7]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.019     ; 3.917      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.019     ; 3.917      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.012     ; 3.924      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.016     ; 3.920      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.017     ; 3.919      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.018     ; 3.918      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[23]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[21]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[19]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[8]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.013     ; 3.923      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[22]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[20]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[27]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[25]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
; 27.346 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[16]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.023     ; 3.913      ;
+--------+-------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                               ;
+--------+-------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                       ; To Node                                                           ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.006     ; 3.929      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.010      ; 3.945      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.006     ; 3.929      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.010      ; 3.945      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.010      ; 3.945      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.023      ; 3.958      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.006     ; 3.929      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.010      ; 3.945      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.006     ; 3.929      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.010      ; 3.945      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.010      ; 3.945      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.023      ; 3.958      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 3.944      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 3.936      ;
+--------+-------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                               ;
+--------+-------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                       ; To Node                                                           ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.006     ; 3.929      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.010      ; 3.945      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.006     ; 3.929      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.010      ; 3.945      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.010      ; 3.945      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.023      ; 3.958      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.006     ; 3.929      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.010      ; 3.945      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.006     ; 3.929      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 3.934      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.010      ; 3.945      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.010      ; 3.945      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.023      ; 3.958      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.001      ; 3.936      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 3.942      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 3.944      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 3.949      ;
; 27.347 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 3.944      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 3.936      ;
; 27.358 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 3.936      ;
+--------+-------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                           ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                           ; To Node                                                                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 80.246 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|dffe4 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0 ; CODEC_SCLK   ; CODEC_SCLK  ; 81.400       ; 0.335      ; 1.488      ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                           ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                           ; To Node                                                                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 1.015 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|dffe4 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.335      ; 1.488      ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                         ;
+-------+------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                      ; To Node                                                                      ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.244 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.396      ;
; 1.244 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.396      ;
; 1.244 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.396      ;
; 1.244 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.396      ;
; 1.244 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.396      ;
; 1.244 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.396      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.823      ;
+-------+------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                         ;
+-------+------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                      ; To Node                                                                      ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.054 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.025      ; 1.231      ;
; 1.244 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 1.396      ;
; 1.244 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 1.396      ;
; 1.244 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 1.396      ;
; 1.244 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 1.396      ;
; 1.244 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 1.396      ;
; 1.244 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 1.396      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.028     ; 2.824      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 2.820      ;
; 2.700 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.823      ;
+-------+------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                  ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                                ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[22]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[23]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[21]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[20]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[18]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[17]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[19]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[16]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[22]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[23]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[21]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[20]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[18]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[17]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[19]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[16]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.018      ; 1.603      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 1.727      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.785      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.764      ;
; 1.642 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.028      ; 1.822      ;
; 1.642 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.028      ; 1.822      ;
; 1.642 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.028      ; 1.822      ;
; 1.642 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.028      ; 1.822      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.025      ; 1.856      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.025      ; 1.856      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.025      ; 1.856      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.025      ; 1.856      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.025      ; 1.856      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.025      ; 1.856      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.025      ; 1.856      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.025      ; 1.856      ;
; 1.750 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_VERSION    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.002      ; 1.904      ;
; 1.750 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_VERSION    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.002      ; 1.904      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.004      ; 1.920      ;
; 1.780 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.005      ; 1.937      ;
; 1.780 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.005      ; 1.937      ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                  ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                                ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[22]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[23]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[21]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[20]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[18]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[17]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[19]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[16]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[22]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[23]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[21]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[20]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[18]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[17]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[19]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[16]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.433 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.018      ; 1.603      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.553 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 1.727      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.785      ;
; 1.607 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.785      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.764      ;
; 1.612 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.764      ;
; 1.642 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.028      ; 1.822      ;
; 1.642 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.028      ; 1.822      ;
; 1.642 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.028      ; 1.822      ;
; 1.642 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.028      ; 1.822      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.025      ; 1.856      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.025      ; 1.856      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.025      ; 1.856      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.025      ; 1.856      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.025      ; 1.856      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.025      ; 1.856      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.025      ; 1.856      ;
; 1.679 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.025      ; 1.856      ;
; 1.750 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_VERSION    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.002      ; 1.904      ;
; 1.750 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_VERSION    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.002      ; 1.904      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.004      ; 1.920      ;
; 1.764 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.004      ; 1.920      ;
; 1.780 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.005      ; 1.937      ;
; 1.780 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.005      ; 1.937      ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                     ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg7  ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                                                                                     ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg7  ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 11.695 ; 12.695       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576                                           ;
; 11.695 ; 12.695       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576                                           ;
; 11.695 ; 12.695       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]                               ;
; 11.695 ; 12.695       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]                               ;
; 11.695 ; 12.695       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]                               ;
; 11.695 ; 12.695       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]                               ;
; 11.695 ; 12.695       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]                               ;
; 11.695 ; 12.695       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]                               ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576|clk                                       ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576|clk                                       ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|inclk[0] ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|inclk[0] ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|outclk   ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|outclk   ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                                                 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4                                            ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4                                            ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]                                   ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]                                   ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|inclk[0] ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|inclk[0] ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|outclk   ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|outclk   ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4|clk                                        ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4|clk                                        ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]|clk                               ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]|clk                               ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CLK_PLL1'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 60.120 ; 62.500       ; 2.380          ; Port Rate        ; CLK_PLL1 ; Rise       ; CLK_PLL1                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                       ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                       ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------+
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[172] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[172] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[173] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[173] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[174] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[174] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[175] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[175] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[176] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[176] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[177] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[177] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[178] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[178] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[179] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[179] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[180] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[180] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[181] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[181] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[182] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[182] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[183] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[183] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[184] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[184] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[185] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[185] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[186] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[186] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[187] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[187] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[188] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[188] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[189] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[189] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[190] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[190] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[191] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[191] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[192] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[192] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[193] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[193] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[194] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[194] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[195] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[195] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[196] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[196] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[197] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[197] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[198] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[198] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[199] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[199] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[200] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[200] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[201] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[201] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[202] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[202] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[203] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[203] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[204] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[204] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[205] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[205] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[206] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[206] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[207] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[207] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[208] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[208] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[209] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[209] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[210] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[210] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[211] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[211] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[212] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[212] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[213] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[213] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[214] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[214] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[215] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[215] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[216] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[216] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[217] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[217] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[218] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[218] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[219] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[219] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[220] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[220] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[221] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; A4299:I_4299|BUFFER_OUT[221] ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                       ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                       ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------+
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[172] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[172] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[173] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[173] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[174] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[174] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[175] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[175] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[176] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[176] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[177] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[177] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[178] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[178] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[179] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[179] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[180] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[180] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[181] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[181] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[182] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[182] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[183] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[183] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[184] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[184] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[185] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[185] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[186] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[186] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[187] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[187] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[188] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[188] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[189] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[189] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[190] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[190] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[191] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[191] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[192] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[192] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[193] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[193] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[194] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[194] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[195] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[195] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[196] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[196] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[197] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[197] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[198] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[198] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[199] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[199] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[200] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[200] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[201] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[201] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[202] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[202] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[203] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[203] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[204] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[204] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[205] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[205] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[206] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[206] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[207] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[207] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[208] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[208] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[209] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[209] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[210] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[210] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[211] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[211] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[212] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[212] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[213] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[213] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[214] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[214] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[215] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[215] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[216] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[216] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[217] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[217] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[218] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[218] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[219] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[219] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[220] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[220] ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[221] ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; A4299:I_4299|BUFFER_OUT[221] ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5                                             ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5                                             ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CLK_PLL2'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 60.120 ; 62.500       ; 2.380          ; Port Rate        ; CLK_PLL2 ; Rise       ; CLK_PLL2                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CRT_PIN4_CLK1'                                                                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock         ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 60.120 ; 62.500       ; 2.380          ; Port Rate        ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1                             ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CODEC_SCLK'                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock      ; Clock Edge ; Target                                                                                                                                                    ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0                    ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0                    ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg0 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg0 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg6 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg6 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_datain_reg0  ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_datain_reg0  ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_memory_reg0  ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_memory_reg0  ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg0 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg0 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[180]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[180]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[181]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[181]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[182]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[182]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[183]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[183]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[184]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[184]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[185]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[185]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[186]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[186]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[187]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[187]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[188]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[188]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[189]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[189]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[190]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[190]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[191]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[191]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[192]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[192]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[193]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[193]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[194]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[194]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[195]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[195]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[196]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[196]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[197]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[197]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[198]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[198]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[199]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[199]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[200]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[200]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[201]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[201]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[202]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[202]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[203]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[203]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[204]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[204]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[205]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[205]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[206]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[206]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[207]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[207]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[208]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[208]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[209]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[209]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[210]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[210]                                                                                                                               ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; -0.716 ; -0.716 ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; 4.582  ; 4.582  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; -0.229 ; -0.229 ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; 5.539  ; 5.539  ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; 12.107 ; 12.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 6.115  ; 6.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 4.442  ; 4.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 4.998  ; 4.998  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 4.637  ; 4.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 4.998  ; 4.998  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 4.587  ; 4.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 4.559  ; 4.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 4.749  ; 4.749  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 4.666  ; 4.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 4.537  ; 4.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 4.470  ; 4.470  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 8.503  ; 8.503  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 8.852  ; 8.852  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 8.100  ; 8.100  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; 5.677  ; 5.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 9.187  ; 9.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 8.713  ; 8.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 8.659  ; 8.659  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 9.187  ; 9.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 6.710  ; 6.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 5.930  ; 5.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 8.481  ; 8.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 6.974  ; 6.974  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 6.852  ; 6.852  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 7.186  ; 7.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 7.236  ; 7.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 7.001  ; 7.001  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 7.616  ; 7.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 7.365  ; 7.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 7.375  ; 7.375  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 8.372  ; 8.372  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 8.438  ; 8.438  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 7.445  ; 7.445  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 7.774  ; 7.774  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 7.639  ; 7.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 7.835  ; 7.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 7.885  ; 7.885  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 8.481  ; 8.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 4.091  ; 4.091  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 5.702  ; 5.702  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 13.057 ; 13.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 13.057 ; 13.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 13.052 ; 13.052 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 12.998 ; 12.998 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; 6.161  ; 6.161  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; 3.521  ; 3.521  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; 5.223  ; 5.223  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; 6.796  ; 6.796  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; 4.690  ; 4.690  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 8.149  ; 8.149  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 4.981  ; 4.981  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 7.991  ; 7.991  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; 3.903  ; 3.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 12.706 ; 12.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 8.306  ; 8.306  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 8.388  ; 8.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 7.831  ; 7.831  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 7.639  ; 7.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 7.479  ; 7.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 7.217  ; 7.217  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 7.686  ; 7.686  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 7.920  ; 7.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 7.647  ; 7.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 8.388  ; 8.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; 3.356  ; 3.356  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; 2.323  ; 2.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; 2.111  ; 2.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; 1.994  ; 1.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; 1.904  ; 1.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; 1.826  ; 1.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 9.036  ; 9.036  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 7.577  ; 7.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 7.386  ; 7.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 7.421  ; 7.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 7.578  ; 7.578  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 7.391  ; 7.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 7.976  ; 7.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 8.738  ; 8.738  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 7.905  ; 7.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 8.223  ; 8.223  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 8.606  ; 8.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 7.881  ; 7.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 8.320  ; 8.320  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 7.820  ; 7.820  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 8.138  ; 8.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 8.397  ; 8.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 9.036  ; 9.036  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; 3.699  ; 3.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 4.140  ; 4.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 13.013 ; 13.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 5.182  ; 5.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 4.913  ; 4.913  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 5.017  ; 5.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 4.637  ; 4.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 4.733  ; 4.733  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 4.424  ; 4.424  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 4.521  ; 4.521  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 4.806  ; 4.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 4.653  ; 4.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 4.716  ; 4.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 5.017  ; 5.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 6.302  ; 6.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 6.241  ; 6.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 5.930  ; 5.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 6.076  ; 6.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 4.849  ; 4.849  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; 6.697  ; 6.697  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; 4.130  ; 4.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; 6.145  ; 6.145  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 10.055 ; 10.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; 4.763  ; 4.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; 4.385  ; 4.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; 4.732  ; 4.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; 4.407  ; 4.407  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; 4.732  ; 4.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; 4.546  ; 4.546  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; 4.209  ; 4.209  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; 4.391  ; 4.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; 4.127  ; 4.127  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 4.085  ; 4.085  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 12.159 ; 12.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 4.275  ; 4.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 11.462 ; 11.462 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 4.274  ; 4.274  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 3.933  ; 3.933  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 4.872  ; 4.872  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; 4.041  ; 4.041  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 8.257  ; 8.257  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 8.741  ; 8.741  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 8.018  ; 8.018  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 8.604  ; 8.604  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 8.581  ; 8.581  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 8.527  ; 8.527  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 8.604  ; 8.604  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 6.578  ; 6.578  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 5.798  ; 5.798  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 8.187  ; 8.187  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 6.752  ; 6.752  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 6.741  ; 6.741  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 6.940  ; 6.940  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 6.995  ; 6.995  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 6.972  ; 6.972  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 7.551  ; 7.551  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 7.283  ; 7.283  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 7.243  ; 7.243  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 8.022  ; 8.022  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 8.187  ; 8.187  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 7.143  ; 7.143  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 7.505  ; 7.505  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 6.994  ; 6.994  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 7.220  ; 7.220  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 7.310  ; 7.310  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 7.538  ; 7.538  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 4.737  ; 4.737  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; 3.064  ; 3.064  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; 3.235  ; 3.235  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; 3.371  ; 3.371  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 12.412 ; 12.412 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 12.412 ; 12.412 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 12.407 ; 12.407 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 12.353 ; 12.353 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; 4.100  ; 4.100  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 4.612  ; 4.612  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 8.084  ; 8.084  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; 4.624  ; 4.624  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 7.926  ; 7.926  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 12.030 ; 12.030 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 8.084  ; 8.084  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 7.481  ; 7.481  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 7.481  ; 7.481  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 7.388  ; 7.388  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 7.177  ; 7.177  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 6.948  ; 6.948  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 7.041  ; 7.041  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 7.305  ; 7.305  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 7.072  ; 7.072  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 7.445  ; 7.445  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 8.656  ; 8.656  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 7.355  ; 7.355  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 7.275  ; 7.275  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 7.175  ; 7.175  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 7.337  ; 7.337  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 7.362  ; 7.362  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 7.911  ; 7.911  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 8.656  ; 8.656  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 7.773  ; 7.773  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 7.873  ; 7.873  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 8.355  ; 8.355  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 7.579  ; 7.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 8.051  ; 8.051  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 7.175  ; 7.175  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 7.523  ; 7.523  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 7.822  ; 7.822  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 8.093  ; 8.093  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 12.368 ; 12.368 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 9.977  ; 9.977  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 3.823  ; 3.823  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; 3.548  ; 3.548  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 11.483 ; 11.483 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; 4.110  ; 4.110  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; 12.107 ; 12.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 6.115  ; 6.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 4.442  ; 4.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 4.998  ; 4.998  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 4.637  ; 4.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 4.998  ; 4.998  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 4.587  ; 4.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 4.559  ; 4.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 4.749  ; 4.749  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 4.666  ; 4.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 4.537  ; 4.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 4.470  ; 4.470  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 8.503  ; 8.503  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 8.852  ; 8.852  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 8.100  ; 8.100  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; 5.677  ; 5.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 9.187  ; 9.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 8.713  ; 8.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 8.659  ; 8.659  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 9.187  ; 9.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 6.710  ; 6.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 5.930  ; 5.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 8.481  ; 8.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 6.974  ; 6.974  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 6.852  ; 6.852  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 7.186  ; 7.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 7.236  ; 7.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 7.001  ; 7.001  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 7.616  ; 7.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 7.365  ; 7.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.375  ; 7.375  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 8.372  ; 8.372  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 8.438  ; 8.438  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 7.445  ; 7.445  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 7.774  ; 7.774  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 7.639  ; 7.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 7.835  ; 7.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 7.885  ; 7.885  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 8.481  ; 8.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 4.091  ; 4.091  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 5.702  ; 5.702  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 13.057 ; 13.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 13.057 ; 13.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 13.052 ; 13.052 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 12.998 ; 12.998 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; 6.161  ; 6.161  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; 3.521  ; 3.521  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; 5.223  ; 5.223  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; 6.796  ; 6.796  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; 4.690  ; 4.690  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 8.149  ; 8.149  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 4.981  ; 4.981  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 7.991  ; 7.991  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; 3.903  ; 3.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 12.706 ; 12.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 8.306  ; 8.306  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 8.388  ; 8.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 7.831  ; 7.831  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 7.639  ; 7.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 7.479  ; 7.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 7.217  ; 7.217  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 7.686  ; 7.686  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 7.920  ; 7.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 7.647  ; 7.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 8.388  ; 8.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; 3.356  ; 3.356  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; 2.323  ; 2.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; 2.111  ; 2.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; 1.994  ; 1.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; 1.904  ; 1.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; 1.826  ; 1.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 9.036  ; 9.036  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 7.577  ; 7.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 7.386  ; 7.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 7.421  ; 7.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 7.578  ; 7.578  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 7.391  ; 7.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 7.976  ; 7.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 8.738  ; 8.738  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 7.905  ; 7.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 8.223  ; 8.223  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 8.606  ; 8.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 7.881  ; 7.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 8.320  ; 8.320  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 7.820  ; 7.820  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 8.138  ; 8.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 8.397  ; 8.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 9.036  ; 9.036  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; 3.699  ; 3.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 4.140  ; 4.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 13.013 ; 13.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 5.182  ; 5.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 4.913  ; 4.913  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 5.017  ; 5.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 4.637  ; 4.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 4.733  ; 4.733  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 4.424  ; 4.424  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 4.521  ; 4.521  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 4.806  ; 4.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 4.653  ; 4.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 4.716  ; 4.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 5.017  ; 5.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 6.302  ; 6.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 6.241  ; 6.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 5.930  ; 5.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 6.076  ; 6.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 4.849  ; 4.849  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; 6.697  ; 6.697  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; 4.130  ; 4.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; 6.145  ; 6.145  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 10.055 ; 10.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; 4.763  ; 4.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; 4.385  ; 4.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; 4.732  ; 4.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; 4.407  ; 4.407  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; 4.732  ; 4.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; 4.546  ; 4.546  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; 4.209  ; 4.209  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; 4.391  ; 4.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; 4.127  ; 4.127  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 4.085  ; 4.085  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 12.159 ; 12.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 4.275  ; 4.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 11.462 ; 11.462 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 4.274  ; 4.274  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 3.933  ; 3.933  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 4.872  ; 4.872  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; 4.041  ; 4.041  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 8.257  ; 8.257  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 8.741  ; 8.741  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 8.018  ; 8.018  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 8.604  ; 8.604  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 8.581  ; 8.581  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 8.527  ; 8.527  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 8.604  ; 8.604  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 6.578  ; 6.578  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 5.798  ; 5.798  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 8.187  ; 8.187  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 6.752  ; 6.752  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 6.741  ; 6.741  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 6.940  ; 6.940  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 6.995  ; 6.995  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 6.972  ; 6.972  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 7.551  ; 7.551  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 7.283  ; 7.283  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.243  ; 7.243  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 8.022  ; 8.022  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 8.187  ; 8.187  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 7.143  ; 7.143  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 7.505  ; 7.505  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 6.994  ; 6.994  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 7.220  ; 7.220  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 7.310  ; 7.310  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 7.538  ; 7.538  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 4.737  ; 4.737  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; 3.064  ; 3.064  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; 3.235  ; 3.235  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; 3.371  ; 3.371  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 12.412 ; 12.412 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 12.412 ; 12.412 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 12.407 ; 12.407 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 12.353 ; 12.353 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; 4.100  ; 4.100  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 4.612  ; 4.612  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 8.084  ; 8.084  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; 4.624  ; 4.624  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 7.926  ; 7.926  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 12.030 ; 12.030 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 8.084  ; 8.084  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 7.481  ; 7.481  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 7.481  ; 7.481  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 7.388  ; 7.388  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 7.177  ; 7.177  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 6.948  ; 6.948  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 7.041  ; 7.041  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 7.305  ; 7.305  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 7.072  ; 7.072  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 7.445  ; 7.445  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 8.656  ; 8.656  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 7.355  ; 7.355  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 7.275  ; 7.275  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 7.175  ; 7.175  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 7.337  ; 7.337  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 7.362  ; 7.362  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 7.911  ; 7.911  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 8.656  ; 8.656  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 7.773  ; 7.773  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 7.873  ; 7.873  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 8.355  ; 8.355  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 7.579  ; 7.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 8.051  ; 8.051  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 7.175  ; 7.175  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 7.523  ; 7.523  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 7.822  ; 7.822  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 8.093  ; 8.093  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 12.368 ; 12.368 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 9.977  ; 9.977  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 3.823  ; 3.823  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; 3.548  ; 3.548  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 11.483 ; 11.483 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; 4.110  ; 4.110  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; 10.690 ; 10.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; 7.966  ; 7.966  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; 8.138  ; 8.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; 7.348  ; 7.348  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 8.220  ; 8.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; 8.220  ; 8.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; 8.166  ; 8.166  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; 6.030  ; 6.030  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; 8.118  ; 8.118  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; 6.217  ; 6.217  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 5.437  ; 5.437  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 7.353  ; 7.353  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 6.391  ; 6.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 6.138  ; 6.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 6.649  ; 6.649  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 6.548  ; 6.548  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 6.362  ; 6.362  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 6.978  ; 6.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 6.613  ; 6.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 6.882  ; 6.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 7.353  ; 7.353  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; 5.218  ; 5.218  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 11.640 ; 11.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 11.640 ; 11.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 11.635 ; 11.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 11.581 ; 11.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; 7.511  ; 7.511  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; 7.353  ; 7.353  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 11.361 ; 11.361 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; 7.723  ; 7.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; 6.812  ; 6.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; 6.812  ; 6.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 7.986  ; 7.986  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 6.994  ; 6.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 6.672  ; 6.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 6.884  ; 6.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 6.890  ; 6.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 6.752  ; 6.752  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 7.338  ; 7.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 7.986  ; 7.986  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 7.412  ; 7.412  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 7.204  ; 7.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 5.966  ; 5.966  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 5.983  ; 5.983  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 6.196  ; 6.196  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 5.952  ; 5.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 6.107  ; 6.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 6.110  ; 6.110  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 5.953  ; 5.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 11.596 ; 11.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 9.420  ; 9.420  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 10.814 ; 10.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 6.649  ; 6.649  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 6.617  ; 6.617  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 6.617  ; 6.617  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 6.611  ; 6.611  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 6.552  ; 6.552  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 5.611  ; 5.611  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 6.572  ; 6.572  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; 10.690 ; 10.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 7.966  ; 7.966  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 8.138  ; 8.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 7.348  ; 7.348  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 8.220  ; 8.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 8.220  ; 8.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 8.166  ; 8.166  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; 6.030  ; 6.030  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 8.118  ; 8.118  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 6.217  ; 6.217  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 5.437  ; 5.437  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.353  ; 7.353  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 6.391  ; 6.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 6.138  ; 6.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 6.649  ; 6.649  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 6.548  ; 6.548  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 6.362  ; 6.362  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.978  ; 6.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.613  ; 6.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.882  ; 6.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 7.353  ; 7.353  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 5.218  ; 5.218  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 11.640 ; 11.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 11.640 ; 11.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 11.635 ; 11.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 11.581 ; 11.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 7.511  ; 7.511  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 7.353  ; 7.353  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 11.361 ; 11.361 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 7.723  ; 7.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 6.812  ; 6.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 6.812  ; 6.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 7.986  ; 7.986  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 6.994  ; 6.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 6.672  ; 6.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 6.884  ; 6.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 6.890  ; 6.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 6.752  ; 6.752  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 7.338  ; 7.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 7.986  ; 7.986  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 7.412  ; 7.412  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 7.204  ; 7.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 5.966  ; 5.966  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 5.983  ; 5.983  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 6.196  ; 6.196  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.952  ; 5.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 6.107  ; 6.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 6.110  ; 6.110  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 5.953  ; 5.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 11.596 ; 11.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 9.420  ; 9.420  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 10.814 ; 10.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 6.649  ; 6.649  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 6.617  ; 6.617  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 6.617  ; 6.617  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 6.611  ; 6.611  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 6.552  ; 6.552  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 5.611  ; 5.611  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 6.572  ; 6.572  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; 10.556 ; 10.556 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; 7.136  ; 7.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; 7.452  ; 7.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; 6.672  ; 6.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; 7.654  ; 7.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; 7.442  ; 7.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; 7.388  ; 7.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; 7.654  ; 7.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; 5.439  ; 5.439  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 4.659  ; 4.659  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; 6.969  ; 6.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 5.653  ; 5.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 5.452  ; 5.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 5.819  ; 5.819  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 5.863  ; 5.863  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 5.705  ; 5.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 6.242  ; 6.242  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 5.937  ; 5.937  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 6.104  ; 6.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 6.920  ; 6.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 6.969  ; 6.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 6.110  ; 6.110  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 6.345  ; 6.345  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 5.916  ; 5.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 6.134  ; 6.134  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 6.230  ; 6.230  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 6.948  ; 6.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; 11.506 ; 11.506 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; 11.506 ; 11.506 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; 11.501 ; 11.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; 11.447 ; 11.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; 6.775  ; 6.775  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; 6.617  ; 6.617  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; 11.173 ; 11.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; 6.985  ; 6.985  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 6.964  ; 6.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; 6.379  ; 6.379  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; 6.170  ; 6.170  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.144  ; 6.144  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 6.779  ; 6.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 6.882  ; 6.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 6.866  ; 6.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 6.964  ; 6.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; 6.855  ; 6.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 7.503  ; 7.503  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 6.256  ; 6.256  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 5.986  ; 5.986  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 6.054  ; 6.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 6.205  ; 6.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 6.095  ; 6.095  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 6.602  ; 6.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 7.310  ; 7.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 6.634  ; 6.634  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 6.771  ; 6.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 7.137  ; 7.137  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 6.546  ; 6.546  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 6.891  ; 6.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 6.097  ; 6.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 6.437  ; 6.437  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 6.742  ; 6.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 7.503  ; 7.503  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; 11.462 ; 11.462 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; 8.682  ; 8.682  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; 10.626 ; 10.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; 10.556 ; 10.556 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 7.136  ; 7.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 7.452  ; 7.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 6.672  ; 6.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 7.654  ; 7.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 7.442  ; 7.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 7.388  ; 7.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 7.654  ; 7.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 5.439  ; 5.439  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 4.659  ; 4.659  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 6.969  ; 6.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 5.653  ; 5.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 5.452  ; 5.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 5.819  ; 5.819  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 5.863  ; 5.863  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 5.705  ; 5.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.242  ; 6.242  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 5.937  ; 5.937  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.104  ; 6.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.920  ; 6.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 6.969  ; 6.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 6.110  ; 6.110  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.345  ; 6.345  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.916  ; 5.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.134  ; 6.134  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 6.230  ; 6.230  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 6.948  ; 6.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 11.506 ; 11.506 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 11.506 ; 11.506 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 11.501 ; 11.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 11.447 ; 11.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 6.775  ; 6.775  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 6.617  ; 6.617  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 11.173 ; 11.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 6.985  ; 6.985  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 6.964  ; 6.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 6.379  ; 6.379  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 6.170  ; 6.170  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.144  ; 6.144  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 6.779  ; 6.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 6.882  ; 6.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 6.866  ; 6.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 6.964  ; 6.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 6.855  ; 6.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 7.503  ; 7.503  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 6.256  ; 6.256  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 5.986  ; 5.986  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 6.054  ; 6.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 6.205  ; 6.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 6.095  ; 6.095  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 6.602  ; 6.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 7.310  ; 7.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 6.634  ; 6.634  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 6.771  ; 6.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 7.137  ; 7.137  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 6.546  ; 6.546  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 6.891  ; 6.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 6.097  ; 6.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 6.437  ; 6.437  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 6.742  ; 6.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 7.503  ; 7.503  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 11.462 ; 11.462 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 8.682  ; 8.682  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 10.626 ; 10.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 0.851  ; 0.851  ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; -3.958 ; -3.958 ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; 0.349  ; 0.349  ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; -4.328 ; -4.328 ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; -3.813 ; -3.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -3.703 ; -3.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -4.322 ; -4.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; -3.456 ; -3.456 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; -3.456 ; -3.456 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; -3.543 ; -3.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; -3.693 ; -3.693 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; -3.466 ; -3.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; -3.520 ; -3.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; -3.594 ; -3.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; -3.548 ; -3.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; -3.606 ; -3.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -4.397 ; -4.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -4.096 ; -4.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -3.972 ; -3.972 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; -4.485 ; -4.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.525 ; -4.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -4.525 ; -4.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -4.575 ; -4.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -4.751 ; -4.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -2.741 ; -2.741 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -2.185 ; -2.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -4.218 ; -4.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -4.524 ; -4.524 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -4.855 ; -4.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -4.595 ; -4.595 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -4.832 ; -4.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -4.635 ; -4.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -4.757 ; -4.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -4.555 ; -4.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -4.600 ; -4.600 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -4.685 ; -4.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -5.031 ; -5.031 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -4.673 ; -4.673 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -4.996 ; -4.996 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.716 ; -4.716 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -4.436 ; -4.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -4.509 ; -4.509 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -4.218 ; -4.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; -3.971 ; -3.971 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -3.840 ; -3.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -5.316 ; -5.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -5.439 ; -5.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -5.316 ; -5.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -5.495 ; -5.495 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; -4.051 ; -4.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; -1.699 ; -1.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; -4.026 ; -4.026 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; -4.478 ; -4.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; -4.066 ; -4.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -4.470 ; -4.470 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; -3.599 ; -3.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -4.312 ; -4.312 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; -3.783 ; -3.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -4.377 ; -4.377 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -3.954 ; -3.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -5.889 ; -5.889 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.509 ; -6.509 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.275 ; -6.275 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.164 ; -6.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -5.889 ; -5.889 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -6.078 ; -6.078 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -6.268 ; -6.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -6.083 ; -6.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.552 ; -6.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; -3.236 ; -3.236 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; -1.799 ; -1.799 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; -1.587 ; -1.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; -1.470 ; -1.470 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; -1.380 ; -1.380 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; -1.278 ; -1.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.657 ; -3.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -3.657 ; -3.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.935 ; -3.935 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -3.831 ; -3.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -4.115 ; -4.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -4.093 ; -4.093 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -4.195 ; -4.195 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -4.493 ; -4.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -4.126 ; -4.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -4.376 ; -4.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -3.747 ; -3.747 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -3.830 ; -3.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -3.918 ; -3.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -3.828 ; -3.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -3.880 ; -3.880 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -4.001 ; -4.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -3.854 ; -3.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; -1.248 ; -1.248 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; -4.020 ; -4.020 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -4.049 ; -4.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; -4.124 ; -4.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; -3.679 ; -3.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; -3.238 ; -3.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; -3.434 ; -3.434 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; -3.459 ; -3.459 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; -3.238 ; -3.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; -3.274 ; -3.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; -3.578 ; -3.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; -3.498 ; -3.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; -3.600 ; -3.600 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; -3.617 ; -3.617 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; -3.672 ; -3.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; -3.721 ; -3.721 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; -3.746 ; -3.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; -3.857 ; -3.857 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; -3.835 ; -3.835 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; -4.340 ; -4.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; -4.006 ; -4.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; -4.287 ; -4.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -4.184 ; -4.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; -4.641 ; -4.641 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; -4.263 ; -4.263 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; -3.691 ; -3.691 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; -3.691 ; -3.691 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; -3.975 ; -3.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; -3.944 ; -3.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; -4.085 ; -4.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; -4.269 ; -4.269 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; -4.005 ; -4.005 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -3.831 ; -3.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -4.507 ; -4.507 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; -3.749 ; -3.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; -5.430 ; -5.430 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -4.154 ; -4.154 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -3.813 ; -3.813 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -4.752 ; -4.752 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; -3.921 ; -3.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -7.423 ; -7.423 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -7.837 ; -7.837 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -6.994 ; -6.994 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.588 ; -4.588 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.488 ; -7.488 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -7.434 ; -7.434 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -4.588 ; -4.588 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -5.485 ; -5.485 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -4.705 ; -4.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -4.216 ; -4.216 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -4.216 ; -4.216 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -4.877 ; -4.877 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -4.730 ; -4.730 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -4.562 ; -4.562 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -4.400 ; -4.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -4.387 ; -4.387 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -4.831 ; -4.831 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -4.379 ; -4.379 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -4.679 ; -4.679 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -5.176 ; -5.176 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -4.787 ; -4.787 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -5.013 ; -5.013 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.817 ; -4.817 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -4.504 ; -4.504 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -4.535 ; -4.535 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -4.300 ; -4.300 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -4.363 ; -4.363 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; -2.328 ; -2.328 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; -2.454 ; -2.454 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; -2.602 ; -2.602 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -5.481 ; -5.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -5.546 ; -5.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -5.540 ; -5.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -5.481 ; -5.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; -3.980 ; -3.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -4.492 ; -4.492 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -6.820 ; -6.820 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; -4.504 ; -4.504 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -6.662 ; -6.662 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -4.602 ; -4.602 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -7.040 ; -7.040 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -5.906 ; -5.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.503 ; -6.503 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.420 ; -6.420 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.278 ; -6.278 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -5.906 ; -5.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -6.179 ; -6.179 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -6.336 ; -6.336 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -6.109 ; -6.109 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.413 ; -6.413 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -6.200 ; -6.200 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -6.311 ; -6.311 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -6.371 ; -6.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -6.341 ; -6.341 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -6.253 ; -6.253 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -6.200 ; -6.200 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -6.647 ; -6.647 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -7.632 ; -7.632 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -6.680 ; -6.680 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -6.895 ; -6.895 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -7.387 ; -7.387 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -6.680 ; -6.680 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -7.009 ; -7.009 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -6.313 ; -6.313 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -6.554 ; -6.554 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -6.859 ; -6.859 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -7.061 ; -7.061 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -5.098 ; -5.098 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -5.297 ; -5.297 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -3.703 ; -3.703 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; -3.428 ; -3.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -6.024 ; -6.024 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; -3.990 ; -3.990 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; -3.813 ; -3.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -3.703 ; -3.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -4.322 ; -4.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -3.456 ; -3.456 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -3.456 ; -3.456 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -3.543 ; -3.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -3.693 ; -3.693 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -3.466 ; -3.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -3.520 ; -3.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -3.594 ; -3.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -3.548 ; -3.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -3.606 ; -3.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -4.397 ; -4.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -4.096 ; -4.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -3.972 ; -3.972 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; -4.485 ; -4.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.525 ; -4.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -4.525 ; -4.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -4.575 ; -4.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -4.751 ; -4.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -2.741 ; -2.741 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -2.185 ; -2.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.218 ; -4.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.524 ; -4.524 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.855 ; -4.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.595 ; -4.595 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.832 ; -4.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.635 ; -4.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.757 ; -4.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.555 ; -4.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.600 ; -4.600 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.685 ; -4.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -5.031 ; -5.031 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.673 ; -4.673 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.996 ; -4.996 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.716 ; -4.716 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.436 ; -4.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.509 ; -4.509 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.218 ; -4.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; -3.971 ; -3.971 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -3.840 ; -3.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.316 ; -5.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.439 ; -5.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.316 ; -5.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.495 ; -5.495 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; -4.051 ; -4.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; -1.699 ; -1.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; -4.026 ; -4.026 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; -4.478 ; -4.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; -4.066 ; -4.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -4.470 ; -4.470 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; -3.599 ; -3.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -4.312 ; -4.312 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; -3.783 ; -3.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.377 ; -4.377 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -3.954 ; -3.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -5.889 ; -5.889 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.509 ; -6.509 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.275 ; -6.275 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.164 ; -6.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -5.889 ; -5.889 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -6.078 ; -6.078 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -6.268 ; -6.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -6.083 ; -6.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.552 ; -6.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; -3.236 ; -3.236 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; -1.799 ; -1.799 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; -1.587 ; -1.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; -1.470 ; -1.470 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; -1.380 ; -1.380 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; -1.278 ; -1.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.657 ; -3.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -3.657 ; -3.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.935 ; -3.935 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -3.831 ; -3.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -4.115 ; -4.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -4.093 ; -4.093 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -4.195 ; -4.195 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -4.493 ; -4.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -4.126 ; -4.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -4.376 ; -4.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -3.747 ; -3.747 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -3.830 ; -3.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -3.918 ; -3.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -3.828 ; -3.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -3.880 ; -3.880 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -4.001 ; -4.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -3.854 ; -3.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; -1.248 ; -1.248 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; -4.020 ; -4.020 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.049 ; -4.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; -4.124 ; -4.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; -3.679 ; -3.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; -3.238 ; -3.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; -3.434 ; -3.434 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; -3.459 ; -3.459 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; -3.238 ; -3.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; -3.274 ; -3.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; -3.578 ; -3.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; -3.498 ; -3.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; -3.600 ; -3.600 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; -3.617 ; -3.617 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; -3.672 ; -3.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; -3.721 ; -3.721 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; -3.746 ; -3.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; -3.857 ; -3.857 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; -3.835 ; -3.835 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; -4.340 ; -4.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; -4.006 ; -4.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; -4.287 ; -4.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -4.184 ; -4.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; -4.641 ; -4.641 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; -4.263 ; -4.263 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; -3.691 ; -3.691 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; -3.691 ; -3.691 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; -3.975 ; -3.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; -3.944 ; -3.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; -4.085 ; -4.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; -4.269 ; -4.269 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; -4.005 ; -4.005 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -3.831 ; -3.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -4.507 ; -4.507 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; -3.749 ; -3.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -5.430 ; -5.430 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -4.154 ; -4.154 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -3.813 ; -3.813 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -4.752 ; -4.752 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; -3.921 ; -3.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -7.423 ; -7.423 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -7.837 ; -7.837 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.994 ; -6.994 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.588 ; -4.588 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.488 ; -7.488 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -7.434 ; -7.434 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -4.588 ; -4.588 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -5.485 ; -5.485 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -4.705 ; -4.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.216 ; -4.216 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.216 ; -4.216 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.877 ; -4.877 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.730 ; -4.730 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.562 ; -4.562 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.400 ; -4.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.387 ; -4.387 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.831 ; -4.831 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.379 ; -4.379 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.679 ; -4.679 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -5.176 ; -5.176 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.787 ; -4.787 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -5.013 ; -5.013 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.817 ; -4.817 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.504 ; -4.504 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.535 ; -4.535 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.300 ; -4.300 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -4.363 ; -4.363 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; -2.328 ; -2.328 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; -2.454 ; -2.454 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; -2.602 ; -2.602 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.481 ; -5.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.546 ; -5.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.540 ; -5.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.481 ; -5.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; -3.980 ; -3.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -4.492 ; -4.492 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -6.820 ; -6.820 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; -4.504 ; -4.504 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -6.662 ; -6.662 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.602 ; -4.602 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.040 ; -7.040 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -5.906 ; -5.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.503 ; -6.503 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.420 ; -6.420 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.278 ; -6.278 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -5.906 ; -5.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -6.179 ; -6.179 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -6.336 ; -6.336 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -6.109 ; -6.109 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.413 ; -6.413 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -6.200 ; -6.200 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -6.311 ; -6.311 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -6.371 ; -6.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -6.341 ; -6.341 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -6.253 ; -6.253 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -6.200 ; -6.200 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -6.647 ; -6.647 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -7.632 ; -7.632 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -6.680 ; -6.680 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -6.895 ; -6.895 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -7.387 ; -7.387 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -6.680 ; -6.680 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -7.009 ; -7.009 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -6.313 ; -6.313 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -6.554 ; -6.554 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -6.859 ; -6.859 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -7.061 ; -7.061 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -5.098 ; -5.098 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.297 ; -5.297 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -3.703 ; -3.703 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; -3.428 ; -3.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -6.024 ; -6.024 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; -3.990 ; -3.990 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; -4.703 ; -4.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; -7.576 ; -7.576 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; -7.731 ; -7.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; -6.948 ; -6.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.156 ; -4.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; -4.215 ; -4.215 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; -4.156 ; -4.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; -5.404 ; -5.404 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; -5.131 ; -5.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; -2.309 ; -2.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -1.753 ; -1.753 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; -4.771 ; -4.771 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; -4.883 ; -4.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; -4.815 ; -4.815 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; -4.566 ; -4.566 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; -4.634 ; -4.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; -4.785 ; -4.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; -4.656 ; -4.656 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; -4.868 ; -4.868 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; -4.906 ; -4.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -5.287 ; -5.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -5.311 ; -5.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -5.287 ; -5.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -5.638 ; -5.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; -7.067 ; -7.067 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; -6.909 ; -6.909 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -5.473 ; -5.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; -7.212 ; -7.212 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; -6.692 ; -6.692 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.692 ; -6.692 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.690 ; -3.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -3.699 ; -3.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.690 ; -3.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -3.721 ; -3.721 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -3.894 ; -3.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -3.944 ; -3.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -3.905 ; -3.905 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -3.990 ; -3.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -3.937 ; -3.937 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -3.783 ; -3.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -3.845 ; -3.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -3.832 ; -3.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -3.760 ; -3.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -3.841 ; -3.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -3.801 ; -3.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -3.716 ; -3.716 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -3.772 ; -3.772 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; -4.364 ; -4.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -5.584 ; -5.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; -5.569 ; -5.569 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; -5.488 ; -5.488 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -6.304 ; -6.304 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -6.369 ; -6.369 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -6.363 ; -6.363 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -6.304 ; -6.304 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -5.363 ; -5.363 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -6.239 ; -6.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; -4.703 ; -4.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -7.576 ; -7.576 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -7.731 ; -7.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.948 ; -6.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.156 ; -4.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -4.215 ; -4.215 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -4.156 ; -4.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; -5.404 ; -5.404 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -5.131 ; -5.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -2.309 ; -2.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -1.753 ; -1.753 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.771 ; -4.771 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.883 ; -4.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.815 ; -4.815 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.566 ; -4.566 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.634 ; -4.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.785 ; -4.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.656 ; -4.656 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.868 ; -4.868 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -4.906 ; -4.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.287 ; -5.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.311 ; -5.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.287 ; -5.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.638 ; -5.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -7.067 ; -7.067 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -6.909 ; -6.909 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -5.473 ; -5.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.212 ; -7.212 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -6.692 ; -6.692 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.692 ; -6.692 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.690 ; -3.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -3.699 ; -3.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.690 ; -3.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -3.721 ; -3.721 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -3.894 ; -3.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -3.944 ; -3.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -3.905 ; -3.905 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -3.990 ; -3.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -3.937 ; -3.937 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -3.783 ; -3.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -3.845 ; -3.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -3.832 ; -3.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -3.760 ; -3.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -3.841 ; -3.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -3.801 ; -3.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -3.716 ; -3.716 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -3.772 ; -3.772 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.364 ; -4.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.584 ; -5.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.569 ; -5.569 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -5.488 ; -5.488 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -6.304 ; -6.304 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -6.369 ; -6.369 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -6.363 ; -6.363 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -6.304 ; -6.304 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -5.363 ; -5.363 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -6.239 ; -6.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; -4.140 ; -4.140 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; -7.016 ; -7.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; -7.332 ; -7.332 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; -6.552 ; -6.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; -5.845 ; -5.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.322 ; -7.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; -7.268 ; -7.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; -5.845 ; -5.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; -5.319 ; -5.319 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -4.539 ; -4.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; -4.041 ; -4.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; -4.041 ; -4.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; -4.372 ; -4.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; -4.323 ; -4.323 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; -4.394 ; -4.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; -4.175 ; -4.175 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; -4.222 ; -4.222 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; -4.389 ; -4.389 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; -4.213 ; -4.213 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; -4.265 ; -4.265 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; -4.637 ; -4.637 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; -4.309 ; -4.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; -4.610 ; -4.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; -4.314 ; -4.314 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; -4.046 ; -4.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; -4.128 ; -4.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; -4.073 ; -4.073 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; -5.988 ; -5.988 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; -6.040 ; -6.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; -6.039 ; -6.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; -5.988 ; -5.988 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; -6.655 ; -6.655 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; -6.497 ; -6.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; -5.643 ; -5.643 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; -6.865 ; -6.865 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.089 ; -6.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; -5.881 ; -5.881 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; -5.800 ; -5.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; -3.519 ; -3.519 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; -3.462 ; -3.462 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; -3.562 ; -3.562 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.186 ; -6.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -5.810 ; -5.810 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -6.136 ; -6.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -5.866 ; -5.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -5.934 ; -5.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -6.085 ; -6.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -5.975 ; -5.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -6.482 ; -6.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -7.190 ; -7.190 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -6.514 ; -6.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -6.481 ; -6.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -6.848 ; -6.848 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -6.202 ; -6.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -6.606 ; -6.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -5.810 ; -5.810 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -6.096 ; -6.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -6.452 ; -6.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -6.834 ; -6.834 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; -4.431 ; -4.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; -5.632 ; -5.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; -5.546 ; -5.546 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; -4.140 ; -4.140 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -7.016 ; -7.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -7.332 ; -7.332 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.552 ; -6.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -5.845 ; -5.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.322 ; -7.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -7.268 ; -7.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -5.845 ; -5.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -5.319 ; -5.319 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -4.539 ; -4.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.041 ; -4.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.041 ; -4.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.372 ; -4.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.323 ; -4.323 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.394 ; -4.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.175 ; -4.175 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.222 ; -4.222 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.389 ; -4.389 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.213 ; -4.213 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.265 ; -4.265 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -4.637 ; -4.637 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.309 ; -4.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.610 ; -4.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.314 ; -4.314 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.046 ; -4.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.128 ; -4.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.073 ; -4.073 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.988 ; -5.988 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -6.040 ; -6.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -6.039 ; -6.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.988 ; -5.988 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -6.655 ; -6.655 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -6.497 ; -6.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -5.643 ; -5.643 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -6.865 ; -6.865 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.089 ; -6.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -5.881 ; -5.881 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -5.800 ; -5.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -3.519 ; -3.519 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -3.462 ; -3.462 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -3.562 ; -3.562 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.186 ; -6.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -5.810 ; -5.810 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -6.136 ; -6.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -5.866 ; -5.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -5.934 ; -5.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -6.085 ; -6.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -5.975 ; -5.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -6.482 ; -6.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -7.190 ; -7.190 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -6.514 ; -6.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -6.481 ; -6.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -6.848 ; -6.848 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -6.202 ; -6.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -6.606 ; -6.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -5.810 ; -5.810 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -6.096 ; -6.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -6.452 ; -6.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -6.834 ; -6.834 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.431 ; -4.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.632 ; -5.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.546 ; -5.546 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                      ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 7.753  ; 7.753  ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 7.756  ; 7.756  ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 7.410  ; 7.410  ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 11.177 ; 11.177 ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 9.757  ; 9.757  ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 9.836  ; 9.836  ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 9.521  ; 9.521  ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 11.060 ; 11.060 ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 10.929 ; 10.929 ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 11.177 ; 11.177 ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 11.109 ; 11.109 ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 9.621  ; 9.621  ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 11.321 ; 11.321 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 10.712 ; 10.712 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 11.115 ; 11.115 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 10.678 ; 10.678 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 10.445 ; 10.445 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 10.583 ; 10.583 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 11.321 ; 11.321 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 11.071 ; 11.071 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 11.182 ; 11.182 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 10.059 ; 10.059 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 10.544 ; 10.544 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 9.511  ; 9.511  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 10.659 ; 10.659 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 10.692 ; 10.692 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 9.920  ; 9.920  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 9.436  ; 9.436  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 9.715  ; 9.715  ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 4.263  ; 4.263  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 11.972 ; 11.972 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 11.243 ; 11.243 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 11.485 ; 11.485 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 11.030 ; 11.030 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 11.424 ; 11.424 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 11.465 ; 11.465 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 11.972 ; 11.972 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 11.443 ; 11.443 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 11.470 ; 11.470 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 10.232 ; 10.232 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 10.702 ; 10.702 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 10.107 ; 10.107 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 10.363 ; 10.363 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 10.526 ; 10.526 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 10.672 ; 10.672 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 10.305 ; 10.305 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 10.384 ; 10.384 ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 6.198  ; 6.198  ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 5.221  ; 5.221  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 4.513  ; 4.513  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 10.599 ; 10.599 ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 10.599 ; 10.599 ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 10.887 ; 10.887 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 10.887 ; 10.887 ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 9.284  ; 9.284  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 8.207  ; 8.207  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 8.987  ; 8.987  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 8.611  ; 8.611  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 7.981  ; 7.981  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 8.211  ; 8.211  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 9.284  ; 9.284  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 8.930  ; 8.930  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 9.191  ; 9.191  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 8.357  ; 8.357  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 9.077  ; 9.077  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 7.380  ; 7.380  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 9.047  ; 9.047  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 8.290  ; 8.290  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 8.419  ; 8.419  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 8.027  ; 8.027  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 8.660  ; 8.660  ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 9.935  ; 9.935  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 8.738  ; 8.738  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 9.357  ; 9.357  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 8.963  ; 8.963  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 8.960  ; 8.960  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 9.093  ; 9.093  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 9.935  ; 9.935  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 9.302  ; 9.302  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 9.479  ; 9.479  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 8.530  ; 8.530  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 9.235  ; 9.235  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 7.976  ; 7.976  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 8.751  ; 8.751  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 8.124  ; 8.124  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 9.171  ; 9.171  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 8.896  ; 8.896  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 9.329  ; 9.329  ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 8.736  ; 8.736  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 8.736  ; 8.736  ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.433  ; 3.433  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 9.024  ; 9.024  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 9.024  ; 9.024  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 4.970  ; 4.970  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.313  ; 5.313  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.022  ; 5.022  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.850  ; 4.850  ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.424  ; 3.424  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 8.736  ; 8.736  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 8.736  ; 8.736  ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.433  ; 3.433  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 9.024  ; 9.024  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 9.024  ; 9.024  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 4.970  ; 4.970  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.313  ; 5.313  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.022  ; 5.022  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.850  ; 4.850  ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.424  ; 3.424  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 15.076 ; 15.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 15.079 ; 15.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 13.712 ; 13.712 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 11.560 ; 11.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 12.443 ; 12.443 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 11.657 ; 11.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 11.885 ; 11.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 12.833 ; 12.833 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 11.494 ; 11.494 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 12.235 ; 12.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 11.784 ; 11.784 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 12.119 ; 12.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 12.267 ; 12.267 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 12.020 ; 12.020 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 12.339 ; 12.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 12.164 ; 12.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 12.312 ; 12.312 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 12.157 ; 12.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 11.702 ; 11.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 13.033 ; 13.033 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 11.961 ; 11.961 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 13.223 ; 13.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 13.413 ; 13.413 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 12.527 ; 12.527 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 12.403 ; 12.403 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 13.712 ; 13.712 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 6.182  ; 6.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 3.100  ; 3.100  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 4.537  ; 4.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 4.138  ; 4.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 3.406  ; 3.406  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 13.920 ; 13.920 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 14.733 ; 14.733 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 18.500 ; 18.500 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 17.080 ; 17.080 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 17.159 ; 17.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 16.844 ; 16.844 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 18.383 ; 18.383 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 18.252 ; 18.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 18.500 ; 18.500 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 18.432 ; 18.432 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 16.944 ; 16.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 3.453  ; 3.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 3.628  ; 3.628  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 2.938  ; 2.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 4.294  ; 4.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 2.295  ; 2.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 2.466  ; 2.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 2.224  ; 2.224  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 2.702  ; 2.702  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 18.915 ; 18.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 18.002 ; 18.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 18.774 ; 18.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 18.015 ; 18.015 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 17.990 ; 17.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 17.842 ; 17.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 18.702 ; 18.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 18.346 ; 18.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 18.915 ; 18.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 18.609 ; 18.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 18.612 ; 18.612 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 17.555 ; 17.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 18.583 ; 18.583 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 18.482 ; 18.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 17.959 ; 17.959 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 17.854 ; 17.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 18.158 ; 18.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 3.616  ; 3.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 3.006  ; 3.006  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 3.619  ; 3.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 3.101  ; 3.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 3.190  ; 3.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 6.275  ; 6.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 6.275  ; 6.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 6.166  ; 6.166  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 6.189  ; 6.189  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 3.488  ; 3.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 3.416  ; 3.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 3.106  ; 3.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 3.430  ; 3.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 3.249  ; 3.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 3.638  ; 3.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 3.285  ; 3.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 12.103 ; 12.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 13.111 ; 13.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 15.084 ; 15.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 14.780 ; 14.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 3.158  ; 3.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 3.949  ; 3.949  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 2.268  ; 2.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 3.974  ; 3.974  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 3.551  ; 3.551  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 3.160  ; 3.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 14.307 ; 14.307 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 13.918 ; 13.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 13.931 ; 13.931 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 14.410 ; 14.410 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 14.253 ; 14.253 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 14.111 ; 14.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 13.812 ; 13.812 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 13.950 ; 13.950 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 13.804 ; 13.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 14.011 ; 14.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 3.828  ; 3.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 3.671  ; 3.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 3.828  ; 3.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 3.810  ; 3.810  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 3.629  ; 3.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 11.768 ; 11.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 2.300  ; 2.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 2.521  ; 2.521  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 3.941  ; 3.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 2.900  ; 2.900  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 2.934  ; 2.934  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 2.964  ; 2.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.587  ; 3.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 3.428  ; 3.428  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 3.852  ; 3.852  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 3.941  ; 3.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 2.935  ; 2.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 3.103  ; 3.103  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 3.262  ; 3.262  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 2.605  ; 2.605  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 15.070 ; 15.070 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 13.968 ; 13.968 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 14.188 ; 14.188 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 14.093 ; 14.093 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 14.789 ; 14.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 14.335 ; 14.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 14.523 ; 14.523 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 14.783 ; 14.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 15.070 ; 15.070 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 14.711 ; 14.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 14.401 ; 14.401 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 14.086 ; 14.086 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 13.705 ; 13.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 13.667 ; 13.667 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 13.982 ; 13.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 13.982 ; 13.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 19.526 ; 19.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 18.533 ; 18.533 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 19.144 ; 19.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 18.367 ; 18.367 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 18.969 ; 18.969 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 18.724 ; 18.724 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 19.481 ; 19.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 19.310 ; 19.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 19.203 ; 19.203 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 19.526 ; 19.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 18.770 ; 18.770 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 18.947 ; 18.947 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 19.013 ; 19.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 18.518 ; 18.518 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 18.711 ; 18.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 18.723 ; 18.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 18.827 ; 18.827 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 4.813  ; 4.813  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 13.808 ; 13.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 13.673 ; 13.673 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 14.137 ; 14.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 13.674 ; 13.674 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 13.575 ; 13.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 14.347 ; 14.347 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 14.865 ; 14.865 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 5.621  ; 5.621  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 3.418  ; 3.418  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 4.130  ; 4.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 2.939  ; 2.939  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 5.386  ; 5.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 3.588  ; 3.588  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 3.111  ; 3.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 3.387  ; 3.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 3.207  ; 3.207  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 3.209  ; 3.209  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 3.271  ; 3.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 3.386  ; 3.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 3.588  ; 3.588  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 3.472  ; 3.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 2.583  ; 2.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 4.076  ; 4.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 2.183  ; 2.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 2.689  ; 2.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 4.510  ; 4.510  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 3.950  ; 3.950  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 3.563  ; 3.563  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 3.262  ; 3.262  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 4.190  ; 4.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 4.167  ; 4.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 4.791  ; 4.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 3.891  ; 3.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 3.699  ; 3.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 3.079  ; 3.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 3.734  ; 3.734  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 3.188  ; 3.188  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 3.734  ; 3.734  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 3.371  ; 3.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 3.426  ; 3.426  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 10.820 ; 10.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 2.258  ; 2.258  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 3.180  ; 3.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 3.050  ; 3.050  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 7.355  ; 7.355  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 6.307  ; 6.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 6.747  ; 6.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 17.141 ; 17.141 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 17.144 ; 17.144 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 15.777 ; 15.777 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 13.625 ; 13.625 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 14.508 ; 14.508 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 13.722 ; 13.722 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 13.950 ; 13.950 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 14.898 ; 14.898 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 13.559 ; 13.559 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 14.300 ; 14.300 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 13.849 ; 13.849 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 14.184 ; 14.184 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 14.332 ; 14.332 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 14.085 ; 14.085 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 14.404 ; 14.404 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 14.229 ; 14.229 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 14.377 ; 14.377 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 14.222 ; 14.222 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 13.767 ; 13.767 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 15.098 ; 15.098 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 14.026 ; 14.026 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 15.288 ; 15.288 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 15.478 ; 15.478 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 14.592 ; 14.592 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 14.468 ; 14.468 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 15.777 ; 15.777 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 5.222  ; 4.001  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 3.017  ; 3.017  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 15.985 ; 15.985 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 16.798 ; 16.798 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 20.565 ; 20.565 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 19.145 ; 19.145 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 19.224 ; 19.224 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 18.909 ; 18.909 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 20.448 ; 20.448 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 20.317 ; 20.317 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 20.565 ; 20.565 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 20.497 ; 20.497 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 19.009 ; 19.009 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 20.980 ; 20.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 20.067 ; 20.067 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 20.839 ; 20.839 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 20.080 ; 20.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 20.055 ; 20.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 19.907 ; 19.907 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 20.767 ; 20.767 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 20.411 ; 20.411 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 20.980 ; 20.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 20.674 ; 20.674 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 20.677 ; 20.677 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 19.620 ; 19.620 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 20.648 ; 20.648 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 20.547 ; 20.547 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 20.024 ; 20.024 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 19.919 ; 19.919 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 20.223 ; 20.223 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 4.091  ; 4.091  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 4.091  ; 4.091  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 3.982  ; 3.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 3.832  ; 3.832  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 14.168 ; 14.168 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 15.176 ; 15.176 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 17.149 ; 17.149 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 16.845 ; 16.845 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 16.372 ; 16.372 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 15.983 ; 15.983 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 15.996 ; 15.996 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 16.475 ; 16.475 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 16.318 ; 16.318 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 16.176 ; 16.176 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 15.877 ; 15.877 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 16.015 ; 16.015 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 15.869 ; 15.869 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 16.076 ; 16.076 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 13.833 ; 13.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 17.135 ; 17.135 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 16.033 ; 16.033 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 16.253 ; 16.253 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 16.158 ; 16.158 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 16.854 ; 16.854 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 16.400 ; 16.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 16.588 ; 16.588 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 16.848 ; 16.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 17.135 ; 17.135 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 16.776 ; 16.776 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 16.466 ; 16.466 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 16.151 ; 16.151 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 15.770 ; 15.770 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 15.732 ; 15.732 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 16.047 ; 16.047 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 16.047 ; 16.047 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 21.591 ; 21.591 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 20.598 ; 20.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 21.209 ; 21.209 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 20.432 ; 20.432 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 21.034 ; 21.034 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 20.789 ; 20.789 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 21.546 ; 21.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 21.375 ; 21.375 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 21.268 ; 21.268 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 21.591 ; 21.591 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 20.835 ; 20.835 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 21.012 ; 21.012 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 21.078 ; 21.078 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 20.583 ; 20.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 20.776 ; 20.776 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 20.788 ; 20.788 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 20.892 ; 20.892 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 15.873 ; 15.873 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 15.738 ; 15.738 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 16.202 ; 16.202 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 15.739 ; 15.739 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 15.640 ; 15.640 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 16.412 ; 16.412 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 16.930 ; 16.930 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 3.440  ; 3.440  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 12.885 ; 12.885 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 15.076 ; 15.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 15.079 ; 15.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 13.712 ; 13.712 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 11.560 ; 11.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 12.443 ; 12.443 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 11.657 ; 11.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 11.885 ; 11.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 12.833 ; 12.833 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 11.494 ; 11.494 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 12.235 ; 12.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 11.784 ; 11.784 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 12.119 ; 12.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 12.267 ; 12.267 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 12.020 ; 12.020 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 12.339 ; 12.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 12.164 ; 12.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 12.312 ; 12.312 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 12.157 ; 12.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 11.702 ; 11.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 13.033 ; 13.033 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 11.961 ; 11.961 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 13.223 ; 13.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 13.413 ; 13.413 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 12.527 ; 12.527 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 12.403 ; 12.403 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 13.712 ; 13.712 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 6.182  ; 6.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 3.100  ; 3.100  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 4.537  ; 4.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 4.138  ; 4.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 3.406  ; 3.406  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 13.920 ; 13.920 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 14.733 ; 14.733 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 18.500 ; 18.500 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 17.080 ; 17.080 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 17.159 ; 17.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 16.844 ; 16.844 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 18.383 ; 18.383 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 18.252 ; 18.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 18.500 ; 18.500 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 18.432 ; 18.432 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 16.944 ; 16.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 3.453  ; 3.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 3.628  ; 3.628  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 2.938  ; 2.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 4.294  ; 4.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 2.295  ; 2.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 2.466  ; 2.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 2.224  ; 2.224  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 2.702  ; 2.702  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 18.915 ; 18.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 18.002 ; 18.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 18.774 ; 18.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 18.015 ; 18.015 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 17.990 ; 17.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 17.842 ; 17.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 18.702 ; 18.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 18.346 ; 18.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 18.915 ; 18.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 18.609 ; 18.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 18.612 ; 18.612 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 17.555 ; 17.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 18.583 ; 18.583 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 18.482 ; 18.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 17.959 ; 17.959 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 17.854 ; 17.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 18.158 ; 18.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 3.616  ; 3.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 3.006  ; 3.006  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 3.619  ; 3.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 3.101  ; 3.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 3.190  ; 3.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 6.275  ; 6.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 6.275  ; 6.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 6.166  ; 6.166  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 6.189  ; 6.189  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 3.488  ; 3.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 3.416  ; 3.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 3.106  ; 3.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 3.430  ; 3.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 3.249  ; 3.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 3.638  ; 3.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 3.285  ; 3.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 12.103 ; 12.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 13.111 ; 13.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 15.084 ; 15.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 14.780 ; 14.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 3.158  ; 3.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 3.949  ; 3.949  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 2.268  ; 2.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 3.974  ; 3.974  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 3.551  ; 3.551  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.160  ; 3.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 14.307 ; 14.307 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 13.918 ; 13.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 13.931 ; 13.931 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 14.410 ; 14.410 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 14.253 ; 14.253 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 14.111 ; 14.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 13.812 ; 13.812 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 13.950 ; 13.950 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 13.804 ; 13.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 14.011 ; 14.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 3.828  ; 3.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 3.671  ; 3.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 3.828  ; 3.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 3.810  ; 3.810  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 3.629  ; 3.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 11.768 ; 11.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 2.300  ; 2.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 2.521  ; 2.521  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 3.941  ; 3.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 2.900  ; 2.900  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 2.934  ; 2.934  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 2.964  ; 2.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.587  ; 3.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 3.428  ; 3.428  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 3.852  ; 3.852  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 3.941  ; 3.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 2.935  ; 2.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 3.103  ; 3.103  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 3.262  ; 3.262  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 2.605  ; 2.605  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 15.070 ; 15.070 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 13.968 ; 13.968 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 14.188 ; 14.188 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 14.093 ; 14.093 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 14.789 ; 14.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 14.335 ; 14.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 14.523 ; 14.523 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 14.783 ; 14.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 15.070 ; 15.070 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 14.711 ; 14.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 14.401 ; 14.401 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 14.086 ; 14.086 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 13.705 ; 13.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 13.667 ; 13.667 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 13.982 ; 13.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 13.982 ; 13.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 19.526 ; 19.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 18.533 ; 18.533 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 19.144 ; 19.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 18.367 ; 18.367 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 18.969 ; 18.969 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 18.724 ; 18.724 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 19.481 ; 19.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 19.310 ; 19.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 19.203 ; 19.203 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 19.526 ; 19.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 18.770 ; 18.770 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 18.947 ; 18.947 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 19.013 ; 19.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 18.518 ; 18.518 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 18.711 ; 18.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 18.723 ; 18.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 18.827 ; 18.827 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 4.813  ; 4.813  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 13.808 ; 13.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 13.673 ; 13.673 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 14.137 ; 14.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 13.674 ; 13.674 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 13.575 ; 13.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 14.347 ; 14.347 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 14.865 ; 14.865 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 5.621  ; 5.621  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 3.418  ; 3.418  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 4.130  ; 4.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 2.939  ; 2.939  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 5.386  ; 5.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 3.588  ; 3.588  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 3.111  ; 3.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 3.387  ; 3.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 3.207  ; 3.207  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 3.209  ; 3.209  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 3.271  ; 3.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 3.386  ; 3.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 3.588  ; 3.588  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 3.472  ; 3.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 2.583  ; 2.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 4.076  ; 4.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 2.183  ; 2.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 2.689  ; 2.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 4.510  ; 4.510  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 3.950  ; 3.950  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 3.563  ; 3.563  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 3.262  ; 3.262  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 4.190  ; 4.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 4.167  ; 4.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 4.791  ; 4.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 3.891  ; 3.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 3.699  ; 3.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 3.079  ; 3.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 3.734  ; 3.734  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 3.188  ; 3.188  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 3.734  ; 3.734  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 3.371  ; 3.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 3.426  ; 3.426  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 10.820 ; 10.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 2.258  ; 2.258  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 3.180  ; 3.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.050  ; 3.050  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 7.355  ; 7.355  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 6.307  ; 6.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 6.747  ; 6.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 17.141 ; 17.141 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 17.144 ; 17.144 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 15.777 ; 15.777 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 13.625 ; 13.625 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 14.508 ; 14.508 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 13.722 ; 13.722 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 13.950 ; 13.950 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 14.898 ; 14.898 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 13.559 ; 13.559 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 14.300 ; 14.300 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 13.849 ; 13.849 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 14.184 ; 14.184 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 14.332 ; 14.332 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 14.085 ; 14.085 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 14.404 ; 14.404 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 14.229 ; 14.229 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 14.377 ; 14.377 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 14.222 ; 14.222 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 13.767 ; 13.767 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 15.098 ; 15.098 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 14.026 ; 14.026 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 15.288 ; 15.288 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 15.478 ; 15.478 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 14.592 ; 14.592 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 14.468 ; 14.468 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 15.777 ; 15.777 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 5.222  ; 4.001  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 3.017  ; 3.017  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 15.985 ; 15.985 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 16.798 ; 16.798 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 20.565 ; 20.565 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 19.145 ; 19.145 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 19.224 ; 19.224 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 18.909 ; 18.909 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 20.448 ; 20.448 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 20.317 ; 20.317 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 20.565 ; 20.565 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 20.497 ; 20.497 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 19.009 ; 19.009 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 20.980 ; 20.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 20.067 ; 20.067 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 20.839 ; 20.839 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 20.080 ; 20.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 20.055 ; 20.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 19.907 ; 19.907 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 20.767 ; 20.767 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 20.411 ; 20.411 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 20.980 ; 20.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 20.674 ; 20.674 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 20.677 ; 20.677 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 19.620 ; 19.620 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 20.648 ; 20.648 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 20.547 ; 20.547 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 20.024 ; 20.024 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 19.919 ; 19.919 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 20.223 ; 20.223 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 4.091  ; 4.091  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 4.091  ; 4.091  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 3.982  ; 3.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 3.832  ; 3.832  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 14.168 ; 14.168 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 15.176 ; 15.176 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 17.149 ; 17.149 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 16.845 ; 16.845 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 16.372 ; 16.372 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 15.983 ; 15.983 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 15.996 ; 15.996 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 16.475 ; 16.475 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 16.318 ; 16.318 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 16.176 ; 16.176 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 15.877 ; 15.877 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 16.015 ; 16.015 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 15.869 ; 15.869 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 16.076 ; 16.076 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 13.833 ; 13.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 17.135 ; 17.135 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 16.033 ; 16.033 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 16.253 ; 16.253 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 16.158 ; 16.158 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 16.854 ; 16.854 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 16.400 ; 16.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 16.588 ; 16.588 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 16.848 ; 16.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 17.135 ; 17.135 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 16.776 ; 16.776 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 16.466 ; 16.466 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 16.151 ; 16.151 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 15.770 ; 15.770 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 15.732 ; 15.732 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 16.047 ; 16.047 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 16.047 ; 16.047 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 21.591 ; 21.591 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 20.598 ; 20.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 21.209 ; 21.209 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 20.432 ; 20.432 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 21.034 ; 21.034 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 20.789 ; 20.789 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 21.546 ; 21.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 21.375 ; 21.375 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 21.268 ; 21.268 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 21.591 ; 21.591 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 20.835 ; 20.835 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 21.012 ; 21.012 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 21.078 ; 21.078 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 20.583 ; 20.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 20.776 ; 20.776 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 20.788 ; 20.788 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 20.892 ; 20.892 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 15.873 ; 15.873 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 15.738 ; 15.738 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 16.202 ; 16.202 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 15.739 ; 15.739 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 15.640 ; 15.640 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 16.412 ; 16.412 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 16.930 ; 16.930 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.440  ; 3.440  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 12.885 ; 12.885 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 5.388  ; 5.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 5.391  ; 5.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 4.946  ; 4.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 4.032  ; 4.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 3.720  ; 3.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 5.045  ; 5.045  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 8.812  ; 8.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 7.392  ; 7.392  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 7.471  ; 7.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 7.156  ; 7.156  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 8.695  ; 8.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 8.564  ; 8.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 8.812  ; 8.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 8.744  ; 8.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 7.256  ; 7.256  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 3.604  ; 3.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 3.604  ; 3.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 3.525  ; 3.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 3.531  ; 3.531  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 3.215  ; 3.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 3.664  ; 3.664  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 3.664  ; 3.664  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 3.404  ; 3.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 3.645  ; 3.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 3.356  ; 3.356  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 5.725  ; 5.725  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 3.371  ; 3.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 3.371  ; 3.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 3.236  ; 3.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 3.245  ; 3.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 3.242  ; 3.242  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 8.956  ; 8.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 8.347  ; 8.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 8.750  ; 8.750  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 8.313  ; 8.313  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 8.080  ; 8.080  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 8.218  ; 8.218  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 8.956  ; 8.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 8.706  ; 8.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 8.817  ; 8.817  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 7.694  ; 7.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 8.179  ; 8.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 7.146  ; 7.146  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 8.294  ; 8.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 8.327  ; 8.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 7.555  ; 7.555  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 7.071  ; 7.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 7.350  ; 7.350  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 3.026  ; 3.026  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 4.890  ; 4.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 2.120  ; 2.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 2.237  ; 2.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 2.592  ; 2.592  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 6.311  ; 6.311  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 5.609  ; 5.609  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 5.419  ; 5.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 5.501  ; 5.501  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 5.842  ; 5.842  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 5.520  ; 5.520  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 5.733  ; 5.733  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 5.777  ; 5.777  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 6.311  ; 6.311  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 6.285  ; 6.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 5.897  ; 5.897  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 5.535  ; 5.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 5.427  ; 5.427  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 5.490  ; 5.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 5.070  ; 5.070  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 5.070  ; 5.070  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 4.942  ; 4.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 4.848  ; 4.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 10.543 ; 10.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 9.351  ; 9.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 9.120  ; 9.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 9.340  ; 9.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 9.480  ; 9.480  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 9.699  ; 9.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 10.498 ; 10.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 10.327 ; 10.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 9.119  ; 9.119  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 10.543 ; 10.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 9.197  ; 9.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 9.964  ; 9.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 10.030 ; 10.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 9.535  ; 9.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 9.371  ; 9.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 9.376  ; 9.376  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 9.800  ; 9.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 4.722  ; 4.722  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 4.579  ; 4.579  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 4.354  ; 4.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 5.207  ; 5.207  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 5.307  ; 5.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 4.510  ; 4.510  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 3.936  ; 3.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 4.214  ; 4.214  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 4.168  ; 4.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]      ; CLK_PLL1      ; 4.349  ; 4.349  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 4.073  ; 4.073  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 4.349  ; 4.349  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 3.979  ; 3.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 3.979  ; 3.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 4.098  ; 4.098  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 4.194  ; 4.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 4.211  ; 4.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 4.280  ; 4.280  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP        ; CLK_PLL1      ; 4.090  ; 4.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 5.583  ; 5.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 4.277  ; 4.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 4.340  ; 4.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 5.263  ; 5.263  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 4.545  ; 4.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 2.302  ; 2.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 2.178  ; 2.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 2.302  ; 2.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 2.180  ; 2.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 2.031  ; 2.031  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 2.017  ; 2.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 5.388  ; 5.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 5.391  ; 5.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 4.946  ; 4.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 4.032  ; 4.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 3.720  ; 3.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 5.045  ; 5.045  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 8.812  ; 8.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 7.392  ; 7.392  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 7.471  ; 7.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 7.156  ; 7.156  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 8.695  ; 8.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 8.564  ; 8.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 8.812  ; 8.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 8.744  ; 8.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 7.256  ; 7.256  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 3.604  ; 3.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 3.604  ; 3.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 3.525  ; 3.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 3.531  ; 3.531  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 3.215  ; 3.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 3.664  ; 3.664  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 3.664  ; 3.664  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 3.404  ; 3.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 3.645  ; 3.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 3.356  ; 3.356  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 5.725  ; 5.725  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 3.371  ; 3.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 3.371  ; 3.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 3.236  ; 3.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 3.245  ; 3.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 3.242  ; 3.242  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 8.956  ; 8.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 8.347  ; 8.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 8.750  ; 8.750  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 8.313  ; 8.313  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 8.080  ; 8.080  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 8.218  ; 8.218  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 8.956  ; 8.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 8.706  ; 8.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 8.817  ; 8.817  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 7.694  ; 7.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 8.179  ; 8.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 7.146  ; 7.146  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 8.294  ; 8.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 8.327  ; 8.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 7.555  ; 7.555  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 7.071  ; 7.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 7.350  ; 7.350  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 3.026  ; 3.026  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 4.890  ; 4.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 2.120  ; 2.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 2.237  ; 2.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 2.592  ; 2.592  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 6.311  ; 6.311  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 5.609  ; 5.609  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 5.419  ; 5.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 5.501  ; 5.501  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 5.842  ; 5.842  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 5.520  ; 5.520  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 5.733  ; 5.733  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 5.777  ; 5.777  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 6.311  ; 6.311  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 6.285  ; 6.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 5.897  ; 5.897  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 5.535  ; 5.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 5.427  ; 5.427  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 5.490  ; 5.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 5.070  ; 5.070  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 5.070  ; 5.070  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 4.942  ; 4.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 4.848  ; 4.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 10.543 ; 10.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 9.351  ; 9.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 9.120  ; 9.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 9.340  ; 9.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 9.480  ; 9.480  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 9.699  ; 9.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 10.498 ; 10.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 10.327 ; 10.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 9.119  ; 9.119  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 10.543 ; 10.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 9.197  ; 9.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 9.964  ; 9.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 10.030 ; 10.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 9.535  ; 9.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 9.371  ; 9.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 9.376  ; 9.376  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 9.800  ; 9.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 4.722  ; 4.722  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 4.579  ; 4.579  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 4.354  ; 4.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 5.207  ; 5.207  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 5.307  ; 5.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 4.510  ; 4.510  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.936  ; 3.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 4.214  ; 4.214  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 4.168  ; 4.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 4.349  ; 4.349  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 4.073  ; 4.073  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 4.349  ; 4.349  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 3.979  ; 3.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 3.979  ; 3.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 4.098  ; 4.098  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 4.194  ; 4.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 4.211  ; 4.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 4.280  ; 4.280  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 4.090  ; 4.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 5.583  ; 5.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 4.277  ; 4.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 4.340  ; 4.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 5.263  ; 5.263  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 4.545  ; 4.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 2.302  ; 2.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 2.178  ; 2.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 2.302  ; 2.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 2.180  ; 2.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 2.031  ; 2.031  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 2.017  ; 2.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 12.443 ; 12.443 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 11.464 ; 11.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 11.953 ; 11.953 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 11.358 ; 11.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 11.279 ; 11.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 11.539 ; 11.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 12.443 ; 12.443 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 11.961 ; 11.961 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 12.177 ; 12.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 11.673 ; 11.673 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 12.022 ; 12.022 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 10.714 ; 10.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 11.557 ; 11.557 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 11.371 ; 11.371 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 10.516 ; 10.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 10.612 ; 10.612 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 10.781 ; 10.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 4.303  ; 4.303  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 4.187  ; 4.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 4.197  ; 4.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 4.303  ; 4.303  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 4.291  ; 4.291  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 13.094 ; 13.094 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 11.995 ; 11.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 12.323 ; 12.323 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 11.710 ; 11.710 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 12.258 ; 12.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 12.421 ; 12.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 13.094 ; 13.094 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 12.333 ; 12.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 12.465 ; 12.465 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 11.846 ; 11.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 12.180 ; 12.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 11.310 ; 11.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 11.261 ; 11.261 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 11.205 ; 11.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 11.268 ; 11.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 11.481 ; 11.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 11.450 ; 11.450 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 12.443 ; 12.443 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 11.464 ; 11.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 11.953 ; 11.953 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 11.358 ; 11.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 11.279 ; 11.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 11.539 ; 11.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 12.443 ; 12.443 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 11.961 ; 11.961 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 12.177 ; 12.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 11.673 ; 11.673 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 12.022 ; 12.022 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 10.714 ; 10.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 11.557 ; 11.557 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 11.371 ; 11.371 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 10.516 ; 10.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 10.612 ; 10.612 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 10.781 ; 10.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 4.303  ; 4.303  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 4.187  ; 4.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 4.197  ; 4.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 4.303  ; 4.303  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 4.291  ; 4.291  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 13.094 ; 13.094 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 11.995 ; 11.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 12.323 ; 12.323 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 11.710 ; 11.710 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 12.258 ; 12.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 12.421 ; 12.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 13.094 ; 13.094 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 12.333 ; 12.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 12.465 ; 12.465 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 11.846 ; 11.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 12.180 ; 12.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 11.310 ; 11.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 11.261 ; 11.261 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 11.205 ; 11.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 11.268 ; 11.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 11.481 ; 11.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 11.450 ; 11.450 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.141  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.141  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 7.722  ; 7.722  ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 7.726  ; 7.726  ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 7.410  ; 7.410  ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 7.437  ; 7.437  ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 8.219  ; 8.219  ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 8.141  ; 8.141  ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 7.437  ; 7.437  ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 8.212  ; 8.212  ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 7.706  ; 7.706  ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 7.698  ; 7.698  ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 7.848  ; 7.848  ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 7.542  ; 7.542  ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 8.270  ; 8.270  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 9.099  ; 9.099  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 9.588  ; 9.588  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 9.369  ; 9.369  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 9.098  ; 9.098  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 9.003  ; 9.003  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 9.976  ; 9.976  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 9.752  ; 9.752  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 9.902  ; 9.902  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 9.422  ; 9.422  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 10.022 ; 10.022 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 8.270  ; 8.270  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 9.847  ; 9.847  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 9.434  ; 9.434  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 9.059  ; 9.059  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 8.655  ; 8.655  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 9.010  ; 9.010  ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 4.263  ; 4.263  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 8.866  ; 8.866  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 9.630  ; 9.630  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 9.958  ; 9.958  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 9.721  ; 9.721  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 10.077 ; 10.077 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 9.885  ; 9.885  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 10.627 ; 10.627 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 10.124 ; 10.124 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 10.190 ; 10.190 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 9.595  ; 9.595  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 10.180 ; 10.180 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 8.866  ; 8.866  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 9.551  ; 9.551  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 9.268  ; 9.268  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 9.811  ; 9.811  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 9.524  ; 9.524  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 9.679  ; 9.679  ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 6.198  ; 6.198  ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 5.221  ; 5.221  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 4.513  ; 4.513  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 10.599 ; 10.599 ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 10.599 ; 10.599 ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 10.887 ; 10.887 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 10.887 ; 10.887 ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 6.925  ; 6.925  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 7.193  ; 7.193  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 8.002  ; 8.002  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 7.628  ; 7.628  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 7.145  ; 7.145  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 7.524  ; 7.524  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 8.056  ; 8.056  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 8.025  ; 8.025  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 8.176  ; 8.176  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 7.720  ; 7.720  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 7.969  ; 7.969  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 6.925  ; 6.925  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 8.286  ; 8.286  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 7.717  ; 7.717  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 7.639  ; 7.639  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 7.250  ; 7.250  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 7.458  ; 7.458  ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 7.521  ; 7.521  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 7.724  ; 7.724  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 8.372  ; 8.372  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 7.980  ; 7.980  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 8.124  ; 8.124  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 8.406  ; 8.406  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 8.707  ; 8.707  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 8.397  ; 8.397  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 8.464  ; 8.464  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 7.893  ; 7.893  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 8.127  ; 8.127  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 7.521  ; 7.521  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 7.990  ; 7.990  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 7.551  ; 7.551  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 8.391  ; 8.391  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 8.119  ; 8.119  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 8.127  ; 8.127  ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 8.736  ; 8.736  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 8.736  ; 8.736  ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.433  ; 3.433  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.735  ; 4.735  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 9.024  ; 9.024  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 4.841  ; 4.841  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.216  ; 5.216  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.954  ; 4.954  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.735  ; 4.735  ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.424  ; 3.424  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 8.736  ; 8.736  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 8.736  ; 8.736  ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.433  ; 3.433  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.735  ; 4.735  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 9.024  ; 9.024  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 4.841  ; 4.841  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.216  ; 5.216  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.954  ; 4.954  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.735  ; 4.735  ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.424  ; 3.424  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 3.243  ; 3.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 3.248  ; 3.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 2.946  ; 2.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 3.760  ; 3.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 4.330  ; 4.330  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 3.728  ; 3.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 4.383  ; 4.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 3.613  ; 3.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 3.765  ; 3.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 3.207  ; 3.207  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 3.527  ; 3.527  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 3.913  ; 3.913  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 3.704  ; 3.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 3.392  ; 3.392  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 2.946  ; 2.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 3.217  ; 3.217  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 3.130  ; 3.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 3.007  ; 3.007  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 3.082  ; 3.082  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 2.994  ; 2.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 3.192  ; 3.192  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 3.730  ; 3.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 3.793  ; 3.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 3.943  ; 3.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 3.951  ; 3.951  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 3.531  ; 3.531  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 3.100  ; 3.100  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 3.196  ; 3.196  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 4.138  ; 4.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 3.406  ; 3.406  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 4.911  ; 4.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 3.253  ; 3.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 2.887  ; 2.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 2.888  ; 2.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 2.887  ; 2.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 3.006  ; 3.006  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 2.943  ; 2.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 2.988  ; 2.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 2.976  ; 2.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 3.053  ; 3.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 3.059  ; 3.059  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 3.453  ; 3.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 3.628  ; 3.628  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 2.938  ; 2.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 2.295  ; 2.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 2.466  ; 2.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 2.224  ; 2.224  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 2.660  ; 2.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 2.766  ; 2.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 3.459  ; 3.459  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 3.477  ; 3.477  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 3.396  ; 3.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 3.318  ; 3.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 3.295  ; 3.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 3.820  ; 3.820  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 3.514  ; 3.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 3.789  ; 3.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 3.488  ; 3.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 3.537  ; 3.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 3.032  ; 3.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 3.230  ; 3.230  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 3.668  ; 3.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 2.982  ; 2.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 2.766  ; 2.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 3.015  ; 3.015  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 3.537  ; 3.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 3.006  ; 3.006  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 3.540  ; 3.540  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 3.101  ; 3.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 3.190  ; 3.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 3.366  ; 3.366  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 3.625  ; 3.625  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 4.046  ; 3.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 3.366  ; 3.366  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 3.488  ; 3.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 3.416  ; 3.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 3.106  ; 3.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 3.430  ; 3.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 3.249  ; 3.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 3.638  ; 3.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 3.285  ; 3.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 3.390  ; 3.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 3.414  ; 3.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 3.401  ; 3.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 3.225  ; 3.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 2.905  ; 2.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 3.949  ; 3.949  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 2.268  ; 2.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 3.463  ; 3.463  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 3.117  ; 3.117  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 3.160  ; 3.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 5.022  ; 5.022  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 4.856  ; 4.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 4.919  ; 4.919  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 5.398  ; 5.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 5.241  ; 5.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 5.099  ; 5.099  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 4.803  ; 4.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 4.941  ; 4.929  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 4.783  ; 4.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 4.990  ; 5.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 3.062  ; 3.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 3.141  ; 3.141  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 3.266  ; 3.266  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 3.238  ; 3.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 3.062  ; 3.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 3.556  ; 3.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 2.300  ; 2.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 2.521  ; 2.521  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 2.900  ; 2.900  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 2.900  ; 2.900  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 2.934  ; 2.934  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 2.964  ; 2.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.357  ; 3.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 3.395  ; 3.395  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 3.581  ; 3.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 3.559  ; 3.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 2.935  ; 2.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 3.103  ; 3.103  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 2.754  ; 2.754  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 2.394  ; 2.394  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 5.745  ; 5.745  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 6.017  ; 6.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 5.745  ; 5.745  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 6.251  ; 6.251  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 6.503  ; 6.503  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 6.435  ; 6.435  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 6.448  ; 6.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 6.638  ; 6.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 6.914  ; 6.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 6.494  ; 6.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 6.655  ; 6.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 6.066  ; 6.066  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 5.936  ; 5.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 5.890  ; 5.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 6.283  ; 6.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 6.283  ; 6.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 5.011  ; 5.011  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 5.359  ; 5.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 5.627  ; 5.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 5.224  ; 5.224  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 5.802  ; 5.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 5.782  ; 5.782  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 6.295  ; 6.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 5.747  ; 5.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 5.947  ; 5.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 5.342  ; 5.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 5.407  ; 5.407  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 5.011  ; 5.011  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 5.072  ; 5.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 5.160  ; 5.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 5.550  ; 5.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 5.203  ; 5.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 5.584  ; 5.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 3.698  ; 3.698  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 5.071  ; 5.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 3.979  ; 3.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 4.465  ; 4.465  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 4.838  ; 4.838  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 4.739  ; 4.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 4.784  ; 4.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 5.837  ; 5.837  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 2.840  ; 2.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 2.582  ; 2.582  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 4.130  ; 4.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 2.899  ; 2.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 2.913  ; 2.913  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 2.165  ; 2.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 2.371  ; 2.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 2.753  ; 2.753  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 2.165  ; 2.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 2.497  ; 2.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 2.382  ; 2.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 2.485  ; 2.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 2.524  ; 2.524  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 2.583  ; 2.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 2.651  ; 2.651  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 2.183  ; 2.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 2.689  ; 2.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 3.990  ; 3.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 2.757  ; 2.757  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 3.536  ; 3.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 2.809  ; 2.809  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 3.670  ; 3.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 4.791  ; 4.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 3.310  ; 3.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 3.699  ; 3.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 2.991  ; 2.991  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 3.005  ; 3.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 3.005  ; 3.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 3.231  ; 3.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 3.185  ; 3.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 3.235  ; 3.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 3.211  ; 2.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 2.258  ; 2.258  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 3.180  ; 3.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 3.050  ; 3.050  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 3.543  ; 3.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 3.752  ; 3.752  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 3.776  ; 3.776  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 6.128  ; 6.128  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 6.132  ; 6.132  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 3.344  ; 3.344  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 3.580  ; 3.580  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 3.726  ; 3.726  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 4.433  ; 4.433  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 3.694  ; 3.694  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 4.349  ; 4.349  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 3.579  ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 3.731  ; 3.731  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 3.344  ; 3.344  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 3.542  ; 3.542  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 3.922  ; 3.922  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 3.713  ; 3.713  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 3.965  ; 3.965  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 3.974  ; 3.974  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 4.118  ; 4.118  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 4.242  ; 4.242  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 3.584  ; 3.584  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 4.398  ; 4.398  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 3.609  ; 3.609  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 3.920  ; 3.920  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 4.698  ; 4.698  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 3.769  ; 3.769  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 3.996  ; 3.996  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 3.921  ; 3.921  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 3.531  ; 3.531  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 3.017  ; 3.017  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 4.865  ; 4.865  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 5.816  ; 5.816  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 5.843  ; 5.843  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 6.625  ; 6.625  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 6.547  ; 6.547  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 5.843  ; 5.843  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 6.618  ; 6.618  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 6.112  ; 6.112  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 6.104  ; 6.104  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 6.254  ; 6.254  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 5.948  ; 5.948  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 5.376  ; 5.376  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 5.482  ; 5.482  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 6.041  ; 6.041  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 5.831  ; 5.831  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 5.909  ; 5.909  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 5.376  ; 5.376  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 6.339  ; 6.339  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 5.748  ; 5.748  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 6.551  ; 6.551  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 6.000  ; 6.000  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 6.676  ; 6.676  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 5.761  ; 5.761  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 6.512  ; 6.512  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 6.051  ; 6.051  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 6.102  ; 6.102  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 5.754  ; 5.754  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 5.962  ; 5.962  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 3.237  ; 3.237  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 3.496  ; 3.496  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 3.387  ; 3.387  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 3.237  ; 3.237  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 3.977  ; 3.977  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 3.926  ; 3.926  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 5.378  ; 5.378  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 5.074  ; 5.074  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 4.988  ; 4.988  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 4.822  ; 4.822  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 4.885  ; 4.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 5.364  ; 5.364  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 5.207  ; 5.207  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 5.065  ; 5.065  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 4.757  ; 4.757  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 4.895  ; 4.895  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 4.749  ; 4.749  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 4.956  ; 4.956  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 3.685  ; 3.556  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 5.711  ; 5.711  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 5.983  ; 5.983  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 5.711  ; 5.711  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 6.217  ; 6.217  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 6.684  ; 6.684  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 6.401  ; 6.401  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 6.414  ; 6.414  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 6.604  ; 6.604  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 6.880  ; 6.880  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 6.460  ; 6.460  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 6.621  ; 6.621  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 6.216  ; 6.216  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 5.902  ; 5.902  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 5.856  ; 5.856  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 6.249  ; 6.249  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 6.249  ; 6.249  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 5.885  ; 5.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 6.013  ; 6.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 6.411  ; 6.411  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 6.183  ; 6.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 6.888  ; 6.888  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 6.258  ; 6.258  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 6.990  ; 6.990  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 6.120  ; 6.120  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 6.591  ; 6.591  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 6.173  ; 6.173  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 6.105  ; 6.105  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 6.278  ; 6.278  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 6.216  ; 6.216  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 5.885  ; 5.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 6.569  ; 6.569  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 6.217  ; 6.217  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 6.107  ; 6.107  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 5.215  ; 5.215  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 3.945  ; 3.945  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 4.431  ; 4.431  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 4.804  ; 4.804  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 4.705  ; 4.705  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 4.750  ; 4.750  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 5.889  ; 5.889  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 2.970  ; 2.970  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 2.914  ; 3.122  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 3.243  ; 3.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 3.248  ; 3.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 2.946  ; 2.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 3.760  ; 3.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 4.330  ; 4.330  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 3.728  ; 3.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 4.383  ; 4.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 3.613  ; 3.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 3.765  ; 3.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 3.207  ; 3.207  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 3.527  ; 3.527  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 3.913  ; 3.913  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 3.704  ; 3.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 3.392  ; 3.392  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 2.946  ; 2.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 3.217  ; 3.217  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 3.130  ; 3.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 3.007  ; 3.007  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 3.082  ; 3.082  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 2.994  ; 2.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 3.192  ; 3.192  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 3.730  ; 3.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 3.793  ; 3.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 3.943  ; 3.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 3.951  ; 3.951  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.531  ; 3.531  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 3.100  ; 3.100  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 3.196  ; 3.196  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 4.138  ; 4.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 3.406  ; 3.406  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.911  ; 4.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 3.253  ; 3.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 2.887  ; 2.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 2.888  ; 2.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 2.887  ; 2.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 3.006  ; 3.006  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 2.943  ; 2.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 2.988  ; 2.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 2.976  ; 2.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 3.053  ; 3.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 3.059  ; 3.059  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 3.453  ; 3.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 3.628  ; 3.628  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 2.938  ; 2.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 2.295  ; 2.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 2.466  ; 2.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 2.224  ; 2.224  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 2.660  ; 2.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 2.766  ; 2.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 3.459  ; 3.459  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 3.477  ; 3.477  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 3.396  ; 3.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 3.318  ; 3.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 3.295  ; 3.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 3.820  ; 3.820  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 3.514  ; 3.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 3.789  ; 3.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 3.488  ; 3.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 3.537  ; 3.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 3.032  ; 3.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 3.230  ; 3.230  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 3.668  ; 3.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 2.982  ; 2.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 2.766  ; 2.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 3.015  ; 3.015  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 3.537  ; 3.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 3.006  ; 3.006  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 3.540  ; 3.540  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 3.101  ; 3.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 3.190  ; 3.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 3.366  ; 3.366  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 3.625  ; 3.625  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 4.046  ; 3.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 3.366  ; 3.366  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 3.488  ; 3.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 3.416  ; 3.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 3.106  ; 3.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 3.430  ; 3.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 3.249  ; 3.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 3.638  ; 3.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 3.285  ; 3.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 3.390  ; 3.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 3.414  ; 3.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 3.401  ; 3.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 3.225  ; 3.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 2.905  ; 2.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 3.949  ; 3.949  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 2.268  ; 2.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 3.463  ; 3.463  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 3.117  ; 3.117  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.160  ; 3.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 5.022  ; 5.022  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 4.856  ; 4.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 4.919  ; 4.919  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 5.398  ; 5.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 5.241  ; 5.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 5.099  ; 5.099  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 4.803  ; 4.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 4.941  ; 4.929  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 4.783  ; 4.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 4.990  ; 5.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 3.062  ; 3.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 3.141  ; 3.141  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 3.266  ; 3.266  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 3.238  ; 3.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 3.062  ; 3.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.556  ; 3.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 2.300  ; 2.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 2.521  ; 2.521  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 2.900  ; 2.900  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 2.900  ; 2.900  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 2.934  ; 2.934  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 2.964  ; 2.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.357  ; 3.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 3.395  ; 3.395  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 3.581  ; 3.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 3.559  ; 3.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 2.935  ; 2.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 3.103  ; 3.103  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 2.754  ; 2.754  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 2.394  ; 2.394  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 5.745  ; 5.745  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 6.017  ; 6.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 5.745  ; 5.745  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 6.251  ; 6.251  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 6.503  ; 6.503  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 6.435  ; 6.435  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 6.448  ; 6.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 6.638  ; 6.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 6.914  ; 6.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 6.494  ; 6.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 6.655  ; 6.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 6.066  ; 6.066  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 5.936  ; 5.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 5.890  ; 5.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 6.283  ; 6.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 6.283  ; 6.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 5.011  ; 5.011  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 5.359  ; 5.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 5.627  ; 5.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 5.224  ; 5.224  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 5.802  ; 5.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 5.782  ; 5.782  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 6.295  ; 6.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 5.747  ; 5.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 5.947  ; 5.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 5.342  ; 5.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 5.407  ; 5.407  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 5.011  ; 5.011  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 5.072  ; 5.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.160  ; 5.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.550  ; 5.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.203  ; 5.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 5.584  ; 5.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 3.698  ; 3.698  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 5.071  ; 5.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 3.979  ; 3.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 4.465  ; 4.465  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 4.838  ; 4.838  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 4.739  ; 4.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 4.784  ; 4.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 5.837  ; 5.837  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 2.840  ; 2.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 2.582  ; 2.582  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 4.130  ; 4.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 2.899  ; 2.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 2.913  ; 2.913  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 2.165  ; 2.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 2.371  ; 2.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 2.753  ; 2.753  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 2.165  ; 2.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 2.497  ; 2.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 2.382  ; 2.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 2.485  ; 2.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 2.524  ; 2.524  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 2.583  ; 2.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 2.651  ; 2.651  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 2.183  ; 2.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 2.689  ; 2.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 3.990  ; 3.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 2.757  ; 2.757  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 3.536  ; 3.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 2.809  ; 2.809  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 3.670  ; 3.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 4.791  ; 4.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 3.310  ; 3.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 3.699  ; 3.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 2.991  ; 2.991  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 3.005  ; 3.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 3.005  ; 3.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 3.231  ; 3.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 3.185  ; 3.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 3.235  ; 3.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.211  ; 2.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 2.258  ; 2.258  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 3.180  ; 3.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.050  ; 3.050  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 3.543  ; 3.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 3.752  ; 3.752  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 3.776  ; 3.776  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 6.128  ; 6.128  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 6.132  ; 6.132  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 3.344  ; 3.344  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 3.580  ; 3.580  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 3.726  ; 3.726  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 4.433  ; 4.433  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 3.694  ; 3.694  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 4.349  ; 4.349  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 3.579  ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 3.731  ; 3.731  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 3.344  ; 3.344  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 3.542  ; 3.542  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 3.922  ; 3.922  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 3.713  ; 3.713  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 3.965  ; 3.965  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 3.974  ; 3.974  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 4.118  ; 4.118  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 4.242  ; 4.242  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 3.584  ; 3.584  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 4.398  ; 4.398  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 3.609  ; 3.609  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 3.920  ; 3.920  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 4.698  ; 4.698  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 3.769  ; 3.769  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 3.996  ; 3.996  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 3.921  ; 3.921  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.531  ; 3.531  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 3.017  ; 3.017  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.865  ; 4.865  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 5.816  ; 5.816  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 5.843  ; 5.843  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 6.625  ; 6.625  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 6.547  ; 6.547  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 5.843  ; 5.843  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 6.618  ; 6.618  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 6.112  ; 6.112  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 6.104  ; 6.104  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 6.254  ; 6.254  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 5.948  ; 5.948  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 5.376  ; 5.376  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 5.482  ; 5.482  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 6.041  ; 6.041  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 5.831  ; 5.831  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 5.909  ; 5.909  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 5.376  ; 5.376  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.339  ; 6.339  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 5.748  ; 5.748  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.551  ; 6.551  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.000  ; 6.000  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 6.676  ; 6.676  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.761  ; 5.761  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.512  ; 6.512  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 6.051  ; 6.051  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.102  ; 6.102  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.754  ; 5.754  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.962  ; 5.962  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 3.237  ; 3.237  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 3.496  ; 3.496  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 3.387  ; 3.387  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 3.237  ; 3.237  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 3.977  ; 3.977  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 3.926  ; 3.926  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 5.378  ; 5.378  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 5.074  ; 5.074  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 4.988  ; 4.988  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 4.822  ; 4.822  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 4.885  ; 4.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 5.364  ; 5.364  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 5.207  ; 5.207  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 5.065  ; 5.065  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 4.757  ; 4.757  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 4.895  ; 4.895  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 4.749  ; 4.749  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 4.956  ; 4.956  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.685  ; 3.556  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 5.711  ; 5.711  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 5.983  ; 5.983  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 5.711  ; 5.711  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 6.217  ; 6.217  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 6.684  ; 6.684  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 6.401  ; 6.401  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 6.414  ; 6.414  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 6.604  ; 6.604  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 6.880  ; 6.880  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 6.460  ; 6.460  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 6.621  ; 6.621  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 6.216  ; 6.216  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 5.902  ; 5.902  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 5.856  ; 5.856  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 6.249  ; 6.249  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 6.249  ; 6.249  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 5.885  ; 5.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 6.013  ; 6.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 6.411  ; 6.411  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 6.183  ; 6.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 6.888  ; 6.888  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 6.258  ; 6.258  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 6.990  ; 6.990  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 6.120  ; 6.120  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 6.591  ; 6.591  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 6.173  ; 6.173  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 6.105  ; 6.105  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 6.278  ; 6.278  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 6.216  ; 6.216  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.885  ; 5.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 6.569  ; 6.569  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 6.217  ; 6.217  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 6.107  ; 6.107  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 5.215  ; 5.215  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 3.945  ; 3.945  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 4.431  ; 4.431  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 4.804  ; 4.804  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 4.705  ; 4.705  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 4.750  ; 4.750  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 5.889  ; 5.889  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 2.970  ; 2.970  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 2.914  ; 3.122  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 4.840  ; 4.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 4.844  ; 4.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 4.769  ; 4.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 4.032  ; 4.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 3.720  ; 3.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 4.528  ; 4.528  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 4.363  ; 4.363  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 4.448  ; 4.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 4.363  ; 4.363  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 4.555  ; 4.555  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 4.630  ; 4.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 4.824  ; 4.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 4.816  ; 4.816  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 4.966  ; 4.966  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 4.660  ; 4.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 2.483  ; 2.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 2.877  ; 2.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 2.795  ; 2.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 2.923  ; 2.923  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 2.483  ; 2.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 2.915  ; 2.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 2.672  ; 2.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 2.890  ; 2.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 3.002  ; 3.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 2.519  ; 2.519  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 2.957  ; 2.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 2.681  ; 2.681  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 2.519  ; 2.519  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 2.525  ; 2.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 4.860  ; 4.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 5.470  ; 5.470  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 5.682  ; 5.682  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 5.165  ; 5.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 5.124  ; 5.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 4.860  ; 4.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 5.794  ; 5.794  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 5.640  ; 5.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 5.878  ; 5.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 6.354  ; 6.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 7.043  ; 7.043  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 5.388  ; 5.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 6.556  ; 6.556  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 5.954  ; 5.954  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 5.795  ; 5.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 5.514  ; 5.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 6.128  ; 6.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 2.174  ; 2.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 4.357  ; 4.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 2.120  ; 2.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 2.237  ; 2.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 2.151  ; 2.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 4.241  ; 4.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 4.162  ; 4.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 4.184  ; 4.184  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 4.564  ; 4.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 4.329  ; 4.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 3.932  ; 3.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 4.401  ; 4.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 4.942  ; 4.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 4.877  ; 4.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 4.369  ; 4.369  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 4.277  ; 4.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 3.947  ; 3.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 4.147  ; 4.147  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 4.147  ; 4.147  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 3.941  ; 3.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 3.821  ; 3.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 3.342  ; 3.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 3.670  ; 3.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 4.174  ; 4.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 4.092  ; 4.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 4.635  ; 4.635  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 3.342  ; 3.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 4.513  ; 4.513  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 4.152  ; 4.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 3.524  ; 3.524  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 3.840  ; 3.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 3.647  ; 3.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 3.529  ; 3.529  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 3.731  ; 3.731  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 3.787  ; 3.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 3.955  ; 3.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 3.616  ; 3.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 3.541  ; 3.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 3.723  ; 3.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 3.621  ; 3.621  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 3.411  ; 3.411  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 3.785  ; 3.785  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 4.103  ; 4.103  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 3.993  ; 3.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 3.936  ; 3.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 3.818  ; 3.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 4.125  ; 4.125  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]      ; CLK_PLL1      ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 4.008  ; 4.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 4.284  ; 4.284  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 4.033  ; 4.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 4.129  ; 4.129  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 4.146  ; 4.146  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 4.215  ; 4.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP        ; CLK_PLL1      ; 4.025  ; 4.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 5.546  ; 5.546  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 4.180  ; 4.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 4.293  ; 4.293  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 5.226  ; 5.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 4.012  ; 4.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 1.262  ; 2.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 2.178  ; 2.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 2.302  ; 2.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 2.180  ; 2.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 2.031  ; 2.031  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 2.017  ; 2.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 4.840  ; 4.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 4.844  ; 4.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 4.769  ; 4.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 4.032  ; 4.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 3.720  ; 3.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 4.528  ; 4.528  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 4.363  ; 4.363  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 4.448  ; 4.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 4.363  ; 4.363  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 4.555  ; 4.555  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 4.630  ; 4.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 4.824  ; 4.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 4.816  ; 4.816  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 4.966  ; 4.966  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 4.660  ; 4.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 2.483  ; 2.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 2.877  ; 2.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 2.795  ; 2.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 2.923  ; 2.923  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 2.483  ; 2.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 2.915  ; 2.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 2.672  ; 2.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 2.890  ; 2.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 3.002  ; 3.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 2.519  ; 2.519  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 2.957  ; 2.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 2.681  ; 2.681  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 2.519  ; 2.519  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 2.525  ; 2.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 4.860  ; 4.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 5.470  ; 5.470  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 5.682  ; 5.682  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 5.165  ; 5.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 5.124  ; 5.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 4.860  ; 4.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 5.794  ; 5.794  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 5.640  ; 5.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 5.878  ; 5.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.354  ; 6.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 7.043  ; 7.043  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.388  ; 5.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.556  ; 6.556  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.954  ; 5.954  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 5.795  ; 5.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.514  ; 5.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 6.128  ; 6.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 2.174  ; 2.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 4.357  ; 4.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 2.120  ; 2.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 2.237  ; 2.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 2.151  ; 2.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 4.241  ; 4.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 4.162  ; 4.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 4.184  ; 4.184  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 4.564  ; 4.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 4.329  ; 4.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 3.932  ; 3.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 4.401  ; 4.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 4.942  ; 4.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 4.877  ; 4.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 4.369  ; 4.369  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 4.277  ; 4.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 3.947  ; 3.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 4.147  ; 4.147  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 4.147  ; 4.147  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 3.941  ; 3.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 3.821  ; 3.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 3.342  ; 3.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 3.670  ; 3.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 4.174  ; 4.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 4.092  ; 4.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 4.635  ; 4.635  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 3.342  ; 3.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 4.513  ; 4.513  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 4.152  ; 4.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 3.524  ; 3.524  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 3.840  ; 3.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 3.647  ; 3.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 3.529  ; 3.529  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 3.731  ; 3.731  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 3.787  ; 3.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 3.955  ; 3.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 3.616  ; 3.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 3.541  ; 3.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 3.723  ; 3.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 3.621  ; 3.621  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 3.411  ; 3.411  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 3.785  ; 3.785  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 4.103  ; 4.103  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 3.993  ; 3.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.936  ; 3.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 3.818  ; 3.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 4.125  ; 4.125  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 4.008  ; 4.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 4.284  ; 4.284  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 4.033  ; 4.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 4.129  ; 4.129  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 4.146  ; 4.146  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 4.215  ; 4.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 4.025  ; 4.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 5.546  ; 5.546  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 4.180  ; 4.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 4.293  ; 4.293  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 5.226  ; 5.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 4.012  ; 4.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 1.262  ; 2.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 2.178  ; 2.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 2.302  ; 2.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 2.180  ; 2.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 2.031  ; 2.031  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 2.017  ; 2.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 5.399  ; 5.399  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 6.042  ; 6.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 6.499  ; 6.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 6.295  ; 6.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 5.746  ; 5.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 5.965  ; 5.965  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 6.785  ; 6.785  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 6.851  ; 6.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 6.850  ; 6.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 6.267  ; 6.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 7.092  ; 7.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 5.399  ; 5.399  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 6.575  ; 6.575  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 6.126  ; 6.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 5.491  ; 5.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 5.513  ; 5.513  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 5.630  ; 5.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 2.603  ; 2.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 2.603  ; 2.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 2.968  ; 2.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 2.961  ; 2.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 5.960  ; 5.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 6.573  ; 6.573  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 6.869  ; 6.869  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 6.647  ; 6.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 6.725  ; 6.725  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 6.847  ; 6.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 7.436  ; 7.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 7.223  ; 7.223  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 7.138  ; 7.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 6.440  ; 6.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 7.250  ; 7.250  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 5.995  ; 5.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 6.279  ; 6.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 5.960  ; 5.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 6.243  ; 6.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 6.382  ; 6.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 6.299  ; 6.299  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 5.399  ; 5.399  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 6.042  ; 6.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 6.499  ; 6.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 6.295  ; 6.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 5.746  ; 5.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 5.965  ; 5.965  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.785  ; 6.785  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.851  ; 6.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.850  ; 6.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.267  ; 6.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 7.092  ; 7.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.399  ; 5.399  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.575  ; 6.575  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 6.126  ; 6.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 5.491  ; 5.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.513  ; 5.513  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.630  ; 5.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 2.603  ; 2.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 2.603  ; 2.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 2.968  ; 2.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 2.961  ; 2.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 5.960  ; 5.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 6.573  ; 6.573  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 6.869  ; 6.869  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 6.647  ; 6.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 6.725  ; 6.725  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 6.847  ; 6.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 7.436  ; 7.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 7.223  ; 7.223  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 7.138  ; 7.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 6.440  ; 6.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 7.250  ; 7.250  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 5.995  ; 5.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 6.279  ; 6.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.960  ; 5.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 6.243  ; 6.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 6.382  ; 6.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 6.299  ; 6.299  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.141  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.141  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------+
; Propagation Delay                                                ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 10.439 ; 10.439 ; 10.439 ; 10.439 ;
; ASn          ; ACSI_WRn      ; 10.442 ; 10.442 ; 10.442 ; 10.442 ;
; ASn          ; BUTTONn       ; 9.679  ;        ;        ; 9.679  ;
; ASn          ; CA1_OUT       ; 10.096 ;        ;        ; 10.096 ;
; ASn          ; CD[0]         ; 12.443 ; 12.443 ; 12.443 ; 12.443 ;
; ASn          ; CD[1]         ; 12.522 ; 12.522 ; 12.522 ; 12.522 ;
; ASn          ; CD[2]         ; 12.207 ; 12.207 ; 12.207 ; 12.207 ;
; ASn          ; CD[3]         ; 13.746 ; 13.746 ; 13.746 ; 13.746 ;
; ASn          ; CD[4]         ; 13.615 ; 13.615 ; 13.615 ; 13.615 ;
; ASn          ; CD[5]         ; 13.863 ; 13.863 ; 13.863 ; 13.863 ;
; ASn          ; CD[6]         ; 13.795 ; 13.795 ; 13.795 ; 13.795 ;
; ASn          ; CD[7]         ; 12.307 ; 12.307 ; 12.307 ; 12.307 ;
; ASn          ; DATA[0]       ; 13.161 ; 13.218 ; 13.218 ; 13.161 ;
; ASn          ; DATA[1]       ; 13.791 ; 13.803 ; 13.803 ; 13.791 ;
; ASn          ; DATA[2]       ; 13.169 ; 13.432 ; 13.432 ; 13.169 ;
; ASn          ; DATA[3]       ; 12.901 ; 12.872 ; 12.872 ; 12.901 ;
; ASn          ; DATA[4]       ; 13.025 ; 13.125 ; 13.125 ; 13.025 ;
; ASn          ; DATA[5]       ; 13.809 ; 13.843 ; 13.843 ; 13.809 ;
; ASn          ; DATA[6]       ; 13.774 ; 13.748 ; 13.748 ; 13.774 ;
; ASn          ; DATA[7]       ; 13.759 ; 13.964 ; 13.964 ; 13.759 ;
; ASn          ; DATA[8]       ; 13.827 ; 13.827 ; 13.827 ; 13.827 ;
; ASn          ; DATA[9]       ; 14.090 ; 14.090 ; 14.090 ; 14.090 ;
; ASn          ; DATA[10]      ; 13.089 ; 13.086 ; 13.086 ; 13.089 ;
; ASn          ; DATA[11]      ; 13.951 ; 13.977 ; 13.977 ; 13.951 ;
; ASn          ; DATA[12]      ; 14.241 ; 14.241 ; 14.241 ; 14.241 ;
; ASn          ; DATA[13]      ; 13.255 ; 13.207 ; 13.207 ; 13.255 ;
; ASn          ; DATA[14]      ; 12.936 ; 12.936 ; 12.936 ; 12.936 ;
; ASn          ; DATA[15]      ; 13.347 ; 13.288 ; 13.288 ; 13.347 ;
; ASn          ; DTACKn        ; 11.191 ; 11.191 ; 11.191 ; 11.191 ;
; ASn          ; FLASH_CEn     ; 9.382  ;        ;        ; 9.382  ;
; ASn          ; FLASH_OEn     ; 9.078  ;        ;        ; 9.078  ;
; ASn          ; IDE_CS0n      ; 6.810  ;        ;        ; 6.810  ;
; ASn          ; IDE_CS1n      ; 6.389  ;        ;        ; 6.389  ;
; ASn          ; IDE_D_EN_INn  ; 7.079  ;        ;        ; 7.079  ;
; ASn          ; IDE_D_EN_OUTn ; 7.793  ;        ;        ; 7.793  ;
; ASn          ; IDE_IORDn     ; 7.636  ;        ;        ; 7.636  ;
; ASn          ; IDE_IOWRn     ; 7.494  ;        ;        ; 7.494  ;
; ASn          ; JOY_RHn       ; 7.135  ;        ;        ; 7.135  ;
; ASn          ; JOY_RLn       ; 7.274  ;        ;        ; 7.274  ;
; ASn          ; JOY_WEn       ;        ; 7.128  ; 7.128  ;        ;
; ASn          ; JOY_WL        ;        ; 7.155  ; 7.155  ;        ;
; ASn          ; RAM_DATA[0]   ; 13.692 ; 13.749 ; 13.749 ; 13.692 ;
; ASn          ; RAM_DATA[1]   ; 14.161 ; 14.173 ; 14.173 ; 14.161 ;
; ASn          ; RAM_DATA[2]   ; 13.521 ; 13.784 ; 13.784 ; 13.521 ;
; ASn          ; RAM_DATA[3]   ; 13.880 ; 13.851 ; 13.851 ; 13.880 ;
; ASn          ; RAM_DATA[4]   ; 13.907 ; 14.007 ; 14.007 ; 13.907 ;
; ASn          ; RAM_DATA[5]   ; 14.460 ; 14.494 ; 14.494 ; 14.460 ;
; ASn          ; RAM_DATA[6]   ; 14.146 ; 14.120 ; 14.120 ; 14.146 ;
; ASn          ; RAM_DATA[7]   ; 14.047 ; 14.252 ; 14.252 ; 14.047 ;
; ASn          ; RAM_DATA[8]   ; 14.000 ; 14.000 ; 14.000 ; 14.000 ;
; ASn          ; RAM_DATA[9]   ; 14.248 ; 14.248 ; 14.248 ; 14.248 ;
; ASn          ; RAM_DATA[10]  ; 13.685 ; 13.682 ; 13.682 ; 13.685 ;
; ASn          ; RAM_DATA[11]  ; 13.655 ; 13.681 ; 13.681 ; 13.655 ;
; ASn          ; RAM_DATA[12]  ; 14.075 ; 14.075 ; 14.075 ; 14.075 ;
; ASn          ; RAM_DATA[13]  ; 14.007 ; 13.959 ; 13.959 ; 14.007 ;
; ASn          ; RAM_DATA[14]  ; 13.805 ; 13.805 ; 13.805 ; 13.805 ;
; ASn          ; RAM_DATA[15]  ; 14.016 ; 13.957 ; 13.957 ; 14.016 ;
; ASn          ; ROM0n         ; 7.771  ;        ;        ; 7.771  ;
; ASn          ; ROM1n         ; 7.660  ;        ;        ; 7.660  ;
; ASn          ; ROM2n         ; 8.435  ;        ;        ; 8.435  ;
; ASn          ; ROM3n         ; 7.493  ;        ;        ; 7.493  ;
; ASn          ; ROM4n         ; 7.551  ;        ;        ; 7.551  ;
; ASn          ; ROM5n         ; 8.465  ;        ;        ; 8.465  ;
; ASn          ; ROM6n         ; 8.447  ;        ;        ; 8.447  ;
; COM_CTS      ; DATA[2]       ;        ; 10.769 ; 10.769 ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 11.121 ; 11.121 ;        ;
; COM_DCD      ; DATA[1]       ;        ; 11.463 ; 11.463 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 11.833 ; 11.833 ;        ;
; COM_RI       ; DATA[6]       ;        ; 10.598 ; 10.598 ;        ;
; COM_RI       ; RAM_DATA[6]   ;        ; 10.970 ; 10.970 ;        ;
; CONFIG[1]    ; DATA[7]       ; 11.519 ; 11.519 ; 11.519 ; 11.519 ;
; CONFIG[1]    ; HSYNC         ; 6.269  ; 6.269  ; 6.269  ; 6.269  ;
; CONFIG[1]    ; RAM_DATA[7]   ; 11.807 ; 11.807 ; 11.807 ; 11.807 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 7.504  ; 7.375  ; 7.375  ; 7.504  ;
; CONFIG[1]    ; RAM_DATA[13]  ; 7.750  ; 7.847  ; 7.847  ; 7.750  ;
; CONFIG[1]    ; RAM_DATA[14]  ; 7.556  ; 7.488  ; 7.488  ; 7.556  ;
; CONFIG[1]    ; RAM_DATA[15]  ; 7.269  ; 7.384  ; 7.384  ; 7.269  ;
; CONFIG[1]    ; VSYNC         ; 6.125  ; 6.125  ; 6.125  ; 6.125  ;
; CONFIG[2]    ; DATA[7]       ; 11.465 ; 11.465 ; 11.465 ; 11.465 ;
; CONFIG[2]    ; HSYNC         ; 6.183  ; 6.183  ; 6.183  ; 6.183  ;
; CONFIG[2]    ; RAM_DATA[7]   ; 11.753 ; 11.753 ; 11.753 ; 11.753 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 7.176  ; 7.305  ; 7.305  ; 7.176  ;
; CONFIG[2]    ; RAM_DATA[13]  ; 7.648  ; 7.551  ; 7.551  ; 7.648  ;
; CONFIG[2]    ; RAM_DATA[14]  ; 7.289  ; 7.357  ; 7.357  ; 7.289  ;
; CONFIG[2]    ; RAM_DATA[15]  ; 7.185  ; 7.070  ; 7.070  ; 7.185  ;
; CONFIG[2]    ; VSYNC         ; 6.051  ; 6.051  ; 6.051  ; 6.051  ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 8.454  ; 8.454  ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 7.432  ; 7.432  ;        ;
; CONFIG[6]    ; DATA[0]       ; 9.728  ; 9.728  ; 9.728  ; 9.728  ;
; CONFIG[6]    ; DATA[1]       ; 10.103 ; 10.103 ; 10.103 ; 10.103 ;
; CONFIG[6]    ; DATA[2]       ; 9.934  ; 9.934  ; 9.934  ; 9.934  ;
; CONFIG[6]    ; DATA[3]       ; 10.239 ; 10.112 ; 10.112 ; 10.239 ;
; CONFIG[6]    ; DATA[4]       ; 10.261 ; 10.388 ; 10.388 ; 10.261 ;
; CONFIG[6]    ; DATA[5]       ; 11.157 ; 11.284 ; 11.284 ; 11.157 ;
; CONFIG[6]    ; DATA[6]       ; 11.057 ; 11.184 ; 11.184 ; 11.057 ;
; CONFIG[6]    ; DATA[7]       ; 11.290 ; 11.417 ; 11.417 ; 11.290 ;
; CONFIG[6]    ; DATA[8]       ; 10.828 ; 10.701 ; 10.701 ; 10.828 ;
; CONFIG[6]    ; DATA[9]       ; 11.277 ; 11.225 ; 11.225 ; 11.277 ;
; CONFIG[6]    ; DATA[10]      ; 10.253 ; 10.380 ; 10.380 ; 10.253 ;
; CONFIG[6]    ; DATA[11]      ; 11.136 ; 11.190 ; 11.190 ; 11.136 ;
; CONFIG[6]    ; DATA[12]      ; 10.990 ; 11.117 ; 11.117 ; 10.990 ;
; CONFIG[6]    ; DATA[13]      ; 10.422 ; 10.549 ; 10.549 ; 10.422 ;
; CONFIG[6]    ; DATA[14]      ; 9.985  ; 9.946  ; 9.946  ; 9.985  ;
; CONFIG[6]    ; DATA[15]      ; 10.318 ; 10.445 ; 10.445 ; 10.318 ;
; CONFIG[6]    ; DTACKn        ; 8.708  ; 8.708  ; 8.708  ; 8.708  ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 7.744  ; 7.744  ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 7.835  ; 7.835  ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 8.608  ; 8.481  ; 8.481  ; 8.608  ;
; CONFIG[6]    ; FLASH_OEn     ; 8.304  ; 8.177  ; 8.177  ; 8.304  ;
; CONFIG[6]    ; RAM_DATA[0]   ; 10.259 ; 10.259 ; 10.259 ; 10.259 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 10.473 ; 10.473 ; 10.473 ; 10.473 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 10.286 ; 10.286 ; 10.286 ; 10.286 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 11.218 ; 11.091 ; 11.091 ; 11.218 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 11.143 ; 11.270 ; 11.270 ; 11.143 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 11.808 ; 11.935 ; 11.935 ; 11.808 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 11.429 ; 11.556 ; 11.556 ; 11.429 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 11.578 ; 11.705 ; 11.705 ; 11.578 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 11.001 ; 10.874 ; 10.874 ; 11.001 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 11.435 ; 11.383 ; 11.383 ; 11.435 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 10.849 ; 10.976 ; 10.976 ; 10.849 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 10.840 ; 10.894 ; 10.894 ; 10.840 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 10.824 ; 10.951 ; 10.951 ; 10.824 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 11.174 ; 11.301 ; 11.301 ; 11.174 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 10.854 ; 10.815 ; 10.815 ; 10.854 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 10.987 ; 11.114 ; 11.114 ; 10.987 ;
; CONFIG[6]    ; ROM2n         ; 7.661  ; 7.534  ; 7.534  ; 7.661  ;
; CRT_PIN3     ; DATA[7]       ; 9.516  ; 9.516  ; 9.516  ; 9.516  ;
; CRT_PIN3     ; RAM_DATA[7]   ; 9.804  ; 9.804  ; 9.804  ; 9.804  ;
; CRT_PIN3     ; RAM_DATA[12]  ; 5.526  ; 5.397  ; 5.397  ; 5.526  ;
; CRT_PIN3     ; RAM_DATA[13]  ; 5.772  ; 5.869  ; 5.869  ; 5.772  ;
; CRT_PIN3     ; RAM_DATA[14]  ; 5.578  ; 5.510  ; 5.510  ; 5.578  ;
; CRT_PIN3     ; RAM_DATA[15]  ; 5.291  ; 5.406  ; 5.406  ; 5.291  ;
; DATA[0]      ; DATA[0]       ; 9.165  ;        ;        ; 9.165  ;
; DATA[0]      ; RAM_DATA[0]   ; 9.696  ;        ;        ; 9.696  ;
; DATA[1]      ; DATA[1]       ; 9.463  ;        ;        ; 9.463  ;
; DATA[1]      ; RAM_DATA[1]   ; 9.833  ;        ;        ; 9.833  ;
; DATA[2]      ; DATA[2]       ; 9.452  ;        ;        ; 9.452  ;
; DATA[2]      ; RAM_DATA[2]   ; 9.804  ;        ;        ; 9.804  ;
; DATA[3]      ; DATA[3]       ; 9.152  ;        ;        ; 9.152  ;
; DATA[3]      ; RAM_DATA[3]   ; 10.131 ;        ;        ; 10.131 ;
; DATA[4]      ; DATA[4]       ; 9.106  ;        ;        ; 9.106  ;
; DATA[4]      ; RAM_DATA[4]   ; 9.988  ;        ;        ; 9.988  ;
; DATA[5]      ; DATA[5]       ; 10.377 ;        ;        ; 10.377 ;
; DATA[5]      ; RAM_DATA[5]   ; 11.028 ;        ;        ; 11.028 ;
; DATA[6]      ; DATA[6]       ; 9.863  ;        ;        ; 9.863  ;
; DATA[6]      ; RAM_DATA[6]   ; 10.235 ;        ;        ; 10.235 ;
; DATA[7]      ; DATA[7]       ; 10.181 ;        ;        ; 10.181 ;
; DATA[7]      ; RAM_DATA[7]   ; 10.469 ;        ;        ; 10.469 ;
; DATA[8]      ; DATA[8]       ; 10.490 ;        ;        ; 10.490 ;
; DATA[8]      ; RAM_DATA[8]   ; 10.663 ;        ;        ; 10.663 ;
; DATA[9]      ; DATA[9]       ; 10.869 ;        ;        ; 10.869 ;
; DATA[9]      ; RAM_DATA[9]   ; 11.027 ;        ;        ; 11.027 ;
; DATA[10]     ; DATA[10]      ; 9.121  ;        ;        ; 9.121  ;
; DATA[10]     ; RAM_DATA[10]  ; 9.717  ;        ;        ; 9.717  ;
; DATA[11]     ; DATA[11]      ; 10.243 ;        ;        ; 10.243 ;
; DATA[11]     ; RAM_DATA[11]  ; 9.947  ;        ;        ; 9.947  ;
; DATA[12]     ; DATA[12]      ; 9.773  ;        ;        ; 9.773  ;
; DATA[12]     ; RAM_DATA[12]  ; 9.607  ;        ;        ; 9.607  ;
; DATA[13]     ; DATA[13]      ; 9.336  ;        ;        ; 9.336  ;
; DATA[13]     ; RAM_DATA[13]  ; 10.088 ;        ;        ; 10.088 ;
; DATA[14]     ; DATA[14]      ; 9.088  ;        ;        ; 9.088  ;
; DATA[14]     ; RAM_DATA[14]  ; 9.957  ;        ;        ; 9.957  ;
; DATA[15]     ; DATA[15]      ; 9.739  ;        ;        ; 9.739  ;
; DATA[15]     ; RAM_DATA[15]  ; 10.408 ;        ;        ; 10.408 ;
; FC[0]        ; ACSI_RDn      ; 9.247  ; 9.247  ; 9.247  ; 9.247  ;
; FC[0]        ; ACSI_WRn      ; 9.250  ; 9.250  ; 9.250  ; 9.250  ;
; FC[0]        ; BUTTONn       ; 8.018  ; 8.018  ; 8.018  ; 8.018  ;
; FC[0]        ; CA1_OUT       ; 8.904  ; 8.904  ; 8.904  ; 8.904  ;
; FC[0]        ; CD[0]         ; 11.251 ; 11.251 ; 11.251 ; 11.251 ;
; FC[0]        ; CD[1]         ; 11.330 ; 11.330 ; 11.330 ; 11.330 ;
; FC[0]        ; CD[2]         ; 11.015 ; 11.015 ; 11.015 ; 11.015 ;
; FC[0]        ; CD[3]         ; 12.554 ; 12.554 ; 12.554 ; 12.554 ;
; FC[0]        ; CD[4]         ; 12.423 ; 12.423 ; 12.423 ; 12.423 ;
; FC[0]        ; CD[5]         ; 12.671 ; 12.671 ; 12.671 ; 12.671 ;
; FC[0]        ; CD[6]         ; 12.603 ; 12.603 ; 12.603 ; 12.603 ;
; FC[0]        ; CD[7]         ; 11.115 ; 11.115 ; 11.115 ; 11.115 ;
; FC[0]        ; DATA[0]       ; 14.168 ; 14.168 ; 14.168 ; 14.168 ;
; FC[0]        ; DATA[1]       ; 14.753 ; 14.753 ; 14.753 ; 14.753 ;
; FC[0]        ; DATA[2]       ; 14.382 ; 14.382 ; 14.382 ; 14.382 ;
; FC[0]        ; DATA[3]       ; 13.686 ; 13.686 ; 13.686 ; 13.686 ;
; FC[0]        ; DATA[4]       ; 14.075 ; 14.075 ; 14.075 ; 14.075 ;
; FC[0]        ; DATA[5]       ; 14.793 ; 14.793 ; 14.793 ; 14.793 ;
; FC[0]        ; DATA[6]       ; 14.698 ; 14.698 ; 14.698 ; 14.698 ;
; FC[0]        ; DATA[7]       ; 14.914 ; 14.914 ; 14.914 ; 14.914 ;
; FC[0]        ; DATA[8]       ; 14.777 ; 14.777 ; 14.777 ; 14.777 ;
; FC[0]        ; DATA[9]       ; 15.040 ; 15.040 ; 15.040 ; 15.040 ;
; FC[0]        ; DATA[10]      ; 14.039 ; 14.039 ; 14.039 ; 14.039 ;
; FC[0]        ; DATA[11]      ; 14.927 ; 14.927 ; 14.927 ; 14.927 ;
; FC[0]        ; DATA[12]      ; 15.191 ; 15.191 ; 15.191 ; 15.191 ;
; FC[0]        ; DATA[13]      ; 14.205 ; 14.205 ; 14.205 ; 14.205 ;
; FC[0]        ; DATA[14]      ; 13.886 ; 13.886 ; 13.886 ; 13.886 ;
; FC[0]        ; DATA[15]      ; 14.297 ; 14.297 ; 14.297 ; 14.297 ;
; FC[0]        ; DTACKn        ; 10.952 ; 10.952 ; 10.952 ; 10.952 ;
; FC[0]        ; FLASH_CEn     ; 9.231  ; 9.231  ; 9.231  ; 9.231  ;
; FC[0]        ; FLASH_OEn     ; 8.927  ; 8.927  ; 8.927  ; 8.927  ;
; FC[0]        ; JOY_RHn       ; 8.213  ; 8.213  ; 8.213  ; 8.213  ;
; FC[0]        ; JOY_RLn       ; 8.352  ; 8.352  ; 8.352  ; 8.352  ;
; FC[0]        ; JOY_WEn       ; 8.206  ; 8.206  ; 8.206  ; 8.206  ;
; FC[0]        ; JOY_WL        ; 8.233  ; 8.233  ; 8.233  ; 8.233  ;
; FC[0]        ; RAM_DATA[0]   ; 14.699 ; 14.699 ; 14.699 ; 14.699 ;
; FC[0]        ; RAM_DATA[1]   ; 15.123 ; 15.123 ; 15.123 ; 15.123 ;
; FC[0]        ; RAM_DATA[2]   ; 14.734 ; 14.734 ; 14.734 ; 14.734 ;
; FC[0]        ; RAM_DATA[3]   ; 14.665 ; 14.665 ; 14.665 ; 14.665 ;
; FC[0]        ; RAM_DATA[4]   ; 14.957 ; 14.957 ; 14.957 ; 14.957 ;
; FC[0]        ; RAM_DATA[5]   ; 15.444 ; 15.444 ; 15.444 ; 15.444 ;
; FC[0]        ; RAM_DATA[6]   ; 15.070 ; 15.070 ; 15.070 ; 15.070 ;
; FC[0]        ; RAM_DATA[7]   ; 15.202 ; 15.202 ; 15.202 ; 15.202 ;
; FC[0]        ; RAM_DATA[8]   ; 14.950 ; 14.950 ; 14.950 ; 14.950 ;
; FC[0]        ; RAM_DATA[9]   ; 15.198 ; 15.198 ; 15.198 ; 15.198 ;
; FC[0]        ; RAM_DATA[10]  ; 14.635 ; 14.635 ; 14.635 ; 14.635 ;
; FC[0]        ; RAM_DATA[11]  ; 14.631 ; 14.631 ; 14.631 ; 14.631 ;
; FC[0]        ; RAM_DATA[12]  ; 15.025 ; 15.025 ; 15.025 ; 15.025 ;
; FC[0]        ; RAM_DATA[13]  ; 14.957 ; 14.957 ; 14.957 ; 14.957 ;
; FC[0]        ; RAM_DATA[14]  ; 14.755 ; 14.755 ; 14.755 ; 14.755 ;
; FC[0]        ; RAM_DATA[15]  ; 14.966 ; 14.966 ; 14.966 ; 14.966 ;
; FC[0]        ; ROM0n         ; 7.620  ; 7.620  ; 7.620  ; 7.620  ;
; FC[0]        ; ROM1n         ; 7.509  ; 7.509  ; 7.509  ; 7.509  ;
; FC[0]        ; ROM2n         ; 8.284  ; 8.284  ; 8.284  ; 8.284  ;
; FC[0]        ; ROM3n         ; 7.342  ; 7.342  ; 7.342  ; 7.342  ;
; FC[0]        ; ROM4n         ; 7.400  ; 7.400  ; 7.400  ; 7.400  ;
; FC[0]        ; ROM5n         ; 8.314  ; 8.314  ; 8.314  ; 8.314  ;
; FC[0]        ; ROM6n         ; 8.296  ; 8.296  ; 8.296  ; 8.296  ;
; FC[1]        ; ACSI_RDn      ; 9.246  ; 9.246  ; 9.246  ; 9.246  ;
; FC[1]        ; ACSI_WRn      ; 9.249  ; 9.249  ; 9.249  ; 9.249  ;
; FC[1]        ; BUTTONn       ; 7.938  ; 7.938  ; 7.938  ; 7.938  ;
; FC[1]        ; CA1_OUT       ; 8.903  ; 8.903  ; 8.903  ; 8.903  ;
; FC[1]        ; CD[0]         ; 11.250 ; 11.250 ; 11.250 ; 11.250 ;
; FC[1]        ; CD[1]         ; 11.329 ; 11.329 ; 11.329 ; 11.329 ;
; FC[1]        ; CD[2]         ; 11.014 ; 11.014 ; 11.014 ; 11.014 ;
; FC[1]        ; CD[3]         ; 12.553 ; 12.553 ; 12.553 ; 12.553 ;
; FC[1]        ; CD[4]         ; 12.422 ; 12.422 ; 12.422 ; 12.422 ;
; FC[1]        ; CD[5]         ; 12.670 ; 12.670 ; 12.670 ; 12.670 ;
; FC[1]        ; CD[6]         ; 12.602 ; 12.602 ; 12.602 ; 12.602 ;
; FC[1]        ; CD[7]         ; 11.114 ; 11.114 ; 11.114 ; 11.114 ;
; FC[1]        ; DATA[0]       ; 14.163 ; 14.163 ; 14.163 ; 14.163 ;
; FC[1]        ; DATA[1]       ; 14.748 ; 14.748 ; 14.748 ; 14.748 ;
; FC[1]        ; DATA[2]       ; 14.377 ; 14.377 ; 14.377 ; 14.377 ;
; FC[1]        ; DATA[3]       ; 13.681 ; 13.681 ; 13.681 ; 13.681 ;
; FC[1]        ; DATA[4]       ; 14.070 ; 14.070 ; 14.070 ; 14.070 ;
; FC[1]        ; DATA[5]       ; 14.788 ; 14.788 ; 14.788 ; 14.788 ;
; FC[1]        ; DATA[6]       ; 14.693 ; 14.693 ; 14.693 ; 14.693 ;
; FC[1]        ; DATA[7]       ; 14.909 ; 14.909 ; 14.909 ; 14.909 ;
; FC[1]        ; DATA[8]       ; 14.772 ; 14.772 ; 14.772 ; 14.772 ;
; FC[1]        ; DATA[9]       ; 15.035 ; 15.035 ; 15.035 ; 15.035 ;
; FC[1]        ; DATA[10]      ; 14.034 ; 14.034 ; 14.034 ; 14.034 ;
; FC[1]        ; DATA[11]      ; 14.922 ; 14.922 ; 14.922 ; 14.922 ;
; FC[1]        ; DATA[12]      ; 15.186 ; 15.186 ; 15.186 ; 15.186 ;
; FC[1]        ; DATA[13]      ; 14.200 ; 14.200 ; 14.200 ; 14.200 ;
; FC[1]        ; DATA[14]      ; 13.881 ; 13.881 ; 13.881 ; 13.881 ;
; FC[1]        ; DATA[15]      ; 14.292 ; 14.292 ; 14.292 ; 14.292 ;
; FC[1]        ; DTACKn        ; 10.947 ; 10.947 ; 10.947 ; 10.947 ;
; FC[1]        ; FLASH_CEn     ; 9.343  ; 9.343  ; 9.343  ; 9.343  ;
; FC[1]        ; FLASH_OEn     ; 9.039  ; 9.039  ; 9.039  ; 9.039  ;
; FC[1]        ; JOY_RHn       ; 8.212  ; 8.212  ; 8.212  ; 8.212  ;
; FC[1]        ; JOY_RLn       ; 8.351  ; 8.351  ; 8.351  ; 8.351  ;
; FC[1]        ; JOY_WEn       ; 8.205  ; 8.205  ; 8.205  ; 8.205  ;
; FC[1]        ; JOY_WL        ; 8.232  ; 8.232  ; 8.232  ; 8.232  ;
; FC[1]        ; RAM_DATA[0]   ; 14.694 ; 14.694 ; 14.694 ; 14.694 ;
; FC[1]        ; RAM_DATA[1]   ; 15.118 ; 15.118 ; 15.118 ; 15.118 ;
; FC[1]        ; RAM_DATA[2]   ; 14.729 ; 14.729 ; 14.729 ; 14.729 ;
; FC[1]        ; RAM_DATA[3]   ; 14.660 ; 14.660 ; 14.660 ; 14.660 ;
; FC[1]        ; RAM_DATA[4]   ; 14.952 ; 14.952 ; 14.952 ; 14.952 ;
; FC[1]        ; RAM_DATA[5]   ; 15.439 ; 15.439 ; 15.439 ; 15.439 ;
; FC[1]        ; RAM_DATA[6]   ; 15.065 ; 15.065 ; 15.065 ; 15.065 ;
; FC[1]        ; RAM_DATA[7]   ; 15.197 ; 15.197 ; 15.197 ; 15.197 ;
; FC[1]        ; RAM_DATA[8]   ; 14.945 ; 14.945 ; 14.945 ; 14.945 ;
; FC[1]        ; RAM_DATA[9]   ; 15.193 ; 15.193 ; 15.193 ; 15.193 ;
; FC[1]        ; RAM_DATA[10]  ; 14.630 ; 14.630 ; 14.630 ; 14.630 ;
; FC[1]        ; RAM_DATA[11]  ; 14.626 ; 14.626 ; 14.626 ; 14.626 ;
; FC[1]        ; RAM_DATA[12]  ; 15.020 ; 15.020 ; 15.020 ; 15.020 ;
; FC[1]        ; RAM_DATA[13]  ; 14.952 ; 14.952 ; 14.952 ; 14.952 ;
; FC[1]        ; RAM_DATA[14]  ; 14.750 ; 14.750 ; 14.750 ; 14.750 ;
; FC[1]        ; RAM_DATA[15]  ; 14.961 ; 14.961 ; 14.961 ; 14.961 ;
; FC[1]        ; ROM0n         ; 7.732  ; 7.732  ; 7.732  ; 7.732  ;
; FC[1]        ; ROM1n         ; 7.621  ; 7.621  ; 7.621  ; 7.621  ;
; FC[1]        ; ROM2n         ; 8.396  ; 8.396  ; 8.396  ; 8.396  ;
; FC[1]        ; ROM3n         ; 7.454  ; 7.454  ; 7.454  ; 7.454  ;
; FC[1]        ; ROM4n         ; 7.512  ; 7.512  ; 7.512  ; 7.512  ;
; FC[1]        ; ROM5n         ; 8.426  ; 8.426  ; 8.426  ; 8.426  ;
; FC[1]        ; ROM6n         ; 8.408  ; 8.408  ; 8.408  ; 8.408  ;
; FC[2]        ; ACSI_RDn      ; 9.195  ; 9.195  ; 9.195  ; 9.195  ;
; FC[2]        ; ACSI_WRn      ; 9.198  ; 9.198  ; 9.198  ; 9.198  ;
; FC[2]        ; CA1_OUT       ;        ; 8.852  ; 8.852  ;        ;
; FC[2]        ; CD[0]         ; 11.199 ; 11.199 ; 11.199 ; 11.199 ;
; FC[2]        ; CD[1]         ; 11.278 ; 11.278 ; 11.278 ; 11.278 ;
; FC[2]        ; CD[2]         ; 10.963 ; 10.963 ; 10.963 ; 10.963 ;
; FC[2]        ; CD[3]         ; 12.502 ; 12.502 ; 12.502 ; 12.502 ;
; FC[2]        ; CD[4]         ; 12.371 ; 12.371 ; 12.371 ; 12.371 ;
; FC[2]        ; CD[5]         ; 12.619 ; 12.619 ; 12.619 ; 12.619 ;
; FC[2]        ; CD[6]         ; 12.551 ; 12.551 ; 12.551 ; 12.551 ;
; FC[2]        ; CD[7]         ; 11.063 ; 11.063 ; 11.063 ; 11.063 ;
; FC[2]        ; DATA[0]       ; 14.109 ; 12.991 ; 12.991 ; 14.109 ;
; FC[2]        ; DATA[1]       ; 14.694 ; 13.401 ; 13.401 ; 14.694 ;
; FC[2]        ; DATA[2]       ; 14.323 ; 12.919 ; 12.919 ; 14.323 ;
; FC[2]        ; DATA[3]       ; 13.627 ; 12.753 ; 12.753 ; 13.627 ;
; FC[2]        ; DATA[4]       ; 14.016 ; 12.853 ; 12.853 ; 14.016 ;
; FC[2]        ; DATA[5]       ; 14.734 ; 13.501 ; 13.501 ; 14.734 ;
; FC[2]        ; DATA[6]       ; 14.639 ; 13.219 ; 13.219 ; 14.639 ;
; FC[2]        ; DATA[7]       ; 14.855 ; 13.390 ; 13.390 ; 14.855 ;
; FC[2]        ; DATA[8]       ; 14.718 ; 14.718 ; 14.718 ; 14.718 ;
; FC[2]        ; DATA[9]       ; 14.981 ; 14.981 ; 14.981 ; 14.981 ;
; FC[2]        ; DATA[10]      ; 13.977 ; 13.980 ; 13.980 ; 13.977 ;
; FC[2]        ; DATA[11]      ; 14.868 ; 14.842 ; 14.842 ; 14.868 ;
; FC[2]        ; DATA[12]      ; 15.132 ; 15.132 ; 15.132 ; 15.132 ;
; FC[2]        ; DATA[13]      ; 14.098 ; 14.146 ; 14.146 ; 14.098 ;
; FC[2]        ; DATA[14]      ; 13.827 ; 13.827 ; 13.827 ; 13.827 ;
; FC[2]        ; DATA[15]      ; 14.179 ; 14.238 ; 14.238 ; 14.179 ;
; FC[2]        ; DTACKn        ; 10.893 ; 10.893 ; 10.893 ; 10.893 ;
; FC[2]        ; JOY_RHn       ;        ; 8.161  ; 8.161  ;        ;
; FC[2]        ; JOY_RLn       ;        ; 8.300  ; 8.300  ;        ;
; FC[2]        ; JOY_WEn       ; 8.154  ;        ;        ; 8.154  ;
; FC[2]        ; JOY_WL        ; 8.181  ;        ;        ; 8.181  ;
; FC[2]        ; RAM_DATA[0]   ; 14.640 ; 13.522 ; 13.522 ; 14.640 ;
; FC[2]        ; RAM_DATA[1]   ; 15.064 ; 13.771 ; 13.771 ; 15.064 ;
; FC[2]        ; RAM_DATA[2]   ; 14.675 ; 13.271 ; 13.271 ; 14.675 ;
; FC[2]        ; RAM_DATA[3]   ; 14.606 ; 13.732 ; 13.732 ; 14.606 ;
; FC[2]        ; RAM_DATA[4]   ; 14.898 ; 13.735 ; 13.735 ; 14.898 ;
; FC[2]        ; RAM_DATA[5]   ; 15.385 ; 14.152 ; 14.152 ; 15.385 ;
; FC[2]        ; RAM_DATA[6]   ; 15.011 ; 13.591 ; 13.591 ; 15.011 ;
; FC[2]        ; RAM_DATA[7]   ; 15.143 ; 13.678 ; 13.678 ; 15.143 ;
; FC[2]        ; RAM_DATA[8]   ; 14.891 ; 14.891 ; 14.891 ; 14.891 ;
; FC[2]        ; RAM_DATA[9]   ; 15.139 ; 15.139 ; 15.139 ; 15.139 ;
; FC[2]        ; RAM_DATA[10]  ; 14.573 ; 14.576 ; 14.576 ; 14.573 ;
; FC[2]        ; RAM_DATA[11]  ; 14.572 ; 14.546 ; 14.546 ; 14.572 ;
; FC[2]        ; RAM_DATA[12]  ; 14.966 ; 14.966 ; 14.966 ; 14.966 ;
; FC[2]        ; RAM_DATA[13]  ; 14.850 ; 14.898 ; 14.898 ; 14.850 ;
; FC[2]        ; RAM_DATA[14]  ; 14.696 ; 14.696 ; 14.696 ; 14.696 ;
; FC[2]        ; RAM_DATA[15]  ; 14.848 ; 14.907 ; 14.907 ; 14.848 ;
; HDINTn       ; DATA[5]       ; 10.910 ;        ;        ; 10.910 ;
; HDINTn       ; RAM_DATA[5]   ; 11.561 ;        ;        ; 11.561 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 10.752 ; 10.752 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 11.403 ; 11.403 ;        ;
; IDE_IORDY    ; DTACKn        ; 7.922  ; 7.922  ; 7.922  ; 7.922  ;
; LDSn         ; ACSI_RDn      ; 10.250 ; 10.250 ; 10.250 ; 10.250 ;
; LDSn         ; ACSI_WRn      ; 10.253 ; 10.253 ; 10.253 ; 10.253 ;
; LDSn         ; BUTTONn       ; 9.490  ;        ;        ; 9.490  ;
; LDSn         ; CA1_OUT       ; 9.907  ;        ;        ; 9.907  ;
; LDSn         ; CD[0]         ; 12.254 ; 12.254 ; 12.254 ; 12.254 ;
; LDSn         ; CD[1]         ; 12.333 ; 12.333 ; 12.333 ; 12.333 ;
; LDSn         ; CD[2]         ; 12.018 ; 12.018 ; 12.018 ; 12.018 ;
; LDSn         ; CD[3]         ; 13.557 ; 13.557 ; 13.557 ; 13.557 ;
; LDSn         ; CD[4]         ; 13.426 ; 13.426 ; 13.426 ; 13.426 ;
; LDSn         ; CD[5]         ; 13.674 ; 13.674 ; 13.674 ; 13.674 ;
; LDSn         ; CD[6]         ; 13.606 ; 13.606 ; 13.606 ; 13.606 ;
; LDSn         ; CD[7]         ; 12.118 ; 12.118 ; 12.118 ; 12.118 ;
; LDSn         ; DATA[0]       ; 13.364 ; 12.971 ; 12.971 ; 13.364 ;
; LDSn         ; DATA[1]       ; 14.493 ; 13.890 ; 13.890 ; 14.493 ;
; LDSn         ; DATA[2]       ; 13.512 ; 13.000 ; 13.000 ; 13.512 ;
; LDSn         ; DATA[3]       ; 13.546 ; 13.259 ; 13.259 ; 13.546 ;
; LDSn         ; DATA[4]       ; 13.094 ; 12.838 ; 12.838 ; 13.094 ;
; LDSn         ; DATA[5]       ; 14.332 ; 13.890 ; 13.890 ; 14.332 ;
; LDSn         ; DATA[6]       ; 13.747 ; 13.414 ; 13.414 ; 13.747 ;
; LDSn         ; DATA[7]       ; 14.456 ; 14.153 ; 14.153 ; 14.456 ;
; LDSn         ; DATA[8]       ; 14.498 ; 13.827 ; 13.827 ; 14.498 ;
; LDSn         ; DATA[9]       ; 14.492 ; 13.855 ; 13.855 ; 14.492 ;
; LDSn         ; DATA[10]      ; 13.451 ; 12.981 ; 12.981 ; 13.451 ;
; LDSn         ; DATA[11]      ; 14.603 ; 13.726 ; 13.726 ; 14.603 ;
; LDSn         ; DATA[12]      ; 13.754 ; 13.652 ; 13.652 ; 13.754 ;
; LDSn         ; DATA[13]      ; 13.788 ; 13.226 ; 13.226 ; 13.788 ;
; LDSn         ; DATA[14]      ; 13.647 ; 12.914 ; 12.914 ; 13.647 ;
; LDSn         ; DATA[15]      ; 13.964 ; 13.316 ; 13.316 ; 13.964 ;
; LDSn         ; DTACKn        ; 11.002 ; 11.002 ; 11.002 ; 11.002 ;
; LDSn         ; IDE_IORDn     ; 7.507  ;        ;        ; 7.507  ;
; LDSn         ; IDE_IOWRn     ; 7.365  ;        ;        ; 7.365  ;
; LDSn         ; JOY_RLn       ; 6.633  ;        ;        ; 6.633  ;
; LDSn         ; JOY_WEn       ;        ; 6.487  ; 6.487  ;        ;
; LDSn         ; JOY_WL        ;        ; 6.291  ; 6.291  ;        ;
; LDSn         ; RAM_CAS0n     ; 8.069  ;        ;        ; 8.069  ;
; LDSn         ; RAM_DATA[0]   ; 13.895 ; 13.502 ; 13.502 ; 13.895 ;
; LDSn         ; RAM_DATA[1]   ; 14.863 ; 14.260 ; 14.260 ; 14.863 ;
; LDSn         ; RAM_DATA[2]   ; 13.864 ; 13.352 ; 13.352 ; 13.864 ;
; LDSn         ; RAM_DATA[3]   ; 14.525 ; 14.238 ; 14.238 ; 14.525 ;
; LDSn         ; RAM_DATA[4]   ; 13.976 ; 13.720 ; 13.720 ; 13.976 ;
; LDSn         ; RAM_DATA[5]   ; 14.983 ; 14.541 ; 14.541 ; 14.983 ;
; LDSn         ; RAM_DATA[6]   ; 14.119 ; 13.786 ; 13.786 ; 14.119 ;
; LDSn         ; RAM_DATA[7]   ; 14.744 ; 14.441 ; 14.441 ; 14.744 ;
; LDSn         ; RAM_DATA[8]   ; 14.671 ; 14.000 ; 14.000 ; 14.671 ;
; LDSn         ; RAM_DATA[9]   ; 14.650 ; 14.013 ; 14.013 ; 14.650 ;
; LDSn         ; RAM_DATA[10]  ; 14.047 ; 13.577 ; 13.577 ; 14.047 ;
; LDSn         ; RAM_DATA[11]  ; 14.307 ; 13.430 ; 13.430 ; 14.307 ;
; LDSn         ; RAM_DATA[12]  ; 13.588 ; 13.486 ; 13.486 ; 13.588 ;
; LDSn         ; RAM_DATA[13]  ; 14.540 ; 13.978 ; 13.978 ; 14.540 ;
; LDSn         ; RAM_DATA[14]  ; 14.516 ; 13.783 ; 13.783 ; 14.516 ;
; LDSn         ; RAM_DATA[15]  ; 14.633 ; 13.985 ; 13.985 ; 14.633 ;
; LDSn         ; RAM_DQM0L     ; 7.228  ;        ;        ; 7.228  ;
; LPT_BSY      ; DATA[0]       ; 10.497 ;        ;        ; 10.497 ;
; LPT_BSY      ; RAM_DATA[0]   ; 11.028 ;        ;        ; 11.028 ;
; LPT_D[0]     ; DATA[8]       ; 9.949  ;        ;        ; 9.949  ;
; LPT_D[0]     ; RAM_DATA[8]   ; 10.122 ;        ;        ; 10.122 ;
; LPT_D[1]     ; DATA[9]       ; 10.070 ;        ;        ; 10.070 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 10.228 ;        ;        ; 10.228 ;
; LPT_D[2]     ; DATA[10]      ; 9.155  ;        ;        ; 9.155  ;
; LPT_D[2]     ; RAM_DATA[10]  ; 9.751  ;        ;        ; 9.751  ;
; LPT_D[3]     ; DATA[11]      ; 9.686  ;        ;        ; 9.686  ;
; LPT_D[3]     ; RAM_DATA[11]  ; 9.390  ;        ;        ; 9.390  ;
; LPT_D[4]     ; DATA[12]      ; 9.820  ;        ;        ; 9.820  ;
; LPT_D[4]     ; RAM_DATA[12]  ; 9.654  ;        ;        ; 9.654  ;
; LPT_D[5]     ; DATA[13]      ; 9.421  ;        ;        ; 9.421  ;
; LPT_D[5]     ; RAM_DATA[13]  ; 10.173 ;        ;        ; 10.173 ;
; LPT_D[6]     ; DATA[14]      ; 8.850  ;        ;        ; 8.850  ;
; LPT_D[6]     ; RAM_DATA[14]  ; 9.719  ;        ;        ; 9.719  ;
; LPT_D[7]     ; DATA[15]      ; 9.646  ;        ;        ; 9.646  ;
; LPT_D[7]     ; RAM_DATA[15]  ; 10.315 ;        ;        ; 10.315 ;
; MIDI_IN      ; MIDI_TLR      ; 4.720  ;        ;        ; 4.720  ;
; RAM_DATA[0]  ; DATA[0]       ; 9.768  ;        ;        ; 9.768  ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 10.299 ;        ;        ; 10.299 ;
; RAM_DATA[1]  ; DATA[1]       ; 9.997  ;        ;        ; 9.997  ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 10.367 ;        ;        ; 10.367 ;
; RAM_DATA[2]  ; DATA[2]       ; 9.687  ;        ;        ; 9.687  ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 10.039 ;        ;        ; 10.039 ;
; RAM_DATA[3]  ; DATA[3]       ; 9.494  ;        ;        ; 9.494  ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 10.473 ;        ;        ; 10.473 ;
; RAM_DATA[4]  ; DATA[4]       ; 9.496  ;        ;        ; 9.496  ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 10.378 ;        ;        ; 10.378 ;
; RAM_DATA[5]  ; DATA[5]       ; 10.737 ;        ;        ; 10.737 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 11.388 ;        ;        ; 11.388 ;
; RAM_DATA[6]  ; DATA[6]       ; 11.236 ;        ;        ; 11.236 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 11.608 ;        ;        ; 11.608 ;
; RAM_DATA[7]  ; DATA[7]       ; 10.711 ;        ;        ; 10.711 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 10.999 ;        ;        ; 10.999 ;
; RAM_DATA[8]  ; DATA[8]       ; 10.341 ;        ;        ; 10.341 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 10.514 ;        ;        ; 10.514 ;
; RAM_DATA[9]  ; DATA[9]       ; 11.037 ;        ;        ; 11.037 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 11.195 ;        ;        ; 11.195 ;
; RAM_DATA[10] ; DATA[10]      ; 9.557  ;        ;        ; 9.557  ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 10.153 ;        ;        ; 10.153 ;
; RAM_DATA[11] ; DATA[11]      ; 10.789 ;        ;        ; 10.789 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 10.493 ;        ;        ; 10.493 ;
; RAM_DATA[12] ; DATA[12]      ; 9.954  ;        ;        ; 9.954  ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 9.788  ;        ;        ; 9.788  ;
; RAM_DATA[13] ; DATA[13]      ; 9.639  ;        ;        ; 9.639  ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 10.391 ;        ;        ; 10.391 ;
; RAM_DATA[14] ; DATA[14]      ; 9.600  ;        ;        ; 9.600  ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 10.469 ;        ;        ; 10.469 ;
; RAM_DATA[15] ; DATA[15]      ; 10.294 ;        ;        ; 10.294 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 10.963 ;        ;        ; 10.963 ;
; RWn          ; ACSI_RDn      ; 9.211  ; 9.211  ; 9.211  ; 9.211  ;
; RWn          ; ACSI_WRn      ; 9.214  ; 9.214  ; 9.214  ; 9.214  ;
; RWn          ; BUTTONn       ;        ; 7.901  ; 7.901  ;        ;
; RWn          ; CA1_OUT       ;        ; 8.868  ; 8.868  ;        ;
; RWn          ; CD[0]         ; 11.215 ; 11.215 ; 11.215 ; 11.215 ;
; RWn          ; CD[1]         ; 11.294 ; 11.294 ; 11.294 ; 11.294 ;
; RWn          ; CD[2]         ; 10.979 ; 10.979 ; 10.979 ; 10.979 ;
; RWn          ; CD[3]         ; 12.518 ; 12.518 ; 12.518 ; 12.518 ;
; RWn          ; CD[4]         ; 12.387 ; 12.387 ; 12.387 ; 12.387 ;
; RWn          ; CD[5]         ; 12.635 ; 12.635 ; 12.635 ; 12.635 ;
; RWn          ; CD[6]         ; 12.567 ; 12.567 ; 12.567 ; 12.567 ;
; RWn          ; CD[7]         ; 11.079 ; 11.079 ; 11.079 ; 11.079 ;
; RWn          ; DATA[0]       ; 13.015 ; 14.124 ; 14.124 ; 13.015 ;
; RWn          ; DATA[1]       ; 13.859 ; 14.709 ; 14.709 ; 13.859 ;
; RWn          ; DATA[2]       ; 12.969 ; 14.338 ; 14.338 ; 12.969 ;
; RWn          ; DATA[3]       ; 13.228 ; 13.642 ; 13.642 ; 13.228 ;
; RWn          ; DATA[4]       ; 12.840 ; 14.031 ; 14.031 ; 12.840 ;
; RWn          ; DATA[5]       ; 13.859 ; 14.749 ; 14.749 ; 13.859 ;
; RWn          ; DATA[6]       ; 13.383 ; 14.654 ; 14.654 ; 13.383 ;
; RWn          ; DATA[7]       ; 14.122 ; 14.870 ; 14.870 ; 14.122 ;
; RWn          ; DATA[8]       ; 14.733 ; 14.733 ; 14.733 ; 14.733 ;
; RWn          ; DATA[9]       ; 14.996 ; 14.996 ; 14.996 ; 14.996 ;
; RWn          ; DATA[10]      ; 13.995 ; 13.992 ; 13.992 ; 13.995 ;
; RWn          ; DATA[11]      ; 14.857 ; 14.883 ; 14.883 ; 14.857 ;
; RWn          ; DATA[12]      ; 15.147 ; 15.147 ; 15.147 ; 15.147 ;
; RWn          ; DATA[13]      ; 14.161 ; 14.113 ; 14.113 ; 14.161 ;
; RWn          ; DATA[14]      ; 13.842 ; 13.842 ; 13.842 ; 13.842 ;
; RWn          ; DATA[15]      ; 14.253 ; 14.194 ; 14.194 ; 14.253 ;
; RWn          ; DTACKn        ; 10.908 ; 10.908 ; 10.908 ; 10.908 ;
; RWn          ; FLASH_CEn     ;        ; 9.189  ; 9.189  ;        ;
; RWn          ; FLASH_OEn     ;        ; 8.885  ; 8.885  ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 7.107  ; 7.107  ;        ;
; RWn          ; IDE_D_EN_OUTn ; 7.372  ;        ;        ; 7.372  ;
; RWn          ; IDE_IORDn     ;        ; 7.214  ; 7.214  ;        ;
; RWn          ; IDE_IOWRn     ; 7.074  ;        ;        ; 7.074  ;
; RWn          ; JOY_RHn       ;        ; 8.177  ; 8.177  ;        ;
; RWn          ; JOY_RLn       ;        ; 8.316  ; 8.316  ;        ;
; RWn          ; JOY_WEn       ; 8.170  ;        ;        ; 8.170  ;
; RWn          ; JOY_WL        ; 8.197  ; 6.120  ; 6.120  ; 8.197  ;
; RWn          ; RAM_DATA[0]   ; 13.546 ; 14.655 ; 14.655 ; 13.546 ;
; RWn          ; RAM_DATA[1]   ; 14.229 ; 15.079 ; 15.079 ; 14.229 ;
; RWn          ; RAM_DATA[2]   ; 13.321 ; 14.690 ; 14.690 ; 13.321 ;
; RWn          ; RAM_DATA[3]   ; 14.207 ; 14.621 ; 14.621 ; 14.207 ;
; RWn          ; RAM_DATA[4]   ; 13.722 ; 14.913 ; 14.913 ; 13.722 ;
; RWn          ; RAM_DATA[5]   ; 14.510 ; 15.400 ; 15.400 ; 14.510 ;
; RWn          ; RAM_DATA[6]   ; 13.755 ; 15.026 ; 15.026 ; 13.755 ;
; RWn          ; RAM_DATA[7]   ; 14.410 ; 15.158 ; 15.158 ; 14.410 ;
; RWn          ; RAM_DATA[8]   ; 14.906 ; 14.906 ; 14.906 ; 14.906 ;
; RWn          ; RAM_DATA[9]   ; 15.154 ; 15.154 ; 15.154 ; 15.154 ;
; RWn          ; RAM_DATA[10]  ; 14.591 ; 14.588 ; 14.588 ; 14.591 ;
; RWn          ; RAM_DATA[11]  ; 14.561 ; 14.587 ; 14.587 ; 14.561 ;
; RWn          ; RAM_DATA[12]  ; 14.981 ; 14.981 ; 14.981 ; 14.981 ;
; RWn          ; RAM_DATA[13]  ; 14.913 ; 14.865 ; 14.865 ; 14.913 ;
; RWn          ; RAM_DATA[14]  ; 14.711 ; 14.711 ; 14.711 ; 14.711 ;
; RWn          ; RAM_DATA[15]  ; 14.922 ; 14.863 ; 14.863 ; 14.922 ;
; RWn          ; RAM_WEn       ; 7.768  ;        ;        ; 7.768  ;
; RWn          ; ROM0n         ;        ; 7.578  ; 7.578  ;        ;
; RWn          ; ROM1n         ;        ; 7.467  ; 7.467  ;        ;
; RWn          ; ROM2n         ;        ; 8.242  ; 8.242  ;        ;
; RWn          ; ROM3n         ;        ; 7.300  ; 7.300  ;        ;
; RWn          ; ROM4n         ;        ; 7.358  ; 7.358  ;        ;
; RWn          ; ROM5n         ;        ; 8.272  ; 8.272  ;        ;
; RWn          ; ROM6n         ;        ; 8.254  ; 8.254  ;        ;
; SCSI_ACKn    ; CD[0]         ; 6.695  ; 6.695  ; 6.695  ; 6.695  ;
; SCSI_ATNn    ; CD[1]         ; 7.735  ; 7.735  ; 7.735  ; 7.735  ;
; SCSI_BSYn    ; CD[6]         ; 8.037  ; 8.037  ; 8.037  ; 8.037  ;
; SCSI_D[0]    ; CD[0]         ; 6.896  ; 6.896  ; 6.896  ; 6.896  ;
; SCSI_D[1]    ; CD[1]         ; 6.937  ; 6.937  ; 6.937  ; 6.937  ;
; SCSI_D[2]    ; CD[2]         ;        ; 6.348  ; 6.348  ;        ;
; SCSI_D[3]    ; CD[3]         ; 7.049  ; 7.049  ; 7.049  ; 7.049  ;
; SCSI_D[4]    ; CD[4]         ; 8.060  ; 8.060  ; 8.060  ; 8.060  ;
; SCSI_D[5]    ; CD[5]         ; 7.640  ; 7.640  ; 7.640  ; 7.640  ;
; SCSI_D[6]    ; CD[6]         ; 7.899  ; 7.899  ; 7.899  ; 7.899  ;
; SCSI_D[7]    ; CD[7]         ; 7.487  ; 7.487  ; 7.487  ; 7.487  ;
; SCSI_DCn     ; CD[3]         ; 8.522  ; 8.522  ; 8.522  ; 8.522  ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 8.297  ; 8.297  ; 8.297  ; 8.297  ;
; SCSI_DCn     ; SCSI_D[0]     ; 7.777  ; 7.777  ; 7.777  ; 7.777  ;
; SCSI_DCn     ; SCSI_D[1]     ; 7.777  ; 7.777  ; 7.777  ; 7.777  ;
; SCSI_DCn     ; SCSI_D[2]     ; 7.772  ; 7.772  ; 7.772  ; 7.772  ;
; SCSI_DCn     ; SCSI_D[3]     ; 7.772  ; 7.772  ; 7.772  ; 7.772  ;
; SCSI_DCn     ; SCSI_D[4]     ; 7.911  ; 7.911  ; 7.911  ; 7.911  ;
; SCSI_DCn     ; SCSI_D[5]     ; 7.911  ; 7.911  ; 7.911  ; 7.911  ;
; SCSI_DCn     ; SCSI_D[6]     ; 8.013  ; 8.013  ; 8.013  ; 8.013  ;
; SCSI_DCn     ; SCSI_D[7]     ; 8.013  ; 8.013  ; 8.013  ; 8.013  ;
; SCSI_DCn     ; SCSI_DP       ; 7.787  ; 7.787  ; 7.787  ; 7.787  ;
; SCSI_DP      ; CD[0]         ; 6.773  ; 6.773  ; 6.773  ; 6.773  ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 5.999  ; 5.999  ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 6.007  ;        ;        ; 6.007  ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 6.001  ; 6.001  ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 6.111  ;        ;        ; 6.111  ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 6.329  ; 6.329  ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 6.306  ;        ;        ; 6.306  ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 6.481  ; 6.481  ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 6.226  ;        ;        ; 6.226  ;
; SCSI_IDn[1]  ; SCSI_DP       ; 6.978  ; 6.978  ; 6.978  ; 6.978  ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 5.849  ; 5.849  ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 5.888  ; 5.888  ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 5.843  ;        ;        ; 5.843  ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 5.980  ;        ;        ; 5.980  ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 6.189  ; 6.189  ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 6.190  ; 6.190  ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 6.340  ;        ;        ; 6.340  ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 6.097  ;        ;        ; 6.097  ;
; SCSI_IDn[2]  ; SCSI_DP       ; 6.847  ; 6.847  ; 6.847  ; 6.847  ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 6.047  ; 6.047  ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 6.083  ; 6.083  ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 6.046  ; 6.046  ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 6.181  ; 6.181  ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 6.376  ;        ;        ; 6.376  ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 6.377  ;        ;        ; 6.377  ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 6.529  ;        ;        ; 6.529  ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 6.296  ;        ;        ; 6.296  ;
; SCSI_IDn[3]  ; SCSI_DP       ; 7.048  ; 7.048  ; 7.048  ; 7.048  ;
; SCSI_IOn     ; CD[2]         ;        ; 7.258  ; 7.258  ;        ;
; SCSI_IOn     ; CD[3]         ; 8.461  ; 8.461  ; 8.461  ; 8.461  ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 8.236  ; 8.236  ; 8.236  ; 8.236  ;
; SCSI_IOn     ; SCSI_D[0]     ; 7.716  ; 7.716  ; 7.716  ; 7.716  ;
; SCSI_IOn     ; SCSI_D[1]     ; 7.716  ; 7.716  ; 7.716  ; 7.716  ;
; SCSI_IOn     ; SCSI_D[2]     ; 7.711  ; 7.711  ; 7.711  ; 7.711  ;
; SCSI_IOn     ; SCSI_D[3]     ; 7.711  ; 7.711  ; 7.711  ; 7.711  ;
; SCSI_IOn     ; SCSI_D[4]     ; 7.850  ; 7.850  ; 7.850  ; 7.850  ;
; SCSI_IOn     ; SCSI_D[5]     ; 7.850  ; 7.850  ; 7.850  ; 7.850  ;
; SCSI_IOn     ; SCSI_D[6]     ; 7.952  ; 7.952  ; 7.952  ; 7.952  ;
; SCSI_IOn     ; SCSI_D[7]     ; 7.952  ; 7.952  ; 7.952  ; 7.952  ;
; SCSI_IOn     ; SCSI_DP       ; 7.726  ; 7.726  ; 7.726  ; 7.726  ;
; SCSI_IOn     ; SCSI_RDn      ; 7.112  ;        ;        ; 7.112  ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 6.793  ; 6.793  ;        ;
; SCSI_MSGn    ; CD[3]         ; 8.150  ; 8.150  ; 8.150  ; 8.150  ;
; SCSI_MSGn    ; CD[4]         ; 8.042  ; 8.042  ; 8.042  ; 8.042  ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 7.925  ; 7.925  ; 7.925  ; 7.925  ;
; SCSI_MSGn    ; SCSI_D[0]     ; 7.405  ; 7.405  ; 7.405  ; 7.405  ;
; SCSI_MSGn    ; SCSI_D[1]     ; 7.405  ; 7.405  ; 7.405  ; 7.405  ;
; SCSI_MSGn    ; SCSI_D[2]     ; 7.400  ; 7.400  ; 7.400  ; 7.400  ;
; SCSI_MSGn    ; SCSI_D[3]     ; 7.400  ; 7.400  ; 7.400  ; 7.400  ;
; SCSI_MSGn    ; SCSI_D[4]     ; 7.539  ; 7.539  ; 7.539  ; 7.539  ;
; SCSI_MSGn    ; SCSI_D[5]     ; 7.539  ; 7.539  ; 7.539  ; 7.539  ;
; SCSI_MSGn    ; SCSI_D[6]     ; 7.641  ; 7.641  ; 7.641  ; 7.641  ;
; SCSI_MSGn    ; SCSI_D[7]     ; 7.641  ; 7.641  ; 7.641  ; 7.641  ;
; SCSI_MSGn    ; SCSI_DP       ; 7.415  ; 7.415  ; 7.415  ; 7.415  ;
; SCSI_REQn    ; CD[3]         ; 8.296  ; 8.296  ; 8.296  ; 8.296  ;
; SCSI_REQn    ; CD[5]         ; 7.860  ; 7.860  ; 7.860  ; 7.860  ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 8.071  ;        ;        ; 8.071  ;
; SCSI_REQn    ; SCSI_D[0]     ; 7.551  ; 7.551  ; 7.551  ; 7.551  ;
; SCSI_REQn    ; SCSI_D[1]     ; 7.551  ; 7.551  ; 7.551  ; 7.551  ;
; SCSI_REQn    ; SCSI_D[2]     ; 7.546  ; 7.546  ; 7.546  ; 7.546  ;
; SCSI_REQn    ; SCSI_D[3]     ; 7.546  ; 7.546  ; 7.546  ; 7.546  ;
; SCSI_REQn    ; SCSI_D[4]     ; 7.685  ; 7.685  ; 7.685  ; 7.685  ;
; SCSI_REQn    ; SCSI_D[5]     ; 7.685  ; 7.685  ; 7.685  ; 7.685  ;
; SCSI_REQn    ; SCSI_D[6]     ; 7.787  ; 7.787  ; 7.787  ; 7.787  ;
; SCSI_REQn    ; SCSI_D[7]     ; 7.787  ; 7.787  ; 7.787  ; 7.787  ;
; SCSI_REQn    ; SCSI_DP       ; 7.561  ; 7.561  ; 7.561  ; 7.561  ;
; SCSI_RSTn    ; CD[7]         ;        ; 7.782  ; 7.782  ;        ;
; SCSI_SELn    ; CD[1]         ; 7.053  ; 7.053  ; 7.053  ; 7.053  ;
; SD_AVR_ENn   ; RESETn        ;        ; 7.768  ; 7.768  ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 6.883  ; 6.883  ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 7.766  ; 7.766  ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 6.633  ;        ;        ; 6.633  ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 6.693  ;        ;        ; 6.693  ;
; SD_RESETn    ; ACSI_RDn      ; 9.235  ; 9.235  ; 9.235  ; 9.235  ;
; SD_RESETn    ; ACSI_WRn      ; 9.238  ; 9.238  ; 9.238  ; 9.238  ;
; SD_RESETn    ; CA1_OUT       ; 8.892  ;        ;        ; 8.892  ;
; SD_RESETn    ; CD[0]         ; 11.239 ; 11.239 ; 11.239 ; 11.239 ;
; SD_RESETn    ; CD[1]         ; 11.318 ; 11.318 ; 11.318 ; 11.318 ;
; SD_RESETn    ; CD[2]         ; 11.003 ; 11.003 ; 11.003 ; 11.003 ;
; SD_RESETn    ; CD[3]         ; 12.542 ; 12.542 ; 12.542 ; 12.542 ;
; SD_RESETn    ; CD[4]         ; 12.411 ; 12.411 ; 12.411 ; 12.411 ;
; SD_RESETn    ; CD[5]         ; 12.659 ; 12.659 ; 12.659 ; 12.659 ;
; SD_RESETn    ; CD[6]         ; 12.591 ; 12.591 ; 12.591 ; 12.591 ;
; SD_RESETn    ; CD[7]         ; 11.103 ; 11.103 ; 11.103 ; 11.103 ;
; SD_RESETn    ; COM_TxD       ; 9.751  ; 9.751  ; 9.751  ; 9.751  ;
; SD_RESETn    ; DATA[0]       ; 12.123 ; 12.194 ; 12.194 ; 12.123 ;
; SD_RESETn    ; DATA[1]       ; 12.597 ; 12.597 ; 12.597 ; 12.597 ;
; SD_RESETn    ; DATA[2]       ; 12.160 ; 12.160 ; 12.160 ; 12.160 ;
; SD_RESETn    ; DATA[3]       ; 11.927 ; 11.921 ; 11.921 ; 11.927 ;
; SD_RESETn    ; DATA[4]       ; 11.949 ; 12.065 ; 12.065 ; 11.949 ;
; SD_RESETn    ; DATA[5]       ; 12.803 ; 12.766 ; 12.766 ; 12.803 ;
; SD_RESETn    ; DATA[6]       ; 12.553 ; 12.491 ; 12.491 ; 12.553 ;
; SD_RESETn    ; DATA[7]       ; 12.661 ; 12.664 ; 12.664 ; 12.661 ;
; SD_RESETn    ; DATA[8]       ; 10.904 ; 11.541 ; 11.541 ; 10.904 ;
; SD_RESETn    ; DATA[9]       ; 11.863 ; 12.026 ; 12.026 ; 11.863 ;
; SD_RESETn    ; DATA[10]      ; 9.752  ; 10.993 ; 10.993 ; 9.752  ;
; SD_RESETn    ; DATA[11]      ; 11.765 ; 12.141 ; 12.141 ; 11.765 ;
; SD_RESETn    ; DATA[12]      ; 11.657 ; 12.174 ; 12.174 ; 11.657 ;
; SD_RESETn    ; DATA[13]      ; 10.541 ; 11.402 ; 11.402 ; 10.541 ;
; SD_RESETn    ; DATA[14]      ; 10.137 ; 10.918 ; 10.918 ; 10.137 ;
; SD_RESETn    ; DATA[15]      ; 10.492 ; 11.197 ; 11.197 ; 10.492 ;
; SD_RESETn    ; DTACKn        ; 9.987  ; 9.987  ; 9.987  ; 9.987  ;
; SD_RESETn    ; RAM_DATA[0]   ; 12.654 ; 12.725 ; 12.725 ; 12.654 ;
; SD_RESETn    ; RAM_DATA[1]   ; 12.967 ; 12.967 ; 12.967 ; 12.967 ;
; SD_RESETn    ; RAM_DATA[2]   ; 12.512 ; 12.512 ; 12.512 ; 12.512 ;
; SD_RESETn    ; RAM_DATA[3]   ; 12.906 ; 12.900 ; 12.900 ; 12.906 ;
; SD_RESETn    ; RAM_DATA[4]   ; 12.831 ; 12.947 ; 12.947 ; 12.831 ;
; SD_RESETn    ; RAM_DATA[5]   ; 13.454 ; 13.417 ; 13.417 ; 13.454 ;
; SD_RESETn    ; RAM_DATA[6]   ; 12.925 ; 12.863 ; 12.863 ; 12.925 ;
; SD_RESETn    ; RAM_DATA[7]   ; 12.949 ; 12.952 ; 12.952 ; 12.949 ;
; SD_RESETn    ; RAM_DATA[8]   ; 11.077 ; 11.714 ; 11.714 ; 11.077 ;
; SD_RESETn    ; RAM_DATA[9]   ; 12.021 ; 12.184 ; 12.184 ; 12.021 ;
; SD_RESETn    ; RAM_DATA[10]  ; 10.348 ; 11.589 ; 11.589 ; 10.348 ;
; SD_RESETn    ; RAM_DATA[11]  ; 11.469 ; 11.845 ; 11.845 ; 11.469 ;
; SD_RESETn    ; RAM_DATA[12]  ; 11.491 ; 12.008 ; 12.008 ; 11.491 ;
; SD_RESETn    ; RAM_DATA[13]  ; 11.293 ; 12.154 ; 12.154 ; 11.293 ;
; SD_RESETn    ; RAM_DATA[14]  ; 11.006 ; 11.787 ; 11.787 ; 11.006 ;
; SD_RESETn    ; RAM_DATA[15]  ; 11.161 ; 11.866 ; 11.866 ; 11.161 ;
; UDSn         ; ACSI_RDn      ; 9.252  ; 9.252  ; 9.252  ; 9.252  ;
; UDSn         ; ACSI_WRn      ; 9.255  ; 9.255  ; 9.255  ; 9.255  ;
; UDSn         ; CA1_OUT       ; 8.909  ;        ;        ; 8.909  ;
; UDSn         ; CD[0]         ; 11.256 ; 11.256 ; 11.256 ; 11.256 ;
; UDSn         ; CD[1]         ; 11.335 ; 11.335 ; 11.335 ; 11.335 ;
; UDSn         ; CD[2]         ; 11.020 ; 11.020 ; 11.020 ; 11.020 ;
; UDSn         ; CD[3]         ; 12.559 ; 12.559 ; 12.559 ; 12.559 ;
; UDSn         ; CD[4]         ; 12.428 ; 12.428 ; 12.428 ; 12.428 ;
; UDSn         ; CD[5]         ; 12.676 ; 12.676 ; 12.676 ; 12.676 ;
; UDSn         ; CD[6]         ; 12.608 ; 12.608 ; 12.608 ; 12.608 ;
; UDSn         ; CD[7]         ; 11.120 ; 11.120 ; 11.120 ; 11.120 ;
; UDSn         ; DATA[0]       ; 12.817 ; 13.187 ; 13.187 ; 12.817 ;
; UDSn         ; DATA[1]       ; 13.946 ; 13.772 ; 13.772 ; 13.946 ;
; UDSn         ; DATA[2]       ; 12.965 ; 13.401 ; 13.401 ; 12.965 ;
; UDSn         ; DATA[3]       ; 12.999 ; 12.712 ; 12.712 ; 12.999 ;
; UDSn         ; DATA[4]       ; 12.547 ; 13.094 ; 13.094 ; 12.547 ;
; UDSn         ; DATA[5]       ; 13.785 ; 13.812 ; 13.812 ; 13.785 ;
; UDSn         ; DATA[6]       ; 13.200 ; 13.717 ; 13.717 ; 13.200 ;
; UDSn         ; DATA[7]       ; 13.909 ; 13.933 ; 13.933 ; 13.909 ;
; UDSn         ; DATA[8]       ; 13.951 ; 13.796 ; 13.796 ; 13.951 ;
; UDSn         ; DATA[9]       ; 14.059 ; 14.059 ; 14.059 ; 14.059 ;
; UDSn         ; DATA[10]      ; 13.058 ; 13.055 ; 13.055 ; 13.058 ;
; UDSn         ; DATA[11]      ; 14.056 ; 13.946 ; 13.946 ; 14.056 ;
; UDSn         ; DATA[12]      ; 14.210 ; 14.210 ; 14.210 ; 14.210 ;
; UDSn         ; DATA[13]      ; 13.241 ; 13.176 ; 13.176 ; 13.241 ;
; UDSn         ; DATA[14]      ; 13.100 ; 12.905 ; 12.905 ; 13.100 ;
; UDSn         ; DATA[15]      ; 13.417 ; 13.257 ; 13.257 ; 13.417 ;
; UDSn         ; DTACKn        ; 10.004 ; 10.004 ; 10.004 ; 10.004 ;
; UDSn         ; JOY_RHn       ; 7.191  ;        ;        ; 7.191  ;
; UDSn         ; RAM_CAS0n     ; 7.834  ;        ;        ; 7.834  ;
; UDSn         ; RAM_DATA[0]   ; 13.348 ; 13.718 ; 13.718 ; 13.348 ;
; UDSn         ; RAM_DATA[1]   ; 14.316 ; 14.142 ; 14.142 ; 14.316 ;
; UDSn         ; RAM_DATA[2]   ; 13.317 ; 13.753 ; 13.753 ; 13.317 ;
; UDSn         ; RAM_DATA[3]   ; 13.978 ; 13.691 ; 13.691 ; 13.978 ;
; UDSn         ; RAM_DATA[4]   ; 13.429 ; 13.976 ; 13.976 ; 13.429 ;
; UDSn         ; RAM_DATA[5]   ; 14.436 ; 14.463 ; 14.463 ; 14.436 ;
; UDSn         ; RAM_DATA[6]   ; 13.572 ; 14.089 ; 14.089 ; 13.572 ;
; UDSn         ; RAM_DATA[7]   ; 14.197 ; 14.221 ; 14.221 ; 14.197 ;
; UDSn         ; RAM_DATA[8]   ; 14.124 ; 13.969 ; 13.969 ; 14.124 ;
; UDSn         ; RAM_DATA[9]   ; 14.217 ; 14.217 ; 14.217 ; 14.217 ;
; UDSn         ; RAM_DATA[10]  ; 13.654 ; 13.651 ; 13.651 ; 13.654 ;
; UDSn         ; RAM_DATA[11]  ; 13.760 ; 13.650 ; 13.650 ; 13.760 ;
; UDSn         ; RAM_DATA[12]  ; 14.044 ; 14.044 ; 14.044 ; 14.044 ;
; UDSn         ; RAM_DATA[13]  ; 13.993 ; 13.928 ; 13.928 ; 13.993 ;
; UDSn         ; RAM_DATA[14]  ; 13.969 ; 13.774 ; 13.774 ; 13.969 ;
; UDSn         ; RAM_DATA[15]  ; 14.086 ; 13.926 ; 13.926 ; 14.086 ;
; UDSn         ; RAM_DQM0H     ; 7.273  ;        ;        ; 7.273  ;
+--------------+---------------+--------+--------+--------+--------+


+------------------------------------------------------------------+
; Minimum Propagation Delay                                        ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 9.546  ; 9.546  ; 9.546  ; 9.546  ;
; ASn          ; ACSI_WRn      ; 9.550  ; 9.550  ; 9.550  ; 9.550  ;
; ASn          ; BUTTONn       ; 9.679  ;        ;        ; 9.679  ;
; ASn          ; CA1_OUT       ; 9.234  ;        ;        ; 9.234  ;
; ASn          ; CD[0]         ; 10.086 ; 10.043 ; 10.043 ; 10.086 ;
; ASn          ; CD[1]         ; 10.008 ; 9.965  ; 9.965  ; 10.008 ;
; ASn          ; CD[2]         ; 9.261  ; 9.261  ; 9.261  ; 9.261  ;
; ASn          ; CD[3]         ; 10.177 ; 10.036 ; 10.036 ; 10.177 ;
; ASn          ; CD[4]         ; 9.530  ; 9.530  ; 9.530  ; 9.530  ;
; ASn          ; CD[5]         ; 9.522  ; 9.522  ; 9.522  ; 9.522  ;
; ASn          ; CD[6]         ; 9.672  ; 9.672  ; 9.672  ; 9.672  ;
; ASn          ; CD[7]         ; 9.366  ; 9.366  ; 9.366  ; 9.366  ;
; ASn          ; DATA[0]       ; 9.125  ; 9.125  ; 9.125  ; 9.125  ;
; ASn          ; DATA[1]       ; 9.125  ; 9.125  ; 9.125  ; 9.125  ;
; ASn          ; DATA[2]       ; 8.977  ; 8.977  ; 8.977  ; 8.977  ;
; ASn          ; DATA[3]       ; 8.977  ; 8.977  ; 8.977  ; 8.977  ;
; ASn          ; DATA[4]       ; 8.998  ; 8.998  ; 8.998  ; 8.998  ;
; ASn          ; DATA[5]       ; 8.998  ; 8.998  ; 8.998  ; 8.998  ;
; ASn          ; DATA[6]       ; 8.836  ; 8.836  ; 8.836  ; 8.836  ;
; ASn          ; DATA[7]       ; 8.826  ; 8.826  ; 8.826  ; 8.826  ;
; ASn          ; DATA[8]       ; 8.953  ; 8.953  ; 8.953  ; 8.953  ;
; ASn          ; DATA[9]       ; 8.953  ; 8.953  ; 8.953  ; 8.953  ;
; ASn          ; DATA[10]      ; 9.090  ; 9.090  ; 9.090  ; 9.090  ;
; ASn          ; DATA[11]      ; 9.090  ; 9.090  ; 9.090  ; 9.090  ;
; ASn          ; DATA[12]      ; 9.133  ; 9.133  ; 9.133  ; 9.133  ;
; ASn          ; DATA[13]      ; 9.133  ; 9.133  ; 9.133  ; 9.133  ;
; ASn          ; DATA[14]      ; 9.105  ; 9.105  ; 9.105  ; 9.105  ;
; ASn          ; DATA[15]      ; 9.095  ; 9.095  ; 9.095  ; 9.095  ;
; ASn          ; DTACKn        ; 7.691  ; 7.691  ; 7.691  ; 7.691  ;
; ASn          ; FLASH_CEn     ; 9.382  ;        ;        ; 9.382  ;
; ASn          ; FLASH_OEn     ; 9.078  ;        ;        ; 9.078  ;
; ASn          ; IDE_CS0n      ; 6.810  ;        ;        ; 6.810  ;
; ASn          ; IDE_CS1n      ; 6.389  ;        ;        ; 6.389  ;
; ASn          ; IDE_D_EN_INn  ; 7.079  ;        ;        ; 7.079  ;
; ASn          ; IDE_D_EN_OUTn ; 7.793  ;        ;        ; 7.793  ;
; ASn          ; IDE_IORDn     ; 7.636  ;        ;        ; 7.636  ;
; ASn          ; IDE_IOWRn     ; 7.494  ;        ;        ; 7.494  ;
; ASn          ; JOY_RHn       ; 7.135  ;        ;        ; 7.135  ;
; ASn          ; JOY_RLn       ; 7.274  ;        ;        ; 7.274  ;
; ASn          ; JOY_WEn       ;        ; 7.128  ; 7.128  ;        ;
; ASn          ; JOY_WL        ;        ; 7.155  ; 7.155  ;        ;
; ASn          ; RAM_DATA[0]   ; 10.434 ; 10.579 ; 10.579 ; 10.434 ;
; ASn          ; RAM_DATA[1]   ; 10.823 ; 10.820 ; 10.820 ; 10.823 ;
; ASn          ; RAM_DATA[2]   ; 10.335 ; 10.393 ; 10.393 ; 10.335 ;
; ASn          ; RAM_DATA[3]   ; 10.755 ; 10.805 ; 10.805 ; 10.755 ;
; ASn          ; RAM_DATA[4]   ; 10.726 ; 10.889 ; 10.889 ; 10.726 ;
; ASn          ; RAM_DATA[5]   ; 11.293 ; 11.196 ; 11.196 ; 11.293 ;
; ASn          ; RAM_DATA[6]   ; 10.507 ; 11.004 ; 11.004 ; 10.507 ;
; ASn          ; RAM_DATA[7]   ; 10.955 ; 11.216 ; 11.216 ; 10.955 ;
; ASn          ; RAM_DATA[8]   ; 10.298 ; 10.651 ; 10.651 ; 10.298 ;
; ASn          ; RAM_DATA[9]   ; 10.624 ; 10.868 ; 10.868 ; 10.624 ;
; ASn          ; RAM_DATA[10]  ; 10.191 ; 10.238 ; 10.238 ; 10.191 ;
; ASn          ; RAM_DATA[11]  ; 9.990  ; 10.197 ; 10.197 ; 9.990  ;
; ASn          ; RAM_DATA[12]  ; 10.072 ; 10.072 ; 10.072 ; 10.072 ;
; ASn          ; RAM_DATA[13]  ; 10.788 ; 10.925 ; 10.925 ; 10.788 ;
; ASn          ; RAM_DATA[14]  ; 10.503 ; 10.503 ; 10.503 ; 10.503 ;
; ASn          ; RAM_DATA[15]  ; 10.703 ; 10.641 ; 10.641 ; 10.703 ;
; ASn          ; ROM0n         ; 7.771  ;        ;        ; 7.771  ;
; ASn          ; ROM1n         ; 7.660  ;        ;        ; 7.660  ;
; ASn          ; ROM2n         ; 8.435  ;        ;        ; 8.435  ;
; ASn          ; ROM3n         ; 7.493  ;        ;        ; 7.493  ;
; ASn          ; ROM4n         ; 7.551  ;        ;        ; 7.551  ;
; ASn          ; ROM5n         ; 8.465  ;        ;        ; 8.465  ;
; ASn          ; ROM6n         ; 8.447  ;        ;        ; 8.447  ;
; COM_CTS      ; DATA[2]       ;        ; 10.769 ; 10.769 ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 11.121 ; 11.121 ;        ;
; COM_DCD      ; DATA[1]       ;        ; 11.463 ; 11.463 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 11.833 ; 11.833 ;        ;
; COM_RI       ; DATA[6]       ;        ; 10.598 ; 10.598 ;        ;
; COM_RI       ; RAM_DATA[6]   ;        ; 10.970 ; 10.970 ;        ;
; CONFIG[1]    ; DATA[7]       ; 11.519 ; 11.519 ; 11.519 ; 11.519 ;
; CONFIG[1]    ; HSYNC         ; 6.269  ; 6.269  ; 6.269  ; 6.269  ;
; CONFIG[1]    ; RAM_DATA[7]   ; 11.807 ; 11.807 ; 11.807 ; 11.807 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 7.504  ; 7.375  ; 7.375  ; 7.504  ;
; CONFIG[1]    ; RAM_DATA[13]  ; 7.750  ; 7.847  ; 7.847  ; 7.750  ;
; CONFIG[1]    ; RAM_DATA[14]  ; 7.556  ; 7.488  ; 7.488  ; 7.556  ;
; CONFIG[1]    ; RAM_DATA[15]  ; 7.269  ; 7.384  ; 7.384  ; 7.269  ;
; CONFIG[1]    ; VSYNC         ; 6.125  ; 6.125  ; 6.125  ; 6.125  ;
; CONFIG[2]    ; DATA[7]       ; 11.465 ; 11.465 ; 11.465 ; 11.465 ;
; CONFIG[2]    ; HSYNC         ; 6.183  ; 6.183  ; 6.183  ; 6.183  ;
; CONFIG[2]    ; RAM_DATA[7]   ; 11.753 ; 11.753 ; 11.753 ; 11.753 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 7.176  ; 7.305  ; 7.305  ; 7.176  ;
; CONFIG[2]    ; RAM_DATA[13]  ; 7.648  ; 7.551  ; 7.551  ; 7.648  ;
; CONFIG[2]    ; RAM_DATA[14]  ; 7.289  ; 7.357  ; 7.357  ; 7.289  ;
; CONFIG[2]    ; RAM_DATA[15]  ; 7.185  ; 7.070  ; 7.070  ; 7.185  ;
; CONFIG[2]    ; VSYNC         ; 6.051  ; 6.051  ; 6.051  ; 6.051  ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 8.454  ; 8.454  ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 7.432  ; 7.432  ;        ;
; CONFIG[6]    ; DATA[0]       ; 9.601  ; 9.601  ; 9.601  ; 9.601  ;
; CONFIG[6]    ; DATA[1]       ; 9.976  ; 9.976  ; 9.976  ; 9.976  ;
; CONFIG[6]    ; DATA[2]       ; 9.807  ; 9.807  ; 9.807  ; 9.807  ;
; CONFIG[6]    ; DATA[3]       ; 9.800  ; 9.927  ; 9.927  ; 9.800  ;
; CONFIG[6]    ; DATA[4]       ; 10.186 ; 10.059 ; 10.059 ; 10.186 ;
; CONFIG[6]    ; DATA[5]       ; 10.892 ; 10.765 ; 10.765 ; 10.892 ;
; CONFIG[6]    ; DATA[6]       ; 10.797 ; 10.670 ; 10.670 ; 10.797 ;
; CONFIG[6]    ; DATA[7]       ; 10.820 ; 10.693 ; 10.693 ; 10.820 ;
; CONFIG[6]    ; DATA[8]       ; 10.560 ; 10.687 ; 10.687 ; 10.560 ;
; CONFIG[6]    ; DATA[9]       ; 11.098 ; 11.150 ; 11.150 ; 11.098 ;
; CONFIG[6]    ; DATA[10]      ; 10.126 ; 9.999  ; 9.999  ; 10.126 ;
; CONFIG[6]    ; DATA[11]      ; 11.063 ; 11.009 ; 11.009 ; 11.063 ;
; CONFIG[6]    ; DATA[12]      ; 10.978 ; 10.851 ; 10.851 ; 10.978 ;
; CONFIG[6]    ; DATA[13]      ; 10.158 ; 10.031 ; 10.031 ; 10.158 ;
; CONFIG[6]    ; DATA[14]      ; 9.819  ; 9.858  ; 9.858  ; 9.819  ;
; CONFIG[6]    ; DATA[15]      ; 10.178 ; 10.051 ; 10.051 ; 10.178 ;
; CONFIG[6]    ; DTACKn        ; 8.581  ; 8.581  ; 8.581  ; 8.581  ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 7.744  ; 7.744  ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 7.835  ; 7.835  ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 8.608  ; 8.481  ; 8.481  ; 8.608  ;
; CONFIG[6]    ; FLASH_OEn     ; 8.304  ; 8.177  ; 8.177  ; 8.304  ;
; CONFIG[6]    ; RAM_DATA[0]   ; 10.132 ; 10.132 ; 10.132 ; 10.132 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 10.346 ; 10.346 ; 10.346 ; 10.346 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 10.159 ; 10.159 ; 10.159 ; 10.159 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 10.779 ; 10.906 ; 10.906 ; 10.779 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 11.068 ; 10.941 ; 10.941 ; 11.068 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 11.543 ; 11.416 ; 11.416 ; 11.543 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 11.169 ; 11.042 ; 11.042 ; 11.169 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 11.108 ; 10.981 ; 10.981 ; 11.108 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 10.733 ; 10.860 ; 10.860 ; 10.733 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 11.256 ; 11.308 ; 11.308 ; 11.256 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 10.722 ; 10.595 ; 10.595 ; 10.722 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 10.767 ; 10.713 ; 10.713 ; 10.767 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 10.812 ; 10.685 ; 10.685 ; 10.812 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 10.910 ; 10.783 ; 10.783 ; 10.910 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 10.688 ; 10.727 ; 10.727 ; 10.688 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 10.847 ; 10.720 ; 10.720 ; 10.847 ;
; CONFIG[6]    ; ROM2n         ; 7.661  ; 7.534  ; 7.534  ; 7.661  ;
; CRT_PIN3     ; DATA[7]       ; 9.516  ; 9.516  ; 9.516  ; 9.516  ;
; CRT_PIN3     ; RAM_DATA[7]   ; 9.804  ; 9.804  ; 9.804  ; 9.804  ;
; CRT_PIN3     ; RAM_DATA[12]  ; 5.526  ; 5.397  ; 5.397  ; 5.526  ;
; CRT_PIN3     ; RAM_DATA[13]  ; 5.772  ; 5.869  ; 5.869  ; 5.772  ;
; CRT_PIN3     ; RAM_DATA[14]  ; 5.578  ; 5.510  ; 5.510  ; 5.578  ;
; CRT_PIN3     ; RAM_DATA[15]  ; 5.291  ; 5.406  ; 5.406  ; 5.291  ;
; DATA[0]      ; DATA[0]       ; 7.673  ;        ;        ; 7.673  ;
; DATA[0]      ; RAM_DATA[0]   ; 8.204  ;        ;        ; 8.204  ;
; DATA[1]      ; DATA[1]       ; 8.503  ;        ;        ; 8.503  ;
; DATA[1]      ; RAM_DATA[1]   ; 8.873  ;        ;        ; 8.873  ;
; DATA[2]      ; DATA[2]       ; 8.076  ;        ;        ; 8.076  ;
; DATA[2]      ; RAM_DATA[2]   ; 8.428  ;        ;        ; 8.428  ;
; DATA[3]      ; DATA[3]       ; 7.803  ;        ;        ; 7.803  ;
; DATA[3]      ; RAM_DATA[3]   ; 8.782  ;        ;        ; 8.782  ;
; DATA[4]      ; DATA[4]       ; 7.696  ;        ;        ; 7.696  ;
; DATA[4]      ; RAM_DATA[4]   ; 8.578  ;        ;        ; 8.578  ;
; DATA[5]      ; DATA[5]       ; 8.477  ;        ;        ; 8.477  ;
; DATA[5]      ; RAM_DATA[5]   ; 9.128  ;        ;        ; 9.128  ;
; DATA[6]      ; DATA[6]       ; 8.435  ;        ;        ; 8.435  ;
; DATA[6]      ; RAM_DATA[6]   ; 8.807  ;        ;        ; 8.807  ;
; DATA[7]      ; DATA[7]       ; 8.410  ;        ;        ; 8.410  ;
; DATA[7]      ; RAM_DATA[7]   ; 8.698  ;        ;        ; 8.698  ;
; DATA[8]      ; DATA[8]       ; 8.125  ;        ;        ; 8.125  ;
; DATA[8]      ; RAM_DATA[8]   ; 8.298  ;        ;        ; 8.298  ;
; DATA[9]      ; DATA[9]       ; 8.826  ;        ;        ; 8.826  ;
; DATA[9]      ; RAM_DATA[9]   ; 8.984  ;        ;        ; 8.984  ;
; DATA[10]     ; DATA[10]      ; 7.664  ;        ;        ; 7.664  ;
; DATA[10]     ; RAM_DATA[10]  ; 8.260  ;        ;        ; 8.260  ;
; DATA[11]     ; DATA[11]      ; 8.793  ;        ;        ; 8.793  ;
; DATA[11]     ; RAM_DATA[11]  ; 8.497  ;        ;        ; 8.497  ;
; DATA[12]     ; DATA[12]      ; 8.458  ;        ;        ; 8.458  ;
; DATA[12]     ; RAM_DATA[12]  ; 8.292  ;        ;        ; 8.292  ;
; DATA[13]     ; DATA[13]      ; 7.589  ;        ;        ; 7.589  ;
; DATA[13]     ; RAM_DATA[13]  ; 8.341  ;        ;        ; 8.341  ;
; DATA[14]     ; DATA[14]      ; 7.276  ;        ;        ; 7.276  ;
; DATA[14]     ; RAM_DATA[14]  ; 8.145  ;        ;        ; 8.145  ;
; DATA[15]     ; DATA[15]      ; 7.533  ;        ;        ; 7.533  ;
; DATA[15]     ; RAM_DATA[15]  ; 8.202  ;        ;        ; 8.202  ;
; FC[0]        ; ACSI_RDn      ; 9.216  ; 9.216  ; 9.216  ; 9.216  ;
; FC[0]        ; ACSI_WRn      ; 9.220  ; 9.220  ; 9.220  ; 9.220  ;
; FC[0]        ; BUTTONn       ; 8.018  ; 8.018  ; 8.018  ; 8.018  ;
; FC[0]        ; CA1_OUT       ; 8.904  ; 8.904  ; 8.904  ; 8.904  ;
; FC[0]        ; CD[0]         ; 9.713  ; 9.713  ; 9.713  ; 9.713  ;
; FC[0]        ; CD[1]         ; 9.635  ; 9.635  ; 9.635  ; 9.635  ;
; FC[0]        ; CD[2]         ; 8.931  ; 8.931  ; 8.931  ; 8.931  ;
; FC[0]        ; CD[3]         ; 9.706  ; 9.706  ; 9.706  ; 9.706  ;
; FC[0]        ; CD[4]         ; 9.200  ; 9.200  ; 9.200  ; 9.200  ;
; FC[0]        ; CD[5]         ; 9.192  ; 9.192  ; 9.192  ; 9.192  ;
; FC[0]        ; CD[6]         ; 9.342  ; 9.342  ; 9.342  ; 9.342  ;
; FC[0]        ; CD[7]         ; 9.036  ; 9.036  ; 9.036  ; 9.036  ;
; FC[0]        ; DATA[0]       ; 9.672  ; 9.672  ; 9.672  ; 9.672  ;
; FC[0]        ; DATA[1]       ; 10.267 ; 10.267 ; 10.267 ; 10.267 ;
; FC[0]        ; DATA[2]       ; 9.820  ; 9.820  ; 9.820  ; 9.820  ;
; FC[0]        ; DATA[3]       ; 9.591  ; 9.591  ; 9.591  ; 9.591  ;
; FC[0]        ; DATA[4]       ; 9.659  ; 9.659  ; 9.659  ; 9.659  ;
; FC[0]        ; DATA[5]       ; 10.457 ; 10.457 ; 10.457 ; 10.457 ;
; FC[0]        ; DATA[6]       ; 10.249 ; 10.249 ; 10.249 ; 10.249 ;
; FC[0]        ; DATA[7]       ; 10.640 ; 10.640 ; 10.640 ; 10.640 ;
; FC[0]        ; DATA[8]       ; 10.282 ; 10.282 ; 10.282 ; 10.282 ;
; FC[0]        ; DATA[9]       ; 10.672 ; 10.672 ; 10.672 ; 10.672 ;
; FC[0]        ; DATA[10]      ; 9.565  ; 9.565  ; 9.565  ; 9.565  ;
; FC[0]        ; DATA[11]      ; 10.686 ; 10.686 ; 10.686 ; 10.686 ;
; FC[0]        ; DATA[12]      ; 10.266 ; 10.266 ; 10.266 ; 10.266 ;
; FC[0]        ; DATA[13]      ; 9.851  ; 9.851  ; 9.851  ; 9.851  ;
; FC[0]        ; DATA[14]      ; 9.544  ; 9.544  ; 9.544  ; 9.544  ;
; FC[0]        ; DATA[15]      ; 9.849  ; 9.849  ; 9.849  ; 9.849  ;
; FC[0]        ; DTACKn        ; 8.535  ; 8.535  ; 8.535  ; 8.535  ;
; FC[0]        ; FLASH_CEn     ; 9.231  ; 9.231  ; 9.231  ; 9.231  ;
; FC[0]        ; FLASH_OEn     ; 8.927  ; 8.927  ; 8.927  ; 8.927  ;
; FC[0]        ; JOY_RHn       ; 8.213  ; 8.213  ; 8.213  ; 8.213  ;
; FC[0]        ; JOY_RLn       ; 8.352  ; 8.352  ; 8.352  ; 8.352  ;
; FC[0]        ; JOY_WEn       ; 8.206  ; 8.206  ; 8.206  ; 8.206  ;
; FC[0]        ; JOY_WL        ; 8.233  ; 8.233  ; 8.233  ; 8.233  ;
; FC[0]        ; RAM_DATA[0]   ; 10.203 ; 10.203 ; 10.203 ; 10.203 ;
; FC[0]        ; RAM_DATA[1]   ; 10.637 ; 10.637 ; 10.637 ; 10.637 ;
; FC[0]        ; RAM_DATA[2]   ; 10.172 ; 10.172 ; 10.172 ; 10.172 ;
; FC[0]        ; RAM_DATA[3]   ; 10.570 ; 10.570 ; 10.570 ; 10.570 ;
; FC[0]        ; RAM_DATA[4]   ; 10.541 ; 10.541 ; 10.541 ; 10.541 ;
; FC[0]        ; RAM_DATA[5]   ; 11.108 ; 11.108 ; 11.108 ; 11.108 ;
; FC[0]        ; RAM_DATA[6]   ; 10.621 ; 10.621 ; 10.621 ; 10.621 ;
; FC[0]        ; RAM_DATA[7]   ; 10.928 ; 10.928 ; 10.928 ; 10.928 ;
; FC[0]        ; RAM_DATA[8]   ; 10.455 ; 10.455 ; 10.455 ; 10.455 ;
; FC[0]        ; RAM_DATA[9]   ; 10.830 ; 10.830 ; 10.830 ; 10.830 ;
; FC[0]        ; RAM_DATA[10]  ; 10.161 ; 10.161 ; 10.161 ; 10.161 ;
; FC[0]        ; RAM_DATA[11]  ; 10.390 ; 10.390 ; 10.390 ; 10.390 ;
; FC[0]        ; RAM_DATA[12]  ; 10.100 ; 10.100 ; 10.100 ; 10.100 ;
; FC[0]        ; RAM_DATA[13]  ; 10.603 ; 10.603 ; 10.603 ; 10.603 ;
; FC[0]        ; RAM_DATA[14]  ; 10.413 ; 10.413 ; 10.413 ; 10.413 ;
; FC[0]        ; RAM_DATA[15]  ; 10.518 ; 10.518 ; 10.518 ; 10.518 ;
; FC[0]        ; ROM0n         ; 7.620  ; 7.620  ; 7.620  ; 7.620  ;
; FC[0]        ; ROM1n         ; 7.509  ; 7.509  ; 7.509  ; 7.509  ;
; FC[0]        ; ROM2n         ; 8.284  ; 8.284  ; 8.284  ; 8.284  ;
; FC[0]        ; ROM3n         ; 7.342  ; 7.342  ; 7.342  ; 7.342  ;
; FC[0]        ; ROM4n         ; 7.400  ; 7.400  ; 7.400  ; 7.400  ;
; FC[0]        ; ROM5n         ; 8.314  ; 8.314  ; 8.314  ; 8.314  ;
; FC[0]        ; ROM6n         ; 8.296  ; 8.296  ; 8.296  ; 8.296  ;
; FC[1]        ; ACSI_RDn      ; 9.215  ; 9.215  ; 9.215  ; 9.215  ;
; FC[1]        ; ACSI_WRn      ; 9.219  ; 9.219  ; 9.219  ; 9.219  ;
; FC[1]        ; BUTTONn       ; 7.938  ; 7.938  ; 7.938  ; 7.938  ;
; FC[1]        ; CA1_OUT       ; 8.903  ; 8.903  ; 8.903  ; 8.903  ;
; FC[1]        ; CD[0]         ; 9.712  ; 9.712  ; 9.712  ; 9.712  ;
; FC[1]        ; CD[1]         ; 9.634  ; 9.634  ; 9.634  ; 9.634  ;
; FC[1]        ; CD[2]         ; 8.930  ; 8.930  ; 8.930  ; 8.930  ;
; FC[1]        ; CD[3]         ; 9.705  ; 9.705  ; 9.705  ; 9.705  ;
; FC[1]        ; CD[4]         ; 9.199  ; 9.199  ; 9.199  ; 9.199  ;
; FC[1]        ; CD[5]         ; 9.191  ; 9.191  ; 9.191  ; 9.191  ;
; FC[1]        ; CD[6]         ; 9.341  ; 9.341  ; 9.341  ; 9.341  ;
; FC[1]        ; CD[7]         ; 9.035  ; 9.035  ; 9.035  ; 9.035  ;
; FC[1]        ; DATA[0]       ; 9.671  ; 9.671  ; 9.671  ; 9.671  ;
; FC[1]        ; DATA[1]       ; 10.266 ; 10.266 ; 10.266 ; 10.266 ;
; FC[1]        ; DATA[2]       ; 9.819  ; 9.819  ; 9.819  ; 9.819  ;
; FC[1]        ; DATA[3]       ; 9.590  ; 9.590  ; 9.590  ; 9.590  ;
; FC[1]        ; DATA[4]       ; 9.658  ; 9.658  ; 9.658  ; 9.658  ;
; FC[1]        ; DATA[5]       ; 10.456 ; 10.456 ; 10.456 ; 10.456 ;
; FC[1]        ; DATA[6]       ; 10.248 ; 10.248 ; 10.248 ; 10.248 ;
; FC[1]        ; DATA[7]       ; 10.639 ; 10.639 ; 10.639 ; 10.639 ;
; FC[1]        ; DATA[8]       ; 10.274 ; 10.274 ; 10.274 ; 10.274 ;
; FC[1]        ; DATA[9]       ; 10.664 ; 10.664 ; 10.664 ; 10.664 ;
; FC[1]        ; DATA[10]      ; 9.557  ; 9.557  ; 9.557  ; 9.557  ;
; FC[1]        ; DATA[11]      ; 10.685 ; 10.685 ; 10.685 ; 10.685 ;
; FC[1]        ; DATA[12]      ; 10.265 ; 10.265 ; 10.265 ; 10.265 ;
; FC[1]        ; DATA[13]      ; 9.850  ; 9.850  ; 9.850  ; 9.850  ;
; FC[1]        ; DATA[14]      ; 9.543  ; 9.543  ; 9.543  ; 9.543  ;
; FC[1]        ; DATA[15]      ; 9.848  ; 9.848  ; 9.848  ; 9.848  ;
; FC[1]        ; DTACKn        ; 8.647  ; 8.647  ; 8.647  ; 8.647  ;
; FC[1]        ; FLASH_CEn     ; 9.343  ; 9.343  ; 9.343  ; 9.343  ;
; FC[1]        ; FLASH_OEn     ; 9.039  ; 9.039  ; 9.039  ; 9.039  ;
; FC[1]        ; JOY_RHn       ; 8.212  ; 8.212  ; 8.212  ; 8.212  ;
; FC[1]        ; JOY_RLn       ; 8.351  ; 8.351  ; 8.351  ; 8.351  ;
; FC[1]        ; JOY_WEn       ; 8.205  ; 8.205  ; 8.205  ; 8.205  ;
; FC[1]        ; JOY_WL        ; 8.232  ; 8.232  ; 8.232  ; 8.232  ;
; FC[1]        ; RAM_DATA[0]   ; 10.202 ; 10.202 ; 10.202 ; 10.202 ;
; FC[1]        ; RAM_DATA[1]   ; 10.636 ; 10.636 ; 10.636 ; 10.636 ;
; FC[1]        ; RAM_DATA[2]   ; 10.171 ; 10.171 ; 10.171 ; 10.171 ;
; FC[1]        ; RAM_DATA[3]   ; 10.569 ; 10.569 ; 10.569 ; 10.569 ;
; FC[1]        ; RAM_DATA[4]   ; 10.540 ; 10.540 ; 10.540 ; 10.540 ;
; FC[1]        ; RAM_DATA[5]   ; 11.107 ; 11.107 ; 11.107 ; 11.107 ;
; FC[1]        ; RAM_DATA[6]   ; 10.620 ; 10.620 ; 10.620 ; 10.620 ;
; FC[1]        ; RAM_DATA[7]   ; 10.927 ; 10.927 ; 10.927 ; 10.927 ;
; FC[1]        ; RAM_DATA[8]   ; 10.447 ; 10.447 ; 10.447 ; 10.447 ;
; FC[1]        ; RAM_DATA[9]   ; 10.822 ; 10.822 ; 10.822 ; 10.822 ;
; FC[1]        ; RAM_DATA[10]  ; 10.153 ; 10.153 ; 10.153 ; 10.153 ;
; FC[1]        ; RAM_DATA[11]  ; 10.389 ; 10.389 ; 10.389 ; 10.389 ;
; FC[1]        ; RAM_DATA[12]  ; 10.099 ; 10.099 ; 10.099 ; 10.099 ;
; FC[1]        ; RAM_DATA[13]  ; 10.602 ; 10.602 ; 10.602 ; 10.602 ;
; FC[1]        ; RAM_DATA[14]  ; 10.412 ; 10.412 ; 10.412 ; 10.412 ;
; FC[1]        ; RAM_DATA[15]  ; 10.517 ; 10.517 ; 10.517 ; 10.517 ;
; FC[1]        ; ROM0n         ; 7.732  ; 7.732  ; 7.732  ; 7.732  ;
; FC[1]        ; ROM1n         ; 7.621  ; 7.621  ; 7.621  ; 7.621  ;
; FC[1]        ; ROM2n         ; 8.396  ; 8.396  ; 8.396  ; 8.396  ;
; FC[1]        ; ROM3n         ; 7.454  ; 7.454  ; 7.454  ; 7.454  ;
; FC[1]        ; ROM4n         ; 7.512  ; 7.512  ; 7.512  ; 7.512  ;
; FC[1]        ; ROM5n         ; 8.426  ; 8.426  ; 8.426  ; 8.426  ;
; FC[1]        ; ROM6n         ; 8.408  ; 8.408  ; 8.408  ; 8.408  ;
; FC[2]        ; ACSI_RDn      ; 9.164  ; 9.164  ; 9.164  ; 9.164  ;
; FC[2]        ; ACSI_WRn      ; 9.168  ; 9.168  ; 9.168  ; 9.168  ;
; FC[2]        ; CA1_OUT       ;        ; 8.852  ; 8.852  ;        ;
; FC[2]        ; CD[0]         ; 9.661  ; 9.704  ; 9.704  ; 9.661  ;
; FC[2]        ; CD[1]         ; 9.583  ; 9.626  ; 9.626  ; 9.583  ;
; FC[2]        ; CD[2]         ; 8.879  ; 8.879  ; 8.879  ; 8.879  ;
; FC[2]        ; CD[3]         ; 9.654  ; 9.795  ; 9.795  ; 9.654  ;
; FC[2]        ; CD[4]         ; 9.148  ; 9.148  ; 9.148  ; 9.148  ;
; FC[2]        ; CD[5]         ; 9.140  ; 9.140  ; 9.140  ; 9.140  ;
; FC[2]        ; CD[6]         ; 9.290  ; 9.290  ; 9.290  ; 9.290  ;
; FC[2]        ; CD[7]         ; 8.984  ; 8.984  ; 8.984  ; 8.984  ;
; FC[2]        ; DATA[0]       ; 10.003 ; 9.620  ; 9.620  ; 10.003 ;
; FC[2]        ; DATA[1]       ; 10.399 ; 10.215 ; 10.215 ; 10.399 ;
; FC[2]        ; DATA[2]       ; 11.423 ; 9.768  ; 9.768  ; 11.423 ;
; FC[2]        ; DATA[3]       ; 10.998 ; 9.539  ; 9.539  ; 10.998 ;
; FC[2]        ; DATA[4]       ; 11.031 ; 9.607  ; 9.607  ; 11.031 ;
; FC[2]        ; DATA[5]       ; 11.844 ; 10.405 ; 10.405 ; 11.844 ;
; FC[2]        ; DATA[6]       ; 11.471 ; 10.197 ; 10.197 ; 11.471 ;
; FC[2]        ; DATA[7]       ; 11.826 ; 10.588 ; 10.588 ; 11.826 ;
; FC[2]        ; DATA[8]       ; 11.464 ; 10.410 ; 10.410 ; 11.464 ;
; FC[2]        ; DATA[9]       ; 11.949 ; 10.800 ; 10.800 ; 11.949 ;
; FC[2]        ; DATA[10]      ; 10.875 ; 9.547  ; 9.547  ; 10.875 ;
; FC[2]        ; DATA[11]      ; 11.705 ; 10.634 ; 10.634 ; 11.705 ;
; FC[2]        ; DATA[12]      ; 11.512 ; 10.214 ; 10.214 ; 11.512 ;
; FC[2]        ; DATA[13]      ; 11.263 ; 9.799  ; 9.799  ; 11.263 ;
; FC[2]        ; DATA[14]      ; 10.660 ; 9.492  ; 9.492  ; 10.660 ;
; FC[2]        ; DATA[15]      ; 11.120 ; 9.797  ; 9.797  ; 11.120 ;
; FC[2]        ; DTACKn        ; 8.817  ; 8.817  ; 8.817  ; 8.817  ;
; FC[2]        ; JOY_RHn       ;        ; 8.161  ; 8.161  ;        ;
; FC[2]        ; JOY_RLn       ;        ; 8.300  ; 8.300  ;        ;
; FC[2]        ; JOY_WEn       ; 8.154  ;        ;        ; 8.154  ;
; FC[2]        ; JOY_WL        ; 8.181  ;        ;        ; 8.181  ;
; FC[2]        ; RAM_DATA[0]   ; 10.534 ; 10.151 ; 10.151 ; 10.534 ;
; FC[2]        ; RAM_DATA[1]   ; 10.769 ; 10.585 ; 10.585 ; 10.769 ;
; FC[2]        ; RAM_DATA[2]   ; 11.775 ; 10.120 ; 10.120 ; 11.775 ;
; FC[2]        ; RAM_DATA[3]   ; 11.977 ; 10.518 ; 10.518 ; 11.977 ;
; FC[2]        ; RAM_DATA[4]   ; 11.913 ; 10.489 ; 10.489 ; 11.913 ;
; FC[2]        ; RAM_DATA[5]   ; 12.495 ; 11.056 ; 11.056 ; 12.495 ;
; FC[2]        ; RAM_DATA[6]   ; 11.843 ; 10.569 ; 10.569 ; 11.843 ;
; FC[2]        ; RAM_DATA[7]   ; 12.114 ; 10.876 ; 10.876 ; 12.114 ;
; FC[2]        ; RAM_DATA[8]   ; 11.637 ; 10.583 ; 10.583 ; 11.637 ;
; FC[2]        ; RAM_DATA[9]   ; 12.107 ; 10.958 ; 10.958 ; 12.107 ;
; FC[2]        ; RAM_DATA[10]  ; 11.471 ; 10.143 ; 10.143 ; 11.471 ;
; FC[2]        ; RAM_DATA[11]  ; 11.409 ; 10.338 ; 10.338 ; 11.409 ;
; FC[2]        ; RAM_DATA[12]  ; 11.346 ; 10.048 ; 10.048 ; 11.346 ;
; FC[2]        ; RAM_DATA[13]  ; 12.015 ; 10.551 ; 10.551 ; 12.015 ;
; FC[2]        ; RAM_DATA[14]  ; 11.529 ; 10.361 ; 10.361 ; 11.529 ;
; FC[2]        ; RAM_DATA[15]  ; 11.789 ; 10.466 ; 10.466 ; 11.789 ;
; HDINTn       ; DATA[5]       ; 10.910 ;        ;        ; 10.910 ;
; HDINTn       ; RAM_DATA[5]   ; 11.561 ;        ;        ; 11.561 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 10.752 ; 10.752 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 11.403 ; 11.403 ;        ;
; IDE_IORDY    ; DTACKn        ; 7.922  ; 7.922  ; 7.922  ; 7.922  ;
; LDSn         ; ACSI_RDn      ; 8.450  ; 8.450  ; 8.450  ; 8.450  ;
; LDSn         ; ACSI_WRn      ; 8.454  ; 8.454  ; 8.454  ; 8.454  ;
; LDSn         ; BUTTONn       ; 9.490  ;        ;        ; 9.490  ;
; LDSn         ; CA1_OUT       ; 8.138  ;        ;        ; 8.138  ;
; LDSn         ; CD[0]         ; 8.990  ; 8.947  ; 8.947  ; 8.990  ;
; LDSn         ; CD[1]         ; 8.912  ; 8.869  ; 8.869  ; 8.912  ;
; LDSn         ; CD[2]         ; 8.165  ; 8.165  ; 8.165  ; 8.165  ;
; LDSn         ; CD[3]         ; 9.081  ; 8.940  ; 8.940  ; 9.081  ;
; LDSn         ; CD[4]         ; 8.434  ; 8.434  ; 8.434  ; 8.434  ;
; LDSn         ; CD[5]         ; 8.426  ; 8.426  ; 8.426  ; 8.426  ;
; LDSn         ; CD[6]         ; 8.576  ; 8.576  ; 8.576  ; 8.576  ;
; LDSn         ; CD[7]         ; 8.270  ; 8.270  ; 8.270  ; 8.270  ;
; LDSn         ; DATA[0]       ; 9.827  ; 9.679  ; 9.679  ; 9.827  ;
; LDSn         ; DATA[1]       ; 9.993  ; 9.955  ; 9.955  ; 9.993  ;
; LDSn         ; DATA[2]       ; 9.818  ; 9.756  ; 9.756  ; 9.818  ;
; LDSn         ; DATA[3]       ; 9.306  ; 9.331  ; 9.331  ; 9.306  ;
; LDSn         ; DATA[4]       ; 9.438  ; 9.512  ; 9.512  ; 9.438  ;
; LDSn         ; DATA[5]       ; 9.966  ; 9.966  ; 9.966  ; 9.966  ;
; LDSn         ; DATA[6]       ; 9.804  ; 9.804  ; 9.804  ; 9.804  ;
; LDSn         ; DATA[7]       ; 9.794  ; 9.794  ; 9.794  ; 9.794  ;
; LDSn         ; DATA[8]       ; 9.921  ; 9.921  ; 9.921  ; 9.921  ;
; LDSn         ; DATA[9]       ; 9.921  ; 9.921  ; 9.921  ; 9.921  ;
; LDSn         ; DATA[10]      ; 8.998  ; 9.208  ; 9.208  ; 8.998  ;
; LDSn         ; DATA[11]      ; 10.058 ; 10.058 ; 10.058 ; 10.058 ;
; LDSn         ; DATA[12]      ; 10.101 ; 9.951  ; 9.951  ; 10.101 ;
; LDSn         ; DATA[13]      ; 9.787  ; 9.596  ; 9.596  ; 9.787  ;
; LDSn         ; DATA[14]      ; 9.383  ; 9.036  ; 9.036  ; 9.383  ;
; LDSn         ; DATA[15]      ; 9.738  ; 10.063 ; 10.063 ; 9.738  ;
; LDSn         ; DTACKn        ; 8.529  ; 8.529  ; 8.529  ; 8.529  ;
; LDSn         ; IDE_IORDn     ; 7.507  ;        ;        ; 7.507  ;
; LDSn         ; IDE_IOWRn     ; 7.365  ;        ;        ; 7.365  ;
; LDSn         ; JOY_RLn       ; 6.633  ;        ;        ; 6.633  ;
; LDSn         ; JOY_WEn       ;        ; 6.487  ; 6.487  ;        ;
; LDSn         ; JOY_WL        ;        ; 6.291  ; 6.291  ;        ;
; LDSn         ; RAM_CAS0n     ; 8.069  ;        ;        ; 8.069  ;
; LDSn         ; RAM_DATA[0]   ; 10.358 ; 10.210 ; 10.210 ; 10.358 ;
; LDSn         ; RAM_DATA[1]   ; 10.363 ; 10.325 ; 10.325 ; 10.363 ;
; LDSn         ; RAM_DATA[2]   ; 10.170 ; 10.108 ; 10.108 ; 10.170 ;
; LDSn         ; RAM_DATA[3]   ; 10.285 ; 10.310 ; 10.310 ; 10.285 ;
; LDSn         ; RAM_DATA[4]   ; 10.320 ; 10.394 ; 10.394 ; 10.320 ;
; LDSn         ; RAM_DATA[5]   ; 11.096 ; 11.246 ; 11.246 ; 11.096 ;
; LDSn         ; RAM_DATA[6]   ; 10.354 ; 10.600 ; 10.600 ; 10.354 ;
; LDSn         ; RAM_DATA[7]   ; 10.663 ; 10.815 ; 10.815 ; 10.663 ;
; LDSn         ; RAM_DATA[8]   ; 10.323 ; 10.330 ; 10.330 ; 10.323 ;
; LDSn         ; RAM_DATA[9]   ; 10.908 ; 10.737 ; 10.737 ; 10.908 ;
; LDSn         ; RAM_DATA[10]  ; 9.594  ; 9.804  ; 9.804  ; 9.594  ;
; LDSn         ; RAM_DATA[11]  ; 10.117 ; 9.785  ; 9.785  ; 10.117 ;
; LDSn         ; RAM_DATA[12]  ; 9.996  ; 9.785  ; 9.785  ; 9.996  ;
; LDSn         ; RAM_DATA[13]  ; 10.539 ; 10.348 ; 10.348 ; 10.539 ;
; LDSn         ; RAM_DATA[14]  ; 10.252 ; 9.905  ; 9.905  ; 10.252 ;
; LDSn         ; RAM_DATA[15]  ; 10.407 ; 10.743 ; 10.743 ; 10.407 ;
; LDSn         ; RAM_DQM0L     ; 7.228  ;        ;        ; 7.228  ;
; LPT_BSY      ; DATA[0]       ; 10.497 ;        ;        ; 10.497 ;
; LPT_BSY      ; RAM_DATA[0]   ; 11.028 ;        ;        ; 11.028 ;
; LPT_D[0]     ; DATA[8]       ; 9.949  ;        ;        ; 9.949  ;
; LPT_D[0]     ; RAM_DATA[8]   ; 10.122 ;        ;        ; 10.122 ;
; LPT_D[1]     ; DATA[9]       ; 10.070 ;        ;        ; 10.070 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 10.228 ;        ;        ; 10.228 ;
; LPT_D[2]     ; DATA[10]      ; 9.155  ;        ;        ; 9.155  ;
; LPT_D[2]     ; RAM_DATA[10]  ; 9.751  ;        ;        ; 9.751  ;
; LPT_D[3]     ; DATA[11]      ; 9.686  ;        ;        ; 9.686  ;
; LPT_D[3]     ; RAM_DATA[11]  ; 9.390  ;        ;        ; 9.390  ;
; LPT_D[4]     ; DATA[12]      ; 9.820  ;        ;        ; 9.820  ;
; LPT_D[4]     ; RAM_DATA[12]  ; 9.654  ;        ;        ; 9.654  ;
; LPT_D[5]     ; DATA[13]      ; 9.421  ;        ;        ; 9.421  ;
; LPT_D[5]     ; RAM_DATA[13]  ; 10.173 ;        ;        ; 10.173 ;
; LPT_D[6]     ; DATA[14]      ; 8.850  ;        ;        ; 8.850  ;
; LPT_D[6]     ; RAM_DATA[14]  ; 9.719  ;        ;        ; 9.719  ;
; LPT_D[7]     ; DATA[15]      ; 9.646  ;        ;        ; 9.646  ;
; LPT_D[7]     ; RAM_DATA[15]  ; 10.315 ;        ;        ; 10.315 ;
; MIDI_IN      ; MIDI_TLR      ; 4.720  ;        ;        ; 4.720  ;
; RAM_DATA[0]  ; DATA[0]       ; 9.768  ;        ;        ; 9.768  ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 10.299 ;        ;        ; 10.299 ;
; RAM_DATA[1]  ; DATA[1]       ; 9.997  ;        ;        ; 9.997  ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 10.367 ;        ;        ; 10.367 ;
; RAM_DATA[2]  ; DATA[2]       ; 9.687  ;        ;        ; 9.687  ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 10.039 ;        ;        ; 10.039 ;
; RAM_DATA[3]  ; DATA[3]       ; 9.494  ;        ;        ; 9.494  ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 10.473 ;        ;        ; 10.473 ;
; RAM_DATA[4]  ; DATA[4]       ; 9.496  ;        ;        ; 9.496  ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 10.378 ;        ;        ; 10.378 ;
; RAM_DATA[5]  ; DATA[5]       ; 10.737 ;        ;        ; 10.737 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 11.388 ;        ;        ; 11.388 ;
; RAM_DATA[6]  ; DATA[6]       ; 11.236 ;        ;        ; 11.236 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 11.608 ;        ;        ; 11.608 ;
; RAM_DATA[7]  ; DATA[7]       ; 10.711 ;        ;        ; 10.711 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 10.999 ;        ;        ; 10.999 ;
; RAM_DATA[8]  ; DATA[8]       ; 10.341 ;        ;        ; 10.341 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 10.514 ;        ;        ; 10.514 ;
; RAM_DATA[9]  ; DATA[9]       ; 11.037 ;        ;        ; 11.037 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 11.195 ;        ;        ; 11.195 ;
; RAM_DATA[10] ; DATA[10]      ; 9.557  ;        ;        ; 9.557  ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 10.153 ;        ;        ; 10.153 ;
; RAM_DATA[11] ; DATA[11]      ; 10.789 ;        ;        ; 10.789 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 10.493 ;        ;        ; 10.493 ;
; RAM_DATA[12] ; DATA[12]      ; 9.954  ;        ;        ; 9.954  ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 9.788  ;        ;        ; 9.788  ;
; RAM_DATA[13] ; DATA[13]      ; 9.639  ;        ;        ; 9.639  ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 10.391 ;        ;        ; 10.391 ;
; RAM_DATA[14] ; DATA[14]      ; 9.600  ;        ;        ; 9.600  ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 10.469 ;        ;        ; 10.469 ;
; RAM_DATA[15] ; DATA[15]      ; 10.294 ;        ;        ; 10.294 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 10.963 ;        ;        ; 10.963 ;
; RWn          ; ACSI_RDn      ; 9.180  ; 7.122  ; 7.122  ; 9.180  ;
; RWn          ; ACSI_WRn      ; 7.126  ; 9.184  ; 9.184  ; 7.126  ;
; RWn          ; BUTTONn       ;        ; 7.901  ; 7.901  ;        ;
; RWn          ; CA1_OUT       ;        ; 8.868  ; 8.868  ;        ;
; RWn          ; CD[0]         ; 7.615  ; 7.489  ; 7.489  ; 7.615  ;
; RWn          ; CD[1]         ; 7.531  ; 7.411  ; 7.411  ; 7.531  ;
; RWn          ; CD[2]         ; 6.707  ; 6.707  ; 6.707  ; 6.707  ;
; RWn          ; CD[3]         ; 7.623  ; 7.482  ; 7.482  ; 7.623  ;
; RWn          ; CD[4]         ; 6.976  ; 6.976  ; 6.976  ; 6.976  ;
; RWn          ; CD[5]         ; 6.968  ; 6.968  ; 6.968  ; 6.968  ;
; RWn          ; CD[6]         ; 7.118  ; 7.118  ; 7.118  ; 7.118  ;
; RWn          ; CD[7]         ; 6.812  ; 6.812  ; 6.812  ; 6.812  ;
; RWn          ; DATA[0]       ; 8.730  ; 8.555  ; 8.555  ; 8.730  ;
; RWn          ; DATA[1]       ; 9.126  ; 9.140  ; 9.140  ; 9.126  ;
; RWn          ; DATA[2]       ; 8.851  ; 8.629  ; 8.629  ; 8.851  ;
; RWn          ; DATA[3]       ; 8.998  ; 8.371  ; 8.371  ; 8.998  ;
; RWn          ; DATA[4]       ; 8.972  ; 8.468  ; 8.468  ; 8.972  ;
; RWn          ; DATA[5]       ; 9.355  ; 9.266  ; 9.266  ; 9.355  ;
; RWn          ; DATA[6]       ; 9.442  ; 9.058  ; 9.058  ; 9.442  ;
; RWn          ; DATA[7]       ; 9.738  ; 9.410  ; 9.410  ; 9.738  ;
; RWn          ; DATA[8]       ; 9.269  ; 9.122  ; 9.122  ; 9.269  ;
; RWn          ; DATA[9]       ; 9.651  ; 9.340  ; 9.340  ; 9.651  ;
; RWn          ; DATA[10]      ; 8.075  ; 8.075  ; 8.075  ; 8.075  ;
; RWn          ; DATA[11]      ; 9.605  ; 9.317  ; 9.317  ; 9.605  ;
; RWn          ; DATA[12]      ; 9.397  ; 9.075  ; 9.075  ; 9.397  ;
; RWn          ; DATA[13]      ; 9.023  ; 8.590  ; 8.590  ; 9.023  ;
; RWn          ; DATA[14]      ; 8.533  ; 8.095  ; 8.095  ; 8.533  ;
; RWn          ; DATA[15]      ; 9.031  ; 8.658  ; 8.658  ; 9.031  ;
; RWn          ; DTACKn        ; 8.493  ; 8.493  ; 8.493  ; 8.493  ;
; RWn          ; FLASH_CEn     ;        ; 9.189  ; 9.189  ;        ;
; RWn          ; FLASH_OEn     ;        ; 8.885  ; 8.885  ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 7.107  ; 7.107  ;        ;
; RWn          ; IDE_D_EN_OUTn ; 7.372  ;        ;        ; 7.372  ;
; RWn          ; IDE_IORDn     ;        ; 7.214  ; 7.214  ;        ;
; RWn          ; IDE_IOWRn     ; 7.074  ;        ;        ; 7.074  ;
; RWn          ; JOY_RHn       ;        ; 6.969  ; 6.969  ;        ;
; RWn          ; JOY_RLn       ;        ; 7.108  ; 7.108  ;        ;
; RWn          ; JOY_WEn       ; 6.962  ;        ;        ; 6.962  ;
; RWn          ; JOY_WL        ; 8.197  ; 6.120  ; 6.120  ; 8.197  ;
; RWn          ; RAM_DATA[0]   ; 7.425  ; 7.425  ; 7.425  ; 7.425  ;
; RWn          ; RAM_DATA[1]   ; 7.427  ; 7.427  ; 7.427  ; 7.427  ;
; RWn          ; RAM_DATA[2]   ; 7.427  ; 7.427  ; 7.427  ; 7.427  ;
; RWn          ; RAM_DATA[3]   ; 7.752  ; 7.752  ; 7.752  ; 7.752  ;
; RWn          ; RAM_DATA[4]   ; 7.752  ; 7.752  ; 7.752  ; 7.752  ;
; RWn          ; RAM_DATA[5]   ; 8.064  ; 8.064  ; 8.064  ; 8.064  ;
; RWn          ; RAM_DATA[6]   ; 7.974  ; 7.974  ; 7.974  ; 7.974  ;
; RWn          ; RAM_DATA[7]   ; 8.064  ; 8.064  ; 8.064  ; 8.064  ;
; RWn          ; RAM_DATA[8]   ; 7.646  ; 7.646  ; 7.646  ; 7.646  ;
; RWn          ; RAM_DATA[9]   ; 7.646  ; 7.646  ; 7.646  ; 7.646  ;
; RWn          ; RAM_DATA[10]  ; 7.563  ; 7.563  ; 7.563  ; 7.563  ;
; RWn          ; RAM_DATA[11]  ; 7.553  ; 7.553  ; 7.553  ; 7.553  ;
; RWn          ; RAM_DATA[12]  ; 7.553  ; 7.553  ; 7.553  ; 7.553  ;
; RWn          ; RAM_DATA[13]  ; 7.553  ; 7.553  ; 7.553  ; 7.553  ;
; RWn          ; RAM_DATA[14]  ; 7.428  ; 7.428  ; 7.428  ; 7.428  ;
; RWn          ; RAM_DATA[15]  ; 7.428  ; 7.428  ; 7.428  ; 7.428  ;
; RWn          ; RAM_WEn       ; 7.768  ;        ;        ; 7.768  ;
; RWn          ; ROM0n         ;        ; 7.578  ; 7.578  ;        ;
; RWn          ; ROM1n         ;        ; 7.467  ; 7.467  ;        ;
; RWn          ; ROM2n         ;        ; 8.242  ; 8.242  ;        ;
; RWn          ; ROM3n         ;        ; 7.300  ; 7.300  ;        ;
; RWn          ; ROM4n         ;        ; 7.358  ; 7.358  ;        ;
; RWn          ; ROM5n         ;        ; 8.272  ; 8.272  ;        ;
; RWn          ; ROM6n         ;        ; 8.254  ; 8.254  ;        ;
; SCSI_ACKn    ; CD[0]         ; 6.695  ; 6.695  ; 6.695  ; 6.695  ;
; SCSI_ATNn    ; CD[1]         ; 7.735  ; 7.735  ; 7.735  ; 7.735  ;
; SCSI_BSYn    ; CD[6]         ; 8.037  ; 8.037  ; 8.037  ; 8.037  ;
; SCSI_D[0]    ; CD[0]         ; 6.896  ; 6.896  ; 6.896  ; 6.896  ;
; SCSI_D[1]    ; CD[1]         ; 6.937  ; 6.937  ; 6.937  ; 6.937  ;
; SCSI_D[2]    ; CD[2]         ;        ; 6.348  ; 6.348  ;        ;
; SCSI_D[3]    ; CD[3]         ; 7.049  ; 7.049  ; 7.049  ; 7.049  ;
; SCSI_D[4]    ; CD[4]         ; 8.060  ; 8.060  ; 8.060  ; 8.060  ;
; SCSI_D[5]    ; CD[5]         ; 7.640  ; 7.640  ; 7.640  ; 7.640  ;
; SCSI_D[6]    ; CD[6]         ; 7.899  ; 7.899  ; 7.899  ; 7.899  ;
; SCSI_D[7]    ; CD[7]         ; 7.487  ; 7.487  ; 7.487  ; 7.487  ;
; SCSI_DCn     ; CD[3]         ; 7.337  ; 7.337  ; 7.337  ; 7.337  ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 8.297  ; 8.297  ; 8.297  ; 8.297  ;
; SCSI_DCn     ; SCSI_D[0]     ; 7.777  ; 7.777  ; 7.777  ; 7.777  ;
; SCSI_DCn     ; SCSI_D[1]     ; 7.777  ; 7.777  ; 7.777  ; 7.777  ;
; SCSI_DCn     ; SCSI_D[2]     ; 7.772  ; 7.772  ; 7.772  ; 7.772  ;
; SCSI_DCn     ; SCSI_D[3]     ; 7.772  ; 7.772  ; 7.772  ; 7.772  ;
; SCSI_DCn     ; SCSI_D[4]     ; 7.911  ; 7.911  ; 7.911  ; 7.911  ;
; SCSI_DCn     ; SCSI_D[5]     ; 7.911  ; 7.911  ; 7.911  ; 7.911  ;
; SCSI_DCn     ; SCSI_D[6]     ; 8.013  ; 8.013  ; 8.013  ; 8.013  ;
; SCSI_DCn     ; SCSI_D[7]     ; 8.013  ; 8.013  ; 8.013  ; 8.013  ;
; SCSI_DCn     ; SCSI_DP       ; 7.787  ; 7.787  ; 7.787  ; 7.787  ;
; SCSI_DP      ; CD[0]         ; 6.773  ; 6.773  ; 6.773  ; 6.773  ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 5.999  ; 5.999  ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 6.007  ;        ;        ; 6.007  ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 6.001  ; 6.001  ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 6.111  ;        ;        ; 6.111  ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 6.329  ; 6.329  ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 6.306  ;        ;        ; 6.306  ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 6.481  ; 6.481  ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 6.226  ;        ;        ; 6.226  ;
; SCSI_IDn[1]  ; SCSI_DP       ; 6.379  ; 6.379  ; 6.379  ; 6.379  ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 5.849  ; 5.849  ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 5.888  ; 5.888  ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 5.843  ;        ;        ; 5.843  ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 5.980  ;        ;        ; 5.980  ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 6.189  ; 6.189  ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 6.190  ; 6.190  ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 6.340  ;        ;        ; 6.340  ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 6.097  ;        ;        ; 6.097  ;
; SCSI_IDn[2]  ; SCSI_DP       ; 6.239  ; 6.239  ; 6.239  ; 6.239  ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 6.047  ; 6.047  ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 6.083  ; 6.083  ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 6.046  ; 6.046  ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 6.181  ; 6.181  ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 6.376  ;        ;        ; 6.376  ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 6.377  ;        ;        ; 6.377  ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 6.529  ;        ;        ; 6.529  ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 6.296  ;        ;        ; 6.296  ;
; SCSI_IDn[3]  ; SCSI_DP       ; 6.426  ; 6.426  ; 6.426  ; 6.426  ;
; SCSI_IOn     ; CD[2]         ;        ; 7.258  ; 7.258  ;        ;
; SCSI_IOn     ; CD[3]         ; 8.461  ; 8.461  ; 8.461  ; 8.461  ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 6.954  ; 8.236  ; 8.236  ; 6.954  ;
; SCSI_IOn     ; SCSI_D[0]     ; 6.434  ; 6.434  ; 6.434  ; 6.434  ;
; SCSI_IOn     ; SCSI_D[1]     ; 6.434  ; 6.434  ; 6.434  ; 6.434  ;
; SCSI_IOn     ; SCSI_D[2]     ; 6.429  ; 6.429  ; 6.429  ; 6.429  ;
; SCSI_IOn     ; SCSI_D[3]     ; 6.429  ; 6.429  ; 6.429  ; 6.429  ;
; SCSI_IOn     ; SCSI_D[4]     ; 6.568  ; 6.568  ; 6.568  ; 6.568  ;
; SCSI_IOn     ; SCSI_D[5]     ; 6.568  ; 6.568  ; 6.568  ; 6.568  ;
; SCSI_IOn     ; SCSI_D[6]     ; 6.670  ; 6.670  ; 6.670  ; 6.670  ;
; SCSI_IOn     ; SCSI_D[7]     ; 6.670  ; 6.670  ; 6.670  ; 6.670  ;
; SCSI_IOn     ; SCSI_DP       ; 6.444  ; 6.444  ; 6.444  ; 6.444  ;
; SCSI_IOn     ; SCSI_RDn      ; 7.112  ;        ;        ; 7.112  ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 6.793  ; 6.793  ;        ;
; SCSI_MSGn    ; CD[3]         ; 8.150  ; 8.150  ; 8.150  ; 8.150  ;
; SCSI_MSGn    ; CD[4]         ; 8.042  ; 8.042  ; 8.042  ; 8.042  ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 7.925  ; 7.925  ; 7.925  ; 7.925  ;
; SCSI_MSGn    ; SCSI_D[0]     ; 7.405  ; 7.405  ; 7.405  ; 7.405  ;
; SCSI_MSGn    ; SCSI_D[1]     ; 7.405  ; 7.405  ; 7.405  ; 7.405  ;
; SCSI_MSGn    ; SCSI_D[2]     ; 7.400  ; 7.400  ; 7.400  ; 7.400  ;
; SCSI_MSGn    ; SCSI_D[3]     ; 7.400  ; 7.400  ; 7.400  ; 7.400  ;
; SCSI_MSGn    ; SCSI_D[4]     ; 7.539  ; 7.539  ; 7.539  ; 7.539  ;
; SCSI_MSGn    ; SCSI_D[5]     ; 7.539  ; 7.539  ; 7.539  ; 7.539  ;
; SCSI_MSGn    ; SCSI_D[6]     ; 7.641  ; 7.641  ; 7.641  ; 7.641  ;
; SCSI_MSGn    ; SCSI_D[7]     ; 7.641  ; 7.641  ; 7.641  ; 7.641  ;
; SCSI_MSGn    ; SCSI_DP       ; 7.415  ; 7.415  ; 7.415  ; 7.415  ;
; SCSI_REQn    ; CD[3]         ; 8.296  ; 8.296  ; 8.296  ; 8.296  ;
; SCSI_REQn    ; CD[5]         ; 7.860  ; 7.860  ; 7.860  ; 7.860  ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 8.071  ;        ;        ; 8.071  ;
; SCSI_REQn    ; SCSI_D[0]     ; 7.551  ; 7.551  ; 7.551  ; 7.551  ;
; SCSI_REQn    ; SCSI_D[1]     ; 7.551  ; 7.551  ; 7.551  ; 7.551  ;
; SCSI_REQn    ; SCSI_D[2]     ; 7.546  ; 7.546  ; 7.546  ; 7.546  ;
; SCSI_REQn    ; SCSI_D[3]     ; 7.546  ; 7.546  ; 7.546  ; 7.546  ;
; SCSI_REQn    ; SCSI_D[4]     ; 7.685  ; 7.685  ; 7.685  ; 7.685  ;
; SCSI_REQn    ; SCSI_D[5]     ; 7.685  ; 7.685  ; 7.685  ; 7.685  ;
; SCSI_REQn    ; SCSI_D[6]     ; 7.787  ; 7.787  ; 7.787  ; 7.787  ;
; SCSI_REQn    ; SCSI_D[7]     ; 7.787  ; 7.787  ; 7.787  ; 7.787  ;
; SCSI_REQn    ; SCSI_DP       ; 7.561  ; 7.561  ; 7.561  ; 7.561  ;
; SCSI_RSTn    ; CD[7]         ;        ; 7.782  ; 7.782  ;        ;
; SCSI_SELn    ; CD[1]         ; 7.053  ; 7.053  ; 7.053  ; 7.053  ;
; SD_AVR_ENn   ; RESETn        ;        ; 7.768  ; 7.768  ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 6.883  ; 6.883  ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 7.766  ; 7.766  ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 6.633  ;        ;        ; 6.633  ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 6.693  ;        ;        ; 6.693  ;
; SD_RESETn    ; ACSI_RDn      ; 9.204  ; 9.204  ; 9.204  ; 9.204  ;
; SD_RESETn    ; ACSI_WRn      ; 9.208  ; 9.208  ; 9.208  ; 9.208  ;
; SD_RESETn    ; CA1_OUT       ; 8.892  ;        ;        ; 8.892  ;
; SD_RESETn    ; CD[0]         ; 9.744  ; 9.701  ; 9.701  ; 9.744  ;
; SD_RESETn    ; CD[1]         ; 9.666  ; 9.623  ; 9.623  ; 9.666  ;
; SD_RESETn    ; CD[2]         ; 8.919  ; 8.919  ; 8.919  ; 8.919  ;
; SD_RESETn    ; CD[3]         ; 9.835  ; 9.694  ; 9.694  ; 9.835  ;
; SD_RESETn    ; CD[4]         ; 9.188  ; 9.188  ; 9.188  ; 9.188  ;
; SD_RESETn    ; CD[5]         ; 9.180  ; 9.180  ; 9.180  ; 9.180  ;
; SD_RESETn    ; CD[6]         ; 9.330  ; 9.330  ; 9.330  ; 9.330  ;
; SD_RESETn    ; CD[7]         ; 9.024  ; 9.024  ; 9.024  ; 9.024  ;
; SD_RESETn    ; COM_TxD       ; 9.751  ; 9.751  ; 9.751  ; 9.751  ;
; SD_RESETn    ; DATA[0]       ; 10.581 ; 11.371 ; 11.371 ; 10.581 ;
; SD_RESETn    ; DATA[1]       ; 11.070 ; 11.507 ; 11.507 ; 11.070 ;
; SD_RESETn    ; DATA[2]       ; 10.851 ; 11.556 ; 11.556 ; 10.851 ;
; SD_RESETn    ; DATA[3]       ; 10.580 ; 11.106 ; 11.106 ; 10.580 ;
; SD_RESETn    ; DATA[4]       ; 10.485 ; 11.071 ; 11.071 ; 10.485 ;
; SD_RESETn    ; DATA[5]       ; 11.458 ; 11.896 ; 11.896 ; 11.458 ;
; SD_RESETn    ; DATA[6]       ; 11.234 ; 11.511 ; 11.511 ; 11.234 ;
; SD_RESETn    ; DATA[7]       ; 11.384 ; 11.878 ; 11.878 ; 11.384 ;
; SD_RESETn    ; DATA[8]       ; 10.904 ; 11.541 ; 11.541 ; 10.904 ;
; SD_RESETn    ; DATA[9]       ; 11.504 ; 12.026 ; 12.026 ; 11.504 ;
; SD_RESETn    ; DATA[10]      ; 9.752  ; 10.993 ; 10.993 ; 9.752  ;
; SD_RESETn    ; DATA[11]      ; 11.329 ; 12.141 ; 12.141 ; 11.329 ;
; SD_RESETn    ; DATA[12]      ; 10.916 ; 12.174 ; 12.174 ; 10.916 ;
; SD_RESETn    ; DATA[13]      ; 10.541 ; 11.402 ; 11.402 ; 10.541 ;
; SD_RESETn    ; DATA[14]      ; 10.137 ; 10.918 ; 10.918 ; 10.137 ;
; SD_RESETn    ; DATA[15]      ; 10.492 ; 11.197 ; 11.197 ; 10.492 ;
; SD_RESETn    ; DTACKn        ; 9.830  ; 9.830  ; 9.830  ; 9.830  ;
; SD_RESETn    ; RAM_DATA[0]   ; 11.112 ; 11.902 ; 11.902 ; 11.112 ;
; SD_RESETn    ; RAM_DATA[1]   ; 11.440 ; 11.877 ; 11.877 ; 11.440 ;
; SD_RESETn    ; RAM_DATA[2]   ; 11.203 ; 11.908 ; 11.908 ; 11.203 ;
; SD_RESETn    ; RAM_DATA[3]   ; 11.559 ; 12.085 ; 12.085 ; 11.559 ;
; SD_RESETn    ; RAM_DATA[4]   ; 11.367 ; 11.953 ; 11.953 ; 11.367 ;
; SD_RESETn    ; RAM_DATA[5]   ; 12.109 ; 12.547 ; 12.547 ; 12.109 ;
; SD_RESETn    ; RAM_DATA[6]   ; 11.606 ; 11.883 ; 11.883 ; 11.606 ;
; SD_RESETn    ; RAM_DATA[7]   ; 11.672 ; 12.166 ; 12.166 ; 11.672 ;
; SD_RESETn    ; RAM_DATA[8]   ; 11.077 ; 11.714 ; 11.714 ; 11.077 ;
; SD_RESETn    ; RAM_DATA[9]   ; 11.662 ; 12.184 ; 12.184 ; 11.662 ;
; SD_RESETn    ; RAM_DATA[10]  ; 10.348 ; 11.589 ; 11.589 ; 10.348 ;
; SD_RESETn    ; RAM_DATA[11]  ; 11.033 ; 11.845 ; 11.845 ; 11.033 ;
; SD_RESETn    ; RAM_DATA[12]  ; 10.750 ; 12.008 ; 12.008 ; 10.750 ;
; SD_RESETn    ; RAM_DATA[13]  ; 11.293 ; 12.154 ; 12.154 ; 11.293 ;
; SD_RESETn    ; RAM_DATA[14]  ; 11.006 ; 11.787 ; 11.787 ; 11.006 ;
; SD_RESETn    ; RAM_DATA[15]  ; 11.161 ; 11.866 ; 11.866 ; 11.161 ;
; UDSn         ; ACSI_RDn      ; 8.353  ; 8.353  ; 8.353  ; 8.353  ;
; UDSn         ; ACSI_WRn      ; 8.357  ; 8.357  ; 8.357  ; 8.357  ;
; UDSn         ; CA1_OUT       ; 8.041  ;        ;        ; 8.041  ;
; UDSn         ; CD[0]         ; 8.893  ; 8.850  ; 8.850  ; 8.893  ;
; UDSn         ; CD[1]         ; 8.815  ; 8.772  ; 8.772  ; 8.815  ;
; UDSn         ; CD[2]         ; 8.068  ; 8.068  ; 8.068  ; 8.068  ;
; UDSn         ; CD[3]         ; 8.984  ; 8.843  ; 8.843  ; 8.984  ;
; UDSn         ; CD[4]         ; 8.337  ; 8.337  ; 8.337  ; 8.337  ;
; UDSn         ; CD[5]         ; 8.329  ; 8.329  ; 8.329  ; 8.329  ;
; UDSn         ; CD[6]         ; 8.479  ; 8.479  ; 8.479  ; 8.479  ;
; UDSn         ; CD[7]         ; 8.173  ; 8.173  ; 8.173  ; 8.173  ;
; UDSn         ; DATA[0]       ; 9.546  ; 9.546  ; 9.546  ; 9.546  ;
; UDSn         ; DATA[1]       ; 9.546  ; 9.546  ; 9.546  ; 9.546  ;
; UDSn         ; DATA[2]       ; 9.398  ; 9.398  ; 9.398  ; 9.398  ;
; UDSn         ; DATA[3]       ; 9.398  ; 9.398  ; 9.398  ; 9.398  ;
; UDSn         ; DATA[4]       ; 9.419  ; 9.419  ; 9.419  ; 9.419  ;
; UDSn         ; DATA[5]       ; 9.419  ; 9.419  ; 9.419  ; 9.419  ;
; UDSn         ; DATA[6]       ; 9.257  ; 9.257  ; 9.257  ; 9.257  ;
; UDSn         ; DATA[7]       ; 9.247  ; 9.247  ; 9.247  ; 9.247  ;
; UDSn         ; DATA[8]       ; 9.374  ; 9.374  ; 9.374  ; 9.374  ;
; UDSn         ; DATA[9]       ; 9.374  ; 9.374  ; 9.374  ; 9.374  ;
; UDSn         ; DATA[10]      ; 8.901  ; 9.511  ; 9.511  ; 8.901  ;
; UDSn         ; DATA[11]      ; 9.511  ; 9.511  ; 9.511  ; 9.511  ;
; UDSn         ; DATA[12]      ; 9.554  ; 9.554  ; 9.554  ; 9.554  ;
; UDSn         ; DATA[13]      ; 9.554  ; 9.554  ; 9.554  ; 9.554  ;
; UDSn         ; DATA[14]      ; 9.286  ; 9.526  ; 9.526  ; 9.286  ;
; UDSn         ; DATA[15]      ; 9.516  ; 9.516  ; 9.516  ; 9.516  ;
; UDSn         ; DTACKn        ; 8.979  ; 8.979  ; 8.979  ; 8.979  ;
; UDSn         ; JOY_RHn       ; 7.191  ;        ;        ; 7.191  ;
; UDSn         ; RAM_CAS0n     ; 7.834  ;        ;        ; 7.834  ;
; UDSn         ; RAM_DATA[0]   ; 10.261 ; 10.962 ; 10.962 ; 10.261 ;
; UDSn         ; RAM_DATA[1]   ; 10.589 ; 10.970 ; 10.970 ; 10.589 ;
; UDSn         ; RAM_DATA[2]   ; 10.352 ; 11.008 ; 11.008 ; 10.352 ;
; UDSn         ; RAM_DATA[3]   ; 10.708 ; 11.021 ; 11.021 ; 10.708 ;
; UDSn         ; RAM_DATA[4]   ; 10.516 ; 11.102 ; 11.102 ; 10.516 ;
; UDSn         ; RAM_DATA[5]   ; 11.258 ; 11.696 ; 11.696 ; 11.258 ;
; UDSn         ; RAM_DATA[6]   ; 10.755 ; 11.032 ; 11.032 ; 10.755 ;
; UDSn         ; RAM_DATA[7]   ; 10.821 ; 11.315 ; 11.315 ; 10.821 ;
; UDSn         ; RAM_DATA[8]   ; 10.226 ; 10.999 ; 10.999 ; 10.226 ;
; UDSn         ; RAM_DATA[9]   ; 10.811 ; 11.225 ; 11.225 ; 10.811 ;
; UDSn         ; RAM_DATA[10]  ; 9.497  ; 10.537 ; 10.537 ; 9.497  ;
; UDSn         ; RAM_DATA[11]  ; 10.182 ; 10.439 ; 10.439 ; 10.182 ;
; UDSn         ; RAM_DATA[12]  ; 9.899  ; 10.376 ; 10.376 ; 9.899  ;
; UDSn         ; RAM_DATA[13]  ; 10.442 ; 11.113 ; 11.113 ; 10.442 ;
; UDSn         ; RAM_DATA[14]  ; 10.155 ; 10.559 ; 10.559 ; 10.155 ;
; UDSn         ; RAM_DATA[15]  ; 10.310 ; 11.062 ; 11.062 ; 10.310 ;
; UDSn         ; RAM_DQM0H     ; 7.273  ;        ;        ; 7.273  ;
+--------------+---------------+--------+--------+--------+--------+


+-------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                     ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise   ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 9.324  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 9.366  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 9.360  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 9.335  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 9.360  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 9.324  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 9.324  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 9.340  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 9.340  ;      ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 8.269  ;      ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 8.505  ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 6.025  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 6.702  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 6.702  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 6.691  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 6.691  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 6.701  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 6.691  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 6.648  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 6.648  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 6.547  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 6.547  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 6.357  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 6.347  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 6.134  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 6.124  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 6.025  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 6.025  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 6.337  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 6.617  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 6.617  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 6.658  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 6.672  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 6.682  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 6.658  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 5.974  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 16.647 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 16.689 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 16.683 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 16.658 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 16.683 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 16.647 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 16.647 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 16.663 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 16.663 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 6.449  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 14.935 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 15.234 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 15.234 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 15.086 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 15.086 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 15.107 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 15.107 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 14.945 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 14.935 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 15.062 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 15.062 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 15.199 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 15.199 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 15.242 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 15.242 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 15.214 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 15.204 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 3.653  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 15.828 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 6.067  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 6.249  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 6.067  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 6.067  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 3.369  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 5.408  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 2.662  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 2.764  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 2.662  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 2.662  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.108  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.108  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 3.232  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 3.232  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 2.816  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 15.415 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 15.415 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 15.417 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 15.417 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 15.742 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 15.742 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 16.054 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 15.964 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 16.054 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 15.636 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 15.636 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 15.553 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 15.543 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 15.543 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 15.543 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 15.418 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 15.418 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 5.355  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 2.896  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 3.946  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.009  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 4.861  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 4.866  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 4.866  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 4.861  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 4.861  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 5.000  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 5.000  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 5.102  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 5.102  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.019  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 4.876  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.691  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.009  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.019  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.392  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.236  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 5.408  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 3.358  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 4.462  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 5.139  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 5.139  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 5.128  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 5.128  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 5.138  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 5.128  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 5.085  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 5.085  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 4.984  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 4.984  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 4.794  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 4.784  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 4.571  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 4.561  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 4.462  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 4.462  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 4.774  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 5.054  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 5.054  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 5.095  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 5.109  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 5.119  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 5.095  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 3.793  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 18.712 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 18.754 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 18.748 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 18.723 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 18.748 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 18.712 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 18.712 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 18.728 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 18.728 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 17.000 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 17.299 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 17.299 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 17.151 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 17.151 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 17.172 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 17.172 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 17.010 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 17.000 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 17.127 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 17.127 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 17.264 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 17.264 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 17.307 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 17.307 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 17.279 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 17.269 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 17.893 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.883  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 4.065  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.883  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.883  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 3.227  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 17.480 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 17.480 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 17.482 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 17.482 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 17.807 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 17.807 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 18.119 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 18.029 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 18.119 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 17.701 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 17.701 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 17.618 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 17.608 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 17.608 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 17.608 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 17.483 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 17.483 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 3.174  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 3.227  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 2.839  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 6.025  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 6.702  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 6.702  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 6.691  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 6.691  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 6.701  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 6.691  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 6.648  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 6.648  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 6.547  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 6.547  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 6.357  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 6.347  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 6.134  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 6.124  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 6.025  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 6.025  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 6.337  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 6.617  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 6.617  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 6.658  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 6.672  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 6.682  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 6.658  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 5.974  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 16.647 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 16.689 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 16.683 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 16.658 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 16.683 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 16.647 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 16.647 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 16.663 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 16.663 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 6.449  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 14.935 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 15.234 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 15.234 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 15.086 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 15.086 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 15.107 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 15.107 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 14.945 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 14.935 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 15.062 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 15.062 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 15.199 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 15.199 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 15.242 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 15.242 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 15.214 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 15.204 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 3.653  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 15.828 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 6.067  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 6.249  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 6.067  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 6.067  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 3.369  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 5.408  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 2.662  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 2.764  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 2.662  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 2.662  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.108  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.108  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 3.232  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 3.232  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 2.816  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 15.415 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 15.415 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 15.417 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 15.417 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 15.742 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 15.742 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 16.054 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 15.964 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 16.054 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 15.636 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 15.636 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 15.553 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 15.543 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 15.543 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 15.543 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 15.418 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 15.418 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 5.355  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 2.896  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 3.946  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.009  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 4.861  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 4.866  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 4.866  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 4.861  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 4.861  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 5.000  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 5.000  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 5.102  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 5.102  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.019  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 4.876  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.691  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.009  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.019  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.392  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.236  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 5.408  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.358  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 4.462  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 5.139  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 5.139  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 5.128  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 5.128  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 5.138  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 5.128  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 5.085  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 5.085  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 4.984  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 4.984  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 4.794  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 4.784  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 4.571  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 4.561  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 4.462  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 4.462  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 4.774  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 5.054  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 5.054  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 5.095  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 5.109  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 5.119  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 5.095  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 3.793  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 18.712 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 18.754 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 18.748 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 18.723 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 18.748 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 18.712 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 18.712 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 18.728 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 18.728 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 17.000 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 17.299 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 17.299 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 17.151 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 17.151 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 17.172 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 17.172 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 17.010 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 17.000 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 17.127 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 17.127 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 17.264 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 17.264 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 17.307 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 17.307 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 17.279 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 17.269 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 17.893 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.883  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 4.065  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.883  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.883  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.227  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 17.480 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 17.480 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 17.482 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 17.482 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 17.807 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 17.807 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 18.119 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 18.029 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 18.119 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 17.701 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 17.701 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 17.618 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 17.608 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 17.608 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 17.608 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 17.483 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 17.483 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.174  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.227  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 2.839  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 4.091  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 6.959  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 7.001  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 6.995  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 6.970  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 6.995  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 6.959  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 6.959  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 6.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 6.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 5.904  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 6.140  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 3.787  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 3.969  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 3.787  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 3.787  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 3.525  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 5.798  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 5.798  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 5.800  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 5.800  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 6.125  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 6.125  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 6.437  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 6.347  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 6.437  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 6.019  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 6.019  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 5.936  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 5.926  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 5.926  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 5.926  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 5.801  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 5.801  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 3.472  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.889  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 5.024  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 4.087  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.818  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.823  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.823  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.818  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.818  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.957  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.957  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 4.059  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 4.059  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 4.092  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 3.833  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 3.764  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 4.082  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 4.092  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 4.384  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 4.229  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 3.525  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 6.153  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 4.091  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 6.959  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 7.001  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 6.995  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 6.970  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 6.995  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 6.959  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 6.959  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 6.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 6.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 5.904  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 6.140  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.787  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.969  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.787  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.787  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.525  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 5.798  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 5.798  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 5.800  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 5.800  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 6.125  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 6.125  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 6.437  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 6.347  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 6.437  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 6.019  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 6.019  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 5.936  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 5.926  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 5.926  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 5.926  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 5.801  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 5.801  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.472  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.889  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 5.024  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 4.087  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.818  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.823  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.823  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.818  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.818  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.957  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.957  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 4.059  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 4.059  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 4.092  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.833  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 3.764  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 4.082  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 4.092  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 4.384  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 4.229  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.525  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 6.153  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 4.084  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 4.084  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 4.084  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 4.263  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 4.263  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 4.084  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 4.084  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 4.084  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 4.263  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 4.263  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                            ;
+---------------+---------------+-------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise  ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-------+------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 8.317 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 8.359 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 8.353 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 8.328 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 8.353 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 8.317 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 8.317 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 8.333 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 8.333 ;      ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 8.269 ;      ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 8.348 ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 3.207 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.884 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.884 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.873 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.873 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.883 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.873 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.830 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.830 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.729 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.729 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.539 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.529 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.316 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.306 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.207 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.207 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.519 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.799 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.799 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.840 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.854 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.864 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.840 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 3.323 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 3.338 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 3.380 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 3.374 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 3.349 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 3.374 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 3.338 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 3.338 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 3.354 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 3.354 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 3.644 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 3.866 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 4.165 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 4.165 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 4.017 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 4.017 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 4.038 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 4.038 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 3.876 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 3.866 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 3.993 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 3.993 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 4.130 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 4.130 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 4.173 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 4.173 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 4.145 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 4.135 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 3.306 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 4.311 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.417 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 3.599 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.417 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.417 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 3.369 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 2.757 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 2.662 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 2.764 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 2.662 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 2.662 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.108 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.108 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 3.232 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 3.232 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 2.816 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 5.550 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 5.550 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 5.552 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 5.552 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 5.877 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 5.877 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 6.189 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 6.099 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 6.189 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 5.771 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 5.771 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 5.688 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 5.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 5.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 5.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 5.553 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 5.553 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 2.704 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 2.566 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 3.946 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.009 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 2.613 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 2.618 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 2.618 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 2.613 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 2.613 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 2.752 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 2.752 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 2.854 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 2.854 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.019 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 2.628 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.691 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.009 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.019 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.061 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 2.906 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 2.757 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 3.358 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 3.340 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 4.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 4.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 4.006 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 4.006 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 4.016 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 4.006 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.963 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.963 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.862 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.862 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.662 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.449 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.439 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.340 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.340 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.652 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.932 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.932 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.973 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.987 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.997 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.973 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 3.323 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 6.723 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 6.765 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 6.759 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 6.734 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 6.759 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 6.723 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 6.723 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 6.739 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 6.739 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 4.748 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 5.047 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 5.047 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 4.899 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 4.899 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 4.920 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 4.920 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 4.758 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 4.748 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 4.875 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 4.875 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 5.012 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 5.012 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 5.055 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 5.055 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 5.027 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 5.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 5.121 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.288 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 3.470 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.288 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.288 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 2.757 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 5.527 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 5.527 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 5.529 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 5.529 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 5.854 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 5.854 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 6.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 6.076 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 6.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 5.748 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 5.748 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 5.665 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 5.655 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 5.655 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 5.655 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 5.530 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 5.530 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 2.704 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 2.757 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 2.839 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.207 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.884 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.884 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.873 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.873 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.883 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.873 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.830 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.830 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.729 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.729 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.539 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.529 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.316 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.306 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.207 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.207 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.519 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.799 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.799 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.840 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.854 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.864 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.840 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 3.323 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 3.338 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 3.380 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 3.374 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 3.349 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 3.374 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 3.338 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 3.338 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 3.354 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 3.354 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 3.644 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 3.866 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 4.165 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 4.165 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 4.017 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 4.017 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 4.038 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 4.038 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 3.876 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 3.866 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 3.993 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 3.993 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 4.130 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 4.130 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 4.173 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 4.173 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 4.145 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 4.135 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 3.306 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 4.311 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.417 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.599 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.417 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.417 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 3.369 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 2.757 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 2.662 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 2.764 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 2.662 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 2.662 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.108 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.108 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 3.232 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 3.232 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 2.816 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 5.550 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 5.550 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 5.552 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 5.552 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 5.877 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 5.877 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 6.189 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 6.099 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 6.189 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 5.771 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 5.771 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 5.688 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 5.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 5.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 5.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 5.553 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 5.553 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 2.704 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 2.566 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 3.946 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.009 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 2.613 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 2.618 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 2.618 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 2.613 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 2.613 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 2.752 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 2.752 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 2.854 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 2.854 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.019 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 2.628 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.691 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.009 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.019 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.061 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 2.906 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 2.757 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.358 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.340 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 4.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 4.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 4.006 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 4.006 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 4.016 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 4.006 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.963 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.963 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.862 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.862 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.662 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.449 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.439 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.340 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.340 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.652 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.932 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.932 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.973 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.987 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.997 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.973 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 3.323 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 6.723 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 6.765 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 6.759 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 6.734 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 6.759 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 6.723 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 6.723 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 6.739 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 6.739 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 4.748 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 5.047 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 5.047 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 4.899 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 4.899 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 4.920 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 4.920 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 4.758 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 4.748 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 4.875 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 4.875 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 5.012 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 5.012 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 5.055 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 5.055 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 5.027 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 5.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 5.121 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.288 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.470 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.288 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.288 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 2.757 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 5.527 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 5.527 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 5.529 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 5.529 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 5.854 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 5.854 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 6.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 6.076 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 6.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 5.748 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 5.748 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 5.665 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 5.655 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 5.655 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 5.655 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 5.530 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 5.530 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 2.704 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 2.757 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 2.839 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 4.091 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 4.445 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 4.487 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 4.481 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 4.456 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 4.481 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 4.445 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 4.445 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 4.461 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 4.461 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 5.387 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 4.615 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 3.787 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 3.969 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 3.787 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 3.787 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 3.525 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 4.376 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.376 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.378 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.378 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.703 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.703 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 5.015 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.925 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 5.015 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.597 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.597 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.514 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.504 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.504 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.504 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.379 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.379 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 3.472 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.788 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 4.977 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 4.040 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.575 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.580 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.580 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.575 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.575 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.714 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.714 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 3.816 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 3.816 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 4.055 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 3.590 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 3.727 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 4.045 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 4.055 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 4.266 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 4.128 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 3.525 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 6.153 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 4.091 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 4.445 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 4.487 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 4.481 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 4.456 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 4.481 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 4.445 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 4.445 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 4.461 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 4.461 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 5.387 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 4.615 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.787 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.969 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.787 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.787 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.525 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 4.376 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.376 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.378 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.378 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.703 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.703 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 5.015 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.925 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 5.015 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.597 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.597 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.514 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.504 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.504 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.504 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.379 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.379 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.472 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.788 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 4.977 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 4.040 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.575 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.580 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.580 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.575 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.575 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.714 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.714 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 3.816 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 3.816 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 4.055 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.590 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 3.727 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 4.045 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 4.055 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 4.266 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 4.128 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.525 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 6.153 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 2.802 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 2.802 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 2.802 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 2.932 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 2.932 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 2.802 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 2.802 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 2.802 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 2.932 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 2.932 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+-------+------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 9.324     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 9.366     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 9.360     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 9.335     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 9.360     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 9.324     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 9.324     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 9.340     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 9.340     ;           ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 8.269     ;           ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 8.505     ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 6.025     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 6.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 6.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 6.691     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 6.691     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 6.701     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 6.691     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 6.648     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 6.648     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 6.547     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 6.547     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 6.357     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 6.347     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 6.134     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 6.124     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 6.025     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 6.025     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 6.337     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 6.617     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 6.617     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 6.658     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 6.672     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 6.682     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 6.658     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 5.974     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 16.647    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 16.689    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 16.683    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 16.658    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 16.683    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 16.647    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 16.647    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 16.663    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 16.663    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 6.449     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 14.935    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 15.234    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 15.234    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 15.086    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 15.086    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 15.107    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 15.107    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 14.945    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 14.935    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 15.062    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 15.062    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 15.199    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 15.199    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 15.242    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 15.242    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 15.214    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 15.204    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 3.653     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 15.828    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 6.067     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 6.249     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 6.067     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 6.067     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 3.369     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 5.408     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 2.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 2.764     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 2.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 2.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.108     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.108     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 3.232     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 3.232     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 2.816     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 15.415    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 15.415    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 15.417    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 15.417    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 15.742    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 15.742    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 16.054    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 15.964    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 16.054    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 15.636    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 15.636    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 15.553    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 15.543    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 15.543    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 15.543    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 15.418    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 15.418    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 5.355     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 2.896     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 3.946     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.009     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 4.861     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 4.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 4.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 4.861     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 4.861     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 5.000     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 5.000     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 5.102     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 5.102     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 4.876     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.691     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.009     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.392     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.236     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 5.408     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 3.358     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 4.462     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 5.139     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 5.139     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 5.128     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 5.128     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 5.138     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 5.128     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 5.085     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 5.085     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 4.984     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 4.984     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 4.794     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 4.784     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 4.571     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 4.561     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 4.462     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 4.462     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 4.774     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 5.054     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 5.054     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 5.095     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 5.109     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 5.119     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 5.095     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 3.793     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 18.712    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 18.754    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 18.748    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 18.723    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 18.748    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 18.712    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 18.712    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 18.728    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 18.728    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 17.000    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 17.299    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 17.299    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 17.151    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 17.151    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 17.172    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 17.172    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 17.010    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 17.000    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 17.127    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 17.127    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 17.264    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 17.264    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 17.307    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 17.307    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 17.279    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 17.269    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 17.893    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.883     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 4.065     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.883     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.883     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 3.227     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 17.480    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 17.480    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 17.482    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 17.482    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 17.807    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 17.807    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 18.119    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 18.029    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 18.119    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 17.701    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 17.701    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 17.618    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 17.608    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 17.608    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 17.608    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 17.483    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 17.483    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 3.174     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 3.227     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 2.839     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 6.025     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 6.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 6.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 6.691     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 6.691     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 6.701     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 6.691     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 6.648     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 6.648     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 6.547     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 6.547     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 6.357     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 6.347     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 6.134     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 6.124     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 6.025     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 6.025     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 6.337     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 6.617     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 6.617     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 6.658     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 6.672     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 6.682     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 6.658     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 5.974     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 16.647    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 16.689    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 16.683    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 16.658    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 16.683    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 16.647    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 16.647    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 16.663    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 16.663    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 6.449     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 14.935    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 15.234    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 15.234    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 15.086    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 15.086    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 15.107    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 15.107    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 14.945    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 14.935    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 15.062    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 15.062    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 15.199    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 15.199    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 15.242    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 15.242    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 15.214    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 15.204    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 3.653     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 15.828    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 6.067     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 6.249     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 6.067     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 6.067     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 3.369     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 5.408     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 2.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 2.764     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 2.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 2.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.108     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.108     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 3.232     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 3.232     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 2.816     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 15.415    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 15.415    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 15.417    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 15.417    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 15.742    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 15.742    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 16.054    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 15.964    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 16.054    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 15.636    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 15.636    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 15.553    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 15.543    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 15.543    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 15.543    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 15.418    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 15.418    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 5.355     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 2.896     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 3.946     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.009     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 4.861     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 4.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 4.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 4.861     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 4.861     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 5.000     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 5.000     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 5.102     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 5.102     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 4.876     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.691     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.009     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.392     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.236     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 5.408     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.358     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 4.462     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 5.139     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 5.139     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 5.128     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 5.128     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 5.138     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 5.128     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 5.085     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 5.085     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 4.984     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 4.984     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 4.794     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 4.784     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 4.571     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 4.561     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 4.462     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 4.462     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 4.774     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 5.054     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 5.054     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 5.095     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 5.109     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 5.119     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 5.095     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 3.793     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 18.712    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 18.754    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 18.748    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 18.723    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 18.748    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 18.712    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 18.712    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 18.728    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 18.728    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 17.000    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 17.299    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 17.299    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 17.151    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 17.151    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 17.172    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 17.172    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 17.010    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 17.000    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 17.127    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 17.127    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 17.264    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 17.264    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 17.307    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 17.307    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 17.279    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 17.269    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 17.893    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.883     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 4.065     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.883     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.883     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.227     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 17.480    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 17.480    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 17.482    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 17.482    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 17.807    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 17.807    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 18.119    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 18.029    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 18.119    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 17.701    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 17.701    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 17.618    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 17.608    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 17.608    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 17.608    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 17.483    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 17.483    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.174     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.227     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 2.839     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 4.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 6.959     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 7.001     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 6.995     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 6.970     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 6.995     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 6.959     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 6.959     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 6.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 6.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 5.904     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 6.140     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 3.787     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 3.969     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 3.787     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 3.787     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 3.525     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 5.798     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 5.798     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 5.800     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 5.800     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 6.125     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 6.125     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 6.437     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 6.347     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 6.437     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 6.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 6.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 5.936     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 5.926     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 5.926     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 5.926     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 5.801     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 5.801     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 3.472     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.889     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 5.024     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 4.087     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.818     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.823     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.823     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.818     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.818     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.957     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.957     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 4.059     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 4.059     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 4.092     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 3.833     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 3.764     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 4.082     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 4.092     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 4.384     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 4.229     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 3.525     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 6.153     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 4.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 6.959     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 7.001     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 6.995     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 6.970     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 6.995     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 6.959     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 6.959     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 6.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 6.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 5.904     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 6.140     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.787     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.969     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.787     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.787     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.525     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 5.798     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 5.798     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 5.800     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 5.800     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 6.125     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 6.125     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 6.437     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 6.347     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 6.437     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 6.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 6.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 5.936     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 5.926     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 5.926     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 5.926     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 5.801     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 5.801     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.472     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.889     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 5.024     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 4.087     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.818     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.823     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.823     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.818     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.818     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.957     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.957     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 4.059     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 4.059     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 4.092     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.833     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 3.764     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 4.082     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 4.092     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 4.384     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 4.229     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.525     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 6.153     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 4.084     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 4.084     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 4.084     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 4.263     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 4.263     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 4.084     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 4.084     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 4.084     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 4.263     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 4.263     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                    ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 8.317     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 8.359     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 8.353     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 8.328     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 8.353     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 8.317     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 8.317     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 8.333     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 8.333     ;           ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 8.269     ;           ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 8.348     ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 3.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.884     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.884     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.873     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.873     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.873     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.830     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.830     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.729     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.729     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.539     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.529     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.316     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.306     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.519     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.799     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.799     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.840     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.854     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.864     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.840     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 3.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 3.338     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 3.380     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 3.374     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 3.349     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 3.374     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 3.338     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 3.338     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 3.354     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 3.354     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 3.644     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 3.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 4.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 4.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 4.017     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 4.017     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 4.038     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 4.038     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 3.876     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 3.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 3.993     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 3.993     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 4.130     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 4.130     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 4.173     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 4.173     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 4.145     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 4.135     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 3.306     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 4.311     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.417     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 3.599     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.417     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.417     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 3.369     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 2.757     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 2.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 2.764     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 2.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 2.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.108     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.108     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 3.232     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 3.232     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 2.816     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 5.550     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 5.550     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 5.552     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 5.552     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 5.877     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 5.877     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 6.189     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 6.099     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 6.189     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 5.771     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 5.771     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 5.688     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 5.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 5.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 5.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 5.553     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 5.553     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 2.704     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 2.566     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 3.946     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.009     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 2.613     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 2.618     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 2.618     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 2.613     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 2.613     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 2.752     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 2.752     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 2.854     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 2.854     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 2.628     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.691     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.009     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.061     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 2.906     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 2.757     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 3.358     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 3.340     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 4.017     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 4.017     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 4.006     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 4.006     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 4.016     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 4.006     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.963     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.963     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.862     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.862     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.662     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.449     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.439     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.340     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.340     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.652     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.932     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.932     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.973     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.987     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.997     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.973     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 3.323     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 6.723     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 6.765     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 6.759     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 6.734     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 6.759     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 6.723     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 6.723     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 6.739     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 6.739     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 4.748     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 5.047     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 5.047     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 4.899     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 4.899     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 4.920     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 4.920     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 4.758     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 4.748     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 4.875     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 4.875     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 5.012     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 5.012     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 5.055     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 5.055     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 5.027     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 5.017     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 5.121     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.288     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 3.470     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.288     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.288     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 2.757     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 5.527     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 5.527     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 5.529     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 5.529     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 5.854     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 5.854     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 6.166     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 6.076     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 6.166     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 5.748     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 5.748     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 5.665     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 5.655     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 5.655     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 5.655     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 5.530     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 5.530     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 2.704     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 2.757     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 2.839     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.884     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.884     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.873     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.873     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.873     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.830     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.830     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.729     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.729     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.539     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.529     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.316     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.306     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.519     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.799     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.799     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.840     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.854     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.864     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.840     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 3.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 3.338     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 3.380     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 3.374     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 3.349     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 3.374     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 3.338     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 3.338     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 3.354     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 3.354     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 3.644     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 3.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 4.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 4.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 4.017     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 4.017     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 4.038     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 4.038     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 3.876     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 3.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 3.993     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 3.993     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 4.130     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 4.130     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 4.173     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 4.173     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 4.145     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 4.135     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 3.306     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 4.311     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.417     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.599     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.417     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.417     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 3.369     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 2.757     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 2.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 2.764     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 2.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 2.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.108     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.108     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 3.232     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 3.232     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 2.816     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 5.550     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 5.550     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 5.552     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 5.552     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 5.877     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 5.877     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 6.189     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 6.099     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 6.189     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 5.771     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 5.771     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 5.688     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 5.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 5.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 5.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 5.553     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 5.553     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 2.704     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 2.566     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 3.946     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.009     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 2.613     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 2.618     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 2.618     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 2.613     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 2.613     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 2.752     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 2.752     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 2.854     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 2.854     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 2.628     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.691     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.009     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.061     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 2.906     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 2.757     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.358     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.340     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 4.017     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 4.017     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 4.006     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 4.006     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 4.016     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 4.006     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.963     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.963     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.862     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.862     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.662     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.449     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.439     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.340     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.340     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.652     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.932     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.932     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.973     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.987     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.997     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.973     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 3.323     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 6.723     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 6.765     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 6.759     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 6.734     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 6.759     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 6.723     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 6.723     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 6.739     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 6.739     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 4.748     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 5.047     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 5.047     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 4.899     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 4.899     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 4.920     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 4.920     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 4.758     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 4.748     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 4.875     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 4.875     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 5.012     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 5.012     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 5.055     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 5.055     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 5.027     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 5.017     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 5.121     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.288     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.470     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.288     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.288     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 2.757     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 5.527     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 5.527     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 5.529     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 5.529     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 5.854     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 5.854     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 6.166     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 6.076     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 6.166     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 5.748     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 5.748     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 5.665     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 5.655     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 5.655     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 5.655     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 5.530     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 5.530     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 2.704     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 2.757     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 2.839     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 4.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 4.445     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 4.487     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 4.481     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 4.456     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 4.481     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 4.445     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 4.445     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 4.461     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 4.461     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 5.387     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 4.615     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 3.787     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 3.969     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 3.787     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 3.787     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 3.525     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 4.376     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.376     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.378     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.378     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.703     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.703     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 5.015     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.925     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 5.015     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.597     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.597     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.514     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.504     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.504     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.504     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.379     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.379     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 3.472     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.788     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 4.977     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 4.040     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.575     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.575     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.575     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.714     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.714     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 3.816     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 3.816     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 4.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 3.590     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 3.727     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 4.045     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 4.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 4.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 4.128     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 3.525     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 6.153     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 4.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 4.445     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 4.487     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 4.481     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 4.456     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 4.481     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 4.445     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 4.445     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 4.461     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 4.461     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 5.387     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 4.615     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.787     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.969     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.787     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.787     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.525     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 4.376     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.376     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.378     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.378     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.703     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.703     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 5.015     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.925     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 5.015     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.597     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.597     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.514     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.504     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.504     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.504     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.379     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.379     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.472     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.788     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 4.977     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 4.040     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.575     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.575     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.575     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.714     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.714     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 3.816     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 3.816     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 4.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.590     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 3.727     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 4.045     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 4.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 4.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 4.128     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.525     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 6.153     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 2.802     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 2.802     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 2.802     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 2.932     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 2.932     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 2.802     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 2.802     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 2.802     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 2.932     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 2.932     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                          ;
+-------------------------------------------------------------+------------+--------+----------+---------+---------------------+
; Clock                                                       ; Setup      ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
+-------------------------------------------------------------+------------+--------+----------+---------+---------------------+
; Worst-case Slack                                            ; -36.638    ; -0.086 ; 22.437   ; 1.015   ; 7.852               ;
;  CLK_PLL1                                                   ; 59.666     ; 0.245  ; N/A      ; N/A     ; 30.139              ;
;  CLK_PLL2                                                   ; N/A        ; N/A    ; N/A      ; N/A     ; 31.250              ;
;  CODEC_SCLK                                                 ; 27.313     ; -0.086 ; 78.982   ; 1.015   ; 38.136              ;
;  CRT_PIN4_CLK1                                              ; N/A        ; N/A    ; N/A      ; N/A     ; 31.250              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -19.476    ; -0.065 ; 22.437   ; 1.433   ; 30.139              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -19.476    ; -0.065 ; 22.437   ; 1.433   ; 30.139              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; -21.205    ; 0.215  ; 22.439   ; 1.054   ; 13.061              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; -21.205    ; 0.215  ; 22.439   ; 1.054   ; 13.061              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; -36.638    ; 0.215  ; N/A      ; N/A     ; 7.852               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; -36.638    ; 0.215  ; N/A      ; N/A     ; 7.852               ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 38.199     ; 0.215  ; N/A      ; N/A     ; 18.420              ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 23.160     ; 0.215  ; N/A      ; N/A     ; 11.584              ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 60.589     ; 0.215  ; N/A      ; N/A     ; 30.139              ;
; Design-wide TNS                                             ; -76883.546 ; -0.263 ; 0.0      ; 0.0     ; 0.0                 ;
;  CLK_PLL1                                                   ; 0.000      ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  CLK_PLL2                                                   ; N/A        ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  CODEC_SCLK                                                 ; 0.000      ; -0.248 ; 0.000    ; 0.000   ; 0.000               ;
;  CRT_PIN4_CLK1                                              ; N/A        ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -32535.297 ; -0.065 ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -32535.297 ; -0.065 ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; -4262.856  ; 0.000  ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; -4262.856  ; 0.000  ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; -1643.620  ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; -1643.620  ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 0.000      ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 0.000      ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 0.000      ; 0.000  ; N/A      ; N/A     ; 0.000               ;
+-------------------------------------------------------------+------------+--------+----------+---------+---------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; -0.716 ; -0.716 ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; 9.690  ; 9.690  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; -0.229 ; -0.229 ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; 12.212 ; 12.212 ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; 28.330 ; 28.330 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 12.525 ; 12.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 8.479  ; 8.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 10.036 ; 10.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 9.145  ; 9.145  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 10.036 ; 10.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 9.174  ; 9.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 8.946  ; 8.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 9.473  ; 9.473  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 9.213  ; 9.213  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 8.847  ; 8.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 8.614  ; 8.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 19.699 ; 19.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 20.630 ; 20.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 18.483 ; 18.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; 11.955 ; 11.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 20.934 ; 20.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 19.948 ; 19.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 19.812 ; 19.812 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 20.934 ; 20.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 16.614 ; 16.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 14.932 ; 14.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 19.045 ; 19.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 15.149 ; 15.149 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 15.039 ; 15.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 15.797 ; 15.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 16.028 ; 16.028 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 15.531 ; 15.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 16.926 ; 16.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 16.614 ; 16.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 16.502 ; 16.502 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 18.994 ; 18.994 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 19.025 ; 19.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 16.647 ; 16.647 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 17.407 ; 17.407 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 16.923 ; 16.923 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 17.419 ; 17.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 17.797 ; 17.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 19.045 ; 19.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 7.576  ; 7.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 11.848 ; 11.848 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 30.458 ; 30.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 30.458 ; 30.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 30.423 ; 30.423 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 30.363 ; 30.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; 13.335 ; 13.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; 8.072  ; 8.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; 10.798 ; 10.798 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; 15.200 ; 15.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; 9.231  ; 9.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 18.897 ; 18.897 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 9.610  ; 9.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 18.638 ; 18.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; 7.203  ; 7.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 29.678 ; 29.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 19.079 ; 19.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 19.044 ; 19.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 17.629 ; 17.629 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 17.251 ; 17.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 16.697 ; 16.697 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 16.182 ; 16.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 17.223 ; 17.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 17.845 ; 17.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 17.194 ; 17.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 19.044 ; 19.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; 5.970  ; 5.970  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; 5.069  ; 5.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; 4.715  ; 4.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; 4.459  ; 4.459  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; 4.186  ; 4.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; 3.799  ; 3.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 20.538 ; 20.538 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 16.890 ; 16.890 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 16.714 ; 16.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 16.725 ; 16.725 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 17.165 ; 17.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 16.418 ; 16.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 17.938 ; 17.938 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 19.801 ; 19.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 17.606 ; 17.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 18.666 ; 18.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 19.553 ; 19.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 17.749 ; 17.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 19.118 ; 19.118 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 17.510 ; 17.510 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 18.270 ; 18.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 19.153 ; 19.153 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 20.538 ; 20.538 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; 8.425  ; 8.425  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 7.657  ; 7.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 30.460 ; 30.460 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 11.123 ; 11.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 10.032 ; 10.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 10.589 ; 10.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 9.586  ; 9.586  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 9.835  ; 9.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 9.005  ; 9.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 9.215  ; 9.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 10.021 ; 10.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 9.589  ; 9.589  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 9.801  ; 9.801  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 10.589 ; 10.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 13.915 ; 13.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 13.833 ; 13.833 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 12.858 ; 12.858 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 13.229 ; 13.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 9.886  ; 9.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; 14.077 ; 14.077 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; 7.882  ; 7.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; 12.785 ; 12.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 23.589 ; 23.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; 9.268  ; 9.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; 8.399  ; 8.399  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; 9.182  ; 9.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; 8.365  ; 8.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; 9.182  ; 9.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; 8.658  ; 8.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; 7.967  ; 7.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; 8.435  ; 8.435  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; 7.800  ; 7.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 7.812  ; 7.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 28.361 ; 28.361 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 8.270  ; 8.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 26.622 ; 26.622 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 7.981  ; 7.981  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 7.164  ; 7.164  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 9.601  ; 9.601  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; 7.460  ; 7.460  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 18.763 ; 18.763 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 19.868 ; 19.868 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 17.762 ; 17.762 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 19.427 ; 19.427 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 19.387 ; 19.387 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 19.251 ; 19.251 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 19.427 ; 19.427 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 16.053 ; 16.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 14.371 ; 14.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 18.202 ; 18.202 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 14.331 ; 14.331 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 14.277 ; 14.277 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 14.861 ; 14.861 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 15.079 ; 15.079 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 15.097 ; 15.097 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 16.414 ; 16.414 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 15.893 ; 15.893 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 15.941 ; 15.941 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 17.811 ; 17.811 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 18.202 ; 18.202 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 15.655 ; 15.655 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 16.598 ; 16.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 15.215 ; 15.215 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 15.833 ; 15.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 16.222 ; 16.222 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 16.582 ; 16.582 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 9.367  ; 9.367  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; 6.861  ; 6.861  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; 7.211  ; 7.211  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; 7.284  ; 7.284  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 28.750 ; 28.750 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 28.750 ; 28.750 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 28.715 ; 28.715 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 28.655 ; 28.655 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; 7.677  ; 7.677  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 9.059  ; 9.059  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 18.385 ; 18.385 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; 8.748  ; 8.748  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 18.126 ; 18.126 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 27.727 ; 27.727 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 18.261 ; 18.261 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 16.581 ; 16.581 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 16.446 ; 16.446 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 16.428 ; 16.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 15.705 ; 15.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 15.373 ; 15.373 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 15.515 ; 15.515 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 16.259 ; 16.259 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 15.619 ; 15.619 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 16.581 ; 16.581 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 19.080 ; 19.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 16.072 ; 16.072 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 15.952 ; 15.952 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 15.789 ; 15.789 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 16.216 ; 16.216 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 15.984 ; 15.984 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 17.426 ; 17.426 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 19.080 ; 19.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 17.045 ; 17.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 17.483 ; 17.483 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 18.730 ; 18.730 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 16.757 ; 16.757 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 18.309 ; 18.309 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 15.802 ; 15.802 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 16.684 ; 16.684 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 17.578 ; 17.578 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 18.075 ; 18.075 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 28.752 ; 28.752 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 22.997 ; 22.997 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 6.951  ; 6.951  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; 6.402  ; 6.402  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 26.525 ; 26.525 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; 7.551  ; 7.551  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; 28.330 ; 28.330 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 12.525 ; 12.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 8.479  ; 8.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 10.036 ; 10.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 9.145  ; 9.145  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 10.036 ; 10.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 9.174  ; 9.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 8.946  ; 8.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 9.473  ; 9.473  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 9.213  ; 9.213  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 8.847  ; 8.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 8.614  ; 8.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 19.699 ; 19.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 20.630 ; 20.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 18.483 ; 18.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; 11.955 ; 11.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 20.934 ; 20.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 19.948 ; 19.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 19.812 ; 19.812 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 20.934 ; 20.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 16.614 ; 16.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 14.932 ; 14.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 19.045 ; 19.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 15.149 ; 15.149 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 15.039 ; 15.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 15.797 ; 15.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 16.028 ; 16.028 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 15.531 ; 15.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 16.926 ; 16.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 16.614 ; 16.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 16.502 ; 16.502 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 18.994 ; 18.994 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 19.025 ; 19.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 16.647 ; 16.647 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 17.407 ; 17.407 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 16.923 ; 16.923 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 17.419 ; 17.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 17.797 ; 17.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 19.045 ; 19.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 7.576  ; 7.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 11.848 ; 11.848 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 30.458 ; 30.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 30.458 ; 30.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 30.423 ; 30.423 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 30.363 ; 30.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; 13.335 ; 13.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; 8.072  ; 8.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; 10.798 ; 10.798 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; 15.200 ; 15.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; 9.231  ; 9.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 18.897 ; 18.897 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.610  ; 9.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 18.638 ; 18.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; 7.203  ; 7.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 29.678 ; 29.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 19.079 ; 19.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 19.044 ; 19.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 17.629 ; 17.629 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 17.251 ; 17.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 16.697 ; 16.697 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 16.182 ; 16.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 17.223 ; 17.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 17.845 ; 17.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 17.194 ; 17.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 19.044 ; 19.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; 5.970  ; 5.970  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; 5.069  ; 5.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; 4.715  ; 4.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; 4.459  ; 4.459  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; 4.186  ; 4.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; 3.799  ; 3.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 20.538 ; 20.538 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 16.890 ; 16.890 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 16.714 ; 16.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 16.725 ; 16.725 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 17.165 ; 17.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 16.418 ; 16.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 17.938 ; 17.938 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 19.801 ; 19.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 17.606 ; 17.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 18.666 ; 18.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 19.553 ; 19.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 17.749 ; 17.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 19.118 ; 19.118 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 17.510 ; 17.510 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 18.270 ; 18.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 19.153 ; 19.153 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 20.538 ; 20.538 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; 8.425  ; 8.425  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 7.657  ; 7.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 30.460 ; 30.460 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 11.123 ; 11.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 10.032 ; 10.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 10.589 ; 10.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 9.586  ; 9.586  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 9.835  ; 9.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 9.005  ; 9.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 9.215  ; 9.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 10.021 ; 10.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 9.589  ; 9.589  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 9.801  ; 9.801  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 10.589 ; 10.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 13.915 ; 13.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 13.833 ; 13.833 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 12.858 ; 12.858 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 13.229 ; 13.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 9.886  ; 9.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; 14.077 ; 14.077 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; 7.882  ; 7.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; 12.785 ; 12.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 23.589 ; 23.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; 9.268  ; 9.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; 8.399  ; 8.399  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; 9.182  ; 9.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; 8.365  ; 8.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; 9.182  ; 9.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; 8.658  ; 8.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; 7.967  ; 7.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; 8.435  ; 8.435  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; 7.800  ; 7.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 7.812  ; 7.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 28.361 ; 28.361 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 8.270  ; 8.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 26.622 ; 26.622 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 7.981  ; 7.981  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 7.164  ; 7.164  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 9.601  ; 9.601  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; 7.460  ; 7.460  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 18.763 ; 18.763 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 19.868 ; 19.868 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 17.762 ; 17.762 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 19.427 ; 19.427 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 19.387 ; 19.387 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 19.251 ; 19.251 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 19.427 ; 19.427 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 16.053 ; 16.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 14.371 ; 14.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 18.202 ; 18.202 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 14.331 ; 14.331 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 14.277 ; 14.277 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 14.861 ; 14.861 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 15.079 ; 15.079 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 15.097 ; 15.097 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 16.414 ; 16.414 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 15.893 ; 15.893 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 15.941 ; 15.941 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 17.811 ; 17.811 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 18.202 ; 18.202 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 15.655 ; 15.655 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 16.598 ; 16.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 15.215 ; 15.215 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 15.833 ; 15.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 16.222 ; 16.222 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 16.582 ; 16.582 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 9.367  ; 9.367  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; 6.861  ; 6.861  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; 7.211  ; 7.211  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; 7.284  ; 7.284  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 28.750 ; 28.750 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 28.750 ; 28.750 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 28.715 ; 28.715 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 28.655 ; 28.655 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; 7.677  ; 7.677  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 9.059  ; 9.059  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 18.385 ; 18.385 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; 8.748  ; 8.748  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 18.126 ; 18.126 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 27.727 ; 27.727 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 18.261 ; 18.261 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 16.581 ; 16.581 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 16.446 ; 16.446 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 16.428 ; 16.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 15.705 ; 15.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 15.373 ; 15.373 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 15.515 ; 15.515 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 16.259 ; 16.259 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 15.619 ; 15.619 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 16.581 ; 16.581 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 19.080 ; 19.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 16.072 ; 16.072 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 15.952 ; 15.952 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 15.789 ; 15.789 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 16.216 ; 16.216 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 15.984 ; 15.984 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 17.426 ; 17.426 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 19.080 ; 19.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 17.045 ; 17.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 17.483 ; 17.483 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 18.730 ; 18.730 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 16.757 ; 16.757 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 18.309 ; 18.309 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 15.802 ; 15.802 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 16.684 ; 16.684 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 17.578 ; 17.578 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 18.075 ; 18.075 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 28.752 ; 28.752 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 22.997 ; 22.997 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 6.951  ; 6.951  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; 6.402  ; 6.402  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 26.525 ; 26.525 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; 7.551  ; 7.551  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; 24.867 ; 24.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; 18.131 ; 18.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; 18.619 ; 18.619 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; 16.383 ; 16.383 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 18.615 ; 18.615 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; 18.615 ; 18.615 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; 18.479 ; 18.479 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; 12.840 ; 12.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; 18.429 ; 18.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; 15.281 ; 15.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 13.599 ; 13.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 16.346 ; 16.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 13.553 ; 13.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 13.028 ; 13.028 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 14.229 ; 14.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 14.119 ; 14.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 13.714 ; 13.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 15.045 ; 15.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 14.514 ; 14.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 15.169 ; 15.169 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 16.346 ; 16.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; 10.597 ; 10.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 26.995 ; 26.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 26.995 ; 26.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 26.960 ; 26.960 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 26.900 ; 26.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; 17.016 ; 17.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; 16.757 ; 16.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 26.262 ; 26.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; 17.483 ; 17.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; 14.981 ; 14.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; 14.981 ; 14.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 17.701 ; 17.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 15.294 ; 15.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 14.703 ; 14.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 15.157 ; 15.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 15.256 ; 15.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 14.601 ; 14.601 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 16.057 ; 16.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 17.701 ; 17.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 16.273 ; 16.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 16.018 ; 16.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 12.220 ; 12.220 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 12.271 ; 12.271 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 12.885 ; 12.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 12.380 ; 12.380 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 12.788 ; 12.788 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 12.778 ; 12.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 12.335 ; 12.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 26.997 ; 26.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 21.869 ; 21.869 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 24.945 ; 24.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 14.362 ; 14.362 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 14.232 ; 14.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 14.232 ; 14.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 14.196 ; 14.196 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 14.131 ; 14.131 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 11.487 ; 11.487 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 14.207 ; 14.207 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; 24.867 ; 24.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 18.131 ; 18.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 18.619 ; 18.619 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 16.383 ; 16.383 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 18.615 ; 18.615 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 18.615 ; 18.615 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 18.479 ; 18.479 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; 12.840 ; 12.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 18.429 ; 18.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 15.281 ; 15.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 13.599 ; 13.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 16.346 ; 16.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 13.553 ; 13.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 13.028 ; 13.028 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 14.229 ; 14.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 14.119 ; 14.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 13.714 ; 13.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 15.045 ; 15.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 14.514 ; 14.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 15.169 ; 15.169 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 16.346 ; 16.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 10.597 ; 10.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 26.995 ; 26.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 26.995 ; 26.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 26.960 ; 26.960 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 26.900 ; 26.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 17.016 ; 17.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 16.757 ; 16.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 26.262 ; 26.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 17.483 ; 17.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 14.981 ; 14.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 14.981 ; 14.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 17.701 ; 17.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 15.294 ; 15.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 14.703 ; 14.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 15.157 ; 15.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 15.256 ; 15.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 14.601 ; 14.601 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 16.057 ; 16.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 17.701 ; 17.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 16.273 ; 16.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 16.018 ; 16.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 12.220 ; 12.220 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 12.271 ; 12.271 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 12.885 ; 12.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 12.380 ; 12.380 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.788 ; 12.788 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.778 ; 12.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 12.335 ; 12.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 26.997 ; 26.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 21.869 ; 21.869 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 24.945 ; 24.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 14.362 ; 14.362 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 14.232 ; 14.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 14.232 ; 14.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 14.196 ; 14.196 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 14.131 ; 14.131 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 11.487 ; 11.487 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 14.207 ; 14.207 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; 24.527 ; 24.527 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; 16.132 ; 16.132 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; 16.855 ; 16.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; 14.688 ; 14.688 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; 17.262 ; 17.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; 16.711 ; 16.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; 16.575 ; 16.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; 17.262 ; 17.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; 13.377 ; 13.377 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 11.695 ; 11.695 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; 15.390 ; 15.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 11.763 ; 11.763 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 11.264 ; 11.264 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 12.230 ; 12.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 12.428 ; 12.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 12.107 ; 12.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 13.270 ; 13.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 12.819 ; 12.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 13.265 ; 13.265 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 15.308 ; 15.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 15.390 ; 15.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 13.279 ; 13.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 13.809 ; 13.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 12.730 ; 12.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 13.285 ; 13.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 13.726 ; 13.726 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 15.373 ; 15.373 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; 26.655 ; 26.655 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; 26.655 ; 26.655 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; 26.620 ; 26.620 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; 26.560 ; 26.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; 15.241 ; 15.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; 14.982 ; 14.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; 26.006 ; 26.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; 15.693 ; 15.693 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 15.553 ; 15.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; 13.943 ; 13.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; 13.616 ; 13.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; 13.329 ; 13.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 15.225 ; 15.225 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 15.420 ; 15.420 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 15.348 ; 15.348 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 15.553 ; 15.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; 15.372 ; 15.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 16.866 ; 16.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 13.504 ; 13.504 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 12.939 ; 12.939 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 13.158 ; 13.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 13.565 ; 13.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 12.994 ; 12.994 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 14.282 ; 14.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 16.006 ; 16.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 14.369 ; 14.369 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 14.980 ; 14.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 15.918 ; 15.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 14.381 ; 14.381 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 15.520 ; 15.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 13.317 ; 13.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 14.136 ; 14.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 15.082 ; 15.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 16.866 ; 16.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; 26.657 ; 26.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; 20.079 ; 20.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; 24.689 ; 24.689 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; 24.527 ; 24.527 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 16.132 ; 16.132 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 16.855 ; 16.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 14.688 ; 14.688 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 17.262 ; 17.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 16.711 ; 16.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 16.575 ; 16.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 17.262 ; 17.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 13.377 ; 13.377 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 11.695 ; 11.695 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 15.390 ; 15.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 11.763 ; 11.763 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 11.264 ; 11.264 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 12.230 ; 12.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 12.428 ; 12.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 12.107 ; 12.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 13.270 ; 13.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 12.819 ; 12.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 13.265 ; 13.265 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 15.308 ; 15.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 15.390 ; 15.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 13.279 ; 13.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 13.809 ; 13.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 12.730 ; 12.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 13.285 ; 13.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 13.726 ; 13.726 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 15.373 ; 15.373 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 26.655 ; 26.655 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 26.655 ; 26.655 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 26.620 ; 26.620 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 26.560 ; 26.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 15.241 ; 15.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 14.982 ; 14.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 26.006 ; 26.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 15.693 ; 15.693 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 15.553 ; 15.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 13.943 ; 13.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 13.616 ; 13.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 13.329 ; 13.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 15.225 ; 15.225 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 15.420 ; 15.420 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 15.348 ; 15.348 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 15.553 ; 15.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 15.372 ; 15.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 16.866 ; 16.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 13.504 ; 13.504 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 12.939 ; 12.939 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 13.158 ; 13.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 13.565 ; 13.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 12.994 ; 12.994 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 14.282 ; 14.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 16.006 ; 16.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 14.369 ; 14.369 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 14.980 ; 14.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 15.918 ; 15.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 14.381 ; 14.381 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 15.520 ; 15.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 13.317 ; 13.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 14.136 ; 14.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 15.082 ; 15.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 16.866 ; 16.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 26.657 ; 26.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 20.079 ; 20.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 24.689 ; 24.689 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 1.129  ; 1.129  ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; -3.958 ; -3.958 ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; 0.621  ; 0.621  ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; -4.328 ; -4.328 ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; -3.813 ; -3.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -3.703 ; -3.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -4.322 ; -4.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; -3.456 ; -3.456 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; -3.456 ; -3.456 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; -3.543 ; -3.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; -3.693 ; -3.693 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; -3.466 ; -3.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; -3.520 ; -3.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; -3.594 ; -3.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; -3.548 ; -3.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; -3.606 ; -3.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -4.397 ; -4.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -4.096 ; -4.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -3.972 ; -3.972 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; -4.485 ; -4.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.525 ; -4.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -4.525 ; -4.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -4.575 ; -4.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -4.751 ; -4.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -2.741 ; -2.741 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -2.185 ; -2.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -4.218 ; -4.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -4.524 ; -4.524 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -4.855 ; -4.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -4.595 ; -4.595 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -4.832 ; -4.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -4.635 ; -4.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -4.757 ; -4.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -4.555 ; -4.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -4.600 ; -4.600 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -4.685 ; -4.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -5.031 ; -5.031 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -4.673 ; -4.673 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -4.996 ; -4.996 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.716 ; -4.716 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -4.436 ; -4.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -4.509 ; -4.509 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -4.218 ; -4.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; -3.971 ; -3.971 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -3.840 ; -3.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -5.316 ; -5.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -5.439 ; -5.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -5.316 ; -5.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -5.495 ; -5.495 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; -4.051 ; -4.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; -1.699 ; -1.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; -4.026 ; -4.026 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; -4.478 ; -4.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; -4.066 ; -4.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -4.470 ; -4.470 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; -3.599 ; -3.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -4.312 ; -4.312 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; -3.783 ; -3.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -4.377 ; -4.377 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -3.954 ; -3.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -5.889 ; -5.889 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.509 ; -6.509 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.275 ; -6.275 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.164 ; -6.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -5.889 ; -5.889 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -6.078 ; -6.078 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -6.268 ; -6.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -6.083 ; -6.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.552 ; -6.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; -3.236 ; -3.236 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; -1.799 ; -1.799 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; -1.587 ; -1.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; -1.470 ; -1.470 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; -1.380 ; -1.380 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; -1.278 ; -1.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.657 ; -3.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -3.657 ; -3.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.935 ; -3.935 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -3.831 ; -3.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -4.115 ; -4.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -4.093 ; -4.093 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -4.195 ; -4.195 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -4.493 ; -4.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -4.126 ; -4.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -4.376 ; -4.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -3.747 ; -3.747 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -3.830 ; -3.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -3.918 ; -3.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -3.828 ; -3.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -3.880 ; -3.880 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -4.001 ; -4.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -3.854 ; -3.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; -1.248 ; -1.248 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; -4.020 ; -4.020 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -4.049 ; -4.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; -4.124 ; -4.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; -3.679 ; -3.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; -3.238 ; -3.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; -3.434 ; -3.434 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; -3.459 ; -3.459 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; -3.238 ; -3.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; -3.274 ; -3.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; -3.578 ; -3.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; -3.498 ; -3.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; -3.600 ; -3.600 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; -3.617 ; -3.617 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; -3.672 ; -3.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; -3.721 ; -3.721 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; -3.746 ; -3.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; -3.857 ; -3.857 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; -3.835 ; -3.835 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; -4.340 ; -4.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; -4.006 ; -4.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; -4.287 ; -4.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -4.184 ; -4.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; -4.641 ; -4.641 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; -4.263 ; -4.263 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; -3.691 ; -3.691 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; -3.691 ; -3.691 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; -3.975 ; -3.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; -3.944 ; -3.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; -4.085 ; -4.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; -4.269 ; -4.269 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; -4.005 ; -4.005 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -3.831 ; -3.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -4.507 ; -4.507 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; -3.749 ; -3.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; -5.430 ; -5.430 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -4.154 ; -4.154 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -3.813 ; -3.813 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -4.752 ; -4.752 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; -3.921 ; -3.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -7.423 ; -7.423 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -7.837 ; -7.837 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -6.994 ; -6.994 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.588 ; -4.588 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.488 ; -7.488 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -7.434 ; -7.434 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -4.588 ; -4.588 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -5.485 ; -5.485 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -4.705 ; -4.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -4.216 ; -4.216 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -4.216 ; -4.216 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -4.877 ; -4.877 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -4.730 ; -4.730 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -4.562 ; -4.562 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -4.400 ; -4.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -4.387 ; -4.387 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -4.831 ; -4.831 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -4.379 ; -4.379 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -4.679 ; -4.679 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -5.176 ; -5.176 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -4.787 ; -4.787 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -5.013 ; -5.013 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.817 ; -4.817 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -4.504 ; -4.504 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -4.535 ; -4.535 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -4.300 ; -4.300 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -4.363 ; -4.363 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; -2.328 ; -2.328 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; -2.454 ; -2.454 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; -2.602 ; -2.602 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -5.481 ; -5.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -5.546 ; -5.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -5.540 ; -5.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -5.481 ; -5.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; -3.980 ; -3.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -4.492 ; -4.492 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -6.820 ; -6.820 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; -4.504 ; -4.504 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -6.662 ; -6.662 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -4.602 ; -4.602 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -7.040 ; -7.040 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -5.906 ; -5.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.503 ; -6.503 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.420 ; -6.420 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.278 ; -6.278 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -5.906 ; -5.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -6.179 ; -6.179 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -6.336 ; -6.336 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -6.109 ; -6.109 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.413 ; -6.413 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -6.200 ; -6.200 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -6.311 ; -6.311 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -6.371 ; -6.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -6.341 ; -6.341 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -6.253 ; -6.253 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -6.200 ; -6.200 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -6.647 ; -6.647 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -7.632 ; -7.632 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -6.680 ; -6.680 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -6.895 ; -6.895 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -7.387 ; -7.387 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -6.680 ; -6.680 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -7.009 ; -7.009 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -6.313 ; -6.313 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -6.554 ; -6.554 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -6.859 ; -6.859 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -7.061 ; -7.061 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -5.098 ; -5.098 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -5.297 ; -5.297 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -3.703 ; -3.703 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; -3.428 ; -3.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -6.024 ; -6.024 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; -3.990 ; -3.990 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; -3.813 ; -3.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -3.703 ; -3.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -4.322 ; -4.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -3.456 ; -3.456 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -3.456 ; -3.456 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -3.543 ; -3.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -3.693 ; -3.693 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -3.466 ; -3.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -3.520 ; -3.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -3.594 ; -3.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -3.548 ; -3.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -3.606 ; -3.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -4.397 ; -4.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -4.096 ; -4.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -3.972 ; -3.972 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; -4.485 ; -4.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.525 ; -4.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -4.525 ; -4.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -4.575 ; -4.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -4.751 ; -4.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -2.741 ; -2.741 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -2.185 ; -2.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.218 ; -4.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.524 ; -4.524 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.855 ; -4.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.595 ; -4.595 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.832 ; -4.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.635 ; -4.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.757 ; -4.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.555 ; -4.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.600 ; -4.600 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.685 ; -4.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -5.031 ; -5.031 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.673 ; -4.673 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.996 ; -4.996 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.716 ; -4.716 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.436 ; -4.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.509 ; -4.509 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.218 ; -4.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; -3.971 ; -3.971 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -3.840 ; -3.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.316 ; -5.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.439 ; -5.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.316 ; -5.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.495 ; -5.495 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; -4.051 ; -4.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; -1.699 ; -1.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; -4.026 ; -4.026 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; -4.478 ; -4.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; -4.066 ; -4.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -4.470 ; -4.470 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; -3.599 ; -3.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -4.312 ; -4.312 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; -3.783 ; -3.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.377 ; -4.377 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -3.954 ; -3.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -5.889 ; -5.889 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.509 ; -6.509 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.275 ; -6.275 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.164 ; -6.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -5.889 ; -5.889 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -6.078 ; -6.078 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -6.268 ; -6.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -6.083 ; -6.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.552 ; -6.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; -3.236 ; -3.236 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; -1.799 ; -1.799 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; -1.587 ; -1.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; -1.470 ; -1.470 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; -1.380 ; -1.380 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; -1.278 ; -1.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.657 ; -3.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -3.657 ; -3.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.935 ; -3.935 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -3.831 ; -3.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -4.115 ; -4.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -4.093 ; -4.093 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -4.195 ; -4.195 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -4.493 ; -4.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -4.126 ; -4.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -4.376 ; -4.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -3.747 ; -3.747 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -3.830 ; -3.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -3.918 ; -3.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -3.828 ; -3.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -3.880 ; -3.880 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -4.001 ; -4.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -3.854 ; -3.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; -1.248 ; -1.248 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; -4.020 ; -4.020 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.049 ; -4.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; -4.124 ; -4.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; -3.679 ; -3.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; -3.238 ; -3.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; -3.434 ; -3.434 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; -3.459 ; -3.459 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; -3.238 ; -3.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; -3.274 ; -3.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; -3.578 ; -3.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; -3.498 ; -3.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; -3.600 ; -3.600 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; -3.617 ; -3.617 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; -3.672 ; -3.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; -3.721 ; -3.721 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; -3.746 ; -3.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; -3.857 ; -3.857 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; -3.835 ; -3.835 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; -4.340 ; -4.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; -4.006 ; -4.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; -4.287 ; -4.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -4.184 ; -4.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; -4.641 ; -4.641 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; -4.263 ; -4.263 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; -3.691 ; -3.691 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; -3.691 ; -3.691 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; -3.975 ; -3.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; -3.944 ; -3.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; -4.085 ; -4.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; -4.269 ; -4.269 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; -4.005 ; -4.005 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -3.831 ; -3.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -4.507 ; -4.507 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; -3.749 ; -3.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -5.430 ; -5.430 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -4.154 ; -4.154 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -3.813 ; -3.813 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -4.752 ; -4.752 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; -3.921 ; -3.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -7.423 ; -7.423 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -7.837 ; -7.837 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.994 ; -6.994 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.588 ; -4.588 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.488 ; -7.488 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -7.434 ; -7.434 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -4.588 ; -4.588 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -5.485 ; -5.485 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -4.705 ; -4.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.216 ; -4.216 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.216 ; -4.216 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.877 ; -4.877 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.730 ; -4.730 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.562 ; -4.562 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.400 ; -4.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.387 ; -4.387 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.831 ; -4.831 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.379 ; -4.379 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.679 ; -4.679 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -5.176 ; -5.176 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.787 ; -4.787 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -5.013 ; -5.013 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.817 ; -4.817 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.504 ; -4.504 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.535 ; -4.535 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.300 ; -4.300 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -4.363 ; -4.363 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; -2.328 ; -2.328 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; -2.454 ; -2.454 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; -2.602 ; -2.602 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.481 ; -5.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.546 ; -5.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.540 ; -5.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.481 ; -5.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; -3.980 ; -3.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -4.492 ; -4.492 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -6.820 ; -6.820 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; -4.504 ; -4.504 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -6.662 ; -6.662 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.602 ; -4.602 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.040 ; -7.040 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -5.906 ; -5.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.503 ; -6.503 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.420 ; -6.420 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.278 ; -6.278 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -5.906 ; -5.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -6.179 ; -6.179 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -6.336 ; -6.336 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -6.109 ; -6.109 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.413 ; -6.413 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -6.200 ; -6.200 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -6.311 ; -6.311 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -6.371 ; -6.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -6.341 ; -6.341 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -6.253 ; -6.253 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -6.200 ; -6.200 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -6.647 ; -6.647 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -7.632 ; -7.632 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -6.680 ; -6.680 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -6.895 ; -6.895 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -7.387 ; -7.387 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -6.680 ; -6.680 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -7.009 ; -7.009 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -6.313 ; -6.313 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -6.554 ; -6.554 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -6.859 ; -6.859 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -7.061 ; -7.061 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -5.098 ; -5.098 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.297 ; -5.297 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -3.703 ; -3.703 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; -3.428 ; -3.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -6.024 ; -6.024 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; -3.990 ; -3.990 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; -4.703 ; -4.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; -7.576 ; -7.576 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; -7.731 ; -7.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; -6.948 ; -6.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.156 ; -4.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; -4.215 ; -4.215 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; -4.156 ; -4.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; -5.404 ; -5.404 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; -5.131 ; -5.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; -2.309 ; -2.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -1.753 ; -1.753 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; -4.771 ; -4.771 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; -4.883 ; -4.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; -4.815 ; -4.815 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; -4.566 ; -4.566 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; -4.634 ; -4.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; -4.785 ; -4.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; -4.656 ; -4.656 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; -4.868 ; -4.868 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; -4.906 ; -4.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -5.287 ; -5.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -5.311 ; -5.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -5.287 ; -5.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -5.638 ; -5.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; -7.067 ; -7.067 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; -6.909 ; -6.909 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -5.473 ; -5.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; -7.212 ; -7.212 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; -6.692 ; -6.692 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.692 ; -6.692 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.690 ; -3.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -3.699 ; -3.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.690 ; -3.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -3.721 ; -3.721 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -3.894 ; -3.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -3.944 ; -3.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -3.905 ; -3.905 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -3.990 ; -3.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -3.937 ; -3.937 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -3.783 ; -3.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -3.845 ; -3.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -3.832 ; -3.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -3.760 ; -3.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -3.841 ; -3.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -3.801 ; -3.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -3.716 ; -3.716 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -3.772 ; -3.772 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; -4.364 ; -4.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -5.584 ; -5.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; -5.569 ; -5.569 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; -5.488 ; -5.488 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -6.304 ; -6.304 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -6.369 ; -6.369 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -6.363 ; -6.363 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -6.304 ; -6.304 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -5.363 ; -5.363 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -6.239 ; -6.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; -4.703 ; -4.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -7.576 ; -7.576 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -7.731 ; -7.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.948 ; -6.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.156 ; -4.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -4.215 ; -4.215 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -4.156 ; -4.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; -5.404 ; -5.404 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -5.131 ; -5.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -2.309 ; -2.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -1.753 ; -1.753 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.771 ; -4.771 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.883 ; -4.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.815 ; -4.815 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.566 ; -4.566 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.634 ; -4.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.785 ; -4.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.656 ; -4.656 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.868 ; -4.868 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -4.906 ; -4.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.287 ; -5.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.311 ; -5.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.287 ; -5.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.638 ; -5.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -7.067 ; -7.067 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -6.909 ; -6.909 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -5.473 ; -5.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.212 ; -7.212 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -6.692 ; -6.692 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.692 ; -6.692 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.690 ; -3.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -3.699 ; -3.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.690 ; -3.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -3.721 ; -3.721 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -3.894 ; -3.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -3.944 ; -3.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -3.905 ; -3.905 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -3.990 ; -3.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -3.937 ; -3.937 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -3.783 ; -3.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -3.845 ; -3.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -3.832 ; -3.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -3.760 ; -3.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -3.841 ; -3.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -3.801 ; -3.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -3.716 ; -3.716 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -3.772 ; -3.772 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.364 ; -4.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.584 ; -5.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.569 ; -5.569 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -5.488 ; -5.488 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -6.304 ; -6.304 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -6.369 ; -6.369 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -6.363 ; -6.363 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -6.304 ; -6.304 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -5.363 ; -5.363 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -6.239 ; -6.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; -4.140 ; -4.140 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; -7.016 ; -7.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; -7.332 ; -7.332 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; -6.552 ; -6.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; -5.845 ; -5.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.322 ; -7.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; -7.268 ; -7.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; -5.845 ; -5.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; -5.319 ; -5.319 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -4.539 ; -4.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; -4.041 ; -4.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; -4.041 ; -4.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; -4.372 ; -4.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; -4.323 ; -4.323 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; -4.394 ; -4.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; -4.175 ; -4.175 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; -4.222 ; -4.222 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; -4.389 ; -4.389 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; -4.213 ; -4.213 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; -4.265 ; -4.265 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; -4.637 ; -4.637 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; -4.309 ; -4.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; -4.610 ; -4.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; -4.314 ; -4.314 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; -4.046 ; -4.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; -4.128 ; -4.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; -4.073 ; -4.073 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; -5.988 ; -5.988 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; -6.040 ; -6.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; -6.039 ; -6.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; -5.988 ; -5.988 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; -6.655 ; -6.655 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; -6.497 ; -6.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; -5.643 ; -5.643 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; -6.865 ; -6.865 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.089 ; -6.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; -5.881 ; -5.881 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; -5.800 ; -5.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; -3.519 ; -3.519 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; -3.462 ; -3.462 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; -3.562 ; -3.562 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.186 ; -6.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -5.810 ; -5.810 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -6.136 ; -6.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -5.866 ; -5.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -5.934 ; -5.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -6.085 ; -6.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -5.975 ; -5.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -6.482 ; -6.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -7.190 ; -7.190 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -6.514 ; -6.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -6.481 ; -6.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -6.848 ; -6.848 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -6.202 ; -6.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -6.606 ; -6.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -5.810 ; -5.810 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -6.096 ; -6.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -6.452 ; -6.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -6.834 ; -6.834 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; -4.431 ; -4.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; -5.632 ; -5.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; -5.546 ; -5.546 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; -4.140 ; -4.140 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -7.016 ; -7.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -7.332 ; -7.332 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.552 ; -6.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -5.845 ; -5.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.322 ; -7.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -7.268 ; -7.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -5.845 ; -5.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -5.319 ; -5.319 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -4.539 ; -4.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.041 ; -4.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.041 ; -4.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.372 ; -4.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.323 ; -4.323 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.394 ; -4.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.175 ; -4.175 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.222 ; -4.222 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.389 ; -4.389 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.213 ; -4.213 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.265 ; -4.265 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -4.637 ; -4.637 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.309 ; -4.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.610 ; -4.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.314 ; -4.314 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.046 ; -4.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.128 ; -4.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.073 ; -4.073 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.988 ; -5.988 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -6.040 ; -6.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -6.039 ; -6.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.988 ; -5.988 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -6.655 ; -6.655 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -6.497 ; -6.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -5.643 ; -5.643 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -6.865 ; -6.865 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.089 ; -6.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -5.881 ; -5.881 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -5.800 ; -5.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -3.519 ; -3.519 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -3.462 ; -3.462 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -3.562 ; -3.562 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.186 ; -6.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -5.810 ; -5.810 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -6.136 ; -6.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -5.866 ; -5.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -5.934 ; -5.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -6.085 ; -6.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -5.975 ; -5.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -6.482 ; -6.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -7.190 ; -7.190 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -6.514 ; -6.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -6.481 ; -6.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -6.848 ; -6.848 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -6.202 ; -6.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -6.606 ; -6.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -5.810 ; -5.810 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -6.096 ; -6.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -6.452 ; -6.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -6.834 ; -6.834 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.431 ; -4.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.632 ; -5.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.546 ; -5.546 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                      ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 17.740 ; 17.740 ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 17.749 ; 17.749 ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 16.620 ; 16.620 ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 27.272 ; 27.272 ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 23.185 ; 23.185 ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 23.601 ; 23.601 ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 22.690 ; 22.690 ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 26.628 ; 26.628 ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 26.632 ; 26.632 ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 27.272 ; 27.272 ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 27.218 ; 27.218 ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 22.974 ; 22.974 ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 27.106 ; 27.106 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 25.614 ; 25.614 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 26.734 ; 26.734 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 25.529 ; 25.529 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 24.882 ; 24.882 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 25.164 ; 25.164 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 26.824 ; 26.824 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 26.561 ; 26.561 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 27.106 ; 27.106 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 23.803 ; 23.803 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 25.043 ; 25.043 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 22.290 ; 22.290 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 25.493 ; 25.493 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 24.923 ; 24.923 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 23.413 ; 23.413 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 22.084 ; 22.084 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 22.752 ; 22.752 ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 8.596  ; 8.596  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 28.328 ; 28.328 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 26.898 ; 26.898 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 27.661 ; 27.661 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 26.279 ; 26.279 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 27.181 ; 27.181 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 27.413 ; 27.413 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 28.328 ; 28.328 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 27.297 ; 27.297 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 27.275 ; 27.275 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 23.764 ; 23.764 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 25.054 ; 25.054 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 23.500 ; 23.500 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 24.175 ; 24.175 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 24.589 ; 24.589 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 25.199 ; 25.199 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 24.211 ; 24.211 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 24.266 ; 24.266 ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 13.526 ; 13.526 ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 11.306 ; 11.306 ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 9.613  ; 9.613  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 25.570 ; 25.570 ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 25.570 ; 25.570 ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 25.739 ; 25.739 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 25.739 ; 25.739 ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 22.250 ; 22.250 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 19.496 ; 19.496 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 21.786 ; 21.786 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 20.636 ; 20.636 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 19.012 ; 19.012 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 19.519 ; 19.519 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 22.004 ; 22.004 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 21.396 ; 21.396 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 22.250 ; 22.250 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 19.905 ; 19.905 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 21.980 ; 21.980 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 17.370 ; 17.370 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 22.128 ; 22.128 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 19.284 ; 19.284 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 20.365 ; 20.365 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 19.303 ; 19.303 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 20.815 ; 20.815 ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 23.508 ; 23.508 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 20.780 ; 20.780 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 22.713 ; 22.713 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 21.386 ; 21.386 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 21.311 ; 21.311 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 21.768 ; 21.768 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 23.508 ; 23.508 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 22.132 ; 22.132 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 22.419 ; 22.419 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 19.866 ; 19.866 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 21.991 ; 21.991 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 18.580 ; 18.580 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 20.810 ; 20.810 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 18.950 ; 18.950 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 22.151 ; 22.151 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 21.430 ; 21.430 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 22.329 ; 22.329 ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 21.639 ; 21.639 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 21.639 ; 21.639 ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 7.538  ; 7.538  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 21.808 ; 21.808 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 21.808 ; 21.808 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 11.397 ; 11.397 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.310 ; 12.310 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 11.662 ; 11.662 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 11.030 ; 11.030 ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 7.567  ; 7.567  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 21.639 ; 21.639 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 21.639 ; 21.639 ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 7.538  ; 7.538  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 21.808 ; 21.808 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 21.808 ; 21.808 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 11.397 ; 11.397 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.310 ; 12.310 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 11.662 ; 11.662 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 11.030 ; 11.030 ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 7.567  ; 7.567  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 39.292 ; 39.292 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 39.301 ; 39.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 35.272 ; 35.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 30.017 ; 30.017 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 32.176 ; 32.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 30.594 ; 30.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 30.901 ; 30.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 33.071 ; 33.071 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 30.016 ; 30.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 31.776 ; 31.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 30.654 ; 30.654 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 31.582 ; 31.582 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 31.764 ; 31.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 31.288 ; 31.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 32.256 ; 32.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 31.744 ; 31.744 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 32.109 ; 32.109 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 31.389 ; 31.389 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 30.418 ; 30.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 33.711 ; 33.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 31.137 ; 31.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 34.383 ; 34.383 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 34.748 ; 34.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 32.466 ; 32.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 32.169 ; 32.169 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 35.272 ; 35.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 14.990 ; 14.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 6.878  ; 6.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 10.673 ; 10.673 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 9.441  ; 9.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 7.875  ; 7.875  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 36.318 ; 36.318 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 38.172 ; 38.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 48.824 ; 48.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 44.737 ; 44.737 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 45.153 ; 45.153 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 44.242 ; 44.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 48.180 ; 48.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 48.184 ; 48.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 48.824 ; 48.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 48.770 ; 48.770 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 44.526 ; 44.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 7.739  ; 7.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 8.054  ; 8.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 6.663  ; 6.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 10.455 ; 10.455 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 5.228  ; 5.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 5.614  ; 5.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 5.107  ; 5.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 6.328  ; 6.328  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 49.741 ; 49.741 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 47.161 ; 47.161 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 49.098 ; 49.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 47.177 ; 47.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 47.280 ; 47.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 46.842 ; 46.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 48.714 ; 48.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 48.274 ; 48.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 49.741 ; 49.741 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 49.036 ; 49.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 49.102 ; 49.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 46.230 ; 46.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 49.150 ; 49.150 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 48.310 ; 48.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 47.181 ; 47.181 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 46.829 ; 46.829 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 47.668 ; 47.668 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 7.974  ; 7.974  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 6.591  ; 6.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 8.205  ; 8.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 6.806  ; 6.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 7.175  ; 7.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 15.497 ; 15.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 15.497 ; 15.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 15.158 ; 15.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 15.276 ; 15.276 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 7.544  ; 7.544  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 7.804  ; 7.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 6.860  ; 6.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 7.726  ; 7.726  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 7.409  ; 7.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 8.254  ; 8.254  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 7.385  ; 7.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 7.381  ; 7.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 31.319 ; 31.319 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 34.141 ; 34.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 38.965 ; 38.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 38.171 ; 38.171 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 7.033  ; 7.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 9.345  ; 9.345  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 5.178  ; 5.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 9.420  ; 9.420  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 8.173  ; 8.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 7.455  ; 7.455  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 37.135 ; 37.135 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 36.033 ; 36.033 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 36.370 ; 36.370 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 37.514 ; 37.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 37.159 ; 37.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 36.820 ; 36.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 36.001 ; 36.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 36.242 ; 36.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 35.884 ; 35.884 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 36.584 ; 36.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 7.588  ; 7.588  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 9.403  ; 9.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 8.866  ; 8.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 9.403  ; 9.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 9.185  ; 9.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 8.644  ; 8.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 30.577 ; 30.577 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 5.155  ; 5.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 5.742  ; 5.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 9.344  ; 9.344  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 6.304  ; 6.304  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 6.677  ; 6.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.717  ; 6.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 8.461  ; 8.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 7.972  ; 7.972  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 9.082  ; 9.082  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 9.344  ; 9.344  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 6.559  ; 6.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 7.062  ; 7.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 7.657  ; 7.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 6.102  ; 6.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 38.645 ; 38.645 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 36.001 ; 36.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 36.648 ; 36.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 36.193 ; 36.193 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 37.751 ; 37.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 37.279 ; 37.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 37.649 ; 37.649 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 37.857 ; 37.857 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 38.645 ; 38.645 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 37.428 ; 37.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 37.257 ; 37.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 36.658 ; 36.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 35.597 ; 35.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 35.472 ; 35.472 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 35.713 ; 35.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 35.713 ; 35.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 51.313 ; 51.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 48.445 ; 48.445 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 50.025 ; 50.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 48.293 ; 48.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 49.579 ; 49.579 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 49.143 ; 49.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 51.025 ; 51.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 50.768 ; 50.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 49.910 ; 49.910 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 51.313 ; 51.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 49.113 ; 49.113 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 50.004 ; 50.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 50.120 ; 50.120 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 48.813 ; 48.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 48.967 ; 48.967 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 48.956 ; 48.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 49.272 ; 49.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 11.571 ; 11.571 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 35.812 ; 35.812 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 35.527 ; 35.527 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 36.605 ; 36.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 35.539 ; 35.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 35.241 ; 35.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 37.095 ; 37.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 38.121 ; 38.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 13.928 ; 13.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 8.241  ; 8.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 9.716  ; 9.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 6.720  ; 6.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 13.650 ; 13.650 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 8.788  ; 8.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 7.458  ; 7.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 8.159  ; 8.159  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 7.730  ; 7.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 7.685  ; 7.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 7.826  ; 7.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 8.102  ; 8.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 8.788  ; 8.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 8.389  ; 8.389  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 5.645  ; 5.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 10.115 ; 10.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 4.759  ; 4.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 6.052  ; 6.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 10.513 ; 10.513 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 9.387  ; 9.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 8.370  ; 8.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 7.748  ; 7.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 10.111 ; 10.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 9.647  ; 9.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 10.864 ; 10.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 9.081  ; 9.081  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 8.747  ; 8.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 7.077  ; 7.077  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 8.992  ; 8.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 7.414  ; 7.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 8.992  ; 8.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 7.937  ; 7.937  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 8.220  ; 8.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 28.482 ; 28.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 5.068  ; 5.068  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 7.179  ; 7.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 7.140  ; 7.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 18.473 ; 18.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 15.606 ; 15.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 17.057 ; 17.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 45.091 ; 45.091 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 45.100 ; 45.100 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 41.071 ; 41.071 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 35.816 ; 35.816 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 37.975 ; 37.975 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 36.393 ; 36.393 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 36.700 ; 36.700 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 38.870 ; 38.870 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 35.815 ; 35.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 37.575 ; 37.575 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 36.453 ; 36.453 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 37.381 ; 37.381 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 37.563 ; 37.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 37.087 ; 37.087 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 38.055 ; 38.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 37.543 ; 37.543 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 37.908 ; 37.908 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 37.188 ; 37.188 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 36.217 ; 36.217 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 39.510 ; 39.510 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 36.936 ; 36.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 40.182 ; 40.182 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 40.547 ; 40.547 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 38.265 ; 38.265 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 37.968 ; 37.968 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 41.071 ; 41.071 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 12.720 ; 9.307  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 6.887  ; 6.887  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 42.117 ; 42.117 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 43.971 ; 43.971 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 54.623 ; 54.623 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 50.536 ; 50.536 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 50.952 ; 50.952 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 50.041 ; 50.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 53.979 ; 53.979 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 53.983 ; 53.983 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 54.623 ; 54.623 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 54.569 ; 54.569 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 50.325 ; 50.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 55.540 ; 55.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 52.960 ; 52.960 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 54.897 ; 54.897 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 52.976 ; 52.976 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 53.079 ; 53.079 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 52.641 ; 52.641 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 54.513 ; 54.513 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 54.073 ; 54.073 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 55.540 ; 55.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 54.835 ; 54.835 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 54.901 ; 54.901 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 52.029 ; 52.029 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 54.949 ; 54.949 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 54.109 ; 54.109 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 52.980 ; 52.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 52.628 ; 52.628 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 53.467 ; 53.467 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 9.853  ; 9.853  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 9.853  ; 9.853  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 9.514  ; 9.514  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 9.190  ; 9.190  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 37.118 ; 37.118 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 39.940 ; 39.940 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 44.764 ; 44.764 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 43.970 ; 43.970 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 42.934 ; 42.934 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 41.832 ; 41.832 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 42.169 ; 42.169 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 43.313 ; 43.313 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 42.958 ; 42.958 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 42.619 ; 42.619 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 41.800 ; 41.800 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 42.041 ; 42.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 41.683 ; 41.683 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 42.383 ; 42.383 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 36.376 ; 36.376 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 44.444 ; 44.444 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 41.800 ; 41.800 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 42.447 ; 42.447 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 41.992 ; 41.992 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 43.550 ; 43.550 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 43.078 ; 43.078 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 43.448 ; 43.448 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 43.656 ; 43.656 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 44.444 ; 44.444 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 43.227 ; 43.227 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 43.056 ; 43.056 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 42.457 ; 42.457 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 41.396 ; 41.396 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 41.271 ; 41.271 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 41.512 ; 41.512 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 41.512 ; 41.512 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 57.112 ; 57.112 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 54.244 ; 54.244 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 55.824 ; 55.824 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 54.092 ; 54.092 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 55.378 ; 55.378 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 54.942 ; 54.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 56.824 ; 56.824 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 56.567 ; 56.567 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 55.709 ; 55.709 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 57.112 ; 57.112 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 54.912 ; 54.912 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 55.803 ; 55.803 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 55.919 ; 55.919 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 54.612 ; 54.612 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 54.766 ; 54.766 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 54.755 ; 54.755 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 55.071 ; 55.071 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 41.611 ; 41.611 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 41.326 ; 41.326 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 42.404 ; 42.404 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 41.338 ; 41.338 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 41.040 ; 41.040 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 42.894 ; 42.894 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 43.920 ; 43.920 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 8.245  ; 8.245  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 34.281 ; 34.281 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 39.292 ; 39.292 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 39.301 ; 39.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 35.272 ; 35.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 30.017 ; 30.017 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 32.176 ; 32.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 30.594 ; 30.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 30.901 ; 30.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 33.071 ; 33.071 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 30.016 ; 30.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 31.776 ; 31.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 30.654 ; 30.654 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 31.582 ; 31.582 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 31.764 ; 31.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 31.288 ; 31.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 32.256 ; 32.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 31.744 ; 31.744 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 32.109 ; 32.109 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 31.389 ; 31.389 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 30.418 ; 30.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 33.711 ; 33.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 31.137 ; 31.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 34.383 ; 34.383 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 34.748 ; 34.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 32.466 ; 32.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 32.169 ; 32.169 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 35.272 ; 35.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 14.990 ; 14.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 6.878  ; 6.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 10.673 ; 10.673 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 9.441  ; 9.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 7.875  ; 7.875  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 36.318 ; 36.318 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 38.172 ; 38.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 48.824 ; 48.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 44.737 ; 44.737 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 45.153 ; 45.153 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 44.242 ; 44.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 48.180 ; 48.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 48.184 ; 48.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 48.824 ; 48.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 48.770 ; 48.770 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 44.526 ; 44.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 7.739  ; 7.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 8.054  ; 8.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 6.663  ; 6.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 10.455 ; 10.455 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 5.228  ; 5.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 5.614  ; 5.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 5.107  ; 5.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 6.328  ; 6.328  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 49.741 ; 49.741 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 47.161 ; 47.161 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 49.098 ; 49.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 47.177 ; 47.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 47.280 ; 47.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 46.842 ; 46.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 48.714 ; 48.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 48.274 ; 48.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 49.741 ; 49.741 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 49.036 ; 49.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 49.102 ; 49.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 46.230 ; 46.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 49.150 ; 49.150 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 48.310 ; 48.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 47.181 ; 47.181 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 46.829 ; 46.829 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 47.668 ; 47.668 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 7.974  ; 7.974  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 6.591  ; 6.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 8.205  ; 8.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 6.806  ; 6.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 7.175  ; 7.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 15.497 ; 15.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 15.497 ; 15.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 15.158 ; 15.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 15.276 ; 15.276 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 7.544  ; 7.544  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 7.804  ; 7.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 6.860  ; 6.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 7.726  ; 7.726  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 7.409  ; 7.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 8.254  ; 8.254  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 7.385  ; 7.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 7.381  ; 7.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 31.319 ; 31.319 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 34.141 ; 34.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 38.965 ; 38.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 38.171 ; 38.171 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 7.033  ; 7.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 9.345  ; 9.345  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 5.178  ; 5.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 9.420  ; 9.420  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 8.173  ; 8.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 7.455  ; 7.455  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 37.135 ; 37.135 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 36.033 ; 36.033 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 36.370 ; 36.370 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 37.514 ; 37.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 37.159 ; 37.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 36.820 ; 36.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 36.001 ; 36.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 36.242 ; 36.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 35.884 ; 35.884 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 36.584 ; 36.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 7.588  ; 7.588  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 9.403  ; 9.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 8.866  ; 8.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 9.403  ; 9.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 9.185  ; 9.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 8.644  ; 8.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 30.577 ; 30.577 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 5.155  ; 5.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 5.742  ; 5.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 9.344  ; 9.344  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 6.304  ; 6.304  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 6.677  ; 6.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.717  ; 6.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 8.461  ; 8.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 7.972  ; 7.972  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 9.082  ; 9.082  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 9.344  ; 9.344  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 6.559  ; 6.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 7.062  ; 7.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 7.657  ; 7.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 6.102  ; 6.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 38.645 ; 38.645 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 36.001 ; 36.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 36.648 ; 36.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 36.193 ; 36.193 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 37.751 ; 37.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 37.279 ; 37.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 37.649 ; 37.649 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 37.857 ; 37.857 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 38.645 ; 38.645 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 37.428 ; 37.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 37.257 ; 37.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 36.658 ; 36.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 35.597 ; 35.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 35.472 ; 35.472 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 35.713 ; 35.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 35.713 ; 35.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 51.313 ; 51.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 48.445 ; 48.445 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 50.025 ; 50.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 48.293 ; 48.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 49.579 ; 49.579 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 49.143 ; 49.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 51.025 ; 51.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 50.768 ; 50.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 49.910 ; 49.910 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 51.313 ; 51.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 49.113 ; 49.113 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 50.004 ; 50.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 50.120 ; 50.120 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 48.813 ; 48.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 48.967 ; 48.967 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 48.956 ; 48.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 49.272 ; 49.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 11.571 ; 11.571 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 35.812 ; 35.812 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 35.527 ; 35.527 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 36.605 ; 36.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 35.539 ; 35.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 35.241 ; 35.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 37.095 ; 37.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 38.121 ; 38.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 13.928 ; 13.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 8.241  ; 8.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 9.716  ; 9.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 6.720  ; 6.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 13.650 ; 13.650 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 8.788  ; 8.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 7.458  ; 7.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 8.159  ; 8.159  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 7.730  ; 7.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 7.685  ; 7.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 7.826  ; 7.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 8.102  ; 8.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 8.788  ; 8.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 8.389  ; 8.389  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 5.645  ; 5.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 10.115 ; 10.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 4.759  ; 4.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 6.052  ; 6.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 10.513 ; 10.513 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 9.387  ; 9.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 8.370  ; 8.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 7.748  ; 7.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 10.111 ; 10.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 9.647  ; 9.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 10.864 ; 10.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 9.081  ; 9.081  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 8.747  ; 8.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 7.077  ; 7.077  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 8.992  ; 8.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 7.414  ; 7.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 8.992  ; 8.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 7.937  ; 7.937  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 8.220  ; 8.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 28.482 ; 28.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 5.068  ; 5.068  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 7.179  ; 7.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 7.140  ; 7.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 18.473 ; 18.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 15.606 ; 15.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 17.057 ; 17.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 45.091 ; 45.091 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 45.100 ; 45.100 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 41.071 ; 41.071 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 35.816 ; 35.816 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 37.975 ; 37.975 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 36.393 ; 36.393 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 36.700 ; 36.700 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 38.870 ; 38.870 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 35.815 ; 35.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 37.575 ; 37.575 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 36.453 ; 36.453 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 37.381 ; 37.381 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 37.563 ; 37.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 37.087 ; 37.087 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 38.055 ; 38.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 37.543 ; 37.543 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 37.908 ; 37.908 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 37.188 ; 37.188 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 36.217 ; 36.217 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 39.510 ; 39.510 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 36.936 ; 36.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 40.182 ; 40.182 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 40.547 ; 40.547 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 38.265 ; 38.265 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 37.968 ; 37.968 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 41.071 ; 41.071 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 12.720 ; 9.307  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 6.887  ; 6.887  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 42.117 ; 42.117 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 43.971 ; 43.971 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 54.623 ; 54.623 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 50.536 ; 50.536 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 50.952 ; 50.952 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 50.041 ; 50.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 53.979 ; 53.979 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 53.983 ; 53.983 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 54.623 ; 54.623 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 54.569 ; 54.569 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 50.325 ; 50.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 55.540 ; 55.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 52.960 ; 52.960 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 54.897 ; 54.897 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 52.976 ; 52.976 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 53.079 ; 53.079 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 52.641 ; 52.641 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 54.513 ; 54.513 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 54.073 ; 54.073 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 55.540 ; 55.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 54.835 ; 54.835 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 54.901 ; 54.901 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 52.029 ; 52.029 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 54.949 ; 54.949 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 54.109 ; 54.109 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 52.980 ; 52.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 52.628 ; 52.628 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 53.467 ; 53.467 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 9.853  ; 9.853  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 9.853  ; 9.853  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 9.514  ; 9.514  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 9.190  ; 9.190  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 37.118 ; 37.118 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 39.940 ; 39.940 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 44.764 ; 44.764 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 43.970 ; 43.970 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 42.934 ; 42.934 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 41.832 ; 41.832 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 42.169 ; 42.169 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 43.313 ; 43.313 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 42.958 ; 42.958 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 42.619 ; 42.619 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 41.800 ; 41.800 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 42.041 ; 42.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 41.683 ; 41.683 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 42.383 ; 42.383 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 36.376 ; 36.376 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 44.444 ; 44.444 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 41.800 ; 41.800 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 42.447 ; 42.447 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 41.992 ; 41.992 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 43.550 ; 43.550 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 43.078 ; 43.078 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 43.448 ; 43.448 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 43.656 ; 43.656 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 44.444 ; 44.444 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 43.227 ; 43.227 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 43.056 ; 43.056 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 42.457 ; 42.457 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 41.396 ; 41.396 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 41.271 ; 41.271 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 41.512 ; 41.512 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 41.512 ; 41.512 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 57.112 ; 57.112 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 54.244 ; 54.244 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 55.824 ; 55.824 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 54.092 ; 54.092 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 55.378 ; 55.378 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 54.942 ; 54.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 56.824 ; 56.824 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 56.567 ; 56.567 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 55.709 ; 55.709 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 57.112 ; 57.112 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 54.912 ; 54.912 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 55.803 ; 55.803 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 55.919 ; 55.919 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 54.612 ; 54.612 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 54.766 ; 54.766 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 54.755 ; 54.755 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 55.071 ; 55.071 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 41.611 ; 41.611 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 41.326 ; 41.326 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 42.404 ; 42.404 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 41.338 ; 41.338 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 41.040 ; 41.040 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 42.894 ; 42.894 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 43.920 ; 43.920 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 8.245  ; 8.245  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 34.281 ; 34.281 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 13.331 ; 13.331 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 13.340 ; 13.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 11.879 ; 11.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 9.608  ; 9.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 8.630  ; 8.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 12.211 ; 12.211 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 22.863 ; 22.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 18.776 ; 18.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 19.192 ; 19.192 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 18.281 ; 18.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 22.219 ; 22.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 22.223 ; 22.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 22.863 ; 22.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 22.809 ; 22.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 18.565 ; 18.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 8.079  ; 8.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 8.099  ; 8.099  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 7.315  ; 7.315  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 8.430  ; 8.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 8.430  ; 8.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 7.766  ; 7.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 8.408  ; 8.408  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 7.694  ; 7.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 14.403 ; 14.403 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 7.735  ; 7.735  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 7.735  ; 7.735  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 7.421  ; 7.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 7.390  ; 7.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 7.398  ; 7.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 22.697 ; 22.697 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 21.205 ; 21.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 22.325 ; 22.325 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 21.120 ; 21.120 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 20.473 ; 20.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 20.755 ; 20.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 22.415 ; 22.415 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 22.152 ; 22.152 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 22.697 ; 22.697 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 19.681 ; 19.681 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 20.634 ; 20.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 17.881 ; 17.881 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 21.084 ; 21.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 20.514 ; 20.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 19.004 ; 19.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 17.675 ; 17.675 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 18.343 ; 18.343 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 7.351  ; 7.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 11.610 ; 11.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 4.880  ; 4.880  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 5.172  ; 5.172  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 6.162  ; 6.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 15.227 ; 15.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 13.439 ; 13.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 13.014 ; 13.014 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 13.199 ; 13.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 13.841 ; 13.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 13.345 ; 13.345 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 13.993 ; 13.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 13.818 ; 13.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 15.227 ; 15.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 14.995 ; 14.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 14.162 ; 14.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 13.533 ; 13.533 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 13.180 ; 13.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 13.387 ; 13.387 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 11.761 ; 11.761 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 11.761 ; 11.761 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 11.840 ; 11.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 11.556 ; 11.556 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 26.855 ; 26.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 23.954 ; 23.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 23.252 ; 23.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 23.835 ; 23.835 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 23.914 ; 23.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 24.685 ; 24.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 26.567 ; 26.567 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 26.310 ; 26.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 23.167 ; 23.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 26.855 ; 26.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 23.365 ; 23.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 25.546 ; 25.546 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 25.662 ; 25.662 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 24.355 ; 24.355 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 23.798 ; 23.798 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 23.954 ; 23.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 24.814 ; 24.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 11.198 ; 11.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 10.990 ; 10.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 10.255 ; 10.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 12.461 ; 12.461 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 12.830 ; 12.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 10.786 ; 10.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 9.581  ; 9.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 10.030 ; 10.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 9.884  ; 9.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]      ; CLK_PLL1      ; 10.322 ; 10.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 9.621  ; 9.621  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 10.322 ; 10.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 9.323  ; 9.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 9.324  ; 9.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 9.662  ; 9.662  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 9.889  ; 9.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 9.925  ; 9.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 10.154 ; 10.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP        ; CLK_PLL1      ; 9.592  ; 9.592  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 13.060 ; 13.060 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 9.952  ; 9.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 10.335 ; 10.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 12.658 ; 12.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 11.119 ; 11.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 5.271  ; 5.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 4.936  ; 4.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 5.271  ; 5.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 4.932  ; 4.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 4.573  ; 4.573  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 4.554  ; 4.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 13.331 ; 13.331 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 13.340 ; 13.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 11.879 ; 11.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 9.608  ; 9.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 8.630  ; 8.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 12.211 ; 12.211 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 22.863 ; 22.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 18.776 ; 18.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 19.192 ; 19.192 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 18.281 ; 18.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 22.219 ; 22.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 22.223 ; 22.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 22.863 ; 22.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 22.809 ; 22.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 18.565 ; 18.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 8.079  ; 8.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 8.099  ; 8.099  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 7.315  ; 7.315  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 8.430  ; 8.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 8.430  ; 8.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 7.766  ; 7.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 8.408  ; 8.408  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 7.694  ; 7.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 14.403 ; 14.403 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 7.735  ; 7.735  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 7.735  ; 7.735  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 7.421  ; 7.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 7.390  ; 7.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 7.398  ; 7.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 22.697 ; 22.697 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 21.205 ; 21.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 22.325 ; 22.325 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 21.120 ; 21.120 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 20.473 ; 20.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 20.755 ; 20.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 22.415 ; 22.415 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 22.152 ; 22.152 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 22.697 ; 22.697 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 19.681 ; 19.681 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 20.634 ; 20.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 17.881 ; 17.881 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 21.084 ; 21.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 20.514 ; 20.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 19.004 ; 19.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 17.675 ; 17.675 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 18.343 ; 18.343 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 7.351  ; 7.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 11.610 ; 11.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 4.880  ; 4.880  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 5.172  ; 5.172  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 6.162  ; 6.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 15.227 ; 15.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 13.439 ; 13.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 13.014 ; 13.014 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 13.199 ; 13.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 13.841 ; 13.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 13.345 ; 13.345 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 13.993 ; 13.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 13.818 ; 13.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 15.227 ; 15.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 14.995 ; 14.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 14.162 ; 14.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 13.533 ; 13.533 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 13.180 ; 13.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 13.387 ; 13.387 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 11.761 ; 11.761 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 11.761 ; 11.761 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 11.840 ; 11.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 11.556 ; 11.556 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 26.855 ; 26.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 23.954 ; 23.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 23.252 ; 23.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 23.835 ; 23.835 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 23.914 ; 23.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 24.685 ; 24.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 26.567 ; 26.567 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 26.310 ; 26.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 23.167 ; 23.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 26.855 ; 26.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 23.365 ; 23.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 25.546 ; 25.546 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 25.662 ; 25.662 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 24.355 ; 24.355 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 23.798 ; 23.798 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 23.954 ; 23.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 24.814 ; 24.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 11.198 ; 11.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 10.990 ; 10.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 10.255 ; 10.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 12.461 ; 12.461 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 12.830 ; 12.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 10.786 ; 10.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 9.581  ; 9.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 10.030 ; 10.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 9.884  ; 9.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 10.322 ; 10.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 9.621  ; 9.621  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 10.322 ; 10.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 9.323  ; 9.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 9.324  ; 9.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 9.662  ; 9.662  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 9.889  ; 9.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 9.925  ; 9.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 10.154 ; 10.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 9.592  ; 9.592  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 13.060 ; 13.060 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 9.952  ; 9.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 10.335 ; 10.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 12.658 ; 12.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 11.119 ; 11.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 5.271  ; 5.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 4.936  ; 4.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 5.271  ; 5.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 4.932  ; 4.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 4.573  ; 4.573  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 4.554  ; 4.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 32.101 ; 32.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 29.838 ; 29.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 31.198 ; 31.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 29.501 ; 29.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 29.419 ; 29.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 30.049 ; 30.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 32.101 ; 32.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 31.181 ; 31.181 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 31.955 ; 31.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 30.540 ; 30.540 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 31.444 ; 31.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 28.004 ; 28.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 30.466 ; 30.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 29.233 ; 29.233 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 27.502 ; 27.502 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 27.654 ; 27.654 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 28.004 ; 28.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 10.428 ; 10.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 10.102 ; 10.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 10.115 ; 10.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 10.428 ; 10.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 10.411 ; 10.411 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 33.605 ; 33.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 31.122 ; 31.122 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 32.125 ; 32.125 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 30.251 ; 30.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 31.718 ; 31.718 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 32.298 ; 32.298 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 33.605 ; 33.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 31.917 ; 31.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 32.124 ; 32.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 30.501 ; 30.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 31.455 ; 31.455 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 29.214 ; 29.214 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 29.148 ; 29.148 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 28.899 ; 28.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 29.288 ; 29.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 29.781 ; 29.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 29.518 ; 29.518 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 32.101 ; 32.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 29.838 ; 29.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 31.198 ; 31.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 29.501 ; 29.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 29.419 ; 29.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 30.049 ; 30.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 32.101 ; 32.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 31.181 ; 31.181 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 31.955 ; 31.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 30.540 ; 30.540 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 31.444 ; 31.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 28.004 ; 28.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 30.466 ; 30.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 29.233 ; 29.233 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 27.502 ; 27.502 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 27.654 ; 27.654 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 28.004 ; 28.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 10.428 ; 10.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 10.102 ; 10.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 10.115 ; 10.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 10.428 ; 10.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 10.411 ; 10.411 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 33.605 ; 33.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 31.122 ; 31.122 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 32.125 ; 32.125 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 30.251 ; 30.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 31.718 ; 31.718 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 32.298 ; 32.298 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 33.605 ; 33.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 31.917 ; 31.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 32.124 ; 32.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 30.501 ; 30.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 31.455 ; 31.455 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 29.214 ; 29.214 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 29.148 ; 29.148 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 28.899 ; 28.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 29.288 ; 29.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 29.781 ; 29.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 29.518 ; 29.518 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.821  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.821  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 7.722  ; 7.722  ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 7.726  ; 7.726  ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 7.410  ; 7.410  ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 7.437  ; 7.437  ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 8.219  ; 8.219  ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 8.141  ; 8.141  ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 7.437  ; 7.437  ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 8.212  ; 8.212  ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 7.706  ; 7.706  ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 7.698  ; 7.698  ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 7.848  ; 7.848  ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 7.542  ; 7.542  ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 8.270  ; 8.270  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 9.099  ; 9.099  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 9.588  ; 9.588  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 9.369  ; 9.369  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 9.098  ; 9.098  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 9.003  ; 9.003  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 9.976  ; 9.976  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 9.752  ; 9.752  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 9.902  ; 9.902  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 9.422  ; 9.422  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 10.022 ; 10.022 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 8.270  ; 8.270  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 9.847  ; 9.847  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 9.434  ; 9.434  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 9.059  ; 9.059  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 8.655  ; 8.655  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 9.010  ; 9.010  ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 4.263  ; 4.263  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 8.866  ; 8.866  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 9.630  ; 9.630  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 9.958  ; 9.958  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 9.721  ; 9.721  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 10.077 ; 10.077 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 9.885  ; 9.885  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 10.627 ; 10.627 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 10.124 ; 10.124 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 10.190 ; 10.190 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 9.595  ; 9.595  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 10.180 ; 10.180 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 8.866  ; 8.866  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 9.551  ; 9.551  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 9.268  ; 9.268  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 9.811  ; 9.811  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 9.524  ; 9.524  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 9.679  ; 9.679  ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 6.198  ; 6.198  ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 5.221  ; 5.221  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 4.513  ; 4.513  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 10.599 ; 10.599 ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 10.599 ; 10.599 ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 10.887 ; 10.887 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 10.887 ; 10.887 ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 6.925  ; 6.925  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 7.193  ; 7.193  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 8.002  ; 8.002  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 7.628  ; 7.628  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 7.145  ; 7.145  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 7.524  ; 7.524  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 8.056  ; 8.056  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 8.025  ; 8.025  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 8.176  ; 8.176  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 7.720  ; 7.720  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 7.969  ; 7.969  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 6.925  ; 6.925  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 8.286  ; 8.286  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 7.717  ; 7.717  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 7.639  ; 7.639  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 7.250  ; 7.250  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 7.458  ; 7.458  ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 7.521  ; 7.521  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 7.724  ; 7.724  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 8.372  ; 8.372  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 7.980  ; 7.980  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 8.124  ; 8.124  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 8.406  ; 8.406  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 8.707  ; 8.707  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 8.397  ; 8.397  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 8.464  ; 8.464  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 7.893  ; 7.893  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 8.127  ; 8.127  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 7.521  ; 7.521  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 7.990  ; 7.990  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 7.551  ; 7.551  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 8.391  ; 8.391  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 8.119  ; 8.119  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 8.127  ; 8.127  ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 8.736  ; 8.736  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 8.736  ; 8.736  ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.433  ; 3.433  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.735  ; 4.735  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 9.024  ; 9.024  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 4.841  ; 4.841  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.216  ; 5.216  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.954  ; 4.954  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.735  ; 4.735  ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.424  ; 3.424  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 8.736  ; 8.736  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 8.736  ; 8.736  ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.433  ; 3.433  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.735  ; 4.735  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 9.024  ; 9.024  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 4.841  ; 4.841  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.216  ; 5.216  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.954  ; 4.954  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.735  ; 4.735  ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.424  ; 3.424  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 3.243  ; 3.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 3.248  ; 3.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 2.946  ; 2.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 3.760  ; 3.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 4.330  ; 4.330  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 3.728  ; 3.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 4.383  ; 4.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 3.613  ; 3.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 3.765  ; 3.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 3.207  ; 3.207  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 3.527  ; 3.527  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 3.913  ; 3.913  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 3.704  ; 3.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 3.392  ; 3.392  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 2.946  ; 2.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 3.217  ; 3.217  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 3.130  ; 3.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 3.007  ; 3.007  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 3.082  ; 3.082  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 2.994  ; 2.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 3.192  ; 3.192  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 3.730  ; 3.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 3.793  ; 3.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 3.943  ; 3.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 3.951  ; 3.951  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 3.531  ; 3.531  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 3.100  ; 3.100  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 3.196  ; 3.196  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 4.138  ; 4.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 3.406  ; 3.406  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 4.911  ; 4.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 3.253  ; 3.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 2.887  ; 2.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 2.888  ; 2.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 2.887  ; 2.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 3.006  ; 3.006  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 2.943  ; 2.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 2.988  ; 2.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 2.976  ; 2.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 3.053  ; 3.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 3.059  ; 3.059  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 3.453  ; 3.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 3.628  ; 3.628  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 2.938  ; 2.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 2.295  ; 2.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 2.466  ; 2.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 2.224  ; 2.224  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 2.660  ; 2.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 2.766  ; 2.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 3.459  ; 3.459  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 3.477  ; 3.477  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 3.396  ; 3.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 3.318  ; 3.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 3.295  ; 3.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 3.820  ; 3.820  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 3.514  ; 3.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 3.789  ; 3.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 3.488  ; 3.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 3.537  ; 3.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 3.032  ; 3.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 3.230  ; 3.230  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 3.668  ; 3.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 2.982  ; 2.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 2.766  ; 2.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 3.015  ; 3.015  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 3.537  ; 3.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 3.006  ; 3.006  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 3.540  ; 3.540  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 3.101  ; 3.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 3.190  ; 3.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 3.366  ; 3.366  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 3.625  ; 3.625  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 4.046  ; 3.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 3.366  ; 3.366  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 3.488  ; 3.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 3.416  ; 3.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 3.106  ; 3.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 3.430  ; 3.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 3.249  ; 3.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 3.638  ; 3.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 3.285  ; 3.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 3.390  ; 3.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 3.414  ; 3.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 3.401  ; 3.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 3.225  ; 3.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 2.905  ; 2.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 3.949  ; 3.949  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 2.268  ; 2.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 3.463  ; 3.463  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 3.117  ; 3.117  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 3.160  ; 3.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 5.022  ; 5.022  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 4.856  ; 4.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 4.919  ; 4.919  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 5.398  ; 5.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 5.241  ; 5.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 5.099  ; 5.099  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 4.803  ; 4.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 4.941  ; 4.929  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 4.783  ; 4.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 4.990  ; 5.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 3.062  ; 3.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 3.141  ; 3.141  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 3.266  ; 3.266  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 3.238  ; 3.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 3.062  ; 3.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 3.556  ; 3.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 2.300  ; 2.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 2.521  ; 2.521  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 2.900  ; 2.900  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 2.900  ; 2.900  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 2.934  ; 2.934  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 2.964  ; 2.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.357  ; 3.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 3.395  ; 3.395  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 3.581  ; 3.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 3.559  ; 3.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 2.935  ; 2.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 3.103  ; 3.103  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 2.754  ; 2.754  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 2.394  ; 2.394  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 5.745  ; 5.745  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 6.017  ; 6.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 5.745  ; 5.745  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 6.251  ; 6.251  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 6.503  ; 6.503  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 6.435  ; 6.435  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 6.448  ; 6.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 6.638  ; 6.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 6.914  ; 6.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 6.494  ; 6.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 6.655  ; 6.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 6.066  ; 6.066  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 5.936  ; 5.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 5.890  ; 5.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 6.283  ; 6.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 6.283  ; 6.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 5.011  ; 5.011  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 5.359  ; 5.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 5.627  ; 5.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 5.224  ; 5.224  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 5.802  ; 5.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 5.782  ; 5.782  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 6.295  ; 6.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 5.747  ; 5.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 5.947  ; 5.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 5.342  ; 5.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 5.407  ; 5.407  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 5.011  ; 5.011  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 5.072  ; 5.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 5.160  ; 5.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 5.550  ; 5.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 5.203  ; 5.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 5.584  ; 5.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 3.698  ; 3.698  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 5.071  ; 5.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 3.979  ; 3.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 4.465  ; 4.465  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 4.838  ; 4.838  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 4.739  ; 4.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 4.784  ; 4.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 5.837  ; 5.837  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 2.840  ; 2.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 2.582  ; 2.582  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 4.130  ; 4.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 2.899  ; 2.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 2.913  ; 2.913  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 2.165  ; 2.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 2.371  ; 2.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 2.753  ; 2.753  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 2.165  ; 2.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 2.497  ; 2.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 2.382  ; 2.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 2.485  ; 2.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 2.524  ; 2.524  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 2.583  ; 2.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 2.651  ; 2.651  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 2.183  ; 2.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 2.689  ; 2.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 3.990  ; 3.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 2.757  ; 2.757  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 3.536  ; 3.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 2.809  ; 2.809  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 3.670  ; 3.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 4.791  ; 4.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 3.310  ; 3.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 3.699  ; 3.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 2.991  ; 2.991  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 3.005  ; 3.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 3.005  ; 3.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 3.231  ; 3.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 3.185  ; 3.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 3.235  ; 3.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 3.211  ; 2.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 2.258  ; 2.258  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 3.180  ; 3.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 3.050  ; 3.050  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 3.543  ; 3.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 3.752  ; 3.752  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 3.776  ; 3.776  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 6.128  ; 6.128  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 6.132  ; 6.132  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 3.344  ; 3.344  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 3.580  ; 3.580  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 3.726  ; 3.726  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 4.433  ; 4.433  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 3.694  ; 3.694  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 4.349  ; 4.349  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 3.579  ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 3.731  ; 3.731  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 3.344  ; 3.344  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 3.542  ; 3.542  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 3.922  ; 3.922  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 3.713  ; 3.713  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 3.965  ; 3.965  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 3.974  ; 3.974  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 4.118  ; 4.118  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 4.242  ; 4.242  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 3.584  ; 3.584  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 4.398  ; 4.398  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 3.609  ; 3.609  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 3.920  ; 3.920  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 4.698  ; 4.698  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 3.769  ; 3.769  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 3.996  ; 3.996  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 3.921  ; 3.921  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 3.531  ; 3.531  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 3.017  ; 3.017  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 4.865  ; 4.865  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 5.816  ; 5.816  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 5.843  ; 5.843  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 6.625  ; 6.625  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 6.547  ; 6.547  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 5.843  ; 5.843  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 6.618  ; 6.618  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 6.112  ; 6.112  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 6.104  ; 6.104  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 6.254  ; 6.254  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 5.948  ; 5.948  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 5.376  ; 5.376  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 5.482  ; 5.482  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 6.041  ; 6.041  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 5.831  ; 5.831  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 5.909  ; 5.909  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 5.376  ; 5.376  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 6.339  ; 6.339  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 5.748  ; 5.748  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 6.551  ; 6.551  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 6.000  ; 6.000  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 6.676  ; 6.676  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 5.761  ; 5.761  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 6.512  ; 6.512  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 6.051  ; 6.051  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 6.102  ; 6.102  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 5.754  ; 5.754  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 5.962  ; 5.962  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 3.237  ; 3.237  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 3.496  ; 3.496  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 3.387  ; 3.387  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 3.237  ; 3.237  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 3.977  ; 3.977  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 3.926  ; 3.926  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 5.378  ; 5.378  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 5.074  ; 5.074  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 4.988  ; 4.988  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 4.822  ; 4.822  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 4.885  ; 4.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 5.364  ; 5.364  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 5.207  ; 5.207  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 5.065  ; 5.065  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 4.757  ; 4.757  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 4.895  ; 4.895  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 4.749  ; 4.749  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 4.956  ; 4.956  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 3.685  ; 3.556  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 5.711  ; 5.711  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 5.983  ; 5.983  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 5.711  ; 5.711  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 6.217  ; 6.217  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 6.684  ; 6.684  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 6.401  ; 6.401  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 6.414  ; 6.414  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 6.604  ; 6.604  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 6.880  ; 6.880  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 6.460  ; 6.460  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 6.621  ; 6.621  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 6.216  ; 6.216  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 5.902  ; 5.902  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 5.856  ; 5.856  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 6.249  ; 6.249  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 6.249  ; 6.249  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 5.885  ; 5.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 6.013  ; 6.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 6.411  ; 6.411  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 6.183  ; 6.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 6.888  ; 6.888  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 6.258  ; 6.258  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 6.990  ; 6.990  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 6.120  ; 6.120  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 6.591  ; 6.591  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 6.173  ; 6.173  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 6.105  ; 6.105  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 6.278  ; 6.278  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 6.216  ; 6.216  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 5.885  ; 5.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 6.569  ; 6.569  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 6.217  ; 6.217  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 6.107  ; 6.107  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 5.215  ; 5.215  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 3.945  ; 3.945  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 4.431  ; 4.431  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 4.804  ; 4.804  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 4.705  ; 4.705  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 4.750  ; 4.750  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 5.889  ; 5.889  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 2.970  ; 2.970  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 2.914  ; 3.122  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 3.243  ; 3.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 3.248  ; 3.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 2.946  ; 2.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 3.760  ; 3.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 4.330  ; 4.330  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 3.728  ; 3.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 4.383  ; 4.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 3.613  ; 3.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 3.765  ; 3.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 3.207  ; 3.207  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 3.527  ; 3.527  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 3.913  ; 3.913  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 3.704  ; 3.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 3.392  ; 3.392  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 2.946  ; 2.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 3.217  ; 3.217  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 3.130  ; 3.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 3.007  ; 3.007  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 3.082  ; 3.082  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 2.994  ; 2.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 3.192  ; 3.192  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 3.730  ; 3.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 3.793  ; 3.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 3.943  ; 3.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 3.951  ; 3.951  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.531  ; 3.531  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 3.100  ; 3.100  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 3.196  ; 3.196  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 4.138  ; 4.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 3.406  ; 3.406  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.911  ; 4.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 3.253  ; 3.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 2.887  ; 2.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 2.888  ; 2.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 2.887  ; 2.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 3.006  ; 3.006  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 2.943  ; 2.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 2.988  ; 2.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 2.976  ; 2.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 3.053  ; 3.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 3.059  ; 3.059  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 3.453  ; 3.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 3.628  ; 3.628  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 2.938  ; 2.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 2.295  ; 2.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 2.466  ; 2.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 2.224  ; 2.224  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 2.660  ; 2.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 2.766  ; 2.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 3.459  ; 3.459  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 3.477  ; 3.477  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 3.396  ; 3.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 3.318  ; 3.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 3.295  ; 3.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 3.820  ; 3.820  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 3.514  ; 3.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 3.789  ; 3.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 3.488  ; 3.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 3.537  ; 3.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 3.032  ; 3.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 3.230  ; 3.230  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 3.668  ; 3.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 2.982  ; 2.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 2.766  ; 2.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 3.015  ; 3.015  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 3.537  ; 3.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 3.006  ; 3.006  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 3.540  ; 3.540  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 3.101  ; 3.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 3.190  ; 3.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 3.366  ; 3.366  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 3.625  ; 3.625  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 4.046  ; 3.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 3.366  ; 3.366  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 3.488  ; 3.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 3.416  ; 3.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 3.106  ; 3.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 3.430  ; 3.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 3.249  ; 3.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 3.638  ; 3.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 3.285  ; 3.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 3.390  ; 3.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 3.414  ; 3.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 3.401  ; 3.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 3.225  ; 3.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 2.905  ; 2.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 3.949  ; 3.949  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 2.268  ; 2.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 3.463  ; 3.463  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 3.117  ; 3.117  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.160  ; 3.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 5.022  ; 5.022  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 4.856  ; 4.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 4.919  ; 4.919  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 5.398  ; 5.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 5.241  ; 5.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 5.099  ; 5.099  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 4.803  ; 4.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 4.941  ; 4.929  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 4.783  ; 4.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 4.990  ; 5.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 3.062  ; 3.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 3.141  ; 3.141  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 3.266  ; 3.266  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 3.238  ; 3.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 3.062  ; 3.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.556  ; 3.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 2.300  ; 2.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 2.521  ; 2.521  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 2.900  ; 2.900  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 2.900  ; 2.900  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 2.934  ; 2.934  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 2.964  ; 2.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.357  ; 3.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 3.395  ; 3.395  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 3.581  ; 3.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 3.559  ; 3.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 2.935  ; 2.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 3.103  ; 3.103  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 2.754  ; 2.754  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 2.394  ; 2.394  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 5.745  ; 5.745  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 6.017  ; 6.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 5.745  ; 5.745  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 6.251  ; 6.251  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 6.503  ; 6.503  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 6.435  ; 6.435  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 6.448  ; 6.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 6.638  ; 6.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 6.914  ; 6.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 6.494  ; 6.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 6.655  ; 6.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 6.066  ; 6.066  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 5.936  ; 5.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 5.890  ; 5.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 6.283  ; 6.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 6.283  ; 6.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 5.011  ; 5.011  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 5.359  ; 5.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 5.627  ; 5.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 5.224  ; 5.224  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 5.802  ; 5.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 5.782  ; 5.782  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 6.295  ; 6.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 5.747  ; 5.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 5.947  ; 5.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 5.342  ; 5.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 5.407  ; 5.407  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 5.011  ; 5.011  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 5.072  ; 5.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.160  ; 5.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.550  ; 5.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.203  ; 5.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 5.584  ; 5.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 3.698  ; 3.698  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 5.071  ; 5.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 3.979  ; 3.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 4.465  ; 4.465  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 4.838  ; 4.838  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 4.739  ; 4.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 4.784  ; 4.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 5.837  ; 5.837  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 2.840  ; 2.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 2.582  ; 2.582  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 4.130  ; 4.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 2.899  ; 2.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 2.913  ; 2.913  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 2.165  ; 2.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 2.371  ; 2.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 2.753  ; 2.753  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 2.165  ; 2.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 2.497  ; 2.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 2.382  ; 2.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 2.485  ; 2.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 2.524  ; 2.524  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 2.583  ; 2.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 2.651  ; 2.651  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 2.183  ; 2.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 2.689  ; 2.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 3.990  ; 3.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 2.757  ; 2.757  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 3.536  ; 3.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 2.809  ; 2.809  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 3.670  ; 3.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 4.791  ; 4.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 3.310  ; 3.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 3.699  ; 3.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 2.991  ; 2.991  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 3.005  ; 3.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 3.005  ; 3.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 3.231  ; 3.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 3.185  ; 3.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 3.235  ; 3.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.211  ; 2.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 2.258  ; 2.258  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 3.180  ; 3.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.050  ; 3.050  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 3.543  ; 3.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 3.752  ; 3.752  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 3.776  ; 3.776  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 6.128  ; 6.128  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 6.132  ; 6.132  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 3.344  ; 3.344  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 3.580  ; 3.580  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 3.726  ; 3.726  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 4.433  ; 4.433  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 3.694  ; 3.694  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 4.349  ; 4.349  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 3.579  ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 3.731  ; 3.731  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 3.344  ; 3.344  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 3.542  ; 3.542  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 3.922  ; 3.922  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 3.713  ; 3.713  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 3.965  ; 3.965  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 3.974  ; 3.974  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 4.118  ; 4.118  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 4.242  ; 4.242  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 3.584  ; 3.584  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 4.398  ; 4.398  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 3.609  ; 3.609  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 3.920  ; 3.920  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 4.698  ; 4.698  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 3.769  ; 3.769  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 3.996  ; 3.996  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 3.921  ; 3.921  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.531  ; 3.531  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 3.017  ; 3.017  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.865  ; 4.865  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 5.816  ; 5.816  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 5.843  ; 5.843  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 6.625  ; 6.625  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 6.547  ; 6.547  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 5.843  ; 5.843  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 6.618  ; 6.618  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 6.112  ; 6.112  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 6.104  ; 6.104  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 6.254  ; 6.254  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 5.948  ; 5.948  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 5.376  ; 5.376  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 5.482  ; 5.482  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 6.041  ; 6.041  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 5.831  ; 5.831  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 5.909  ; 5.909  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 5.376  ; 5.376  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.339  ; 6.339  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 5.748  ; 5.748  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.551  ; 6.551  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.000  ; 6.000  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 6.676  ; 6.676  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.761  ; 5.761  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.512  ; 6.512  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 6.051  ; 6.051  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.102  ; 6.102  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.754  ; 5.754  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.962  ; 5.962  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 3.237  ; 3.237  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 3.496  ; 3.496  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 3.387  ; 3.387  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 3.237  ; 3.237  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 3.977  ; 3.977  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 3.926  ; 3.926  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 5.378  ; 5.378  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 5.074  ; 5.074  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 4.988  ; 4.988  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 4.822  ; 4.822  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 4.885  ; 4.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 5.364  ; 5.364  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 5.207  ; 5.207  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 5.065  ; 5.065  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 4.757  ; 4.757  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 4.895  ; 4.895  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 4.749  ; 4.749  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 4.956  ; 4.956  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.685  ; 3.556  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 5.711  ; 5.711  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 5.983  ; 5.983  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 5.711  ; 5.711  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 6.217  ; 6.217  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 6.684  ; 6.684  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 6.401  ; 6.401  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 6.414  ; 6.414  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 6.604  ; 6.604  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 6.880  ; 6.880  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 6.460  ; 6.460  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 6.621  ; 6.621  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 6.216  ; 6.216  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 5.902  ; 5.902  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 5.856  ; 5.856  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 6.249  ; 6.249  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 6.249  ; 6.249  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 5.885  ; 5.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 6.013  ; 6.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 6.411  ; 6.411  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 6.183  ; 6.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 6.888  ; 6.888  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 6.258  ; 6.258  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 6.990  ; 6.990  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 6.120  ; 6.120  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 6.591  ; 6.591  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 6.173  ; 6.173  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 6.105  ; 6.105  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 6.278  ; 6.278  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 6.216  ; 6.216  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.885  ; 5.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 6.569  ; 6.569  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 6.217  ; 6.217  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 6.107  ; 6.107  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 5.215  ; 5.215  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 3.945  ; 3.945  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 4.431  ; 4.431  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 4.804  ; 4.804  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 4.705  ; 4.705  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 4.750  ; 4.750  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 5.889  ; 5.889  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 2.970  ; 2.970  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 2.914  ; 3.122  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 4.840  ; 4.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 4.844  ; 4.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 4.769  ; 4.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 4.032  ; 4.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 3.720  ; 3.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 4.528  ; 4.528  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 4.363  ; 4.363  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 4.448  ; 4.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 4.363  ; 4.363  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 4.555  ; 4.555  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 4.630  ; 4.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 4.824  ; 4.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 4.816  ; 4.816  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 4.966  ; 4.966  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 4.660  ; 4.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 2.483  ; 2.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 2.877  ; 2.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 2.795  ; 2.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 2.923  ; 2.923  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 2.483  ; 2.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 2.915  ; 2.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 2.672  ; 2.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 2.890  ; 2.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 3.002  ; 3.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 2.519  ; 2.519  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 2.957  ; 2.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 2.681  ; 2.681  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 2.519  ; 2.519  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 2.525  ; 2.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 4.860  ; 4.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 5.470  ; 5.470  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 5.682  ; 5.682  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 5.165  ; 5.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 5.124  ; 5.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 4.860  ; 4.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 5.794  ; 5.794  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 5.640  ; 5.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 5.878  ; 5.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 6.354  ; 6.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 7.043  ; 7.043  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 5.388  ; 5.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 6.556  ; 6.556  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 5.954  ; 5.954  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 5.795  ; 5.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 5.514  ; 5.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 6.128  ; 6.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 2.174  ; 2.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 4.357  ; 4.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 2.120  ; 2.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 2.237  ; 2.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 2.151  ; 2.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 4.241  ; 4.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 4.162  ; 4.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 4.184  ; 4.184  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 4.564  ; 4.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 4.329  ; 4.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 3.932  ; 3.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 4.401  ; 4.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 4.942  ; 4.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 4.877  ; 4.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 4.369  ; 4.369  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 4.277  ; 4.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 3.947  ; 3.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 4.147  ; 4.147  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 4.147  ; 4.147  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 3.941  ; 3.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 3.821  ; 3.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 3.342  ; 3.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 3.670  ; 3.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 4.174  ; 4.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 4.092  ; 4.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 4.635  ; 4.635  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 3.342  ; 3.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 4.513  ; 4.513  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 4.152  ; 4.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 3.524  ; 3.524  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 3.840  ; 3.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 3.647  ; 3.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 3.529  ; 3.529  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 3.731  ; 3.731  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 3.787  ; 3.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 3.955  ; 3.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 3.616  ; 3.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 3.541  ; 3.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 3.723  ; 3.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 3.621  ; 3.621  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 3.411  ; 3.411  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 3.785  ; 3.785  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 4.103  ; 4.103  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 3.993  ; 3.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 3.936  ; 3.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 3.818  ; 3.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 4.125  ; 4.125  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]      ; CLK_PLL1      ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 4.008  ; 4.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 4.284  ; 4.284  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 4.033  ; 4.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 4.129  ; 4.129  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 4.146  ; 4.146  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 4.215  ; 4.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP        ; CLK_PLL1      ; 4.025  ; 4.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 5.546  ; 5.546  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 4.180  ; 4.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 4.293  ; 4.293  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 5.226  ; 5.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 4.012  ; 4.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 1.262  ; 2.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 2.178  ; 2.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 2.302  ; 2.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 2.180  ; 2.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 2.031  ; 2.031  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 2.017  ; 2.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 4.840  ; 4.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 4.844  ; 4.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 4.769  ; 4.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 4.032  ; 4.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 3.720  ; 3.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 4.528  ; 4.528  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 4.363  ; 4.363  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 4.448  ; 4.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 4.363  ; 4.363  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 4.555  ; 4.555  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 4.630  ; 4.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 4.824  ; 4.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 4.816  ; 4.816  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 4.966  ; 4.966  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 4.660  ; 4.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 2.483  ; 2.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 2.877  ; 2.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 2.795  ; 2.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 2.923  ; 2.923  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 2.483  ; 2.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 2.915  ; 2.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 2.672  ; 2.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 2.890  ; 2.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 3.002  ; 3.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 2.519  ; 2.519  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 2.957  ; 2.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 2.681  ; 2.681  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 2.519  ; 2.519  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 2.525  ; 2.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 4.860  ; 4.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 5.470  ; 5.470  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 5.682  ; 5.682  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 5.165  ; 5.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 5.124  ; 5.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 4.860  ; 4.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 5.794  ; 5.794  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 5.640  ; 5.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 5.878  ; 5.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.354  ; 6.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 7.043  ; 7.043  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.388  ; 5.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.556  ; 6.556  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.954  ; 5.954  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 5.795  ; 5.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.514  ; 5.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 6.128  ; 6.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 2.174  ; 2.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 4.357  ; 4.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 2.120  ; 2.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 2.237  ; 2.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 2.151  ; 2.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 4.241  ; 4.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 4.162  ; 4.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 4.184  ; 4.184  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 4.564  ; 4.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 4.329  ; 4.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 3.932  ; 3.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 4.401  ; 4.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 4.942  ; 4.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 4.877  ; 4.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 4.369  ; 4.369  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 4.277  ; 4.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 3.947  ; 3.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 4.147  ; 4.147  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 4.147  ; 4.147  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 3.941  ; 3.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 3.821  ; 3.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 3.342  ; 3.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 3.670  ; 3.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 4.174  ; 4.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 4.092  ; 4.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 4.635  ; 4.635  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 3.342  ; 3.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 4.513  ; 4.513  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 4.152  ; 4.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 3.524  ; 3.524  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 3.840  ; 3.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 3.647  ; 3.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 3.529  ; 3.529  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 3.731  ; 3.731  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 3.787  ; 3.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 3.955  ; 3.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 3.616  ; 3.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 3.541  ; 3.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 3.723  ; 3.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 3.621  ; 3.621  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 3.411  ; 3.411  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 3.785  ; 3.785  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 4.103  ; 4.103  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 3.993  ; 3.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.936  ; 3.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 3.818  ; 3.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 4.125  ; 4.125  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 4.008  ; 4.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 4.284  ; 4.284  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 4.033  ; 4.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 4.129  ; 4.129  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 4.146  ; 4.146  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 4.215  ; 4.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 4.025  ; 4.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 5.546  ; 5.546  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 4.180  ; 4.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 4.293  ; 4.293  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 5.226  ; 5.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 4.012  ; 4.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 1.262  ; 2.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 2.178  ; 2.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 2.302  ; 2.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 2.180  ; 2.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 2.031  ; 2.031  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 2.017  ; 2.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 5.399  ; 5.399  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 6.042  ; 6.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 6.499  ; 6.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 6.295  ; 6.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 5.746  ; 5.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 5.965  ; 5.965  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 6.785  ; 6.785  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 6.851  ; 6.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 6.850  ; 6.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 6.267  ; 6.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 7.092  ; 7.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 5.399  ; 5.399  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 6.575  ; 6.575  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 6.126  ; 6.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 5.491  ; 5.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 5.513  ; 5.513  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 5.630  ; 5.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 2.603  ; 2.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 2.603  ; 2.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 2.968  ; 2.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 2.961  ; 2.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 5.960  ; 5.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 6.573  ; 6.573  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 6.869  ; 6.869  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 6.647  ; 6.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 6.725  ; 6.725  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 6.847  ; 6.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 7.436  ; 7.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 7.223  ; 7.223  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 7.138  ; 7.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 6.440  ; 6.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 7.250  ; 7.250  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 5.995  ; 5.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 6.279  ; 6.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 5.960  ; 5.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 6.243  ; 6.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 6.382  ; 6.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 6.299  ; 6.299  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 5.399  ; 5.399  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 6.042  ; 6.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 6.499  ; 6.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 6.295  ; 6.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 5.746  ; 5.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 5.965  ; 5.965  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.785  ; 6.785  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.851  ; 6.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.850  ; 6.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.267  ; 6.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 7.092  ; 7.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.399  ; 5.399  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.575  ; 6.575  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 6.126  ; 6.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 5.491  ; 5.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.513  ; 5.513  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.630  ; 5.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 2.603  ; 2.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 2.603  ; 2.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 2.968  ; 2.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 2.961  ; 2.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 5.960  ; 5.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 6.573  ; 6.573  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 6.869  ; 6.869  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 6.647  ; 6.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 6.725  ; 6.725  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 6.847  ; 6.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 7.436  ; 7.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 7.223  ; 7.223  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 7.138  ; 7.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 6.440  ; 6.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 7.250  ; 7.250  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 5.995  ; 5.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 6.279  ; 6.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.960  ; 5.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 6.243  ; 6.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 6.382  ; 6.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 6.299  ; 6.299  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.141  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.141  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------+
; Progagation Delay                                                ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 23.083 ; 23.083 ; 23.083 ; 23.083 ;
; ASn          ; ACSI_WRn      ; 23.092 ; 23.092 ; 23.092 ; 23.092 ;
; ASn          ; BUTTONn       ; 20.989 ;        ;        ; 20.989 ;
; ASn          ; CA1_OUT       ; 21.963 ;        ;        ; 21.963 ;
; ASn          ; CD[0]         ; 28.528 ; 28.528 ; 28.528 ; 28.528 ;
; ASn          ; CD[1]         ; 28.944 ; 28.944 ; 28.944 ; 28.944 ;
; ASn          ; CD[2]         ; 28.033 ; 28.033 ; 28.033 ; 28.033 ;
; ASn          ; CD[3]         ; 31.971 ; 31.971 ; 31.971 ; 31.971 ;
; ASn          ; CD[4]         ; 31.975 ; 31.975 ; 31.975 ; 31.975 ;
; ASn          ; CD[5]         ; 32.615 ; 32.615 ; 32.615 ; 32.615 ;
; ASn          ; CD[6]         ; 32.561 ; 32.561 ; 32.561 ; 32.561 ;
; ASn          ; CD[7]         ; 28.317 ; 28.317 ; 28.317 ; 28.317 ;
; ASn          ; DATA[0]       ; 29.974 ; 30.430 ; 30.430 ; 29.974 ;
; ASn          ; DATA[1]       ; 32.262 ; 32.063 ; 32.063 ; 32.262 ;
; ASn          ; DATA[2]       ; 30.185 ; 30.998 ; 30.998 ; 30.185 ;
; ASn          ; DATA[3]       ; 29.658 ; 29.601 ; 29.601 ; 29.658 ;
; ASn          ; DATA[4]       ; 29.681 ; 30.134 ; 30.134 ; 29.681 ;
; ASn          ; DATA[5]       ; 31.401 ; 31.670 ; 31.670 ; 31.401 ;
; ASn          ; DATA[6]       ; 31.775 ; 31.809 ; 31.809 ; 31.775 ;
; ASn          ; DATA[7]       ; 31.875 ; 32.468 ; 32.468 ; 31.875 ;
; ASn          ; DATA[8]       ; 32.345 ; 32.345 ; 32.345 ; 32.345 ;
; ASn          ; DATA[9]       ; 32.988 ; 32.988 ; 32.988 ; 32.988 ;
; ASn          ; DATA[10]      ; 30.316 ; 30.316 ; 30.316 ; 30.316 ;
; ASn          ; DATA[11]      ; 32.749 ; 32.847 ; 32.847 ; 32.749 ;
; ASn          ; DATA[12]      ; 32.920 ; 32.920 ; 32.920 ; 32.920 ;
; ASn          ; DATA[13]      ; 30.778 ; 30.656 ; 30.656 ; 30.778 ;
; ASn          ; DATA[14]      ; 29.905 ; 29.905 ; 29.905 ; 29.905 ;
; ASn          ; DATA[15]      ; 30.940 ; 30.803 ; 30.803 ; 30.940 ;
; ASn          ; DTACKn        ; 24.836 ; 24.836 ; 24.836 ; 24.836 ;
; ASn          ; FLASH_CEn     ; 20.413 ;        ;        ; 20.413 ;
; ASn          ; FLASH_OEn     ; 19.619 ;        ;        ; 19.619 ;
; ASn          ; IDE_CS0n      ; 13.851 ;        ;        ; 13.851 ;
; ASn          ; IDE_CS1n      ; 12.631 ;        ;        ; 12.631 ;
; ASn          ; IDE_D_EN_INn  ; 14.492 ;        ;        ; 14.492 ;
; ASn          ; IDE_D_EN_OUTn ; 16.088 ;        ;        ; 16.088 ;
; ASn          ; IDE_IORDn     ; 15.733 ;        ;        ; 15.733 ;
; ASn          ; IDE_IOWRn     ; 15.394 ;        ;        ; 15.394 ;
; ASn          ; JOY_RHn       ; 14.716 ;        ;        ; 14.716 ;
; ASn          ; JOY_RLn       ; 14.957 ;        ;        ; 14.957 ;
; ASn          ; JOY_WEn       ;        ; 14.599 ; 14.599 ;        ;
; ASn          ; JOY_WL        ;        ; 14.871 ; 14.871 ;        ;
; ASn          ; RAM_DATA[0]   ; 31.258 ; 31.714 ; 31.714 ; 31.258 ;
; ASn          ; RAM_DATA[1]   ; 33.189 ; 32.990 ; 32.990 ; 33.189 ;
; ASn          ; RAM_DATA[2]   ; 30.935 ; 31.748 ; 31.748 ; 30.935 ;
; ASn          ; RAM_DATA[3]   ; 31.957 ; 31.900 ; 31.900 ; 31.957 ;
; ASn          ; RAM_DATA[4]   ; 31.930 ; 32.383 ; 32.383 ; 31.930 ;
; ASn          ; RAM_DATA[5]   ; 32.905 ; 33.174 ; 33.174 ; 32.905 ;
; ASn          ; RAM_DATA[6]   ; 32.511 ; 32.545 ; 32.545 ; 32.511 ;
; ASn          ; RAM_DATA[7]   ; 32.044 ; 32.637 ; 32.637 ; 32.044 ;
; ASn          ; RAM_DATA[8]   ; 32.306 ; 32.306 ; 32.306 ; 32.306 ;
; ASn          ; RAM_DATA[9]   ; 32.999 ; 32.999 ; 32.999 ; 32.999 ;
; ASn          ; RAM_DATA[10]  ; 31.526 ; 31.526 ; 31.526 ; 31.526 ;
; ASn          ; RAM_DATA[11]  ; 31.431 ; 31.529 ; 31.529 ; 31.431 ;
; ASn          ; RAM_DATA[12]  ; 32.586 ; 32.586 ; 32.586 ; 32.586 ;
; ASn          ; RAM_DATA[13]  ; 32.564 ; 32.442 ; 32.442 ; 32.564 ;
; ASn          ; RAM_DATA[14]  ; 32.032 ; 32.032 ; 32.032 ; 32.032 ;
; ASn          ; RAM_DATA[15]  ; 32.454 ; 32.317 ; 32.317 ; 32.454 ;
; ASn          ; ROM0n         ; 16.366 ;        ;        ; 16.366 ;
; ASn          ; ROM1n         ; 16.094 ;        ;        ; 16.094 ;
; ASn          ; ROM2n         ; 18.053 ;        ;        ; 18.053 ;
; ASn          ; ROM3n         ; 15.611 ;        ;        ; 15.611 ;
; ASn          ; ROM4n         ; 15.766 ;        ;        ; 15.766 ;
; ASn          ; ROM5n         ; 18.044 ;        ;        ; 18.044 ;
; ASn          ; ROM6n         ; 17.579 ;        ;        ; 17.579 ;
; COM_CTS      ; DATA[2]       ;        ; 24.709 ; 24.709 ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 25.459 ; 25.459 ;        ;
; COM_DCD      ; DATA[1]       ;        ; 26.470 ; 26.470 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 27.397 ; 27.397 ;        ;
; COM_RI       ; DATA[6]       ;        ; 24.094 ; 24.094 ;        ;
; COM_RI       ; RAM_DATA[6]   ;        ; 24.830 ; 24.830 ;        ;
; CONFIG[1]    ; DATA[7]       ; 26.655 ; 26.655 ; 26.655 ; 26.655 ;
; CONFIG[1]    ; HSYNC         ; 12.714 ; 12.714 ; 12.714 ; 12.714 ;
; CONFIG[1]    ; RAM_DATA[7]   ; 26.824 ; 26.824 ; 26.824 ; 26.824 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 15.729 ; 15.375 ; 15.375 ; 15.729 ;
; CONFIG[1]    ; RAM_DATA[13]  ; 16.401 ; 16.642 ; 16.642 ; 16.401 ;
; CONFIG[1]    ; RAM_DATA[14]  ; 15.994 ; 15.761 ; 15.761 ; 15.994 ;
; CONFIG[1]    ; RAM_DATA[15]  ; 15.088 ; 15.362 ; 15.362 ; 15.088 ;
; CONFIG[1]    ; VSYNC         ; 12.351 ; 12.351 ; 12.351 ; 12.351 ;
; CONFIG[2]    ; DATA[7]       ; 26.519 ; 26.519 ; 26.519 ; 26.519 ;
; CONFIG[2]    ; HSYNC         ; 12.442 ; 12.442 ; 12.442 ; 12.442 ;
; CONFIG[2]    ; RAM_DATA[7]   ; 26.688 ; 26.688 ; 26.688 ; 26.688 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 14.767 ; 15.121 ; 15.121 ; 14.767 ;
; CONFIG[2]    ; RAM_DATA[13]  ; 16.034 ; 15.793 ; 15.793 ; 16.034 ;
; CONFIG[2]    ; RAM_DATA[14]  ; 15.153 ; 15.386 ; 15.386 ; 15.153 ;
; CONFIG[2]    ; RAM_DATA[15]  ; 14.754 ; 14.480 ; 14.480 ; 14.754 ;
; CONFIG[2]    ; VSYNC         ; 12.094 ; 12.094 ; 12.094 ; 12.094 ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 17.486 ; 17.486 ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 14.935 ; 14.935 ;        ;
; CONFIG[6]    ; DATA[0]       ; 21.623 ; 21.623 ; 21.623 ; 21.623 ;
; CONFIG[6]    ; DATA[1]       ; 22.767 ; 22.767 ; 22.767 ; 22.767 ;
; CONFIG[6]    ; DATA[2]       ; 22.271 ; 22.271 ; 22.271 ; 22.271 ;
; CONFIG[6]    ; DATA[3]       ; 23.180 ; 22.831 ; 22.831 ; 23.180 ;
; CONFIG[6]    ; DATA[4]       ; 23.211 ; 23.560 ; 23.560 ; 23.211 ;
; CONFIG[6]    ; DATA[5]       ; 25.278 ; 25.627 ; 25.627 ; 25.278 ;
; CONFIG[6]    ; DATA[6]       ; 25.410 ; 25.759 ; 25.759 ; 25.410 ;
; CONFIG[6]    ; DATA[7]       ; 26.120 ; 26.469 ; 26.469 ; 26.120 ;
; CONFIG[6]    ; DATA[8]       ; 24.753 ; 24.404 ; 24.404 ; 24.753 ;
; CONFIG[6]    ; DATA[9]       ; 25.935 ; 25.923 ; 25.923 ; 25.935 ;
; CONFIG[6]    ; DATA[10]      ; 23.316 ; 23.665 ; 23.665 ; 23.316 ;
; CONFIG[6]    ; DATA[11]      ; 25.711 ; 25.885 ; 25.885 ; 25.711 ;
; CONFIG[6]    ; DATA[12]      ; 24.623 ; 24.972 ; 24.972 ; 24.623 ;
; CONFIG[6]    ; DATA[13]      ; 23.798 ; 24.147 ; 24.147 ; 23.798 ;
; CONFIG[6]    ; DATA[14]      ; 22.454 ; 22.480 ; 22.480 ; 22.454 ;
; CONFIG[6]    ; DATA[15]      ; 23.326 ; 23.675 ; 23.675 ; 23.326 ;
; CONFIG[6]    ; DTACKn        ; 19.020 ; 19.020 ; 19.020 ; 19.020 ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 16.100 ; 16.100 ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 16.489 ; 16.489 ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 18.429 ; 18.080 ; 18.080 ; 18.429 ;
; CONFIG[6]    ; FLASH_OEn     ; 17.635 ; 17.286 ; 17.286 ; 17.635 ;
; CONFIG[6]    ; RAM_DATA[0]   ; 22.907 ; 22.907 ; 22.907 ; 22.907 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 23.694 ; 23.694 ; 23.694 ; 23.694 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 23.021 ; 23.021 ; 23.021 ; 23.021 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 25.479 ; 25.130 ; 25.130 ; 25.479 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 25.460 ; 25.809 ; 25.809 ; 25.460 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 26.782 ; 27.131 ; 27.131 ; 26.782 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 26.146 ; 26.495 ; 26.495 ; 26.146 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 26.289 ; 26.638 ; 26.638 ; 26.289 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 24.714 ; 24.365 ; 24.365 ; 24.714 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 25.946 ; 25.934 ; 25.934 ; 25.946 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 24.526 ; 24.875 ; 24.875 ; 24.526 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 24.393 ; 24.567 ; 24.567 ; 24.393 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 24.289 ; 24.638 ; 24.638 ; 24.289 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 25.584 ; 25.933 ; 25.933 ; 25.584 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 24.581 ; 24.607 ; 24.607 ; 24.581 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 24.840 ; 25.189 ; 25.189 ; 24.840 ;
; CONFIG[6]    ; ROM2n         ; 16.069 ; 15.720 ; 15.720 ; 16.069 ;
; CRT_PIN3     ; DATA[7]       ; 23.321 ; 23.321 ; 23.321 ; 23.321 ;
; CRT_PIN3     ; RAM_DATA[7]   ; 23.490 ; 23.490 ; 23.490 ; 23.490 ;
; CRT_PIN3     ; RAM_DATA[12]  ; 12.419 ; 12.065 ; 12.065 ; 12.419 ;
; CRT_PIN3     ; RAM_DATA[13]  ; 13.091 ; 13.332 ; 13.332 ; 13.091 ;
; CRT_PIN3     ; RAM_DATA[14]  ; 12.684 ; 12.451 ; 12.451 ; 12.684 ;
; CRT_PIN3     ; RAM_DATA[15]  ; 11.778 ; 12.052 ; 12.052 ; 11.778 ;
; DATA[0]      ; DATA[0]       ; 19.937 ;        ;        ; 19.937 ;
; DATA[0]      ; RAM_DATA[0]   ; 21.221 ;        ;        ; 21.221 ;
; DATA[1]      ; DATA[1]       ; 20.879 ;        ;        ; 20.879 ;
; DATA[1]      ; RAM_DATA[1]   ; 21.806 ;        ;        ; 21.806 ;
; DATA[2]      ; DATA[2]       ; 20.807 ;        ;        ; 20.807 ;
; DATA[2]      ; RAM_DATA[2]   ; 21.557 ;        ;        ; 21.557 ;
; DATA[3]      ; DATA[3]       ; 20.099 ;        ;        ; 20.099 ;
; DATA[3]      ; RAM_DATA[3]   ; 22.398 ;        ;        ; 22.398 ;
; DATA[4]      ; DATA[4]       ; 20.034 ;        ;        ; 20.034 ;
; DATA[4]      ; RAM_DATA[4]   ; 22.283 ;        ;        ; 22.283 ;
; DATA[5]      ; DATA[5]       ; 22.880 ;        ;        ; 22.880 ;
; DATA[5]      ; RAM_DATA[5]   ; 24.384 ;        ;        ; 24.384 ;
; DATA[6]      ; DATA[6]       ; 22.225 ;        ;        ; 22.225 ;
; DATA[6]      ; RAM_DATA[6]   ; 22.961 ;        ;        ; 22.961 ;
; DATA[7]      ; DATA[7]       ; 23.209 ;        ;        ; 23.209 ;
; DATA[7]      ; RAM_DATA[7]   ; 23.378 ;        ;        ; 23.378 ;
; DATA[8]      ; DATA[8]       ; 23.824 ;        ;        ; 23.824 ;
; DATA[8]      ; RAM_DATA[8]   ; 23.785 ;        ;        ; 23.785 ;
; DATA[9]      ; DATA[9]       ; 24.810 ;        ;        ; 24.810 ;
; DATA[9]      ; RAM_DATA[9]   ; 24.821 ;        ;        ; 24.821 ;
; DATA[10]     ; DATA[10]      ; 20.286 ;        ;        ; 20.286 ;
; DATA[10]     ; RAM_DATA[10]  ; 21.496 ;        ;        ; 21.496 ;
; DATA[11]     ; DATA[11]      ; 23.334 ;        ;        ; 23.334 ;
; DATA[11]     ; RAM_DATA[11]  ; 22.016 ;        ;        ; 22.016 ;
; DATA[12]     ; DATA[12]      ; 21.513 ;        ;        ; 21.513 ;
; DATA[12]     ; RAM_DATA[12]  ; 21.179 ;        ;        ; 21.179 ;
; DATA[13]     ; DATA[13]      ; 20.805 ;        ;        ; 20.805 ;
; DATA[13]     ; RAM_DATA[13]  ; 22.591 ;        ;        ; 22.591 ;
; DATA[14]     ; DATA[14]      ; 20.326 ;        ;        ; 20.326 ;
; DATA[14]     ; RAM_DATA[14]  ; 22.453 ;        ;        ; 22.453 ;
; DATA[15]     ; DATA[15]      ; 21.786 ;        ;        ; 21.786 ;
; DATA[15]     ; RAM_DATA[15]  ; 23.300 ;        ;        ; 23.300 ;
; FC[0]        ; ACSI_RDn      ; 20.164 ; 20.164 ; 20.164 ; 20.164 ;
; FC[0]        ; ACSI_WRn      ; 20.173 ; 20.173 ; 20.173 ; 20.173 ;
; FC[0]        ; BUTTONn       ; 16.891 ; 16.891 ; 16.891 ; 16.891 ;
; FC[0]        ; CA1_OUT       ; 19.044 ; 19.044 ; 19.044 ; 19.044 ;
; FC[0]        ; CD[0]         ; 25.609 ; 25.609 ; 25.609 ; 25.609 ;
; FC[0]        ; CD[1]         ; 26.025 ; 26.025 ; 26.025 ; 26.025 ;
; FC[0]        ; CD[2]         ; 25.114 ; 25.114 ; 25.114 ; 25.114 ;
; FC[0]        ; CD[3]         ; 29.052 ; 29.052 ; 29.052 ; 29.052 ;
; FC[0]        ; CD[4]         ; 29.056 ; 29.056 ; 29.056 ; 29.056 ;
; FC[0]        ; CD[5]         ; 29.696 ; 29.696 ; 29.696 ; 29.696 ;
; FC[0]        ; CD[6]         ; 29.642 ; 29.642 ; 29.642 ; 29.642 ;
; FC[0]        ; CD[7]         ; 25.398 ; 25.398 ; 25.398 ; 25.398 ;
; FC[0]        ; DATA[0]       ; 32.558 ; 32.558 ; 32.558 ; 32.558 ;
; FC[0]        ; DATA[1]       ; 34.191 ; 34.191 ; 34.191 ; 34.191 ;
; FC[0]        ; DATA[2]       ; 33.126 ; 33.126 ; 33.126 ; 33.126 ;
; FC[0]        ; DATA[3]       ; 31.424 ; 31.424 ; 31.424 ; 31.424 ;
; FC[0]        ; DATA[4]       ; 32.262 ; 32.262 ; 32.262 ; 32.262 ;
; FC[0]        ; DATA[5]       ; 33.798 ; 33.798 ; 33.798 ; 33.798 ;
; FC[0]        ; DATA[6]       ; 33.937 ; 33.937 ; 33.937 ; 33.937 ;
; FC[0]        ; DATA[7]       ; 34.596 ; 34.596 ; 34.596 ; 34.596 ;
; FC[0]        ; DATA[8]       ; 34.473 ; 34.473 ; 34.473 ; 34.473 ;
; FC[0]        ; DATA[9]       ; 35.116 ; 35.116 ; 35.116 ; 35.116 ;
; FC[0]        ; DATA[10]      ; 32.444 ; 32.444 ; 32.444 ; 32.444 ;
; FC[0]        ; DATA[11]      ; 34.975 ; 34.975 ; 34.975 ; 34.975 ;
; FC[0]        ; DATA[12]      ; 35.048 ; 35.048 ; 35.048 ; 35.048 ;
; FC[0]        ; DATA[13]      ; 32.906 ; 32.906 ; 32.906 ; 32.906 ;
; FC[0]        ; DATA[14]      ; 32.033 ; 32.033 ; 32.033 ; 32.033 ;
; FC[0]        ; DATA[15]      ; 33.068 ; 33.068 ; 33.068 ; 33.068 ;
; FC[0]        ; DTACKn        ; 24.095 ; 24.095 ; 24.095 ; 24.095 ;
; FC[0]        ; FLASH_CEn     ; 20.033 ; 20.033 ; 20.033 ; 20.033 ;
; FC[0]        ; FLASH_OEn     ; 19.239 ; 19.239 ; 19.239 ; 19.239 ;
; FC[0]        ; JOY_RHn       ; 17.488 ; 17.488 ; 17.488 ; 17.488 ;
; FC[0]        ; JOY_RLn       ; 17.729 ; 17.729 ; 17.729 ; 17.729 ;
; FC[0]        ; JOY_WEn       ; 17.371 ; 17.371 ; 17.371 ; 17.371 ;
; FC[0]        ; JOY_WL        ; 17.643 ; 17.643 ; 17.643 ; 17.643 ;
; FC[0]        ; RAM_DATA[0]   ; 33.842 ; 33.842 ; 33.842 ; 33.842 ;
; FC[0]        ; RAM_DATA[1]   ; 35.118 ; 35.118 ; 35.118 ; 35.118 ;
; FC[0]        ; RAM_DATA[2]   ; 33.876 ; 33.876 ; 33.876 ; 33.876 ;
; FC[0]        ; RAM_DATA[3]   ; 33.723 ; 33.723 ; 33.723 ; 33.723 ;
; FC[0]        ; RAM_DATA[4]   ; 34.511 ; 34.511 ; 34.511 ; 34.511 ;
; FC[0]        ; RAM_DATA[5]   ; 35.302 ; 35.302 ; 35.302 ; 35.302 ;
; FC[0]        ; RAM_DATA[6]   ; 34.673 ; 34.673 ; 34.673 ; 34.673 ;
; FC[0]        ; RAM_DATA[7]   ; 34.765 ; 34.765 ; 34.765 ; 34.765 ;
; FC[0]        ; RAM_DATA[8]   ; 34.434 ; 34.434 ; 34.434 ; 34.434 ;
; FC[0]        ; RAM_DATA[9]   ; 35.127 ; 35.127 ; 35.127 ; 35.127 ;
; FC[0]        ; RAM_DATA[10]  ; 33.654 ; 33.654 ; 33.654 ; 33.654 ;
; FC[0]        ; RAM_DATA[11]  ; 33.657 ; 33.657 ; 33.657 ; 33.657 ;
; FC[0]        ; RAM_DATA[12]  ; 34.714 ; 34.714 ; 34.714 ; 34.714 ;
; FC[0]        ; RAM_DATA[13]  ; 34.692 ; 34.692 ; 34.692 ; 34.692 ;
; FC[0]        ; RAM_DATA[14]  ; 34.160 ; 34.160 ; 34.160 ; 34.160 ;
; FC[0]        ; RAM_DATA[15]  ; 34.582 ; 34.582 ; 34.582 ; 34.582 ;
; FC[0]        ; ROM0n         ; 15.986 ; 15.986 ; 15.986 ; 15.986 ;
; FC[0]        ; ROM1n         ; 15.714 ; 15.714 ; 15.714 ; 15.714 ;
; FC[0]        ; ROM2n         ; 17.673 ; 17.673 ; 17.673 ; 17.673 ;
; FC[0]        ; ROM3n         ; 15.231 ; 15.231 ; 15.231 ; 15.231 ;
; FC[0]        ; ROM4n         ; 15.386 ; 15.386 ; 15.386 ; 15.386 ;
; FC[0]        ; ROM5n         ; 17.664 ; 17.664 ; 17.664 ; 17.664 ;
; FC[0]        ; ROM6n         ; 17.199 ; 17.199 ; 17.199 ; 17.199 ;
; FC[1]        ; ACSI_RDn      ; 20.136 ; 20.136 ; 20.136 ; 20.136 ;
; FC[1]        ; ACSI_WRn      ; 20.145 ; 20.145 ; 20.145 ; 20.145 ;
; FC[1]        ; BUTTONn       ; 16.619 ; 16.619 ; 16.619 ; 16.619 ;
; FC[1]        ; CA1_OUT       ; 19.016 ; 19.016 ; 19.016 ; 19.016 ;
; FC[1]        ; CD[0]         ; 25.581 ; 25.581 ; 25.581 ; 25.581 ;
; FC[1]        ; CD[1]         ; 25.997 ; 25.997 ; 25.997 ; 25.997 ;
; FC[1]        ; CD[2]         ; 25.086 ; 25.086 ; 25.086 ; 25.086 ;
; FC[1]        ; CD[3]         ; 29.024 ; 29.024 ; 29.024 ; 29.024 ;
; FC[1]        ; CD[4]         ; 29.028 ; 29.028 ; 29.028 ; 29.028 ;
; FC[1]        ; CD[5]         ; 29.668 ; 29.668 ; 29.668 ; 29.668 ;
; FC[1]        ; CD[6]         ; 29.614 ; 29.614 ; 29.614 ; 29.614 ;
; FC[1]        ; CD[7]         ; 25.370 ; 25.370 ; 25.370 ; 25.370 ;
; FC[1]        ; DATA[0]       ; 32.523 ; 32.523 ; 32.523 ; 32.523 ;
; FC[1]        ; DATA[1]       ; 34.156 ; 34.156 ; 34.156 ; 34.156 ;
; FC[1]        ; DATA[2]       ; 33.091 ; 33.091 ; 33.091 ; 33.091 ;
; FC[1]        ; DATA[3]       ; 31.389 ; 31.389 ; 31.389 ; 31.389 ;
; FC[1]        ; DATA[4]       ; 32.227 ; 32.227 ; 32.227 ; 32.227 ;
; FC[1]        ; DATA[5]       ; 33.763 ; 33.763 ; 33.763 ; 33.763 ;
; FC[1]        ; DATA[6]       ; 33.902 ; 33.902 ; 33.902 ; 33.902 ;
; FC[1]        ; DATA[7]       ; 34.561 ; 34.561 ; 34.561 ; 34.561 ;
; FC[1]        ; DATA[8]       ; 34.438 ; 34.438 ; 34.438 ; 34.438 ;
; FC[1]        ; DATA[9]       ; 35.081 ; 35.081 ; 35.081 ; 35.081 ;
; FC[1]        ; DATA[10]      ; 32.409 ; 32.409 ; 32.409 ; 32.409 ;
; FC[1]        ; DATA[11]      ; 34.940 ; 34.940 ; 34.940 ; 34.940 ;
; FC[1]        ; DATA[12]      ; 35.013 ; 35.013 ; 35.013 ; 35.013 ;
; FC[1]        ; DATA[13]      ; 32.871 ; 32.871 ; 32.871 ; 32.871 ;
; FC[1]        ; DATA[14]      ; 31.998 ; 31.998 ; 31.998 ; 31.998 ;
; FC[1]        ; DATA[15]      ; 33.033 ; 33.033 ; 33.033 ; 33.033 ;
; FC[1]        ; DTACKn        ; 24.060 ; 24.060 ; 24.060 ; 24.060 ;
; FC[1]        ; FLASH_CEn     ; 20.293 ; 20.293 ; 20.293 ; 20.293 ;
; FC[1]        ; FLASH_OEn     ; 19.499 ; 19.499 ; 19.499 ; 19.499 ;
; FC[1]        ; JOY_RHn       ; 17.460 ; 17.460 ; 17.460 ; 17.460 ;
; FC[1]        ; JOY_RLn       ; 17.701 ; 17.701 ; 17.701 ; 17.701 ;
; FC[1]        ; JOY_WEn       ; 17.343 ; 17.343 ; 17.343 ; 17.343 ;
; FC[1]        ; JOY_WL        ; 17.615 ; 17.615 ; 17.615 ; 17.615 ;
; FC[1]        ; RAM_DATA[0]   ; 33.807 ; 33.807 ; 33.807 ; 33.807 ;
; FC[1]        ; RAM_DATA[1]   ; 35.083 ; 35.083 ; 35.083 ; 35.083 ;
; FC[1]        ; RAM_DATA[2]   ; 33.841 ; 33.841 ; 33.841 ; 33.841 ;
; FC[1]        ; RAM_DATA[3]   ; 33.688 ; 33.688 ; 33.688 ; 33.688 ;
; FC[1]        ; RAM_DATA[4]   ; 34.476 ; 34.476 ; 34.476 ; 34.476 ;
; FC[1]        ; RAM_DATA[5]   ; 35.267 ; 35.267 ; 35.267 ; 35.267 ;
; FC[1]        ; RAM_DATA[6]   ; 34.638 ; 34.638 ; 34.638 ; 34.638 ;
; FC[1]        ; RAM_DATA[7]   ; 34.730 ; 34.730 ; 34.730 ; 34.730 ;
; FC[1]        ; RAM_DATA[8]   ; 34.399 ; 34.399 ; 34.399 ; 34.399 ;
; FC[1]        ; RAM_DATA[9]   ; 35.092 ; 35.092 ; 35.092 ; 35.092 ;
; FC[1]        ; RAM_DATA[10]  ; 33.619 ; 33.619 ; 33.619 ; 33.619 ;
; FC[1]        ; RAM_DATA[11]  ; 33.622 ; 33.622 ; 33.622 ; 33.622 ;
; FC[1]        ; RAM_DATA[12]  ; 34.679 ; 34.679 ; 34.679 ; 34.679 ;
; FC[1]        ; RAM_DATA[13]  ; 34.657 ; 34.657 ; 34.657 ; 34.657 ;
; FC[1]        ; RAM_DATA[14]  ; 34.125 ; 34.125 ; 34.125 ; 34.125 ;
; FC[1]        ; RAM_DATA[15]  ; 34.547 ; 34.547 ; 34.547 ; 34.547 ;
; FC[1]        ; ROM0n         ; 16.246 ; 16.246 ; 16.246 ; 16.246 ;
; FC[1]        ; ROM1n         ; 15.974 ; 15.974 ; 15.974 ; 15.974 ;
; FC[1]        ; ROM2n         ; 17.933 ; 17.933 ; 17.933 ; 17.933 ;
; FC[1]        ; ROM3n         ; 15.491 ; 15.491 ; 15.491 ; 15.491 ;
; FC[1]        ; ROM4n         ; 15.646 ; 15.646 ; 15.646 ; 15.646 ;
; FC[1]        ; ROM5n         ; 17.924 ; 17.924 ; 17.924 ; 17.924 ;
; FC[1]        ; ROM6n         ; 17.459 ; 17.459 ; 17.459 ; 17.459 ;
; FC[2]        ; ACSI_RDn      ; 20.080 ; 20.080 ; 20.080 ; 20.080 ;
; FC[2]        ; ACSI_WRn      ; 20.089 ; 20.089 ; 20.089 ; 20.089 ;
; FC[2]        ; CA1_OUT       ;        ; 18.960 ; 18.960 ;        ;
; FC[2]        ; CD[0]         ; 25.525 ; 25.525 ; 25.525 ; 25.525 ;
; FC[2]        ; CD[1]         ; 25.941 ; 25.941 ; 25.941 ; 25.941 ;
; FC[2]        ; CD[2]         ; 25.030 ; 25.030 ; 25.030 ; 25.030 ;
; FC[2]        ; CD[3]         ; 28.968 ; 28.968 ; 28.968 ; 28.968 ;
; FC[2]        ; CD[4]         ; 28.972 ; 28.972 ; 28.972 ; 28.972 ;
; FC[2]        ; CD[5]         ; 29.612 ; 29.612 ; 29.612 ; 29.612 ;
; FC[2]        ; CD[6]         ; 29.558 ; 29.558 ; 29.558 ; 29.558 ;
; FC[2]        ; CD[7]         ; 25.314 ; 25.314 ; 25.314 ; 25.314 ;
; FC[2]        ; DATA[0]       ; 32.463 ; 30.199 ; 30.199 ; 32.463 ;
; FC[2]        ; DATA[1]       ; 34.096 ; 31.570 ; 31.570 ; 34.096 ;
; FC[2]        ; DATA[2]       ; 33.031 ; 30.041 ; 30.041 ; 33.031 ;
; FC[2]        ; DATA[3]       ; 31.329 ; 29.507 ; 29.507 ; 31.329 ;
; FC[2]        ; DATA[4]       ; 32.167 ; 29.854 ; 29.854 ; 32.167 ;
; FC[2]        ; DATA[5]       ; 33.703 ; 31.475 ; 31.475 ; 33.703 ;
; FC[2]        ; DATA[6]       ; 33.842 ; 30.971 ; 30.971 ; 33.842 ;
; FC[2]        ; DATA[7]       ; 34.501 ; 31.330 ; 31.330 ; 34.501 ;
; FC[2]        ; DATA[8]       ; 34.378 ; 34.378 ; 34.378 ; 34.378 ;
; FC[2]        ; DATA[9]       ; 35.021 ; 35.021 ; 35.021 ; 35.021 ;
; FC[2]        ; DATA[10]      ; 32.349 ; 32.349 ; 32.349 ; 32.349 ;
; FC[2]        ; DATA[11]      ; 34.880 ; 34.782 ; 34.782 ; 34.880 ;
; FC[2]        ; DATA[12]      ; 34.953 ; 34.953 ; 34.953 ; 34.953 ;
; FC[2]        ; DATA[13]      ; 32.689 ; 32.811 ; 32.811 ; 32.689 ;
; FC[2]        ; DATA[14]      ; 31.938 ; 31.938 ; 31.938 ; 31.938 ;
; FC[2]        ; DATA[15]      ; 32.836 ; 32.973 ; 32.973 ; 32.836 ;
; FC[2]        ; DTACKn        ; 24.000 ; 24.000 ; 24.000 ; 24.000 ;
; FC[2]        ; JOY_RHn       ;        ; 17.404 ; 17.404 ;        ;
; FC[2]        ; JOY_RLn       ;        ; 17.645 ; 17.645 ;        ;
; FC[2]        ; JOY_WEn       ; 17.287 ;        ;        ; 17.287 ;
; FC[2]        ; JOY_WL        ; 17.559 ;        ;        ; 17.559 ;
; FC[2]        ; RAM_DATA[0]   ; 33.747 ; 31.483 ; 31.483 ; 33.747 ;
; FC[2]        ; RAM_DATA[1]   ; 35.023 ; 32.497 ; 32.497 ; 35.023 ;
; FC[2]        ; RAM_DATA[2]   ; 33.781 ; 30.791 ; 30.791 ; 33.781 ;
; FC[2]        ; RAM_DATA[3]   ; 33.628 ; 31.806 ; 31.806 ; 33.628 ;
; FC[2]        ; RAM_DATA[4]   ; 34.416 ; 32.103 ; 32.103 ; 34.416 ;
; FC[2]        ; RAM_DATA[5]   ; 35.207 ; 32.979 ; 32.979 ; 35.207 ;
; FC[2]        ; RAM_DATA[6]   ; 34.578 ; 31.707 ; 31.707 ; 34.578 ;
; FC[2]        ; RAM_DATA[7]   ; 34.670 ; 31.499 ; 31.499 ; 34.670 ;
; FC[2]        ; RAM_DATA[8]   ; 34.339 ; 34.339 ; 34.339 ; 34.339 ;
; FC[2]        ; RAM_DATA[9]   ; 35.032 ; 35.032 ; 35.032 ; 35.032 ;
; FC[2]        ; RAM_DATA[10]  ; 33.559 ; 33.559 ; 33.559 ; 33.559 ;
; FC[2]        ; RAM_DATA[11]  ; 33.562 ; 33.464 ; 33.464 ; 33.562 ;
; FC[2]        ; RAM_DATA[12]  ; 34.619 ; 34.619 ; 34.619 ; 34.619 ;
; FC[2]        ; RAM_DATA[13]  ; 34.475 ; 34.597 ; 34.597 ; 34.475 ;
; FC[2]        ; RAM_DATA[14]  ; 34.065 ; 34.065 ; 34.065 ; 34.065 ;
; FC[2]        ; RAM_DATA[15]  ; 34.350 ; 34.487 ; 34.487 ; 34.350 ;
; HDINTn       ; DATA[5]       ; 24.851 ;        ;        ; 24.851 ;
; HDINTn       ; RAM_DATA[5]   ; 26.355 ;        ;        ; 26.355 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 24.592 ; 24.592 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 26.096 ; 26.096 ;        ;
; IDE_IORDY    ; DTACKn        ; 17.181 ; 17.181 ; 17.181 ; 17.181 ;
; LDSn         ; ACSI_RDn      ; 22.710 ; 22.710 ; 22.710 ; 22.710 ;
; LDSn         ; ACSI_WRn      ; 22.719 ; 22.719 ; 22.719 ; 22.719 ;
; LDSn         ; BUTTONn       ; 20.616 ;        ;        ; 20.616 ;
; LDSn         ; CA1_OUT       ; 21.590 ;        ;        ; 21.590 ;
; LDSn         ; CD[0]         ; 28.155 ; 28.155 ; 28.155 ; 28.155 ;
; LDSn         ; CD[1]         ; 28.571 ; 28.571 ; 28.571 ; 28.571 ;
; LDSn         ; CD[2]         ; 27.660 ; 27.660 ; 27.660 ; 27.660 ;
; LDSn         ; CD[3]         ; 31.598 ; 31.598 ; 31.598 ; 31.598 ;
; LDSn         ; CD[4]         ; 31.602 ; 31.602 ; 31.602 ; 31.602 ;
; LDSn         ; CD[5]         ; 32.242 ; 32.242 ; 32.242 ; 32.242 ;
; LDSn         ; CD[6]         ; 32.188 ; 32.188 ; 32.188 ; 32.188 ;
; LDSn         ; CD[7]         ; 27.944 ; 27.944 ; 27.944 ; 27.944 ;
; LDSn         ; DATA[0]       ; 30.598 ; 29.758 ; 29.758 ; 30.598 ;
; LDSn         ; DATA[1]       ; 33.460 ; 32.094 ; 32.094 ; 33.460 ;
; LDSn         ; DATA[2]       ; 30.929 ; 29.812 ; 29.812 ; 30.929 ;
; LDSn         ; DATA[3]       ; 31.018 ; 30.511 ; 30.511 ; 31.018 ;
; LDSn         ; DATA[4]       ; 29.889 ; 29.461 ; 29.461 ; 29.889 ;
; LDSn         ; DATA[5]       ; 32.606 ; 31.839 ; 31.839 ; 32.606 ;
; LDSn         ; DATA[6]       ; 31.812 ; 31.168 ; 31.168 ; 31.812 ;
; LDSn         ; DATA[7]       ; 33.689 ; 33.073 ; 33.073 ; 33.689 ;
; LDSn         ; DATA[8]       ; 33.740 ; 31.914 ; 31.914 ; 33.740 ;
; LDSn         ; DATA[9]       ; 33.770 ; 32.139 ; 32.139 ; 33.770 ;
; LDSn         ; DATA[10]      ; 31.042 ; 29.694 ; 29.694 ; 31.042 ;
; LDSn         ; DATA[11]      ; 34.308 ; 32.348 ; 32.348 ; 34.308 ;
; LDSn         ; DATA[12]      ; 31.358 ; 31.145 ; 31.145 ; 31.358 ;
; LDSn         ; DATA[13]      ; 31.986 ; 30.531 ; 30.531 ; 31.986 ;
; LDSn         ; DATA[14]      ; 31.557 ; 29.662 ; 29.662 ; 31.557 ;
; LDSn         ; DATA[15]      ; 32.419 ; 30.659 ; 30.659 ; 32.419 ;
; LDSn         ; DTACKn        ; 24.463 ; 24.463 ; 24.463 ; 24.463 ;
; LDSn         ; IDE_IORDn     ; 15.551 ;        ;        ; 15.551 ;
; LDSn         ; IDE_IOWRn     ; 15.211 ;        ;        ; 15.211 ;
; LDSn         ; JOY_RLn       ; 13.301 ;        ;        ; 13.301 ;
; LDSn         ; JOY_WEn       ;        ; 12.943 ; 12.943 ;        ;
; LDSn         ; JOY_WL        ;        ; 12.687 ; 12.687 ;        ;
; LDSn         ; RAM_CAS0n     ; 17.071 ;        ;        ; 17.071 ;
; LDSn         ; RAM_DATA[0]   ; 31.882 ; 31.042 ; 31.042 ; 31.882 ;
; LDSn         ; RAM_DATA[1]   ; 34.387 ; 33.021 ; 33.021 ; 34.387 ;
; LDSn         ; RAM_DATA[2]   ; 31.679 ; 30.562 ; 30.562 ; 31.679 ;
; LDSn         ; RAM_DATA[3]   ; 33.317 ; 32.810 ; 32.810 ; 33.317 ;
; LDSn         ; RAM_DATA[4]   ; 32.138 ; 31.710 ; 31.710 ; 32.138 ;
; LDSn         ; RAM_DATA[5]   ; 34.110 ; 33.343 ; 33.343 ; 34.110 ;
; LDSn         ; RAM_DATA[6]   ; 32.548 ; 31.904 ; 31.904 ; 32.548 ;
; LDSn         ; RAM_DATA[7]   ; 33.858 ; 33.242 ; 33.242 ; 33.858 ;
; LDSn         ; RAM_DATA[8]   ; 33.701 ; 31.875 ; 31.875 ; 33.701 ;
; LDSn         ; RAM_DATA[9]   ; 33.781 ; 32.150 ; 32.150 ; 33.781 ;
; LDSn         ; RAM_DATA[10]  ; 32.252 ; 30.904 ; 30.904 ; 32.252 ;
; LDSn         ; RAM_DATA[11]  ; 32.990 ; 31.030 ; 31.030 ; 32.990 ;
; LDSn         ; RAM_DATA[12]  ; 31.024 ; 30.811 ; 30.811 ; 31.024 ;
; LDSn         ; RAM_DATA[13]  ; 33.772 ; 32.317 ; 32.317 ; 33.772 ;
; LDSn         ; RAM_DATA[14]  ; 33.684 ; 31.789 ; 31.789 ; 33.684 ;
; LDSn         ; RAM_DATA[15]  ; 33.933 ; 32.173 ; 32.173 ; 33.933 ;
; LDSn         ; RAM_DQM0L     ; 14.828 ;        ;        ; 14.828 ;
; LPT_BSY      ; DATA[0]       ; 23.867 ;        ;        ; 23.867 ;
; LPT_BSY      ; RAM_DATA[0]   ; 25.151 ;        ;        ; 25.151 ;
; LPT_D[0]     ; DATA[8]       ; 22.459 ;        ;        ; 22.459 ;
; LPT_D[0]     ; RAM_DATA[8]   ; 22.420 ;        ;        ; 22.420 ;
; LPT_D[1]     ; DATA[9]       ; 23.036 ;        ;        ; 23.036 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 23.047 ;        ;        ; 23.047 ;
; LPT_D[2]     ; DATA[10]      ; 20.336 ;        ;        ; 20.336 ;
; LPT_D[2]     ; RAM_DATA[10]  ; 21.546 ;        ;        ; 21.546 ;
; LPT_D[3]     ; DATA[11]      ; 22.109 ;        ;        ; 22.109 ;
; LPT_D[3]     ; RAM_DATA[11]  ; 20.791 ;        ;        ; 20.791 ;
; LPT_D[4]     ; DATA[12]      ; 21.813 ;        ;        ; 21.813 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 21.479 ;        ;        ; 21.479 ;
; LPT_D[5]     ; DATA[13]      ; 21.231 ;        ;        ; 21.231 ;
; LPT_D[5]     ; RAM_DATA[13]  ; 23.017 ;        ;        ; 23.017 ;
; LPT_D[6]     ; DATA[14]      ; 19.723 ;        ;        ; 19.723 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 21.850 ;        ;        ; 21.850 ;
; LPT_D[7]     ; DATA[15]      ; 21.785 ;        ;        ; 21.785 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 23.299 ;        ;        ; 23.299 ;
; MIDI_IN      ; MIDI_TLR      ; 8.873  ;        ;        ; 8.873  ;
; RAM_DATA[0]  ; DATA[0]       ; 21.678 ;        ;        ; 21.678 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 22.962 ;        ;        ; 22.962 ;
; RAM_DATA[1]  ; DATA[1]       ; 22.554 ;        ;        ; 22.554 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 23.481 ;        ;        ; 23.481 ;
; RAM_DATA[2]  ; DATA[2]       ; 21.735 ;        ;        ; 21.735 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 22.485 ;        ;        ; 22.485 ;
; RAM_DATA[3]  ; DATA[3]       ; 21.236 ;        ;        ; 21.236 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 23.535 ;        ;        ; 23.535 ;
; RAM_DATA[4]  ; DATA[4]       ; 20.921 ;        ;        ; 20.921 ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 23.170 ;        ;        ; 23.170 ;
; RAM_DATA[5]  ; DATA[5]       ; 23.892 ;        ;        ; 23.892 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 25.396 ;        ;        ; 25.396 ;
; RAM_DATA[6]  ; DATA[6]       ; 25.412 ;        ;        ; 25.412 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 26.148 ;        ;        ; 26.148 ;
; RAM_DATA[7]  ; DATA[7]       ; 24.313 ;        ;        ; 24.313 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 24.482 ;        ;        ; 24.482 ;
; RAM_DATA[8]  ; DATA[8]       ; 23.496 ;        ;        ; 23.496 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 23.457 ;        ;        ; 23.457 ;
; RAM_DATA[9]  ; DATA[9]       ; 25.338 ;        ;        ; 25.338 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 25.349 ;        ;        ; 25.349 ;
; RAM_DATA[10] ; DATA[10]      ; 21.388 ;        ;        ; 21.388 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 22.598 ;        ;        ; 22.598 ;
; RAM_DATA[11] ; DATA[11]      ; 25.045 ;        ;        ; 25.045 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 23.727 ;        ;        ; 23.727 ;
; RAM_DATA[12] ; DATA[12]      ; 22.100 ;        ;        ; 22.100 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 21.766 ;        ;        ; 21.766 ;
; RAM_DATA[13] ; DATA[13]      ; 21.656 ;        ;        ; 21.656 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 23.442 ;        ;        ; 23.442 ;
; RAM_DATA[14] ; DATA[14]      ; 21.682 ;        ;        ; 21.682 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 23.809 ;        ;        ; 23.809 ;
; RAM_DATA[15] ; DATA[15]      ; 23.279 ;        ;        ; 23.279 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 24.793 ;        ;        ; 24.793 ;
; RWn          ; ACSI_RDn      ; 20.173 ; 20.173 ; 20.173 ; 20.173 ;
; RWn          ; ACSI_WRn      ; 20.182 ; 20.182 ; 20.182 ; 20.182 ;
; RWn          ; BUTTONn       ;        ; 16.692 ; 16.692 ;        ;
; RWn          ; CA1_OUT       ;        ; 19.053 ; 19.053 ;        ;
; RWn          ; CD[0]         ; 25.618 ; 25.618 ; 25.618 ; 25.618 ;
; RWn          ; CD[1]         ; 26.034 ; 26.034 ; 26.034 ; 26.034 ;
; RWn          ; CD[2]         ; 25.123 ; 25.123 ; 25.123 ; 25.123 ;
; RWn          ; CD[3]         ; 29.061 ; 29.061 ; 29.061 ; 29.061 ;
; RWn          ; CD[4]         ; 29.065 ; 29.065 ; 29.065 ; 29.065 ;
; RWn          ; CD[5]         ; 29.705 ; 29.705 ; 29.705 ; 29.705 ;
; RWn          ; CD[6]         ; 29.651 ; 29.651 ; 29.651 ; 29.651 ;
; RWn          ; CD[7]         ; 25.407 ; 25.407 ; 25.407 ; 25.407 ;
; RWn          ; DATA[0]       ; 30.304 ; 32.560 ; 32.560 ; 30.304 ;
; RWn          ; DATA[1]       ; 31.951 ; 34.193 ; 34.193 ; 31.951 ;
; RWn          ; DATA[2]       ; 30.035 ; 33.128 ; 33.128 ; 30.035 ;
; RWn          ; DATA[3]       ; 30.368 ; 31.426 ; 31.426 ; 30.368 ;
; RWn          ; DATA[4]       ; 29.947 ; 32.264 ; 32.264 ; 29.947 ;
; RWn          ; DATA[5]       ; 31.696 ; 33.800 ; 33.800 ; 31.696 ;
; RWn          ; DATA[6]       ; 31.135 ; 33.939 ; 33.939 ; 31.135 ;
; RWn          ; DATA[7]       ; 32.930 ; 34.598 ; 34.598 ; 32.930 ;
; RWn          ; DATA[8]       ; 34.475 ; 34.475 ; 34.475 ; 34.475 ;
; RWn          ; DATA[9]       ; 35.118 ; 35.118 ; 35.118 ; 35.118 ;
; RWn          ; DATA[10]      ; 32.446 ; 32.446 ; 32.446 ; 32.446 ;
; RWn          ; DATA[11]      ; 34.879 ; 34.977 ; 34.977 ; 34.879 ;
; RWn          ; DATA[12]      ; 35.050 ; 35.050 ; 35.050 ; 35.050 ;
; RWn          ; DATA[13]      ; 32.908 ; 32.786 ; 32.786 ; 32.908 ;
; RWn          ; DATA[14]      ; 32.035 ; 32.035 ; 32.035 ; 32.035 ;
; RWn          ; DATA[15]      ; 33.070 ; 32.933 ; 32.933 ; 33.070 ;
; RWn          ; DTACKn        ; 24.097 ; 24.097 ; 24.097 ; 24.097 ;
; RWn          ; FLASH_CEn     ;        ; 20.033 ; 20.033 ;        ;
; RWn          ; FLASH_OEn     ;        ; 19.239 ; 19.239 ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 14.460 ; 14.460 ;        ;
; RWn          ; IDE_D_EN_OUTn ; 15.046 ;        ;        ; 15.046 ;
; RWn          ; IDE_IORDn     ;        ; 14.732 ; 14.732 ;        ;
; RWn          ; IDE_IOWRn     ; 14.352 ;        ;        ; 14.352 ;
; RWn          ; JOY_RHn       ;        ; 17.497 ; 17.497 ;        ;
; RWn          ; JOY_RLn       ;        ; 17.738 ; 17.738 ;        ;
; RWn          ; JOY_WEn       ; 17.380 ;        ;        ; 17.380 ;
; RWn          ; JOY_WL        ; 17.652 ; 12.211 ; 12.211 ; 17.652 ;
; RWn          ; RAM_DATA[0]   ; 31.588 ; 33.844 ; 33.844 ; 31.588 ;
; RWn          ; RAM_DATA[1]   ; 32.878 ; 35.120 ; 35.120 ; 32.878 ;
; RWn          ; RAM_DATA[2]   ; 30.785 ; 33.878 ; 33.878 ; 30.785 ;
; RWn          ; RAM_DATA[3]   ; 32.667 ; 33.725 ; 33.725 ; 32.667 ;
; RWn          ; RAM_DATA[4]   ; 32.196 ; 34.513 ; 34.513 ; 32.196 ;
; RWn          ; RAM_DATA[5]   ; 33.200 ; 35.304 ; 35.304 ; 33.200 ;
; RWn          ; RAM_DATA[6]   ; 31.871 ; 34.675 ; 34.675 ; 31.871 ;
; RWn          ; RAM_DATA[7]   ; 33.099 ; 34.767 ; 34.767 ; 33.099 ;
; RWn          ; RAM_DATA[8]   ; 34.436 ; 34.436 ; 34.436 ; 34.436 ;
; RWn          ; RAM_DATA[9]   ; 35.129 ; 35.129 ; 35.129 ; 35.129 ;
; RWn          ; RAM_DATA[10]  ; 33.656 ; 33.656 ; 33.656 ; 33.656 ;
; RWn          ; RAM_DATA[11]  ; 33.561 ; 33.659 ; 33.659 ; 33.561 ;
; RWn          ; RAM_DATA[12]  ; 34.716 ; 34.716 ; 34.716 ; 34.716 ;
; RWn          ; RAM_DATA[13]  ; 34.694 ; 34.572 ; 34.572 ; 34.694 ;
; RWn          ; RAM_DATA[14]  ; 34.162 ; 34.162 ; 34.162 ; 34.162 ;
; RWn          ; RAM_DATA[15]  ; 34.584 ; 34.447 ; 34.447 ; 34.584 ;
; RWn          ; RAM_WEn       ; 16.091 ;        ;        ; 16.091 ;
; RWn          ; ROM0n         ;        ; 15.986 ; 15.986 ;        ;
; RWn          ; ROM1n         ;        ; 15.714 ; 15.714 ;        ;
; RWn          ; ROM2n         ;        ; 17.673 ; 17.673 ;        ;
; RWn          ; ROM3n         ;        ; 15.231 ; 15.231 ;        ;
; RWn          ; ROM4n         ;        ; 15.386 ; 15.386 ;        ;
; RWn          ; ROM5n         ;        ; 17.664 ; 17.664 ;        ;
; RWn          ; ROM6n         ;        ; 17.199 ; 17.199 ;        ;
; SCSI_ACKn    ; CD[0]         ; 14.204 ; 14.204 ; 14.204 ; 14.204 ;
; SCSI_ATNn    ; CD[1]         ; 16.332 ; 16.332 ; 16.332 ; 16.332 ;
; SCSI_BSYn    ; CD[6]         ; 17.707 ; 17.707 ; 17.707 ; 17.707 ;
; SCSI_D[0]    ; CD[0]         ; 14.770 ; 14.770 ; 14.770 ; 14.770 ;
; SCSI_D[1]    ; CD[1]         ; 15.008 ; 15.008 ; 15.008 ; 15.008 ;
; SCSI_D[2]    ; CD[2]         ;        ; 13.276 ; 13.276 ;        ;
; SCSI_D[3]    ; CD[3]         ; 15.444 ; 15.444 ; 15.444 ; 15.444 ;
; SCSI_D[4]    ; CD[4]         ; 17.943 ; 17.943 ; 17.943 ; 17.943 ;
; SCSI_D[5]    ; CD[5]         ; 16.747 ; 16.747 ; 16.747 ; 16.747 ;
; SCSI_D[6]    ; CD[6]         ; 17.645 ; 17.645 ; 17.645 ; 17.645 ;
; SCSI_D[7]    ; CD[7]         ; 16.361 ; 16.361 ; 16.361 ; 16.361 ;
; SCSI_DCn     ; CD[3]         ; 19.285 ; 19.285 ; 19.285 ; 19.285 ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 18.454 ; 18.454 ; 18.454 ; 18.454 ;
; SCSI_DCn     ; SCSI_D[0]     ; 17.103 ; 17.103 ; 17.103 ; 17.103 ;
; SCSI_DCn     ; SCSI_D[1]     ; 17.103 ; 17.103 ; 17.103 ; 17.103 ;
; SCSI_DCn     ; SCSI_D[2]     ; 17.096 ; 17.096 ; 17.096 ; 17.096 ;
; SCSI_DCn     ; SCSI_D[3]     ; 17.096 ; 17.096 ; 17.096 ; 17.096 ;
; SCSI_DCn     ; SCSI_D[4]     ; 17.430 ; 17.430 ; 17.430 ; 17.430 ;
; SCSI_DCn     ; SCSI_D[5]     ; 17.430 ; 17.430 ; 17.430 ; 17.430 ;
; SCSI_DCn     ; SCSI_D[6]     ; 17.705 ; 17.705 ; 17.705 ; 17.705 ;
; SCSI_DCn     ; SCSI_D[7]     ; 17.705 ; 17.705 ; 17.705 ; 17.705 ;
; SCSI_DCn     ; SCSI_DP       ; 17.113 ; 17.113 ; 17.113 ; 17.113 ;
; SCSI_DP      ; CD[0]         ; 14.407 ; 14.407 ; 14.407 ; 14.407 ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 12.296 ; 12.296 ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 12.292 ;        ;        ; 12.292 ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 12.274 ; 12.274 ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 12.643 ;        ;        ; 12.643 ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 13.212 ; 13.212 ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 13.208 ;        ;        ; 13.208 ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 13.616 ; 13.616 ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 12.942 ;        ;        ; 12.942 ;
; SCSI_IDn[1]  ; SCSI_DP       ; 15.073 ; 15.073 ; 15.073 ; 15.073 ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 11.936 ; 11.936 ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 11.936 ; 11.936 ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 11.905 ;        ;        ; 11.905 ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 12.277 ;        ;        ; 12.277 ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 12.863 ; 12.863 ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 12.856 ; 12.856 ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 13.266 ;        ;        ; 13.266 ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 12.578 ;        ;        ; 12.578 ;
; SCSI_IDn[2]  ; SCSI_DP       ; 14.707 ; 14.707 ; 14.707 ; 14.707 ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 12.483 ; 12.483 ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 12.477 ; 12.477 ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 12.495 ; 12.495 ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 12.865 ; 12.865 ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 13.339 ;        ;        ; 13.339 ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 13.332 ;        ;        ; 13.332 ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 13.775 ;        ;        ; 13.775 ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 13.101 ;        ;        ; 13.101 ;
; SCSI_IDn[3]  ; SCSI_DP       ; 15.295 ; 15.295 ; 15.295 ; 15.295 ;
; SCSI_IOn     ; CD[2]         ;        ; 15.779 ; 15.779 ;        ;
; SCSI_IOn     ; CD[3]         ; 19.203 ; 19.203 ; 19.203 ; 19.203 ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 18.372 ; 18.372 ; 18.372 ; 18.372 ;
; SCSI_IOn     ; SCSI_D[0]     ; 17.021 ; 17.021 ; 17.021 ; 17.021 ;
; SCSI_IOn     ; SCSI_D[1]     ; 17.021 ; 17.021 ; 17.021 ; 17.021 ;
; SCSI_IOn     ; SCSI_D[2]     ; 17.014 ; 17.014 ; 17.014 ; 17.014 ;
; SCSI_IOn     ; SCSI_D[3]     ; 17.014 ; 17.014 ; 17.014 ; 17.014 ;
; SCSI_IOn     ; SCSI_D[4]     ; 17.348 ; 17.348 ; 17.348 ; 17.348 ;
; SCSI_IOn     ; SCSI_D[5]     ; 17.348 ; 17.348 ; 17.348 ; 17.348 ;
; SCSI_IOn     ; SCSI_D[6]     ; 17.623 ; 17.623 ; 17.623 ; 17.623 ;
; SCSI_IOn     ; SCSI_D[7]     ; 17.623 ; 17.623 ; 17.623 ; 17.623 ;
; SCSI_IOn     ; SCSI_DP       ; 17.031 ; 17.031 ; 17.031 ; 17.031 ;
; SCSI_IOn     ; SCSI_RDn      ; 14.482 ;        ;        ; 14.482 ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 14.079 ; 14.079 ;        ;
; SCSI_MSGn    ; CD[3]         ; 18.228 ; 18.228 ; 18.228 ; 18.228 ;
; SCSI_MSGn    ; CD[4]         ; 17.647 ; 17.647 ; 17.647 ; 17.647 ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 17.397 ; 17.397 ; 17.397 ; 17.397 ;
; SCSI_MSGn    ; SCSI_D[0]     ; 16.046 ; 16.046 ; 16.046 ; 16.046 ;
; SCSI_MSGn    ; SCSI_D[1]     ; 16.046 ; 16.046 ; 16.046 ; 16.046 ;
; SCSI_MSGn    ; SCSI_D[2]     ; 16.039 ; 16.039 ; 16.039 ; 16.039 ;
; SCSI_MSGn    ; SCSI_D[3]     ; 16.039 ; 16.039 ; 16.039 ; 16.039 ;
; SCSI_MSGn    ; SCSI_D[4]     ; 16.373 ; 16.373 ; 16.373 ; 16.373 ;
; SCSI_MSGn    ; SCSI_D[5]     ; 16.373 ; 16.373 ; 16.373 ; 16.373 ;
; SCSI_MSGn    ; SCSI_D[6]     ; 16.648 ; 16.648 ; 16.648 ; 16.648 ;
; SCSI_MSGn    ; SCSI_D[7]     ; 16.648 ; 16.648 ; 16.648 ; 16.648 ;
; SCSI_MSGn    ; SCSI_DP       ; 16.056 ; 16.056 ; 16.056 ; 16.056 ;
; SCSI_REQn    ; CD[3]         ; 18.599 ; 18.599 ; 18.599 ; 18.599 ;
; SCSI_REQn    ; CD[5]         ; 17.150 ; 17.150 ; 17.150 ; 17.150 ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 17.768 ;        ;        ; 17.768 ;
; SCSI_REQn    ; SCSI_D[0]     ; 16.417 ; 16.417 ; 16.417 ; 16.417 ;
; SCSI_REQn    ; SCSI_D[1]     ; 16.417 ; 16.417 ; 16.417 ; 16.417 ;
; SCSI_REQn    ; SCSI_D[2]     ; 16.410 ; 16.410 ; 16.410 ; 16.410 ;
; SCSI_REQn    ; SCSI_D[3]     ; 16.410 ; 16.410 ; 16.410 ; 16.410 ;
; SCSI_REQn    ; SCSI_D[4]     ; 16.744 ; 16.744 ; 16.744 ; 16.744 ;
; SCSI_REQn    ; SCSI_D[5]     ; 16.744 ; 16.744 ; 16.744 ; 16.744 ;
; SCSI_REQn    ; SCSI_D[6]     ; 17.019 ; 17.019 ; 17.019 ; 17.019 ;
; SCSI_REQn    ; SCSI_D[7]     ; 17.019 ; 17.019 ; 17.019 ; 17.019 ;
; SCSI_REQn    ; SCSI_DP       ; 16.427 ; 16.427 ; 16.427 ; 16.427 ;
; SCSI_RSTn    ; CD[7]         ;        ; 16.793 ; 16.793 ;        ;
; SCSI_SELn    ; CD[1]         ; 15.091 ; 15.091 ; 15.091 ; 15.091 ;
; SD_AVR_ENn   ; RESETn        ;        ; 16.134 ; 16.134 ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 13.868 ; 13.868 ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 15.607 ; 15.607 ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 13.293 ;        ;        ; 13.293 ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 13.484 ;        ;        ; 13.484 ;
; SD_RESETn    ; ACSI_RDn      ; 20.379 ; 20.379 ; 20.379 ; 20.379 ;
; SD_RESETn    ; ACSI_WRn      ; 20.388 ; 20.388 ; 20.388 ; 20.388 ;
; SD_RESETn    ; CA1_OUT       ; 19.259 ;        ;        ; 19.259 ;
; SD_RESETn    ; CD[0]         ; 25.824 ; 25.824 ; 25.824 ; 25.824 ;
; SD_RESETn    ; CD[1]         ; 26.240 ; 26.240 ; 26.240 ; 26.240 ;
; SD_RESETn    ; CD[2]         ; 25.329 ; 25.329 ; 25.329 ; 25.329 ;
; SD_RESETn    ; CD[3]         ; 29.267 ; 29.267 ; 29.267 ; 29.267 ;
; SD_RESETn    ; CD[4]         ; 29.271 ; 29.271 ; 29.271 ; 29.271 ;
; SD_RESETn    ; CD[5]         ; 29.911 ; 29.911 ; 29.911 ; 29.911 ;
; SD_RESETn    ; CD[6]         ; 29.857 ; 29.857 ; 29.857 ; 29.857 ;
; SD_RESETn    ; CD[7]         ; 25.613 ; 25.613 ; 25.613 ; 25.613 ;
; SD_RESETn    ; COM_TxD       ; 21.253 ; 21.253 ; 21.253 ; 21.253 ;
; SD_RESETn    ; DATA[0]       ; 27.921 ; 28.253 ; 28.253 ; 27.921 ;
; SD_RESETn    ; DATA[1]       ; 29.373 ; 29.373 ; 29.373 ; 29.373 ;
; SD_RESETn    ; DATA[2]       ; 28.168 ; 28.168 ; 28.168 ; 28.168 ;
; SD_RESETn    ; DATA[3]       ; 27.521 ; 27.521 ; 27.521 ; 27.521 ;
; SD_RESETn    ; DATA[4]       ; 27.461 ; 27.803 ; 27.803 ; 27.461 ;
; SD_RESETn    ; DATA[5]       ; 29.463 ; 29.463 ; 29.463 ; 29.463 ;
; SD_RESETn    ; DATA[6]       ; 29.200 ; 29.105 ; 29.105 ; 29.200 ;
; SD_RESETn    ; DATA[7]       ; 29.677 ; 29.745 ; 29.745 ; 29.677 ;
; SD_RESETn    ; DATA[8]       ; 24.867 ; 26.442 ; 26.442 ; 24.867 ;
; SD_RESETn    ; DATA[9]       ; 27.506 ; 27.682 ; 27.682 ; 27.506 ;
; SD_RESETn    ; DATA[10]      ; 21.875 ; 24.929 ; 24.929 ; 21.875 ;
; SD_RESETn    ; DATA[11]      ; 27.416 ; 28.132 ; 28.132 ; 27.416 ;
; SD_RESETn    ; DATA[12]      ; 26.478 ; 27.562 ; 27.562 ; 26.478 ;
; SD_RESETn    ; DATA[13]      ; 23.934 ; 26.052 ; 26.052 ; 23.934 ;
; SD_RESETn    ; DATA[14]      ; 22.924 ; 24.723 ; 24.723 ; 22.924 ;
; SD_RESETn    ; DATA[15]      ; 23.762 ; 25.391 ; 25.391 ; 23.762 ;
; SD_RESETn    ; DTACKn        ; 22.132 ; 22.132 ; 22.132 ; 22.132 ;
; SD_RESETn    ; RAM_DATA[0]   ; 29.205 ; 29.537 ; 29.537 ; 29.205 ;
; SD_RESETn    ; RAM_DATA[1]   ; 30.300 ; 30.300 ; 30.300 ; 30.300 ;
; SD_RESETn    ; RAM_DATA[2]   ; 28.918 ; 28.918 ; 28.918 ; 28.918 ;
; SD_RESETn    ; RAM_DATA[3]   ; 29.820 ; 29.820 ; 29.820 ; 29.820 ;
; SD_RESETn    ; RAM_DATA[4]   ; 29.710 ; 30.052 ; 30.052 ; 29.710 ;
; SD_RESETn    ; RAM_DATA[5]   ; 30.967 ; 30.967 ; 30.967 ; 30.967 ;
; SD_RESETn    ; RAM_DATA[6]   ; 29.936 ; 29.841 ; 29.841 ; 29.936 ;
; SD_RESETn    ; RAM_DATA[7]   ; 29.846 ; 29.914 ; 29.914 ; 29.846 ;
; SD_RESETn    ; RAM_DATA[8]   ; 24.828 ; 26.403 ; 26.403 ; 24.828 ;
; SD_RESETn    ; RAM_DATA[9]   ; 27.517 ; 27.693 ; 27.693 ; 27.517 ;
; SD_RESETn    ; RAM_DATA[10]  ; 23.085 ; 26.139 ; 26.139 ; 23.085 ;
; SD_RESETn    ; RAM_DATA[11]  ; 26.098 ; 26.814 ; 26.814 ; 26.098 ;
; SD_RESETn    ; RAM_DATA[12]  ; 26.144 ; 27.228 ; 27.228 ; 26.144 ;
; SD_RESETn    ; RAM_DATA[13]  ; 25.720 ; 27.838 ; 27.838 ; 25.720 ;
; SD_RESETn    ; RAM_DATA[14]  ; 25.051 ; 26.850 ; 26.850 ; 25.051 ;
; SD_RESETn    ; RAM_DATA[15]  ; 25.276 ; 26.905 ; 26.905 ; 25.276 ;
; UDSn         ; ACSI_RDn      ; 20.215 ; 20.215 ; 20.215 ; 20.215 ;
; UDSn         ; ACSI_WRn      ; 20.224 ; 20.224 ; 20.224 ; 20.224 ;
; UDSn         ; CA1_OUT       ; 19.095 ;        ;        ; 19.095 ;
; UDSn         ; CD[0]         ; 25.660 ; 25.660 ; 25.660 ; 25.660 ;
; UDSn         ; CD[1]         ; 26.076 ; 26.076 ; 26.076 ; 26.076 ;
; UDSn         ; CD[2]         ; 25.165 ; 25.165 ; 25.165 ; 25.165 ;
; UDSn         ; CD[3]         ; 29.103 ; 29.103 ; 29.103 ; 29.103 ;
; UDSn         ; CD[4]         ; 29.107 ; 29.107 ; 29.107 ; 29.107 ;
; UDSn         ; CD[5]         ; 29.747 ; 29.747 ; 29.747 ; 29.747 ;
; UDSn         ; CD[6]         ; 29.693 ; 29.693 ; 29.693 ; 29.693 ;
; UDSn         ; CD[7]         ; 25.449 ; 25.449 ; 25.449 ; 25.449 ;
; UDSn         ; DATA[0]       ; 29.281 ; 30.333 ; 30.333 ; 29.281 ;
; UDSn         ; DATA[1]       ; 32.143 ; 31.966 ; 31.966 ; 32.143 ;
; UDSn         ; DATA[2]       ; 29.612 ; 30.901 ; 30.901 ; 29.612 ;
; UDSn         ; DATA[3]       ; 29.701 ; 29.199 ; 29.199 ; 29.701 ;
; UDSn         ; DATA[4]       ; 28.572 ; 30.037 ; 30.037 ; 28.572 ;
; UDSn         ; DATA[5]       ; 31.289 ; 31.573 ; 31.573 ; 31.289 ;
; UDSn         ; DATA[6]       ; 30.495 ; 31.712 ; 31.712 ; 30.495 ;
; UDSn         ; DATA[7]       ; 32.372 ; 32.371 ; 32.371 ; 32.372 ;
; UDSn         ; DATA[8]       ; 32.423 ; 32.248 ; 32.248 ; 32.423 ;
; UDSn         ; DATA[9]       ; 32.891 ; 32.891 ; 32.891 ; 32.891 ;
; UDSn         ; DATA[10]      ; 30.219 ; 30.219 ; 30.219 ; 30.219 ;
; UDSn         ; DATA[11]      ; 32.991 ; 32.750 ; 32.750 ; 32.991 ;
; UDSn         ; DATA[12]      ; 32.823 ; 32.823 ; 32.823 ; 32.823 ;
; UDSn         ; DATA[13]      ; 30.681 ; 30.559 ; 30.559 ; 30.681 ;
; UDSn         ; DATA[14]      ; 30.240 ; 29.808 ; 29.808 ; 30.240 ;
; UDSn         ; DATA[15]      ; 31.102 ; 30.706 ; 30.706 ; 31.102 ;
; UDSn         ; DTACKn        ; 21.968 ; 21.968 ; 21.968 ; 21.968 ;
; UDSn         ; JOY_RHn       ; 14.783 ;        ;        ; 14.783 ;
; UDSn         ; RAM_CAS0n     ; 16.464 ;        ;        ; 16.464 ;
; UDSn         ; RAM_DATA[0]   ; 30.565 ; 31.617 ; 31.617 ; 30.565 ;
; UDSn         ; RAM_DATA[1]   ; 33.070 ; 32.893 ; 32.893 ; 33.070 ;
; UDSn         ; RAM_DATA[2]   ; 30.362 ; 31.651 ; 31.651 ; 30.362 ;
; UDSn         ; RAM_DATA[3]   ; 32.000 ; 31.498 ; 31.498 ; 32.000 ;
; UDSn         ; RAM_DATA[4]   ; 30.821 ; 32.286 ; 32.286 ; 30.821 ;
; UDSn         ; RAM_DATA[5]   ; 32.793 ; 33.077 ; 33.077 ; 32.793 ;
; UDSn         ; RAM_DATA[6]   ; 31.231 ; 32.448 ; 32.448 ; 31.231 ;
; UDSn         ; RAM_DATA[7]   ; 32.541 ; 32.540 ; 32.540 ; 32.541 ;
; UDSn         ; RAM_DATA[8]   ; 32.384 ; 32.209 ; 32.209 ; 32.384 ;
; UDSn         ; RAM_DATA[9]   ; 32.902 ; 32.902 ; 32.902 ; 32.902 ;
; UDSn         ; RAM_DATA[10]  ; 31.429 ; 31.429 ; 31.429 ; 31.429 ;
; UDSn         ; RAM_DATA[11]  ; 31.673 ; 31.432 ; 31.432 ; 31.673 ;
; UDSn         ; RAM_DATA[12]  ; 32.489 ; 32.489 ; 32.489 ; 32.489 ;
; UDSn         ; RAM_DATA[13]  ; 32.467 ; 32.345 ; 32.345 ; 32.467 ;
; UDSn         ; RAM_DATA[14]  ; 32.367 ; 31.935 ; 31.935 ; 32.367 ;
; UDSn         ; RAM_DATA[15]  ; 32.616 ; 32.220 ; 32.220 ; 32.616 ;
; UDSn         ; RAM_DQM0H     ; 14.860 ;        ;        ; 14.860 ;
+--------------+---------------+--------+--------+--------+--------+


+------------------------------------------------------------------+
; Minimum Progagation Delay                                        ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 9.546  ; 9.546  ; 9.546  ; 9.546  ;
; ASn          ; ACSI_WRn      ; 9.550  ; 9.550  ; 9.550  ; 9.550  ;
; ASn          ; BUTTONn       ; 9.679  ;        ;        ; 9.679  ;
; ASn          ; CA1_OUT       ; 9.234  ;        ;        ; 9.234  ;
; ASn          ; CD[0]         ; 10.086 ; 10.043 ; 10.043 ; 10.086 ;
; ASn          ; CD[1]         ; 10.008 ; 9.965  ; 9.965  ; 10.008 ;
; ASn          ; CD[2]         ; 9.261  ; 9.261  ; 9.261  ; 9.261  ;
; ASn          ; CD[3]         ; 10.177 ; 10.036 ; 10.036 ; 10.177 ;
; ASn          ; CD[4]         ; 9.530  ; 9.530  ; 9.530  ; 9.530  ;
; ASn          ; CD[5]         ; 9.522  ; 9.522  ; 9.522  ; 9.522  ;
; ASn          ; CD[6]         ; 9.672  ; 9.672  ; 9.672  ; 9.672  ;
; ASn          ; CD[7]         ; 9.366  ; 9.366  ; 9.366  ; 9.366  ;
; ASn          ; DATA[0]       ; 9.125  ; 9.125  ; 9.125  ; 9.125  ;
; ASn          ; DATA[1]       ; 9.125  ; 9.125  ; 9.125  ; 9.125  ;
; ASn          ; DATA[2]       ; 8.977  ; 8.977  ; 8.977  ; 8.977  ;
; ASn          ; DATA[3]       ; 8.977  ; 8.977  ; 8.977  ; 8.977  ;
; ASn          ; DATA[4]       ; 8.998  ; 8.998  ; 8.998  ; 8.998  ;
; ASn          ; DATA[5]       ; 8.998  ; 8.998  ; 8.998  ; 8.998  ;
; ASn          ; DATA[6]       ; 8.836  ; 8.836  ; 8.836  ; 8.836  ;
; ASn          ; DATA[7]       ; 8.826  ; 8.826  ; 8.826  ; 8.826  ;
; ASn          ; DATA[8]       ; 8.953  ; 8.953  ; 8.953  ; 8.953  ;
; ASn          ; DATA[9]       ; 8.953  ; 8.953  ; 8.953  ; 8.953  ;
; ASn          ; DATA[10]      ; 9.090  ; 9.090  ; 9.090  ; 9.090  ;
; ASn          ; DATA[11]      ; 9.090  ; 9.090  ; 9.090  ; 9.090  ;
; ASn          ; DATA[12]      ; 9.133  ; 9.133  ; 9.133  ; 9.133  ;
; ASn          ; DATA[13]      ; 9.133  ; 9.133  ; 9.133  ; 9.133  ;
; ASn          ; DATA[14]      ; 9.105  ; 9.105  ; 9.105  ; 9.105  ;
; ASn          ; DATA[15]      ; 9.095  ; 9.095  ; 9.095  ; 9.095  ;
; ASn          ; DTACKn        ; 7.691  ; 7.691  ; 7.691  ; 7.691  ;
; ASn          ; FLASH_CEn     ; 9.382  ;        ;        ; 9.382  ;
; ASn          ; FLASH_OEn     ; 9.078  ;        ;        ; 9.078  ;
; ASn          ; IDE_CS0n      ; 6.810  ;        ;        ; 6.810  ;
; ASn          ; IDE_CS1n      ; 6.389  ;        ;        ; 6.389  ;
; ASn          ; IDE_D_EN_INn  ; 7.079  ;        ;        ; 7.079  ;
; ASn          ; IDE_D_EN_OUTn ; 7.793  ;        ;        ; 7.793  ;
; ASn          ; IDE_IORDn     ; 7.636  ;        ;        ; 7.636  ;
; ASn          ; IDE_IOWRn     ; 7.494  ;        ;        ; 7.494  ;
; ASn          ; JOY_RHn       ; 7.135  ;        ;        ; 7.135  ;
; ASn          ; JOY_RLn       ; 7.274  ;        ;        ; 7.274  ;
; ASn          ; JOY_WEn       ;        ; 7.128  ; 7.128  ;        ;
; ASn          ; JOY_WL        ;        ; 7.155  ; 7.155  ;        ;
; ASn          ; RAM_DATA[0]   ; 10.434 ; 10.579 ; 10.579 ; 10.434 ;
; ASn          ; RAM_DATA[1]   ; 10.823 ; 10.820 ; 10.820 ; 10.823 ;
; ASn          ; RAM_DATA[2]   ; 10.335 ; 10.393 ; 10.393 ; 10.335 ;
; ASn          ; RAM_DATA[3]   ; 10.755 ; 10.805 ; 10.805 ; 10.755 ;
; ASn          ; RAM_DATA[4]   ; 10.726 ; 10.889 ; 10.889 ; 10.726 ;
; ASn          ; RAM_DATA[5]   ; 11.293 ; 11.196 ; 11.196 ; 11.293 ;
; ASn          ; RAM_DATA[6]   ; 10.507 ; 11.004 ; 11.004 ; 10.507 ;
; ASn          ; RAM_DATA[7]   ; 10.955 ; 11.216 ; 11.216 ; 10.955 ;
; ASn          ; RAM_DATA[8]   ; 10.298 ; 10.651 ; 10.651 ; 10.298 ;
; ASn          ; RAM_DATA[9]   ; 10.624 ; 10.868 ; 10.868 ; 10.624 ;
; ASn          ; RAM_DATA[10]  ; 10.191 ; 10.238 ; 10.238 ; 10.191 ;
; ASn          ; RAM_DATA[11]  ; 9.990  ; 10.197 ; 10.197 ; 9.990  ;
; ASn          ; RAM_DATA[12]  ; 10.072 ; 10.072 ; 10.072 ; 10.072 ;
; ASn          ; RAM_DATA[13]  ; 10.788 ; 10.925 ; 10.925 ; 10.788 ;
; ASn          ; RAM_DATA[14]  ; 10.503 ; 10.503 ; 10.503 ; 10.503 ;
; ASn          ; RAM_DATA[15]  ; 10.703 ; 10.641 ; 10.641 ; 10.703 ;
; ASn          ; ROM0n         ; 7.771  ;        ;        ; 7.771  ;
; ASn          ; ROM1n         ; 7.660  ;        ;        ; 7.660  ;
; ASn          ; ROM2n         ; 8.435  ;        ;        ; 8.435  ;
; ASn          ; ROM3n         ; 7.493  ;        ;        ; 7.493  ;
; ASn          ; ROM4n         ; 7.551  ;        ;        ; 7.551  ;
; ASn          ; ROM5n         ; 8.465  ;        ;        ; 8.465  ;
; ASn          ; ROM6n         ; 8.447  ;        ;        ; 8.447  ;
; COM_CTS      ; DATA[2]       ;        ; 10.769 ; 10.769 ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 11.121 ; 11.121 ;        ;
; COM_DCD      ; DATA[1]       ;        ; 11.463 ; 11.463 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 11.833 ; 11.833 ;        ;
; COM_RI       ; DATA[6]       ;        ; 10.598 ; 10.598 ;        ;
; COM_RI       ; RAM_DATA[6]   ;        ; 10.970 ; 10.970 ;        ;
; CONFIG[1]    ; DATA[7]       ; 11.519 ; 11.519 ; 11.519 ; 11.519 ;
; CONFIG[1]    ; HSYNC         ; 6.269  ; 6.269  ; 6.269  ; 6.269  ;
; CONFIG[1]    ; RAM_DATA[7]   ; 11.807 ; 11.807 ; 11.807 ; 11.807 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 7.504  ; 7.375  ; 7.375  ; 7.504  ;
; CONFIG[1]    ; RAM_DATA[13]  ; 7.750  ; 7.847  ; 7.847  ; 7.750  ;
; CONFIG[1]    ; RAM_DATA[14]  ; 7.556  ; 7.488  ; 7.488  ; 7.556  ;
; CONFIG[1]    ; RAM_DATA[15]  ; 7.269  ; 7.384  ; 7.384  ; 7.269  ;
; CONFIG[1]    ; VSYNC         ; 6.125  ; 6.125  ; 6.125  ; 6.125  ;
; CONFIG[2]    ; DATA[7]       ; 11.465 ; 11.465 ; 11.465 ; 11.465 ;
; CONFIG[2]    ; HSYNC         ; 6.183  ; 6.183  ; 6.183  ; 6.183  ;
; CONFIG[2]    ; RAM_DATA[7]   ; 11.753 ; 11.753 ; 11.753 ; 11.753 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 7.176  ; 7.305  ; 7.305  ; 7.176  ;
; CONFIG[2]    ; RAM_DATA[13]  ; 7.648  ; 7.551  ; 7.551  ; 7.648  ;
; CONFIG[2]    ; RAM_DATA[14]  ; 7.289  ; 7.357  ; 7.357  ; 7.289  ;
; CONFIG[2]    ; RAM_DATA[15]  ; 7.185  ; 7.070  ; 7.070  ; 7.185  ;
; CONFIG[2]    ; VSYNC         ; 6.051  ; 6.051  ; 6.051  ; 6.051  ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 8.454  ; 8.454  ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 7.432  ; 7.432  ;        ;
; CONFIG[6]    ; DATA[0]       ; 9.601  ; 9.601  ; 9.601  ; 9.601  ;
; CONFIG[6]    ; DATA[1]       ; 9.976  ; 9.976  ; 9.976  ; 9.976  ;
; CONFIG[6]    ; DATA[2]       ; 9.807  ; 9.807  ; 9.807  ; 9.807  ;
; CONFIG[6]    ; DATA[3]       ; 9.800  ; 9.927  ; 9.927  ; 9.800  ;
; CONFIG[6]    ; DATA[4]       ; 10.186 ; 10.059 ; 10.059 ; 10.186 ;
; CONFIG[6]    ; DATA[5]       ; 10.892 ; 10.765 ; 10.765 ; 10.892 ;
; CONFIG[6]    ; DATA[6]       ; 10.797 ; 10.670 ; 10.670 ; 10.797 ;
; CONFIG[6]    ; DATA[7]       ; 10.820 ; 10.693 ; 10.693 ; 10.820 ;
; CONFIG[6]    ; DATA[8]       ; 10.560 ; 10.687 ; 10.687 ; 10.560 ;
; CONFIG[6]    ; DATA[9]       ; 11.098 ; 11.150 ; 11.150 ; 11.098 ;
; CONFIG[6]    ; DATA[10]      ; 10.126 ; 9.999  ; 9.999  ; 10.126 ;
; CONFIG[6]    ; DATA[11]      ; 11.063 ; 11.009 ; 11.009 ; 11.063 ;
; CONFIG[6]    ; DATA[12]      ; 10.978 ; 10.851 ; 10.851 ; 10.978 ;
; CONFIG[6]    ; DATA[13]      ; 10.158 ; 10.031 ; 10.031 ; 10.158 ;
; CONFIG[6]    ; DATA[14]      ; 9.819  ; 9.858  ; 9.858  ; 9.819  ;
; CONFIG[6]    ; DATA[15]      ; 10.178 ; 10.051 ; 10.051 ; 10.178 ;
; CONFIG[6]    ; DTACKn        ; 8.581  ; 8.581  ; 8.581  ; 8.581  ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 7.744  ; 7.744  ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 7.835  ; 7.835  ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 8.608  ; 8.481  ; 8.481  ; 8.608  ;
; CONFIG[6]    ; FLASH_OEn     ; 8.304  ; 8.177  ; 8.177  ; 8.304  ;
; CONFIG[6]    ; RAM_DATA[0]   ; 10.132 ; 10.132 ; 10.132 ; 10.132 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 10.346 ; 10.346 ; 10.346 ; 10.346 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 10.159 ; 10.159 ; 10.159 ; 10.159 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 10.779 ; 10.906 ; 10.906 ; 10.779 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 11.068 ; 10.941 ; 10.941 ; 11.068 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 11.543 ; 11.416 ; 11.416 ; 11.543 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 11.169 ; 11.042 ; 11.042 ; 11.169 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 11.108 ; 10.981 ; 10.981 ; 11.108 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 10.733 ; 10.860 ; 10.860 ; 10.733 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 11.256 ; 11.308 ; 11.308 ; 11.256 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 10.722 ; 10.595 ; 10.595 ; 10.722 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 10.767 ; 10.713 ; 10.713 ; 10.767 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 10.812 ; 10.685 ; 10.685 ; 10.812 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 10.910 ; 10.783 ; 10.783 ; 10.910 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 10.688 ; 10.727 ; 10.727 ; 10.688 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 10.847 ; 10.720 ; 10.720 ; 10.847 ;
; CONFIG[6]    ; ROM2n         ; 7.661  ; 7.534  ; 7.534  ; 7.661  ;
; CRT_PIN3     ; DATA[7]       ; 9.516  ; 9.516  ; 9.516  ; 9.516  ;
; CRT_PIN3     ; RAM_DATA[7]   ; 9.804  ; 9.804  ; 9.804  ; 9.804  ;
; CRT_PIN3     ; RAM_DATA[12]  ; 5.526  ; 5.397  ; 5.397  ; 5.526  ;
; CRT_PIN3     ; RAM_DATA[13]  ; 5.772  ; 5.869  ; 5.869  ; 5.772  ;
; CRT_PIN3     ; RAM_DATA[14]  ; 5.578  ; 5.510  ; 5.510  ; 5.578  ;
; CRT_PIN3     ; RAM_DATA[15]  ; 5.291  ; 5.406  ; 5.406  ; 5.291  ;
; DATA[0]      ; DATA[0]       ; 7.673  ;        ;        ; 7.673  ;
; DATA[0]      ; RAM_DATA[0]   ; 8.204  ;        ;        ; 8.204  ;
; DATA[1]      ; DATA[1]       ; 8.503  ;        ;        ; 8.503  ;
; DATA[1]      ; RAM_DATA[1]   ; 8.873  ;        ;        ; 8.873  ;
; DATA[2]      ; DATA[2]       ; 8.076  ;        ;        ; 8.076  ;
; DATA[2]      ; RAM_DATA[2]   ; 8.428  ;        ;        ; 8.428  ;
; DATA[3]      ; DATA[3]       ; 7.803  ;        ;        ; 7.803  ;
; DATA[3]      ; RAM_DATA[3]   ; 8.782  ;        ;        ; 8.782  ;
; DATA[4]      ; DATA[4]       ; 7.696  ;        ;        ; 7.696  ;
; DATA[4]      ; RAM_DATA[4]   ; 8.578  ;        ;        ; 8.578  ;
; DATA[5]      ; DATA[5]       ; 8.477  ;        ;        ; 8.477  ;
; DATA[5]      ; RAM_DATA[5]   ; 9.128  ;        ;        ; 9.128  ;
; DATA[6]      ; DATA[6]       ; 8.435  ;        ;        ; 8.435  ;
; DATA[6]      ; RAM_DATA[6]   ; 8.807  ;        ;        ; 8.807  ;
; DATA[7]      ; DATA[7]       ; 8.410  ;        ;        ; 8.410  ;
; DATA[7]      ; RAM_DATA[7]   ; 8.698  ;        ;        ; 8.698  ;
; DATA[8]      ; DATA[8]       ; 8.125  ;        ;        ; 8.125  ;
; DATA[8]      ; RAM_DATA[8]   ; 8.298  ;        ;        ; 8.298  ;
; DATA[9]      ; DATA[9]       ; 8.826  ;        ;        ; 8.826  ;
; DATA[9]      ; RAM_DATA[9]   ; 8.984  ;        ;        ; 8.984  ;
; DATA[10]     ; DATA[10]      ; 7.664  ;        ;        ; 7.664  ;
; DATA[10]     ; RAM_DATA[10]  ; 8.260  ;        ;        ; 8.260  ;
; DATA[11]     ; DATA[11]      ; 8.793  ;        ;        ; 8.793  ;
; DATA[11]     ; RAM_DATA[11]  ; 8.497  ;        ;        ; 8.497  ;
; DATA[12]     ; DATA[12]      ; 8.458  ;        ;        ; 8.458  ;
; DATA[12]     ; RAM_DATA[12]  ; 8.292  ;        ;        ; 8.292  ;
; DATA[13]     ; DATA[13]      ; 7.589  ;        ;        ; 7.589  ;
; DATA[13]     ; RAM_DATA[13]  ; 8.341  ;        ;        ; 8.341  ;
; DATA[14]     ; DATA[14]      ; 7.276  ;        ;        ; 7.276  ;
; DATA[14]     ; RAM_DATA[14]  ; 8.145  ;        ;        ; 8.145  ;
; DATA[15]     ; DATA[15]      ; 7.533  ;        ;        ; 7.533  ;
; DATA[15]     ; RAM_DATA[15]  ; 8.202  ;        ;        ; 8.202  ;
; FC[0]        ; ACSI_RDn      ; 9.216  ; 9.216  ; 9.216  ; 9.216  ;
; FC[0]        ; ACSI_WRn      ; 9.220  ; 9.220  ; 9.220  ; 9.220  ;
; FC[0]        ; BUTTONn       ; 8.018  ; 8.018  ; 8.018  ; 8.018  ;
; FC[0]        ; CA1_OUT       ; 8.904  ; 8.904  ; 8.904  ; 8.904  ;
; FC[0]        ; CD[0]         ; 9.713  ; 9.713  ; 9.713  ; 9.713  ;
; FC[0]        ; CD[1]         ; 9.635  ; 9.635  ; 9.635  ; 9.635  ;
; FC[0]        ; CD[2]         ; 8.931  ; 8.931  ; 8.931  ; 8.931  ;
; FC[0]        ; CD[3]         ; 9.706  ; 9.706  ; 9.706  ; 9.706  ;
; FC[0]        ; CD[4]         ; 9.200  ; 9.200  ; 9.200  ; 9.200  ;
; FC[0]        ; CD[5]         ; 9.192  ; 9.192  ; 9.192  ; 9.192  ;
; FC[0]        ; CD[6]         ; 9.342  ; 9.342  ; 9.342  ; 9.342  ;
; FC[0]        ; CD[7]         ; 9.036  ; 9.036  ; 9.036  ; 9.036  ;
; FC[0]        ; DATA[0]       ; 9.672  ; 9.672  ; 9.672  ; 9.672  ;
; FC[0]        ; DATA[1]       ; 10.267 ; 10.267 ; 10.267 ; 10.267 ;
; FC[0]        ; DATA[2]       ; 9.820  ; 9.820  ; 9.820  ; 9.820  ;
; FC[0]        ; DATA[3]       ; 9.591  ; 9.591  ; 9.591  ; 9.591  ;
; FC[0]        ; DATA[4]       ; 9.659  ; 9.659  ; 9.659  ; 9.659  ;
; FC[0]        ; DATA[5]       ; 10.457 ; 10.457 ; 10.457 ; 10.457 ;
; FC[0]        ; DATA[6]       ; 10.249 ; 10.249 ; 10.249 ; 10.249 ;
; FC[0]        ; DATA[7]       ; 10.640 ; 10.640 ; 10.640 ; 10.640 ;
; FC[0]        ; DATA[8]       ; 10.282 ; 10.282 ; 10.282 ; 10.282 ;
; FC[0]        ; DATA[9]       ; 10.672 ; 10.672 ; 10.672 ; 10.672 ;
; FC[0]        ; DATA[10]      ; 9.565  ; 9.565  ; 9.565  ; 9.565  ;
; FC[0]        ; DATA[11]      ; 10.686 ; 10.686 ; 10.686 ; 10.686 ;
; FC[0]        ; DATA[12]      ; 10.266 ; 10.266 ; 10.266 ; 10.266 ;
; FC[0]        ; DATA[13]      ; 9.851  ; 9.851  ; 9.851  ; 9.851  ;
; FC[0]        ; DATA[14]      ; 9.544  ; 9.544  ; 9.544  ; 9.544  ;
; FC[0]        ; DATA[15]      ; 9.849  ; 9.849  ; 9.849  ; 9.849  ;
; FC[0]        ; DTACKn        ; 8.535  ; 8.535  ; 8.535  ; 8.535  ;
; FC[0]        ; FLASH_CEn     ; 9.231  ; 9.231  ; 9.231  ; 9.231  ;
; FC[0]        ; FLASH_OEn     ; 8.927  ; 8.927  ; 8.927  ; 8.927  ;
; FC[0]        ; JOY_RHn       ; 8.213  ; 8.213  ; 8.213  ; 8.213  ;
; FC[0]        ; JOY_RLn       ; 8.352  ; 8.352  ; 8.352  ; 8.352  ;
; FC[0]        ; JOY_WEn       ; 8.206  ; 8.206  ; 8.206  ; 8.206  ;
; FC[0]        ; JOY_WL        ; 8.233  ; 8.233  ; 8.233  ; 8.233  ;
; FC[0]        ; RAM_DATA[0]   ; 10.203 ; 10.203 ; 10.203 ; 10.203 ;
; FC[0]        ; RAM_DATA[1]   ; 10.637 ; 10.637 ; 10.637 ; 10.637 ;
; FC[0]        ; RAM_DATA[2]   ; 10.172 ; 10.172 ; 10.172 ; 10.172 ;
; FC[0]        ; RAM_DATA[3]   ; 10.570 ; 10.570 ; 10.570 ; 10.570 ;
; FC[0]        ; RAM_DATA[4]   ; 10.541 ; 10.541 ; 10.541 ; 10.541 ;
; FC[0]        ; RAM_DATA[5]   ; 11.108 ; 11.108 ; 11.108 ; 11.108 ;
; FC[0]        ; RAM_DATA[6]   ; 10.621 ; 10.621 ; 10.621 ; 10.621 ;
; FC[0]        ; RAM_DATA[7]   ; 10.928 ; 10.928 ; 10.928 ; 10.928 ;
; FC[0]        ; RAM_DATA[8]   ; 10.455 ; 10.455 ; 10.455 ; 10.455 ;
; FC[0]        ; RAM_DATA[9]   ; 10.830 ; 10.830 ; 10.830 ; 10.830 ;
; FC[0]        ; RAM_DATA[10]  ; 10.161 ; 10.161 ; 10.161 ; 10.161 ;
; FC[0]        ; RAM_DATA[11]  ; 10.390 ; 10.390 ; 10.390 ; 10.390 ;
; FC[0]        ; RAM_DATA[12]  ; 10.100 ; 10.100 ; 10.100 ; 10.100 ;
; FC[0]        ; RAM_DATA[13]  ; 10.603 ; 10.603 ; 10.603 ; 10.603 ;
; FC[0]        ; RAM_DATA[14]  ; 10.413 ; 10.413 ; 10.413 ; 10.413 ;
; FC[0]        ; RAM_DATA[15]  ; 10.518 ; 10.518 ; 10.518 ; 10.518 ;
; FC[0]        ; ROM0n         ; 7.620  ; 7.620  ; 7.620  ; 7.620  ;
; FC[0]        ; ROM1n         ; 7.509  ; 7.509  ; 7.509  ; 7.509  ;
; FC[0]        ; ROM2n         ; 8.284  ; 8.284  ; 8.284  ; 8.284  ;
; FC[0]        ; ROM3n         ; 7.342  ; 7.342  ; 7.342  ; 7.342  ;
; FC[0]        ; ROM4n         ; 7.400  ; 7.400  ; 7.400  ; 7.400  ;
; FC[0]        ; ROM5n         ; 8.314  ; 8.314  ; 8.314  ; 8.314  ;
; FC[0]        ; ROM6n         ; 8.296  ; 8.296  ; 8.296  ; 8.296  ;
; FC[1]        ; ACSI_RDn      ; 9.215  ; 9.215  ; 9.215  ; 9.215  ;
; FC[1]        ; ACSI_WRn      ; 9.219  ; 9.219  ; 9.219  ; 9.219  ;
; FC[1]        ; BUTTONn       ; 7.938  ; 7.938  ; 7.938  ; 7.938  ;
; FC[1]        ; CA1_OUT       ; 8.903  ; 8.903  ; 8.903  ; 8.903  ;
; FC[1]        ; CD[0]         ; 9.712  ; 9.712  ; 9.712  ; 9.712  ;
; FC[1]        ; CD[1]         ; 9.634  ; 9.634  ; 9.634  ; 9.634  ;
; FC[1]        ; CD[2]         ; 8.930  ; 8.930  ; 8.930  ; 8.930  ;
; FC[1]        ; CD[3]         ; 9.705  ; 9.705  ; 9.705  ; 9.705  ;
; FC[1]        ; CD[4]         ; 9.199  ; 9.199  ; 9.199  ; 9.199  ;
; FC[1]        ; CD[5]         ; 9.191  ; 9.191  ; 9.191  ; 9.191  ;
; FC[1]        ; CD[6]         ; 9.341  ; 9.341  ; 9.341  ; 9.341  ;
; FC[1]        ; CD[7]         ; 9.035  ; 9.035  ; 9.035  ; 9.035  ;
; FC[1]        ; DATA[0]       ; 9.671  ; 9.671  ; 9.671  ; 9.671  ;
; FC[1]        ; DATA[1]       ; 10.266 ; 10.266 ; 10.266 ; 10.266 ;
; FC[1]        ; DATA[2]       ; 9.819  ; 9.819  ; 9.819  ; 9.819  ;
; FC[1]        ; DATA[3]       ; 9.590  ; 9.590  ; 9.590  ; 9.590  ;
; FC[1]        ; DATA[4]       ; 9.658  ; 9.658  ; 9.658  ; 9.658  ;
; FC[1]        ; DATA[5]       ; 10.456 ; 10.456 ; 10.456 ; 10.456 ;
; FC[1]        ; DATA[6]       ; 10.248 ; 10.248 ; 10.248 ; 10.248 ;
; FC[1]        ; DATA[7]       ; 10.639 ; 10.639 ; 10.639 ; 10.639 ;
; FC[1]        ; DATA[8]       ; 10.274 ; 10.274 ; 10.274 ; 10.274 ;
; FC[1]        ; DATA[9]       ; 10.664 ; 10.664 ; 10.664 ; 10.664 ;
; FC[1]        ; DATA[10]      ; 9.557  ; 9.557  ; 9.557  ; 9.557  ;
; FC[1]        ; DATA[11]      ; 10.685 ; 10.685 ; 10.685 ; 10.685 ;
; FC[1]        ; DATA[12]      ; 10.265 ; 10.265 ; 10.265 ; 10.265 ;
; FC[1]        ; DATA[13]      ; 9.850  ; 9.850  ; 9.850  ; 9.850  ;
; FC[1]        ; DATA[14]      ; 9.543  ; 9.543  ; 9.543  ; 9.543  ;
; FC[1]        ; DATA[15]      ; 9.848  ; 9.848  ; 9.848  ; 9.848  ;
; FC[1]        ; DTACKn        ; 8.647  ; 8.647  ; 8.647  ; 8.647  ;
; FC[1]        ; FLASH_CEn     ; 9.343  ; 9.343  ; 9.343  ; 9.343  ;
; FC[1]        ; FLASH_OEn     ; 9.039  ; 9.039  ; 9.039  ; 9.039  ;
; FC[1]        ; JOY_RHn       ; 8.212  ; 8.212  ; 8.212  ; 8.212  ;
; FC[1]        ; JOY_RLn       ; 8.351  ; 8.351  ; 8.351  ; 8.351  ;
; FC[1]        ; JOY_WEn       ; 8.205  ; 8.205  ; 8.205  ; 8.205  ;
; FC[1]        ; JOY_WL        ; 8.232  ; 8.232  ; 8.232  ; 8.232  ;
; FC[1]        ; RAM_DATA[0]   ; 10.202 ; 10.202 ; 10.202 ; 10.202 ;
; FC[1]        ; RAM_DATA[1]   ; 10.636 ; 10.636 ; 10.636 ; 10.636 ;
; FC[1]        ; RAM_DATA[2]   ; 10.171 ; 10.171 ; 10.171 ; 10.171 ;
; FC[1]        ; RAM_DATA[3]   ; 10.569 ; 10.569 ; 10.569 ; 10.569 ;
; FC[1]        ; RAM_DATA[4]   ; 10.540 ; 10.540 ; 10.540 ; 10.540 ;
; FC[1]        ; RAM_DATA[5]   ; 11.107 ; 11.107 ; 11.107 ; 11.107 ;
; FC[1]        ; RAM_DATA[6]   ; 10.620 ; 10.620 ; 10.620 ; 10.620 ;
; FC[1]        ; RAM_DATA[7]   ; 10.927 ; 10.927 ; 10.927 ; 10.927 ;
; FC[1]        ; RAM_DATA[8]   ; 10.447 ; 10.447 ; 10.447 ; 10.447 ;
; FC[1]        ; RAM_DATA[9]   ; 10.822 ; 10.822 ; 10.822 ; 10.822 ;
; FC[1]        ; RAM_DATA[10]  ; 10.153 ; 10.153 ; 10.153 ; 10.153 ;
; FC[1]        ; RAM_DATA[11]  ; 10.389 ; 10.389 ; 10.389 ; 10.389 ;
; FC[1]        ; RAM_DATA[12]  ; 10.099 ; 10.099 ; 10.099 ; 10.099 ;
; FC[1]        ; RAM_DATA[13]  ; 10.602 ; 10.602 ; 10.602 ; 10.602 ;
; FC[1]        ; RAM_DATA[14]  ; 10.412 ; 10.412 ; 10.412 ; 10.412 ;
; FC[1]        ; RAM_DATA[15]  ; 10.517 ; 10.517 ; 10.517 ; 10.517 ;
; FC[1]        ; ROM0n         ; 7.732  ; 7.732  ; 7.732  ; 7.732  ;
; FC[1]        ; ROM1n         ; 7.621  ; 7.621  ; 7.621  ; 7.621  ;
; FC[1]        ; ROM2n         ; 8.396  ; 8.396  ; 8.396  ; 8.396  ;
; FC[1]        ; ROM3n         ; 7.454  ; 7.454  ; 7.454  ; 7.454  ;
; FC[1]        ; ROM4n         ; 7.512  ; 7.512  ; 7.512  ; 7.512  ;
; FC[1]        ; ROM5n         ; 8.426  ; 8.426  ; 8.426  ; 8.426  ;
; FC[1]        ; ROM6n         ; 8.408  ; 8.408  ; 8.408  ; 8.408  ;
; FC[2]        ; ACSI_RDn      ; 9.164  ; 9.164  ; 9.164  ; 9.164  ;
; FC[2]        ; ACSI_WRn      ; 9.168  ; 9.168  ; 9.168  ; 9.168  ;
; FC[2]        ; CA1_OUT       ;        ; 8.852  ; 8.852  ;        ;
; FC[2]        ; CD[0]         ; 9.661  ; 9.704  ; 9.704  ; 9.661  ;
; FC[2]        ; CD[1]         ; 9.583  ; 9.626  ; 9.626  ; 9.583  ;
; FC[2]        ; CD[2]         ; 8.879  ; 8.879  ; 8.879  ; 8.879  ;
; FC[2]        ; CD[3]         ; 9.654  ; 9.795  ; 9.795  ; 9.654  ;
; FC[2]        ; CD[4]         ; 9.148  ; 9.148  ; 9.148  ; 9.148  ;
; FC[2]        ; CD[5]         ; 9.140  ; 9.140  ; 9.140  ; 9.140  ;
; FC[2]        ; CD[6]         ; 9.290  ; 9.290  ; 9.290  ; 9.290  ;
; FC[2]        ; CD[7]         ; 8.984  ; 8.984  ; 8.984  ; 8.984  ;
; FC[2]        ; DATA[0]       ; 10.003 ; 9.620  ; 9.620  ; 10.003 ;
; FC[2]        ; DATA[1]       ; 10.399 ; 10.215 ; 10.215 ; 10.399 ;
; FC[2]        ; DATA[2]       ; 11.423 ; 9.768  ; 9.768  ; 11.423 ;
; FC[2]        ; DATA[3]       ; 10.998 ; 9.539  ; 9.539  ; 10.998 ;
; FC[2]        ; DATA[4]       ; 11.031 ; 9.607  ; 9.607  ; 11.031 ;
; FC[2]        ; DATA[5]       ; 11.844 ; 10.405 ; 10.405 ; 11.844 ;
; FC[2]        ; DATA[6]       ; 11.471 ; 10.197 ; 10.197 ; 11.471 ;
; FC[2]        ; DATA[7]       ; 11.826 ; 10.588 ; 10.588 ; 11.826 ;
; FC[2]        ; DATA[8]       ; 11.464 ; 10.410 ; 10.410 ; 11.464 ;
; FC[2]        ; DATA[9]       ; 11.949 ; 10.800 ; 10.800 ; 11.949 ;
; FC[2]        ; DATA[10]      ; 10.875 ; 9.547  ; 9.547  ; 10.875 ;
; FC[2]        ; DATA[11]      ; 11.705 ; 10.634 ; 10.634 ; 11.705 ;
; FC[2]        ; DATA[12]      ; 11.512 ; 10.214 ; 10.214 ; 11.512 ;
; FC[2]        ; DATA[13]      ; 11.263 ; 9.799  ; 9.799  ; 11.263 ;
; FC[2]        ; DATA[14]      ; 10.660 ; 9.492  ; 9.492  ; 10.660 ;
; FC[2]        ; DATA[15]      ; 11.120 ; 9.797  ; 9.797  ; 11.120 ;
; FC[2]        ; DTACKn        ; 8.817  ; 8.817  ; 8.817  ; 8.817  ;
; FC[2]        ; JOY_RHn       ;        ; 8.161  ; 8.161  ;        ;
; FC[2]        ; JOY_RLn       ;        ; 8.300  ; 8.300  ;        ;
; FC[2]        ; JOY_WEn       ; 8.154  ;        ;        ; 8.154  ;
; FC[2]        ; JOY_WL        ; 8.181  ;        ;        ; 8.181  ;
; FC[2]        ; RAM_DATA[0]   ; 10.534 ; 10.151 ; 10.151 ; 10.534 ;
; FC[2]        ; RAM_DATA[1]   ; 10.769 ; 10.585 ; 10.585 ; 10.769 ;
; FC[2]        ; RAM_DATA[2]   ; 11.775 ; 10.120 ; 10.120 ; 11.775 ;
; FC[2]        ; RAM_DATA[3]   ; 11.977 ; 10.518 ; 10.518 ; 11.977 ;
; FC[2]        ; RAM_DATA[4]   ; 11.913 ; 10.489 ; 10.489 ; 11.913 ;
; FC[2]        ; RAM_DATA[5]   ; 12.495 ; 11.056 ; 11.056 ; 12.495 ;
; FC[2]        ; RAM_DATA[6]   ; 11.843 ; 10.569 ; 10.569 ; 11.843 ;
; FC[2]        ; RAM_DATA[7]   ; 12.114 ; 10.876 ; 10.876 ; 12.114 ;
; FC[2]        ; RAM_DATA[8]   ; 11.637 ; 10.583 ; 10.583 ; 11.637 ;
; FC[2]        ; RAM_DATA[9]   ; 12.107 ; 10.958 ; 10.958 ; 12.107 ;
; FC[2]        ; RAM_DATA[10]  ; 11.471 ; 10.143 ; 10.143 ; 11.471 ;
; FC[2]        ; RAM_DATA[11]  ; 11.409 ; 10.338 ; 10.338 ; 11.409 ;
; FC[2]        ; RAM_DATA[12]  ; 11.346 ; 10.048 ; 10.048 ; 11.346 ;
; FC[2]        ; RAM_DATA[13]  ; 12.015 ; 10.551 ; 10.551 ; 12.015 ;
; FC[2]        ; RAM_DATA[14]  ; 11.529 ; 10.361 ; 10.361 ; 11.529 ;
; FC[2]        ; RAM_DATA[15]  ; 11.789 ; 10.466 ; 10.466 ; 11.789 ;
; HDINTn       ; DATA[5]       ; 10.910 ;        ;        ; 10.910 ;
; HDINTn       ; RAM_DATA[5]   ; 11.561 ;        ;        ; 11.561 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 10.752 ; 10.752 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 11.403 ; 11.403 ;        ;
; IDE_IORDY    ; DTACKn        ; 7.922  ; 7.922  ; 7.922  ; 7.922  ;
; LDSn         ; ACSI_RDn      ; 8.450  ; 8.450  ; 8.450  ; 8.450  ;
; LDSn         ; ACSI_WRn      ; 8.454  ; 8.454  ; 8.454  ; 8.454  ;
; LDSn         ; BUTTONn       ; 9.490  ;        ;        ; 9.490  ;
; LDSn         ; CA1_OUT       ; 8.138  ;        ;        ; 8.138  ;
; LDSn         ; CD[0]         ; 8.990  ; 8.947  ; 8.947  ; 8.990  ;
; LDSn         ; CD[1]         ; 8.912  ; 8.869  ; 8.869  ; 8.912  ;
; LDSn         ; CD[2]         ; 8.165  ; 8.165  ; 8.165  ; 8.165  ;
; LDSn         ; CD[3]         ; 9.081  ; 8.940  ; 8.940  ; 9.081  ;
; LDSn         ; CD[4]         ; 8.434  ; 8.434  ; 8.434  ; 8.434  ;
; LDSn         ; CD[5]         ; 8.426  ; 8.426  ; 8.426  ; 8.426  ;
; LDSn         ; CD[6]         ; 8.576  ; 8.576  ; 8.576  ; 8.576  ;
; LDSn         ; CD[7]         ; 8.270  ; 8.270  ; 8.270  ; 8.270  ;
; LDSn         ; DATA[0]       ; 9.827  ; 9.679  ; 9.679  ; 9.827  ;
; LDSn         ; DATA[1]       ; 9.993  ; 9.955  ; 9.955  ; 9.993  ;
; LDSn         ; DATA[2]       ; 9.818  ; 9.756  ; 9.756  ; 9.818  ;
; LDSn         ; DATA[3]       ; 9.306  ; 9.331  ; 9.331  ; 9.306  ;
; LDSn         ; DATA[4]       ; 9.438  ; 9.512  ; 9.512  ; 9.438  ;
; LDSn         ; DATA[5]       ; 9.966  ; 9.966  ; 9.966  ; 9.966  ;
; LDSn         ; DATA[6]       ; 9.804  ; 9.804  ; 9.804  ; 9.804  ;
; LDSn         ; DATA[7]       ; 9.794  ; 9.794  ; 9.794  ; 9.794  ;
; LDSn         ; DATA[8]       ; 9.921  ; 9.921  ; 9.921  ; 9.921  ;
; LDSn         ; DATA[9]       ; 9.921  ; 9.921  ; 9.921  ; 9.921  ;
; LDSn         ; DATA[10]      ; 8.998  ; 9.208  ; 9.208  ; 8.998  ;
; LDSn         ; DATA[11]      ; 10.058 ; 10.058 ; 10.058 ; 10.058 ;
; LDSn         ; DATA[12]      ; 10.101 ; 9.951  ; 9.951  ; 10.101 ;
; LDSn         ; DATA[13]      ; 9.787  ; 9.596  ; 9.596  ; 9.787  ;
; LDSn         ; DATA[14]      ; 9.383  ; 9.036  ; 9.036  ; 9.383  ;
; LDSn         ; DATA[15]      ; 9.738  ; 10.063 ; 10.063 ; 9.738  ;
; LDSn         ; DTACKn        ; 8.529  ; 8.529  ; 8.529  ; 8.529  ;
; LDSn         ; IDE_IORDn     ; 7.507  ;        ;        ; 7.507  ;
; LDSn         ; IDE_IOWRn     ; 7.365  ;        ;        ; 7.365  ;
; LDSn         ; JOY_RLn       ; 6.633  ;        ;        ; 6.633  ;
; LDSn         ; JOY_WEn       ;        ; 6.487  ; 6.487  ;        ;
; LDSn         ; JOY_WL        ;        ; 6.291  ; 6.291  ;        ;
; LDSn         ; RAM_CAS0n     ; 8.069  ;        ;        ; 8.069  ;
; LDSn         ; RAM_DATA[0]   ; 10.358 ; 10.210 ; 10.210 ; 10.358 ;
; LDSn         ; RAM_DATA[1]   ; 10.363 ; 10.325 ; 10.325 ; 10.363 ;
; LDSn         ; RAM_DATA[2]   ; 10.170 ; 10.108 ; 10.108 ; 10.170 ;
; LDSn         ; RAM_DATA[3]   ; 10.285 ; 10.310 ; 10.310 ; 10.285 ;
; LDSn         ; RAM_DATA[4]   ; 10.320 ; 10.394 ; 10.394 ; 10.320 ;
; LDSn         ; RAM_DATA[5]   ; 11.096 ; 11.246 ; 11.246 ; 11.096 ;
; LDSn         ; RAM_DATA[6]   ; 10.354 ; 10.600 ; 10.600 ; 10.354 ;
; LDSn         ; RAM_DATA[7]   ; 10.663 ; 10.815 ; 10.815 ; 10.663 ;
; LDSn         ; RAM_DATA[8]   ; 10.323 ; 10.330 ; 10.330 ; 10.323 ;
; LDSn         ; RAM_DATA[9]   ; 10.908 ; 10.737 ; 10.737 ; 10.908 ;
; LDSn         ; RAM_DATA[10]  ; 9.594  ; 9.804  ; 9.804  ; 9.594  ;
; LDSn         ; RAM_DATA[11]  ; 10.117 ; 9.785  ; 9.785  ; 10.117 ;
; LDSn         ; RAM_DATA[12]  ; 9.996  ; 9.785  ; 9.785  ; 9.996  ;
; LDSn         ; RAM_DATA[13]  ; 10.539 ; 10.348 ; 10.348 ; 10.539 ;
; LDSn         ; RAM_DATA[14]  ; 10.252 ; 9.905  ; 9.905  ; 10.252 ;
; LDSn         ; RAM_DATA[15]  ; 10.407 ; 10.743 ; 10.743 ; 10.407 ;
; LDSn         ; RAM_DQM0L     ; 7.228  ;        ;        ; 7.228  ;
; LPT_BSY      ; DATA[0]       ; 10.497 ;        ;        ; 10.497 ;
; LPT_BSY      ; RAM_DATA[0]   ; 11.028 ;        ;        ; 11.028 ;
; LPT_D[0]     ; DATA[8]       ; 9.949  ;        ;        ; 9.949  ;
; LPT_D[0]     ; RAM_DATA[8]   ; 10.122 ;        ;        ; 10.122 ;
; LPT_D[1]     ; DATA[9]       ; 10.070 ;        ;        ; 10.070 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 10.228 ;        ;        ; 10.228 ;
; LPT_D[2]     ; DATA[10]      ; 9.155  ;        ;        ; 9.155  ;
; LPT_D[2]     ; RAM_DATA[10]  ; 9.751  ;        ;        ; 9.751  ;
; LPT_D[3]     ; DATA[11]      ; 9.686  ;        ;        ; 9.686  ;
; LPT_D[3]     ; RAM_DATA[11]  ; 9.390  ;        ;        ; 9.390  ;
; LPT_D[4]     ; DATA[12]      ; 9.820  ;        ;        ; 9.820  ;
; LPT_D[4]     ; RAM_DATA[12]  ; 9.654  ;        ;        ; 9.654  ;
; LPT_D[5]     ; DATA[13]      ; 9.421  ;        ;        ; 9.421  ;
; LPT_D[5]     ; RAM_DATA[13]  ; 10.173 ;        ;        ; 10.173 ;
; LPT_D[6]     ; DATA[14]      ; 8.850  ;        ;        ; 8.850  ;
; LPT_D[6]     ; RAM_DATA[14]  ; 9.719  ;        ;        ; 9.719  ;
; LPT_D[7]     ; DATA[15]      ; 9.646  ;        ;        ; 9.646  ;
; LPT_D[7]     ; RAM_DATA[15]  ; 10.315 ;        ;        ; 10.315 ;
; MIDI_IN      ; MIDI_TLR      ; 4.720  ;        ;        ; 4.720  ;
; RAM_DATA[0]  ; DATA[0]       ; 9.768  ;        ;        ; 9.768  ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 10.299 ;        ;        ; 10.299 ;
; RAM_DATA[1]  ; DATA[1]       ; 9.997  ;        ;        ; 9.997  ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 10.367 ;        ;        ; 10.367 ;
; RAM_DATA[2]  ; DATA[2]       ; 9.687  ;        ;        ; 9.687  ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 10.039 ;        ;        ; 10.039 ;
; RAM_DATA[3]  ; DATA[3]       ; 9.494  ;        ;        ; 9.494  ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 10.473 ;        ;        ; 10.473 ;
; RAM_DATA[4]  ; DATA[4]       ; 9.496  ;        ;        ; 9.496  ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 10.378 ;        ;        ; 10.378 ;
; RAM_DATA[5]  ; DATA[5]       ; 10.737 ;        ;        ; 10.737 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 11.388 ;        ;        ; 11.388 ;
; RAM_DATA[6]  ; DATA[6]       ; 11.236 ;        ;        ; 11.236 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 11.608 ;        ;        ; 11.608 ;
; RAM_DATA[7]  ; DATA[7]       ; 10.711 ;        ;        ; 10.711 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 10.999 ;        ;        ; 10.999 ;
; RAM_DATA[8]  ; DATA[8]       ; 10.341 ;        ;        ; 10.341 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 10.514 ;        ;        ; 10.514 ;
; RAM_DATA[9]  ; DATA[9]       ; 11.037 ;        ;        ; 11.037 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 11.195 ;        ;        ; 11.195 ;
; RAM_DATA[10] ; DATA[10]      ; 9.557  ;        ;        ; 9.557  ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 10.153 ;        ;        ; 10.153 ;
; RAM_DATA[11] ; DATA[11]      ; 10.789 ;        ;        ; 10.789 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 10.493 ;        ;        ; 10.493 ;
; RAM_DATA[12] ; DATA[12]      ; 9.954  ;        ;        ; 9.954  ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 9.788  ;        ;        ; 9.788  ;
; RAM_DATA[13] ; DATA[13]      ; 9.639  ;        ;        ; 9.639  ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 10.391 ;        ;        ; 10.391 ;
; RAM_DATA[14] ; DATA[14]      ; 9.600  ;        ;        ; 9.600  ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 10.469 ;        ;        ; 10.469 ;
; RAM_DATA[15] ; DATA[15]      ; 10.294 ;        ;        ; 10.294 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 10.963 ;        ;        ; 10.963 ;
; RWn          ; ACSI_RDn      ; 9.180  ; 7.122  ; 7.122  ; 9.180  ;
; RWn          ; ACSI_WRn      ; 7.126  ; 9.184  ; 9.184  ; 7.126  ;
; RWn          ; BUTTONn       ;        ; 7.901  ; 7.901  ;        ;
; RWn          ; CA1_OUT       ;        ; 8.868  ; 8.868  ;        ;
; RWn          ; CD[0]         ; 7.615  ; 7.489  ; 7.489  ; 7.615  ;
; RWn          ; CD[1]         ; 7.531  ; 7.411  ; 7.411  ; 7.531  ;
; RWn          ; CD[2]         ; 6.707  ; 6.707  ; 6.707  ; 6.707  ;
; RWn          ; CD[3]         ; 7.623  ; 7.482  ; 7.482  ; 7.623  ;
; RWn          ; CD[4]         ; 6.976  ; 6.976  ; 6.976  ; 6.976  ;
; RWn          ; CD[5]         ; 6.968  ; 6.968  ; 6.968  ; 6.968  ;
; RWn          ; CD[6]         ; 7.118  ; 7.118  ; 7.118  ; 7.118  ;
; RWn          ; CD[7]         ; 6.812  ; 6.812  ; 6.812  ; 6.812  ;
; RWn          ; DATA[0]       ; 8.730  ; 8.555  ; 8.555  ; 8.730  ;
; RWn          ; DATA[1]       ; 9.126  ; 9.140  ; 9.140  ; 9.126  ;
; RWn          ; DATA[2]       ; 8.851  ; 8.629  ; 8.629  ; 8.851  ;
; RWn          ; DATA[3]       ; 8.998  ; 8.371  ; 8.371  ; 8.998  ;
; RWn          ; DATA[4]       ; 8.972  ; 8.468  ; 8.468  ; 8.972  ;
; RWn          ; DATA[5]       ; 9.355  ; 9.266  ; 9.266  ; 9.355  ;
; RWn          ; DATA[6]       ; 9.442  ; 9.058  ; 9.058  ; 9.442  ;
; RWn          ; DATA[7]       ; 9.738  ; 9.410  ; 9.410  ; 9.738  ;
; RWn          ; DATA[8]       ; 9.269  ; 9.122  ; 9.122  ; 9.269  ;
; RWn          ; DATA[9]       ; 9.651  ; 9.340  ; 9.340  ; 9.651  ;
; RWn          ; DATA[10]      ; 8.075  ; 8.075  ; 8.075  ; 8.075  ;
; RWn          ; DATA[11]      ; 9.605  ; 9.317  ; 9.317  ; 9.605  ;
; RWn          ; DATA[12]      ; 9.397  ; 9.075  ; 9.075  ; 9.397  ;
; RWn          ; DATA[13]      ; 9.023  ; 8.590  ; 8.590  ; 9.023  ;
; RWn          ; DATA[14]      ; 8.533  ; 8.095  ; 8.095  ; 8.533  ;
; RWn          ; DATA[15]      ; 9.031  ; 8.658  ; 8.658  ; 9.031  ;
; RWn          ; DTACKn        ; 8.493  ; 8.493  ; 8.493  ; 8.493  ;
; RWn          ; FLASH_CEn     ;        ; 9.189  ; 9.189  ;        ;
; RWn          ; FLASH_OEn     ;        ; 8.885  ; 8.885  ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 7.107  ; 7.107  ;        ;
; RWn          ; IDE_D_EN_OUTn ; 7.372  ;        ;        ; 7.372  ;
; RWn          ; IDE_IORDn     ;        ; 7.214  ; 7.214  ;        ;
; RWn          ; IDE_IOWRn     ; 7.074  ;        ;        ; 7.074  ;
; RWn          ; JOY_RHn       ;        ; 6.969  ; 6.969  ;        ;
; RWn          ; JOY_RLn       ;        ; 7.108  ; 7.108  ;        ;
; RWn          ; JOY_WEn       ; 6.962  ;        ;        ; 6.962  ;
; RWn          ; JOY_WL        ; 8.197  ; 6.120  ; 6.120  ; 8.197  ;
; RWn          ; RAM_DATA[0]   ; 7.425  ; 7.425  ; 7.425  ; 7.425  ;
; RWn          ; RAM_DATA[1]   ; 7.427  ; 7.427  ; 7.427  ; 7.427  ;
; RWn          ; RAM_DATA[2]   ; 7.427  ; 7.427  ; 7.427  ; 7.427  ;
; RWn          ; RAM_DATA[3]   ; 7.752  ; 7.752  ; 7.752  ; 7.752  ;
; RWn          ; RAM_DATA[4]   ; 7.752  ; 7.752  ; 7.752  ; 7.752  ;
; RWn          ; RAM_DATA[5]   ; 8.064  ; 8.064  ; 8.064  ; 8.064  ;
; RWn          ; RAM_DATA[6]   ; 7.974  ; 7.974  ; 7.974  ; 7.974  ;
; RWn          ; RAM_DATA[7]   ; 8.064  ; 8.064  ; 8.064  ; 8.064  ;
; RWn          ; RAM_DATA[8]   ; 7.646  ; 7.646  ; 7.646  ; 7.646  ;
; RWn          ; RAM_DATA[9]   ; 7.646  ; 7.646  ; 7.646  ; 7.646  ;
; RWn          ; RAM_DATA[10]  ; 7.563  ; 7.563  ; 7.563  ; 7.563  ;
; RWn          ; RAM_DATA[11]  ; 7.553  ; 7.553  ; 7.553  ; 7.553  ;
; RWn          ; RAM_DATA[12]  ; 7.553  ; 7.553  ; 7.553  ; 7.553  ;
; RWn          ; RAM_DATA[13]  ; 7.553  ; 7.553  ; 7.553  ; 7.553  ;
; RWn          ; RAM_DATA[14]  ; 7.428  ; 7.428  ; 7.428  ; 7.428  ;
; RWn          ; RAM_DATA[15]  ; 7.428  ; 7.428  ; 7.428  ; 7.428  ;
; RWn          ; RAM_WEn       ; 7.768  ;        ;        ; 7.768  ;
; RWn          ; ROM0n         ;        ; 7.578  ; 7.578  ;        ;
; RWn          ; ROM1n         ;        ; 7.467  ; 7.467  ;        ;
; RWn          ; ROM2n         ;        ; 8.242  ; 8.242  ;        ;
; RWn          ; ROM3n         ;        ; 7.300  ; 7.300  ;        ;
; RWn          ; ROM4n         ;        ; 7.358  ; 7.358  ;        ;
; RWn          ; ROM5n         ;        ; 8.272  ; 8.272  ;        ;
; RWn          ; ROM6n         ;        ; 8.254  ; 8.254  ;        ;
; SCSI_ACKn    ; CD[0]         ; 6.695  ; 6.695  ; 6.695  ; 6.695  ;
; SCSI_ATNn    ; CD[1]         ; 7.735  ; 7.735  ; 7.735  ; 7.735  ;
; SCSI_BSYn    ; CD[6]         ; 8.037  ; 8.037  ; 8.037  ; 8.037  ;
; SCSI_D[0]    ; CD[0]         ; 6.896  ; 6.896  ; 6.896  ; 6.896  ;
; SCSI_D[1]    ; CD[1]         ; 6.937  ; 6.937  ; 6.937  ; 6.937  ;
; SCSI_D[2]    ; CD[2]         ;        ; 6.348  ; 6.348  ;        ;
; SCSI_D[3]    ; CD[3]         ; 7.049  ; 7.049  ; 7.049  ; 7.049  ;
; SCSI_D[4]    ; CD[4]         ; 8.060  ; 8.060  ; 8.060  ; 8.060  ;
; SCSI_D[5]    ; CD[5]         ; 7.640  ; 7.640  ; 7.640  ; 7.640  ;
; SCSI_D[6]    ; CD[6]         ; 7.899  ; 7.899  ; 7.899  ; 7.899  ;
; SCSI_D[7]    ; CD[7]         ; 7.487  ; 7.487  ; 7.487  ; 7.487  ;
; SCSI_DCn     ; CD[3]         ; 7.337  ; 7.337  ; 7.337  ; 7.337  ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 8.297  ; 8.297  ; 8.297  ; 8.297  ;
; SCSI_DCn     ; SCSI_D[0]     ; 7.777  ; 7.777  ; 7.777  ; 7.777  ;
; SCSI_DCn     ; SCSI_D[1]     ; 7.777  ; 7.777  ; 7.777  ; 7.777  ;
; SCSI_DCn     ; SCSI_D[2]     ; 7.772  ; 7.772  ; 7.772  ; 7.772  ;
; SCSI_DCn     ; SCSI_D[3]     ; 7.772  ; 7.772  ; 7.772  ; 7.772  ;
; SCSI_DCn     ; SCSI_D[4]     ; 7.911  ; 7.911  ; 7.911  ; 7.911  ;
; SCSI_DCn     ; SCSI_D[5]     ; 7.911  ; 7.911  ; 7.911  ; 7.911  ;
; SCSI_DCn     ; SCSI_D[6]     ; 8.013  ; 8.013  ; 8.013  ; 8.013  ;
; SCSI_DCn     ; SCSI_D[7]     ; 8.013  ; 8.013  ; 8.013  ; 8.013  ;
; SCSI_DCn     ; SCSI_DP       ; 7.787  ; 7.787  ; 7.787  ; 7.787  ;
; SCSI_DP      ; CD[0]         ; 6.773  ; 6.773  ; 6.773  ; 6.773  ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 5.999  ; 5.999  ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 6.007  ;        ;        ; 6.007  ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 6.001  ; 6.001  ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 6.111  ;        ;        ; 6.111  ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 6.329  ; 6.329  ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 6.306  ;        ;        ; 6.306  ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 6.481  ; 6.481  ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 6.226  ;        ;        ; 6.226  ;
; SCSI_IDn[1]  ; SCSI_DP       ; 6.379  ; 6.379  ; 6.379  ; 6.379  ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 5.849  ; 5.849  ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 5.888  ; 5.888  ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 5.843  ;        ;        ; 5.843  ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 5.980  ;        ;        ; 5.980  ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 6.189  ; 6.189  ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 6.190  ; 6.190  ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 6.340  ;        ;        ; 6.340  ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 6.097  ;        ;        ; 6.097  ;
; SCSI_IDn[2]  ; SCSI_DP       ; 6.239  ; 6.239  ; 6.239  ; 6.239  ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 6.047  ; 6.047  ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 6.083  ; 6.083  ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 6.046  ; 6.046  ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 6.181  ; 6.181  ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 6.376  ;        ;        ; 6.376  ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 6.377  ;        ;        ; 6.377  ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 6.529  ;        ;        ; 6.529  ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 6.296  ;        ;        ; 6.296  ;
; SCSI_IDn[3]  ; SCSI_DP       ; 6.426  ; 6.426  ; 6.426  ; 6.426  ;
; SCSI_IOn     ; CD[2]         ;        ; 7.258  ; 7.258  ;        ;
; SCSI_IOn     ; CD[3]         ; 8.461  ; 8.461  ; 8.461  ; 8.461  ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 6.954  ; 8.236  ; 8.236  ; 6.954  ;
; SCSI_IOn     ; SCSI_D[0]     ; 6.434  ; 6.434  ; 6.434  ; 6.434  ;
; SCSI_IOn     ; SCSI_D[1]     ; 6.434  ; 6.434  ; 6.434  ; 6.434  ;
; SCSI_IOn     ; SCSI_D[2]     ; 6.429  ; 6.429  ; 6.429  ; 6.429  ;
; SCSI_IOn     ; SCSI_D[3]     ; 6.429  ; 6.429  ; 6.429  ; 6.429  ;
; SCSI_IOn     ; SCSI_D[4]     ; 6.568  ; 6.568  ; 6.568  ; 6.568  ;
; SCSI_IOn     ; SCSI_D[5]     ; 6.568  ; 6.568  ; 6.568  ; 6.568  ;
; SCSI_IOn     ; SCSI_D[6]     ; 6.670  ; 6.670  ; 6.670  ; 6.670  ;
; SCSI_IOn     ; SCSI_D[7]     ; 6.670  ; 6.670  ; 6.670  ; 6.670  ;
; SCSI_IOn     ; SCSI_DP       ; 6.444  ; 6.444  ; 6.444  ; 6.444  ;
; SCSI_IOn     ; SCSI_RDn      ; 7.112  ;        ;        ; 7.112  ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 6.793  ; 6.793  ;        ;
; SCSI_MSGn    ; CD[3]         ; 8.150  ; 8.150  ; 8.150  ; 8.150  ;
; SCSI_MSGn    ; CD[4]         ; 8.042  ; 8.042  ; 8.042  ; 8.042  ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 7.925  ; 7.925  ; 7.925  ; 7.925  ;
; SCSI_MSGn    ; SCSI_D[0]     ; 7.405  ; 7.405  ; 7.405  ; 7.405  ;
; SCSI_MSGn    ; SCSI_D[1]     ; 7.405  ; 7.405  ; 7.405  ; 7.405  ;
; SCSI_MSGn    ; SCSI_D[2]     ; 7.400  ; 7.400  ; 7.400  ; 7.400  ;
; SCSI_MSGn    ; SCSI_D[3]     ; 7.400  ; 7.400  ; 7.400  ; 7.400  ;
; SCSI_MSGn    ; SCSI_D[4]     ; 7.539  ; 7.539  ; 7.539  ; 7.539  ;
; SCSI_MSGn    ; SCSI_D[5]     ; 7.539  ; 7.539  ; 7.539  ; 7.539  ;
; SCSI_MSGn    ; SCSI_D[6]     ; 7.641  ; 7.641  ; 7.641  ; 7.641  ;
; SCSI_MSGn    ; SCSI_D[7]     ; 7.641  ; 7.641  ; 7.641  ; 7.641  ;
; SCSI_MSGn    ; SCSI_DP       ; 7.415  ; 7.415  ; 7.415  ; 7.415  ;
; SCSI_REQn    ; CD[3]         ; 8.296  ; 8.296  ; 8.296  ; 8.296  ;
; SCSI_REQn    ; CD[5]         ; 7.860  ; 7.860  ; 7.860  ; 7.860  ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 8.071  ;        ;        ; 8.071  ;
; SCSI_REQn    ; SCSI_D[0]     ; 7.551  ; 7.551  ; 7.551  ; 7.551  ;
; SCSI_REQn    ; SCSI_D[1]     ; 7.551  ; 7.551  ; 7.551  ; 7.551  ;
; SCSI_REQn    ; SCSI_D[2]     ; 7.546  ; 7.546  ; 7.546  ; 7.546  ;
; SCSI_REQn    ; SCSI_D[3]     ; 7.546  ; 7.546  ; 7.546  ; 7.546  ;
; SCSI_REQn    ; SCSI_D[4]     ; 7.685  ; 7.685  ; 7.685  ; 7.685  ;
; SCSI_REQn    ; SCSI_D[5]     ; 7.685  ; 7.685  ; 7.685  ; 7.685  ;
; SCSI_REQn    ; SCSI_D[6]     ; 7.787  ; 7.787  ; 7.787  ; 7.787  ;
; SCSI_REQn    ; SCSI_D[7]     ; 7.787  ; 7.787  ; 7.787  ; 7.787  ;
; SCSI_REQn    ; SCSI_DP       ; 7.561  ; 7.561  ; 7.561  ; 7.561  ;
; SCSI_RSTn    ; CD[7]         ;        ; 7.782  ; 7.782  ;        ;
; SCSI_SELn    ; CD[1]         ; 7.053  ; 7.053  ; 7.053  ; 7.053  ;
; SD_AVR_ENn   ; RESETn        ;        ; 7.768  ; 7.768  ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 6.883  ; 6.883  ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 7.766  ; 7.766  ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 6.633  ;        ;        ; 6.633  ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 6.693  ;        ;        ; 6.693  ;
; SD_RESETn    ; ACSI_RDn      ; 9.204  ; 9.204  ; 9.204  ; 9.204  ;
; SD_RESETn    ; ACSI_WRn      ; 9.208  ; 9.208  ; 9.208  ; 9.208  ;
; SD_RESETn    ; CA1_OUT       ; 8.892  ;        ;        ; 8.892  ;
; SD_RESETn    ; CD[0]         ; 9.744  ; 9.701  ; 9.701  ; 9.744  ;
; SD_RESETn    ; CD[1]         ; 9.666  ; 9.623  ; 9.623  ; 9.666  ;
; SD_RESETn    ; CD[2]         ; 8.919  ; 8.919  ; 8.919  ; 8.919  ;
; SD_RESETn    ; CD[3]         ; 9.835  ; 9.694  ; 9.694  ; 9.835  ;
; SD_RESETn    ; CD[4]         ; 9.188  ; 9.188  ; 9.188  ; 9.188  ;
; SD_RESETn    ; CD[5]         ; 9.180  ; 9.180  ; 9.180  ; 9.180  ;
; SD_RESETn    ; CD[6]         ; 9.330  ; 9.330  ; 9.330  ; 9.330  ;
; SD_RESETn    ; CD[7]         ; 9.024  ; 9.024  ; 9.024  ; 9.024  ;
; SD_RESETn    ; COM_TxD       ; 9.751  ; 9.751  ; 9.751  ; 9.751  ;
; SD_RESETn    ; DATA[0]       ; 10.581 ; 11.371 ; 11.371 ; 10.581 ;
; SD_RESETn    ; DATA[1]       ; 11.070 ; 11.507 ; 11.507 ; 11.070 ;
; SD_RESETn    ; DATA[2]       ; 10.851 ; 11.556 ; 11.556 ; 10.851 ;
; SD_RESETn    ; DATA[3]       ; 10.580 ; 11.106 ; 11.106 ; 10.580 ;
; SD_RESETn    ; DATA[4]       ; 10.485 ; 11.071 ; 11.071 ; 10.485 ;
; SD_RESETn    ; DATA[5]       ; 11.458 ; 11.896 ; 11.896 ; 11.458 ;
; SD_RESETn    ; DATA[6]       ; 11.234 ; 11.511 ; 11.511 ; 11.234 ;
; SD_RESETn    ; DATA[7]       ; 11.384 ; 11.878 ; 11.878 ; 11.384 ;
; SD_RESETn    ; DATA[8]       ; 10.904 ; 11.541 ; 11.541 ; 10.904 ;
; SD_RESETn    ; DATA[9]       ; 11.504 ; 12.026 ; 12.026 ; 11.504 ;
; SD_RESETn    ; DATA[10]      ; 9.752  ; 10.993 ; 10.993 ; 9.752  ;
; SD_RESETn    ; DATA[11]      ; 11.329 ; 12.141 ; 12.141 ; 11.329 ;
; SD_RESETn    ; DATA[12]      ; 10.916 ; 12.174 ; 12.174 ; 10.916 ;
; SD_RESETn    ; DATA[13]      ; 10.541 ; 11.402 ; 11.402 ; 10.541 ;
; SD_RESETn    ; DATA[14]      ; 10.137 ; 10.918 ; 10.918 ; 10.137 ;
; SD_RESETn    ; DATA[15]      ; 10.492 ; 11.197 ; 11.197 ; 10.492 ;
; SD_RESETn    ; DTACKn        ; 9.830  ; 9.830  ; 9.830  ; 9.830  ;
; SD_RESETn    ; RAM_DATA[0]   ; 11.112 ; 11.902 ; 11.902 ; 11.112 ;
; SD_RESETn    ; RAM_DATA[1]   ; 11.440 ; 11.877 ; 11.877 ; 11.440 ;
; SD_RESETn    ; RAM_DATA[2]   ; 11.203 ; 11.908 ; 11.908 ; 11.203 ;
; SD_RESETn    ; RAM_DATA[3]   ; 11.559 ; 12.085 ; 12.085 ; 11.559 ;
; SD_RESETn    ; RAM_DATA[4]   ; 11.367 ; 11.953 ; 11.953 ; 11.367 ;
; SD_RESETn    ; RAM_DATA[5]   ; 12.109 ; 12.547 ; 12.547 ; 12.109 ;
; SD_RESETn    ; RAM_DATA[6]   ; 11.606 ; 11.883 ; 11.883 ; 11.606 ;
; SD_RESETn    ; RAM_DATA[7]   ; 11.672 ; 12.166 ; 12.166 ; 11.672 ;
; SD_RESETn    ; RAM_DATA[8]   ; 11.077 ; 11.714 ; 11.714 ; 11.077 ;
; SD_RESETn    ; RAM_DATA[9]   ; 11.662 ; 12.184 ; 12.184 ; 11.662 ;
; SD_RESETn    ; RAM_DATA[10]  ; 10.348 ; 11.589 ; 11.589 ; 10.348 ;
; SD_RESETn    ; RAM_DATA[11]  ; 11.033 ; 11.845 ; 11.845 ; 11.033 ;
; SD_RESETn    ; RAM_DATA[12]  ; 10.750 ; 12.008 ; 12.008 ; 10.750 ;
; SD_RESETn    ; RAM_DATA[13]  ; 11.293 ; 12.154 ; 12.154 ; 11.293 ;
; SD_RESETn    ; RAM_DATA[14]  ; 11.006 ; 11.787 ; 11.787 ; 11.006 ;
; SD_RESETn    ; RAM_DATA[15]  ; 11.161 ; 11.866 ; 11.866 ; 11.161 ;
; UDSn         ; ACSI_RDn      ; 8.353  ; 8.353  ; 8.353  ; 8.353  ;
; UDSn         ; ACSI_WRn      ; 8.357  ; 8.357  ; 8.357  ; 8.357  ;
; UDSn         ; CA1_OUT       ; 8.041  ;        ;        ; 8.041  ;
; UDSn         ; CD[0]         ; 8.893  ; 8.850  ; 8.850  ; 8.893  ;
; UDSn         ; CD[1]         ; 8.815  ; 8.772  ; 8.772  ; 8.815  ;
; UDSn         ; CD[2]         ; 8.068  ; 8.068  ; 8.068  ; 8.068  ;
; UDSn         ; CD[3]         ; 8.984  ; 8.843  ; 8.843  ; 8.984  ;
; UDSn         ; CD[4]         ; 8.337  ; 8.337  ; 8.337  ; 8.337  ;
; UDSn         ; CD[5]         ; 8.329  ; 8.329  ; 8.329  ; 8.329  ;
; UDSn         ; CD[6]         ; 8.479  ; 8.479  ; 8.479  ; 8.479  ;
; UDSn         ; CD[7]         ; 8.173  ; 8.173  ; 8.173  ; 8.173  ;
; UDSn         ; DATA[0]       ; 9.546  ; 9.546  ; 9.546  ; 9.546  ;
; UDSn         ; DATA[1]       ; 9.546  ; 9.546  ; 9.546  ; 9.546  ;
; UDSn         ; DATA[2]       ; 9.398  ; 9.398  ; 9.398  ; 9.398  ;
; UDSn         ; DATA[3]       ; 9.398  ; 9.398  ; 9.398  ; 9.398  ;
; UDSn         ; DATA[4]       ; 9.419  ; 9.419  ; 9.419  ; 9.419  ;
; UDSn         ; DATA[5]       ; 9.419  ; 9.419  ; 9.419  ; 9.419  ;
; UDSn         ; DATA[6]       ; 9.257  ; 9.257  ; 9.257  ; 9.257  ;
; UDSn         ; DATA[7]       ; 9.247  ; 9.247  ; 9.247  ; 9.247  ;
; UDSn         ; DATA[8]       ; 9.374  ; 9.374  ; 9.374  ; 9.374  ;
; UDSn         ; DATA[9]       ; 9.374  ; 9.374  ; 9.374  ; 9.374  ;
; UDSn         ; DATA[10]      ; 8.901  ; 9.511  ; 9.511  ; 8.901  ;
; UDSn         ; DATA[11]      ; 9.511  ; 9.511  ; 9.511  ; 9.511  ;
; UDSn         ; DATA[12]      ; 9.554  ; 9.554  ; 9.554  ; 9.554  ;
; UDSn         ; DATA[13]      ; 9.554  ; 9.554  ; 9.554  ; 9.554  ;
; UDSn         ; DATA[14]      ; 9.286  ; 9.526  ; 9.526  ; 9.286  ;
; UDSn         ; DATA[15]      ; 9.516  ; 9.516  ; 9.516  ; 9.516  ;
; UDSn         ; DTACKn        ; 8.979  ; 8.979  ; 8.979  ; 8.979  ;
; UDSn         ; JOY_RHn       ; 7.191  ;        ;        ; 7.191  ;
; UDSn         ; RAM_CAS0n     ; 7.834  ;        ;        ; 7.834  ;
; UDSn         ; RAM_DATA[0]   ; 10.261 ; 10.962 ; 10.962 ; 10.261 ;
; UDSn         ; RAM_DATA[1]   ; 10.589 ; 10.970 ; 10.970 ; 10.589 ;
; UDSn         ; RAM_DATA[2]   ; 10.352 ; 11.008 ; 11.008 ; 10.352 ;
; UDSn         ; RAM_DATA[3]   ; 10.708 ; 11.021 ; 11.021 ; 10.708 ;
; UDSn         ; RAM_DATA[4]   ; 10.516 ; 11.102 ; 11.102 ; 10.516 ;
; UDSn         ; RAM_DATA[5]   ; 11.258 ; 11.696 ; 11.696 ; 11.258 ;
; UDSn         ; RAM_DATA[6]   ; 10.755 ; 11.032 ; 11.032 ; 10.755 ;
; UDSn         ; RAM_DATA[7]   ; 10.821 ; 11.315 ; 11.315 ; 10.821 ;
; UDSn         ; RAM_DATA[8]   ; 10.226 ; 10.999 ; 10.999 ; 10.226 ;
; UDSn         ; RAM_DATA[9]   ; 10.811 ; 11.225 ; 11.225 ; 10.811 ;
; UDSn         ; RAM_DATA[10]  ; 9.497  ; 10.537 ; 10.537 ; 9.497  ;
; UDSn         ; RAM_DATA[11]  ; 10.182 ; 10.439 ; 10.439 ; 10.182 ;
; UDSn         ; RAM_DATA[12]  ; 9.899  ; 10.376 ; 10.376 ; 9.899  ;
; UDSn         ; RAM_DATA[13]  ; 10.442 ; 11.113 ; 11.113 ; 10.442 ;
; UDSn         ; RAM_DATA[14]  ; 10.155 ; 10.559 ; 10.559 ; 10.155 ;
; UDSn         ; RAM_DATA[15]  ; 10.310 ; 11.062 ; 11.062 ; 10.310 ;
; UDSn         ; RAM_DQM0H     ; 7.273  ;        ;        ; 7.273  ;
+--------------+---------------+--------+--------+--------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                     ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+--------------+--------------+--------------+
; From Clock                                                 ; To Clock                                                   ; RR Paths     ; FR Paths     ; RF Paths     ; FF Paths     ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+--------------+--------------+--------------+
; CLK_PLL1                                                   ; CLK_PLL1                                                   ; 51           ; 0            ; 0            ; 0            ;
; CLK_PLL1                                                   ; CODEC_SCLK                                                 ; false path   ; 0            ; false path   ; 0            ;
; CODEC_SCLK                                                 ; CODEC_SCLK                                                 ; 102503       ; 9122         ; 76           ; 469          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; CODEC_SCLK                                                 ; false path   ; 0            ; false path   ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; CODEC_SCLK                                                 ; false path   ; 0            ; false path   ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; CODEC_SCLK                                                 ; false path   ; 0            ; false path   ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; CODEC_SCLK                                                 ; false path   ; 0            ; false path   ; 0            ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path   ; 0            ; false path   ; 0            ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path   ; false path   ; false path   ; false path   ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 126          ; 126          ; 17           ; 17           ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; > 2147483647 ; > 2147483647 ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; > 2147483647 ; > 2147483647 ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 521938       ; 0            ; 89917        ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 521938       ; 0            ; 89917        ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 677263       ; 0            ; 118132       ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 677263       ; 0            ; 118132       ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1            ; 0            ; 0            ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 129          ; 0            ; 0            ; 0            ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path   ; 0            ; false path   ; 0            ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path   ; false path   ; false path   ; false path   ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 126          ; 126          ; 17           ; 17           ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; > 2147483647 ; > 2147483647 ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; > 2147483647 ; > 2147483647 ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 521938       ; 0            ; 89917        ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 521938       ; 0            ; 89917        ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 677263       ; 0            ; 118132       ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 677263       ; 0            ; 118132       ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1            ; 0            ; 0            ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 129          ; 0            ; 0            ; 0            ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path   ; 0            ; false path   ; 0            ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path   ; false path   ; 0            ; 0            ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 67           ; 67           ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; > 2147483647 ; 816861784    ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; > 2147483647 ; 816861784    ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 158084       ; 0            ; 120          ; 2            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 158084       ; 0            ; 120          ; 2            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 59892        ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 59892        ; 0            ; 0            ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 11           ; 0            ; 0            ; 0            ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path   ; 0            ; false path   ; 0            ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path   ; false path   ; 0            ; 0            ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 67           ; 67           ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; > 2147483647 ; 816861784    ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; > 2147483647 ; 816861784    ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 158084       ; 0            ; 120          ; 2            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 158084       ; 0            ; 120          ; 2            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 59892        ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 59892        ; 0            ; 0            ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 11           ; 0            ; 0            ; 0            ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; false path   ; 0            ; 0            ; 0            ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; false path   ; false path   ; 0            ; 0            ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 1            ; 1            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; > 2147483647 ; > 2147483647 ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; > 2147483647 ; > 2147483647 ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 5711         ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 5711         ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 2204531      ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 2204531      ; 0            ; 0            ; 0            ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; false path   ; 0            ; 0            ; 0            ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; false path   ; false path   ; 0            ; 0            ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 1            ; 1            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; > 2147483647 ; > 2147483647 ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; > 2147483647 ; > 2147483647 ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 5711         ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 5711         ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 2204531      ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 2204531      ; 0            ; 0            ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 3            ; 0            ; 0            ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 10           ; 0            ; 0            ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 18           ; 0            ; 0            ; 0            ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+--------------+--------------+--------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                      ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+--------------+--------------+--------------+
; From Clock                                                 ; To Clock                                                   ; RR Paths     ; FR Paths     ; RF Paths     ; FF Paths     ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+--------------+--------------+--------------+
; CLK_PLL1                                                   ; CLK_PLL1                                                   ; 51           ; 0            ; 0            ; 0            ;
; CLK_PLL1                                                   ; CODEC_SCLK                                                 ; false path   ; 0            ; false path   ; 0            ;
; CODEC_SCLK                                                 ; CODEC_SCLK                                                 ; 102503       ; 9122         ; 76           ; 469          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; CODEC_SCLK                                                 ; false path   ; 0            ; false path   ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; CODEC_SCLK                                                 ; false path   ; 0            ; false path   ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; CODEC_SCLK                                                 ; false path   ; 0            ; false path   ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; CODEC_SCLK                                                 ; false path   ; 0            ; false path   ; 0            ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path   ; 0            ; false path   ; 0            ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path   ; false path   ; false path   ; false path   ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 126          ; 126          ; 17           ; 17           ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; > 2147483647 ; > 2147483647 ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; > 2147483647 ; > 2147483647 ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 521938       ; 0            ; 89917        ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 521938       ; 0            ; 89917        ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 677263       ; 0            ; 118132       ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 677263       ; 0            ; 118132       ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1            ; 0            ; 0            ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 129          ; 0            ; 0            ; 0            ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path   ; 0            ; false path   ; 0            ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path   ; false path   ; false path   ; false path   ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 126          ; 126          ; 17           ; 17           ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; > 2147483647 ; > 2147483647 ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; > 2147483647 ; > 2147483647 ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 521938       ; 0            ; 89917        ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 521938       ; 0            ; 89917        ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 677263       ; 0            ; 118132       ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 677263       ; 0            ; 118132       ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1            ; 0            ; 0            ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 129          ; 0            ; 0            ; 0            ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path   ; 0            ; false path   ; 0            ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path   ; false path   ; 0            ; 0            ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 67           ; 67           ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; > 2147483647 ; 816861784    ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; > 2147483647 ; 816861784    ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 158084       ; 0            ; 120          ; 2            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 158084       ; 0            ; 120          ; 2            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 59892        ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 59892        ; 0            ; 0            ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 11           ; 0            ; 0            ; 0            ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path   ; 0            ; false path   ; 0            ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path   ; false path   ; 0            ; 0            ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 67           ; 67           ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; > 2147483647 ; 816861784    ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; > 2147483647 ; 816861784    ; > 2147483647 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 158084       ; 0            ; 120          ; 2            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 158084       ; 0            ; 120          ; 2            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 59892        ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 59892        ; 0            ; 0            ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 11           ; 0            ; 0            ; 0            ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; false path   ; 0            ; 0            ; 0            ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; false path   ; false path   ; 0            ; 0            ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 1            ; 1            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; > 2147483647 ; > 2147483647 ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; > 2147483647 ; > 2147483647 ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 5711         ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 5711         ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 2204531      ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 2204531      ; 0            ; 0            ; 0            ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; false path   ; 0            ; 0            ; 0            ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; false path   ; false path   ; 0            ; 0            ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 1            ; 1            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; > 2147483647 ; > 2147483647 ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; > 2147483647 ; > 2147483647 ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 5711         ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 5711         ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 2204531      ; 0            ; 0            ; 0            ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 2204531      ; 0            ; 0            ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 3            ; 0            ; 0            ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 10           ; 0            ; 0            ; 0            ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 18           ; 0            ; 0            ; 0            ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+--------------+--------------+--------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                      ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                 ; To Clock                                                   ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; CLK_PLL1                                                   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; CODEC_SCLK                                                 ; CODEC_SCLK                                                 ; 0          ; 0        ; 0          ; 1        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 18781      ; 0        ; 790        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 18781      ; 0        ; 790        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 23352      ; 0        ; 816        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 23352      ; 0        ; 816        ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 18781      ; 0        ; 790        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 18781      ; 0        ; 790        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 23352      ; 0        ; 816        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 23352      ; 0        ; 816        ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 9192       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 9192       ; 0        ; 0          ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 9192       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 9192       ; 0        ; 0          ; 0        ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                       ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                 ; To Clock                                                   ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; CLK_PLL1                                                   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; CODEC_SCLK                                                 ; CODEC_SCLK                                                 ; 0          ; 0        ; 0          ; 1        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 18781      ; 0        ; 790        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 18781      ; 0        ; 790        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 23352      ; 0        ; 816        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 23352      ; 0        ; 816        ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 18781      ; 0        ; 790        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 18781      ; 0        ; 790        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 23352      ; 0        ; 816        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 23352      ; 0        ; 816        ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 9192       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 9192       ; 0        ; 0          ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 9192       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 9192       ; 0        ; 0          ; 0        ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+-------------------------------------------------+
; Unconstrained Paths                             ;
+---------------------------------+-------+-------+
; Property                        ; Setup ; Hold  ;
+---------------------------------+-------+-------+
; Illegal Clocks                  ; 0     ; 0     ;
; Unconstrained Clocks            ; 0     ; 0     ;
; Unconstrained Input Ports       ; 134   ; 134   ;
; Unconstrained Input Port Paths  ; 28155 ; 28155 ;
; Unconstrained Output Ports      ; 231   ; 231   ;
; Unconstrained Output Port Paths ; 83901 ; 83901 ;
+---------------------------------+-------+-------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
    Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
    Info: Processing started: Thu Dec 09 15:57:47 2021
Info: Command: quartus_sta SUSKA-III-C -c SUSKA-III-C
Info: qsta_default_script.tcl version: #1
Warning: Parallel compilation is not licensed and has been disabled
Info: Reading SDC File: '../../../rtl/vhdl/SUSKA-III-C/suska_cycloneII_core_ste.sdc'
Info: Deriving PLL Clocks
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[1]} -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1} {I_SYSCLOCKS|altpll_component|pll|clk[0]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[0]} -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0} {I_SYSCLOCKS|altpll_component|pll|clk[0]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[1]} -multiply_by 2 -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1} {I_SYSCLOCKS|altpll_component|pll|clk[1]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1} {I_SYSCLOCKS|altpll_component|pll|clk[1]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[1]} -multiply_by 3 -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1} {I_SYSCLOCKS|altpll_component|pll|clk[2]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2} {I_SYSCLOCKS|altpll_component|pll|clk[2]}
    Info: create_generated_clock -source {I_AUXCLOCKS|altpll_component|pll|inclk[0]} -divide_by 5 -multiply_by 8 -duty_cycle 50.00 -name {cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0} {I_AUXCLOCKS|altpll_component|pll|clk[0]}
    Info: create_generated_clock -source {I_AUXCLOCKS|altpll_component|pll|inclk[0]} -divide_by 13 -multiply_by 32 -duty_cycle 50.00 -name {cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1} {I_AUXCLOCKS|altpll_component|pll|clk[1]}
    Info: create_generated_clock -source {I_AUXCLOCKS|altpll_component|pll|inclk[0]} -duty_cycle 50.00 -name {cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2} {I_AUXCLOCKS|altpll_component|pll|clk[2]}
Info: Analyzing Slow Model
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -36.638
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:   -36.638     -1643.620 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:   -36.638     -1643.620 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:   -21.205     -4262.856 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:   -21.205     -4262.856 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:   -19.476    -32535.297 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:   -19.476    -32535.297 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    23.160         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    27.313         0.000 CODEC_SCLK 
    Info:    38.199         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    59.666         0.000 CLK_PLL1 
    Info:    60.589         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
Info: Worst-case hold slack is -0.086
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    -0.086        -0.248 CODEC_SCLK 
    Info:     0.224         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     0.224         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:     0.445         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:     0.445         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.445         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:     0.629         0.000 CLK_PLL1 
Info: Worst-case recovery slack is 22.437
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    22.437         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    22.437         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    22.439         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    22.439         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    78.982         0.000 CODEC_SCLK 
Info: Worst-case removal slack is 2.128
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     2.128         0.000 CODEC_SCLK 
    Info:     2.403         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     2.403         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     3.362         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     3.362         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
Info: Worst-case minimum pulse width slack is 7.852
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     7.852         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:     7.852         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:    11.584         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.061         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.061         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    18.420         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    30.139         0.000 CLK_PLL1 
    Info:    30.139         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    30.139         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    30.139         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:    31.250         0.000 CLK_PLL2 
    Info:    31.250         0.000 CRT_PIN4_CLK1 
    Info:    38.136         0.000 CODEC_SCLK 
Info: The selected device family is not supported by the report_metastability command.
Info: Analyzing Fast Model
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -7.016
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    -7.016      -270.683 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:    -7.016      -270.683 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:     0.800         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     0.800         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:     1.373         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     1.373         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    24.565         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    35.364         0.000 CODEC_SCLK 
    Info:    38.703         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    61.345         0.000 CLK_PLL1 
    Info:    61.755         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
Info: Worst-case hold slack is -0.065
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    -0.065        -0.065 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    -0.065        -0.065 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    -0.046        -0.133 CODEC_SCLK 
    Info:     0.215         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.215         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     0.215         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:     0.215         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:     0.215         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:     0.215         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.215         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:     0.245         0.000 CLK_PLL1 
Info: Worst-case recovery slack is 27.346
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    27.346         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    27.346         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    27.347         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    27.347         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    80.246         0.000 CODEC_SCLK 
Info: Worst-case removal slack is 1.015
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     1.015         0.000 CODEC_SCLK 
    Info:     1.054         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     1.054         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     1.433         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     1.433         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
Info: Worst-case minimum pulse width slack is 8.289
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     8.289         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:     8.289         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:    11.695         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.498         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.498         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    18.531         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    30.250         0.000 CLK_PLL1 
    Info:    30.250         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    30.250         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    30.250         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:    31.250         0.000 CLK_PLL2 
    Info:    31.250         0.000 CRT_PIN4_CLK1 
    Info:    38.573         0.000 CODEC_SCLK 
Info: The selected device family is not supported by the report_metastability command.
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 667 megabytes
    Info: Processing ended: Thu Dec 09 15:58:29 2021
    Info: Elapsed time: 00:00:42
    Info: Total CPU time (on all processors): 00:00:42


