TimeQuest Timing Analyzer report for SUSKA-III-C
Thu Dec 09 15:46:14 2021
Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow Model Fmax Summary
  7. Slow Model Setup Summary
  8. Slow Model Hold Summary
  9. Slow Model Recovery Summary
 10. Slow Model Removal Summary
 11. Slow Model Minimum Pulse Width Summary
 12. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 13. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 14. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 15. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 16. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
 17. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
 18. Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 19. Slow Model Setup: 'CODEC_SCLK'
 20. Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 21. Slow Model Setup: 'CLK_PLL1'
 22. Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 23. Slow Model Hold: 'CODEC_SCLK'
 24. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 25. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 26. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 27. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 28. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
 29. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
 30. Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 31. Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 32. Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 33. Slow Model Hold: 'CLK_PLL1'
 34. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 35. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 36. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 37. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 38. Slow Model Recovery: 'CODEC_SCLK'
 39. Slow Model Removal: 'CODEC_SCLK'
 40. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 41. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 42. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 43. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 44. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
 45. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
 46. Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 47. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 48. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 49. Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 50. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 51. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 52. Slow Model Minimum Pulse Width: 'CLK_PLL1'
 53. Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 54. Slow Model Minimum Pulse Width: 'CLK_PLL2'
 55. Slow Model Minimum Pulse Width: 'CRT_PIN4_CLK1'
 56. Slow Model Minimum Pulse Width: 'CODEC_SCLK'
 57. Setup Times
 58. Hold Times
 59. Clock to Output Times
 60. Minimum Clock to Output Times
 61. Propagation Delay
 62. Minimum Propagation Delay
 63. Output Enable Times
 64. Minimum Output Enable Times
 65. Output Disable Times
 66. Minimum Output Disable Times
 67. Fast Model Setup Summary
 68. Fast Model Hold Summary
 69. Fast Model Recovery Summary
 70. Fast Model Removal Summary
 71. Fast Model Minimum Pulse Width Summary
 72. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 73. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 74. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 75. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 76. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
 77. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
 78. Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 79. Fast Model Setup: 'CODEC_SCLK'
 80. Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 81. Fast Model Setup: 'CLK_PLL1'
 82. Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 83. Fast Model Hold: 'CODEC_SCLK'
 84. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 85. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 86. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 87. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 88. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
 89. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
 90. Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 91. Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 92. Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 93. Fast Model Hold: 'CLK_PLL1'
 94. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 95. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 96. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 97. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 98. Fast Model Recovery: 'CODEC_SCLK'
 99. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
100. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
101. Fast Model Removal: 'CODEC_SCLK'
102. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
103. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
104. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
105. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
106. Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
107. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
108. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
109. Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
110. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
111. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
112. Fast Model Minimum Pulse Width: 'CLK_PLL1'
113. Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
114. Fast Model Minimum Pulse Width: 'CLK_PLL2'
115. Fast Model Minimum Pulse Width: 'CRT_PIN4_CLK1'
116. Fast Model Minimum Pulse Width: 'CODEC_SCLK'
117. Setup Times
118. Hold Times
119. Clock to Output Times
120. Minimum Clock to Output Times
121. Propagation Delay
122. Minimum Propagation Delay
123. Output Enable Times
124. Minimum Output Enable Times
125. Output Disable Times
126. Minimum Output Disable Times
127. Multicorner Timing Analysis Summary
128. Setup Times
129. Hold Times
130. Clock to Output Times
131. Minimum Clock to Output Times
132. Progagation Delay
133. Minimum Progagation Delay
134. Setup Transfers
135. Hold Transfers
136. Recovery Transfers
137. Removal Transfers
138. Report TCCS
139. Report RSKM
140. Unconstrained Paths
141. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
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(including device programming or simulation files), and any 
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without limitation, that your use is for the sole purpose of 
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Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                    ;
+--------------------+-----------------------------------------------------------------+
; Quartus II Version ; Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition ;
; Revision Name      ; SUSKA-III-C                                                     ;
; Device Family      ; Cyclone II                                                      ;
; Device Name        ; EP2C35F484C7                                                    ;
; Timing Models      ; Final                                                           ;
; Delay Model        ; Combined                                                        ;
; Rise/Fall Delays   ; Unavailable                                                     ;
+--------------------+-----------------------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+------------------------------------------------------------------------------------------------+
; SDC File List                                                                                  ;
+------------------------------------------------------------+--------+--------------------------+
; SDC File Path                                              ; Status ; Read at                  ;
+------------------------------------------------------------+--------+--------------------------+
; ../../../rtl/vhdl/SUSKA-III-C/suska_cycloneII_core_ste.sdc ; OK     ; Thu Dec 09 15:45:49 2021 ;
+------------------------------------------------------------+--------+--------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                             ;
+------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------+-------------------------------------------+---------------------------------------------+
; Clock Name                                                 ; Type      ; Period ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master        ; Source                                    ; Targets                                     ;
+------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------+-------------------------------------------+---------------------------------------------+
; CLK_PLL1                                                   ; Base      ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { CLK_PLL1 }                                ;
; CLK_PLL2                                                   ; Base      ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { CLK_PLL2 }                                ;
; CODEC_SCLK                                                 ; Base      ; 81.400 ; 12.29 MHz ; 0.000 ; 40.700 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { CODEC_SCLK }                              ;
; CRT_PIN4_CLK1                                              ; Base      ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { CRT_PIN4_CLK1 }                           ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; Generated ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CLK_PLL1      ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ; { I_SYSCLOCKS|altpll_component|pll|clk[0] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Generated ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CRT_PIN4_CLK1 ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ; { I_SYSCLOCKS|altpll_component|pll|clk[0] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; Generated ; 31.250 ; 32.0 MHz  ; 0.000 ; 15.625 ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; CLK_PLL1      ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ; { I_SYSCLOCKS|altpll_component|pll|clk[1] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Generated ; 31.250 ; 32.0 MHz  ; 0.000 ; 15.625 ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; CRT_PIN4_CLK1 ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ; { I_SYSCLOCKS|altpll_component|pll|clk[1] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; Generated ; 20.833 ; 48.0 MHz  ; 0.000 ; 10.416 ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; CLK_PLL1      ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ; { I_SYSCLOCKS|altpll_component|pll|clk[2] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Generated ; 20.833 ; 48.0 MHz  ; 0.000 ; 10.416 ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; CRT_PIN4_CLK1 ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ; { I_SYSCLOCKS|altpll_component|pll|clk[2] } ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; Generated ; 39.062 ; 25.6 MHz  ; 0.000 ; 19.531 ; 50.00      ; 5         ; 8           ;       ;        ;           ;            ; false    ; CLK_PLL2      ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ; { I_AUXCLOCKS|altpll_component|pll|clk[0] } ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; Generated ; 25.390 ; 39.39 MHz ; 0.000 ; 12.695 ; 50.00      ; 13        ; 32          ;       ;        ;           ;            ; false    ; CLK_PLL2      ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ; { I_AUXCLOCKS|altpll_component|pll|clk[1] } ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; Generated ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CLK_PLL2      ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ; { I_AUXCLOCKS|altpll_component|pll|clk[2] } ;
+------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------+-------------------------------------------+---------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Fmax Summary                                                                                                                            ;
+-------------+-----------------+------------------------------------------------------------+-------------------------------------------------------+
; Fmax        ; Restricted Fmax ; Clock Name                                                 ; Note                                                  ;
+-------------+-----------------+------------------------------------------------------------+-------------------------------------------------------+
; 14.96 MHz   ; 14.96 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;                                                       ;
; 14.96 MHz   ; 14.96 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;                                                       ;
; 41.08 MHz   ; 41.08 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;                                                       ;
; 41.08 MHz   ; 41.08 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;                                                       ;
; 48.16 MHz   ; 48.16 MHz       ; CODEC_SCLK                                                 ;                                                       ;
; 60.79 MHz   ; 60.79 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;                                                       ;
; 60.79 MHz   ; 60.79 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;                                                       ;
; 360.23 MHz  ; 360.23 MHz      ; CLK_PLL1                                                   ;                                                       ;
; 405.19 MHz  ; 405.19 MHz      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ;                                                       ;
; 470.81 MHz  ; 450.05 MHz      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; limit due to high minimum pulse width violation (tch) ;
; 1164.14 MHz ; 450.05 MHz      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; limit due to high minimum pulse width violation (tch) ;
+-------------+-----------------+------------------------------------------------------------+-------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------+
; Slow Model Setup Summary                                                             ;
+------------------------------------------------------------+---------+---------------+
; Clock                                                      ; Slack   ; End Point TNS ;
+------------------------------------------------------------+---------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -15.012 ; -5654.283     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -15.012 ; -5654.283     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; -14.850 ; -1984.888     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; -14.850 ; -1984.888     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; -12.179 ; -347.707      ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; -12.179 ; -347.707      ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 22.922  ; 0.000         ;
; CODEC_SCLK                                                 ; 30.318  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 38.203  ; 0.000         ;
; CLK_PLL1                                                   ; 59.724  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 60.376  ; 0.000         ;
+------------------------------------------------------------+---------+---------------+


+------------------------------------------------------------------------------------+
; Slow Model Hold Summary                                                            ;
+------------------------------------------------------------+-------+---------------+
; Clock                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------+-------+---------------+
; CODEC_SCLK                                                 ; 0.228 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 0.445 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.445 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 0.445 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.445 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 0.445 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.445 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 0.445 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 0.445 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 0.445 ; 0.000         ;
; CLK_PLL1                                                   ; 0.615 ; 0.000         ;
+------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------+
; Slow Model Recovery Summary                                                         ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 20.664 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 20.664 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 20.664 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 20.664 ; 0.000         ;
; CODEC_SCLK                                                 ; 78.914 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------+
; Slow Model Removal Summary                                                         ;
+------------------------------------------------------------+-------+---------------+
; Clock                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------+-------+---------------+
; CODEC_SCLK                                                 ; 2.196 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 2.424 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 2.424 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 2.574 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 2.574 ; 0.000         ;
+------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width Summary                                              ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 7.852  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 7.852  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 11.584 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 13.061 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 13.061 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 18.420 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 28.943 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 28.943 ; 0.000         ;
; CLK_PLL1                                                   ; 30.139 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 30.139 ; 0.000         ;
; CLK_PLL2                                                   ; 31.250 ; 0.000         ;
; CRT_PIN4_CLK1                                              ; 31.250 ; 0.000         ;
; CODEC_SCLK                                                 ; 38.136 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                    ;
+---------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                         ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -15.012 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.029      ; 25.496     ;
; -15.012 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.029      ; 25.496     ;
; -15.009 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.029      ; 25.493     ;
; -15.009 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.029      ; 25.493     ;
; -14.873 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.362     ;
; -14.873 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.362     ;
; -14.870 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.359     ;
; -14.870 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.359     ;
; -14.803 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.003     ; 25.255     ;
; -14.803 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.003     ; 25.255     ;
; -14.796 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.021      ; 25.272     ;
; -14.796 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.021      ; 25.272     ;
; -14.781 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.270     ;
; -14.781 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.270     ;
; -14.778 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.267     ;
; -14.778 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.267     ;
; -14.769 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.002      ; 25.226     ;
; -14.769 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.002      ; 25.226     ;
; -14.707 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.013      ; 25.175     ;
; -14.707 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.013      ; 25.175     ;
; -14.677 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.002      ; 25.134     ;
; -14.677 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.002      ; 25.134     ;
; -14.673 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.018      ; 25.146     ;
; -14.673 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.018      ; 25.146     ;
; -14.671 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.010     ; 25.116     ;
; -14.671 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.010     ; 25.116     ;
; -14.663 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.024     ; 25.094     ;
; -14.663 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.024     ; 25.094     ;
; -14.657 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 25.138     ;
; -14.657 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 25.138     ;
; -14.637 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.005     ; 25.087     ;
; -14.637 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.005     ; 25.087     ;
; -14.632 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.121     ;
; -14.632 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.121     ;
; -14.629 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.118     ;
; -14.629 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.118     ;
; -14.620 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.009     ; 25.066     ;
; -14.620 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.009     ; 25.066     ;
; -14.596 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 25.059     ;
; -14.596 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 25.059     ;
; -14.593 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 25.056     ;
; -14.593 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 25.056     ;
; -14.581 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.018      ; 25.054     ;
; -14.581 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.018      ; 25.054     ;
; -14.580 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.069     ;
; -14.580 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.069     ;
; -14.577 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.066     ;
; -14.577 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 25.066     ;
; -14.567 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 25.014     ;
; -14.567 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 25.014     ;
; -14.565 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 25.046     ;
; -14.565 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 25.046     ;
; -14.545 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.005     ; 24.995     ;
; -14.545 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.005     ; 24.995     ;
; -14.531 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.031     ; 24.955     ;
; -14.531 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.031     ; 24.955     ;
; -14.528 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.002      ; 24.985     ;
; -14.528 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.002      ; 24.985     ;
; -14.486 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 24.947     ;
; -14.486 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 24.947     ;
; -14.481 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.004     ; 24.932     ;
; -14.481 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.004     ; 24.932     ;
; -14.476 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 24.965     ;
; -14.476 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.002      ; 24.933     ;
; -14.476 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 24.965     ;
; -14.476 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.002      ; 24.933     ;
; -14.473 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 24.962     ;
; -14.473 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.034      ; 24.962     ;
; -14.472 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 24.933     ;
; -14.472 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 24.933     ;
; -14.471 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 24.932     ;
; -14.471 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 24.932     ;
; -14.457 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.013      ; 24.925     ;
; -14.457 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.013      ; 24.925     ;
; -14.452 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 24.918     ;
; -14.452 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 24.918     ;
; -14.438 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 24.904     ;
; -14.438 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 24.904     ;
; -14.437 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 24.903     ;
; -14.437 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 24.903     ;
; -14.432 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.018      ; 24.905     ;
; -14.432 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.018      ; 24.905     ;
; -14.423 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.018      ; 24.896     ;
; -14.423 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.018      ; 24.896     ;
; -14.416 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 24.897     ;
; -14.416 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 24.897     ;
; -14.396 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.005     ; 24.846     ;
; -14.396 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.005     ; 24.846     ;
; -14.395 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.021      ; 24.871     ;
; -14.395 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.021      ; 24.871     ;
; -14.391 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 24.852     ;
; -14.391 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 24.852     ;
; -14.389 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.004     ; 24.840     ;
; -14.389 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.004     ; 24.840     ;
; -14.380 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.018      ; 24.853     ;
; -14.380 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.000      ; 24.835     ;
; -14.380 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.018      ; 24.853     ;
; -14.380 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.000      ; 24.835     ;
; -14.372 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.002      ; 24.829     ;
; -14.372 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.002      ; 24.829     ;
+---------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                    ;
+---------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                         ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -15.012 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.029      ; 25.496     ;
; -15.012 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.029      ; 25.496     ;
; -15.009 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.029      ; 25.493     ;
; -15.009 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.029      ; 25.493     ;
; -14.873 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.362     ;
; -14.873 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.362     ;
; -14.870 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.359     ;
; -14.870 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.359     ;
; -14.803 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.003     ; 25.255     ;
; -14.803 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.003     ; 25.255     ;
; -14.796 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.021      ; 25.272     ;
; -14.796 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.021      ; 25.272     ;
; -14.781 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.270     ;
; -14.781 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.270     ;
; -14.778 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.267     ;
; -14.778 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.267     ;
; -14.769 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.002      ; 25.226     ;
; -14.769 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.002      ; 25.226     ;
; -14.707 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.013      ; 25.175     ;
; -14.707 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.013      ; 25.175     ;
; -14.677 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.002      ; 25.134     ;
; -14.677 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.002      ; 25.134     ;
; -14.673 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.018      ; 25.146     ;
; -14.673 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.018      ; 25.146     ;
; -14.671 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.010     ; 25.116     ;
; -14.671 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.010     ; 25.116     ;
; -14.663 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.024     ; 25.094     ;
; -14.663 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.024     ; 25.094     ;
; -14.657 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 25.138     ;
; -14.657 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 25.138     ;
; -14.637 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.005     ; 25.087     ;
; -14.637 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.005     ; 25.087     ;
; -14.632 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.121     ;
; -14.632 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.121     ;
; -14.629 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.118     ;
; -14.629 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.118     ;
; -14.620 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.009     ; 25.066     ;
; -14.620 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.009     ; 25.066     ;
; -14.596 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 25.059     ;
; -14.596 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 25.059     ;
; -14.593 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 25.056     ;
; -14.593 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 25.056     ;
; -14.581 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.018      ; 25.054     ;
; -14.581 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.018      ; 25.054     ;
; -14.580 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.069     ;
; -14.580 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.069     ;
; -14.577 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.066     ;
; -14.577 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 25.066     ;
; -14.567 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 25.014     ;
; -14.567 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 25.014     ;
; -14.565 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 25.046     ;
; -14.565 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 25.046     ;
; -14.545 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.005     ; 24.995     ;
; -14.545 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.005     ; 24.995     ;
; -14.531 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.031     ; 24.955     ;
; -14.531 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.031     ; 24.955     ;
; -14.528 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.002      ; 24.985     ;
; -14.528 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.002      ; 24.985     ;
; -14.486 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 24.947     ;
; -14.486 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 24.947     ;
; -14.481 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.004     ; 24.932     ;
; -14.481 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.004     ; 24.932     ;
; -14.476 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 24.965     ;
; -14.476 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.002      ; 24.933     ;
; -14.476 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 24.965     ;
; -14.476 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.002      ; 24.933     ;
; -14.473 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 24.962     ;
; -14.473 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.034      ; 24.962     ;
; -14.472 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 24.933     ;
; -14.472 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 24.933     ;
; -14.471 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 24.932     ;
; -14.471 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 24.932     ;
; -14.457 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.013      ; 24.925     ;
; -14.457 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.013      ; 24.925     ;
; -14.452 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 24.918     ;
; -14.452 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 24.918     ;
; -14.438 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 24.904     ;
; -14.438 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 24.904     ;
; -14.437 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 24.903     ;
; -14.437 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 24.903     ;
; -14.432 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.018      ; 24.905     ;
; -14.432 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.018      ; 24.905     ;
; -14.423 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.018      ; 24.896     ;
; -14.423 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.018      ; 24.896     ;
; -14.416 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 24.897     ;
; -14.416 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 24.897     ;
; -14.396 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.005     ; 24.846     ;
; -14.396 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.005     ; 24.846     ;
; -14.395 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.021      ; 24.871     ;
; -14.395 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.021      ; 24.871     ;
; -14.391 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 24.852     ;
; -14.391 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 24.852     ;
; -14.389 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.004     ; 24.840     ;
; -14.389 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.004     ; 24.840     ;
; -14.380 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.018      ; 24.853     ;
; -14.380 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.000      ; 24.835     ;
; -14.380 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.018      ; 24.853     ;
; -14.380 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.000      ; 24.835     ;
; -14.372 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.002      ; 24.829     ;
; -14.372 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.002      ; 24.829     ;
+---------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                            ;
+---------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                         ; To Node                                                                                  ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -14.850 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.034      ; 25.339     ;
; -14.850 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.034      ; 25.339     ;
; -14.847 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.034      ; 25.336     ;
; -14.847 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.034      ; 25.336     ;
; -14.804 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.033      ; 25.292     ;
; -14.804 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.033      ; 25.292     ;
; -14.711 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 25.205     ;
; -14.711 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 25.205     ;
; -14.708 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 25.202     ;
; -14.708 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 25.202     ;
; -14.665 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 25.158     ;
; -14.665 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 25.158     ;
; -14.654 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.035      ; 25.144     ;
; -14.654 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.035      ; 25.144     ;
; -14.619 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 25.113     ;
; -14.619 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 25.113     ;
; -14.616 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.027      ; 25.098     ;
; -14.616 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 25.110     ;
; -14.616 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.027      ; 25.098     ;
; -14.616 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 25.110     ;
; -14.573 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 25.066     ;
; -14.573 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 25.066     ;
; -14.528 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.033      ; 25.016     ;
; -14.528 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.033      ; 25.016     ;
; -14.516 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.007      ; 24.978     ;
; -14.516 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.007      ; 24.978     ;
; -14.515 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.040      ; 25.010     ;
; -14.515 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.040      ; 25.010     ;
; -14.512 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.033      ; 25.000     ;
; -14.512 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.033      ; 25.000     ;
; -14.512 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.033      ; 25.000     ;
; -14.512 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.033      ; 25.000     ;
; -14.498 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.034      ; 24.987     ;
; -14.498 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.034      ; 24.987     ;
; -14.482 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 24.949     ;
; -14.482 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 24.949     ;
; -14.477 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.032      ; 24.964     ;
; -14.477 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.032      ; 24.964     ;
; -14.470 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.964     ;
; -14.470 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.964     ;
; -14.467 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.961     ;
; -14.467 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.961     ;
; -14.459 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.034      ; 24.948     ;
; -14.459 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.034      ; 24.948     ;
; -14.458 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.034      ; 24.947     ;
; -14.458 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.034      ; 24.947     ;
; -14.440 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 24.926     ;
; -14.440 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 24.926     ;
; -14.439 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 24.925     ;
; -14.439 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 24.925     ;
; -14.437 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[17]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 24.922     ;
; -14.437 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[17]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 24.922     ;
; -14.434 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.013      ; 24.902     ;
; -14.434 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.013      ; 24.902     ;
; -14.431 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.013      ; 24.899     ;
; -14.431 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.013      ; 24.899     ;
; -14.425 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.919     ;
; -14.425 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.919     ;
; -14.424 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 24.917     ;
; -14.424 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.918     ;
; -14.424 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 24.917     ;
; -14.424 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.918     ;
; -14.423 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.040      ; 24.918     ;
; -14.423 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.040      ; 24.918     ;
; -14.419 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.032      ; 24.906     ;
; -14.419 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.029      ; 24.903     ;
; -14.419 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.032      ; 24.906     ;
; -14.419 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.029      ; 24.903     ;
; -14.418 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.912     ;
; -14.418 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.912     ;
; -14.415 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.909     ;
; -14.415 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.909     ;
; -14.390 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 24.857     ;
; -14.390 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 24.857     ;
; -14.389 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 24.882     ;
; -14.389 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 24.882     ;
; -14.388 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 24.855     ;
; -14.388 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 24.855     ;
; -14.385 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.032      ; 24.872     ;
; -14.385 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.032      ; 24.872     ;
; -14.382 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.033      ; 24.870     ;
; -14.382 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.034      ; 24.871     ;
; -14.382 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.033      ; 24.870     ;
; -14.382 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.034      ; 24.871     ;
; -14.379 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.033      ; 24.867     ;
; -14.379 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.033      ; 24.867     ;
; -14.376 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.014     ; 24.817     ;
; -14.376 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.014     ; 24.817     ;
; -14.373 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 24.866     ;
; -14.373 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 24.866     ;
; -14.373 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 24.866     ;
; -14.373 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 24.866     ;
; -14.372 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 24.865     ;
; -14.372 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 24.865     ;
; -14.359 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.853     ;
; -14.359 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.853     ;
; -14.348 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 24.841     ;
; -14.348 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.842     ;
; -14.348 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.038      ; 24.841     ;
; -14.348 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.039      ; 24.842     ;
+---------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                            ;
+---------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                         ; To Node                                                                                  ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -14.850 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.034      ; 25.339     ;
; -14.850 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.034      ; 25.339     ;
; -14.847 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.034      ; 25.336     ;
; -14.847 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.034      ; 25.336     ;
; -14.804 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.033      ; 25.292     ;
; -14.804 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.033      ; 25.292     ;
; -14.711 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 25.205     ;
; -14.711 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 25.205     ;
; -14.708 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 25.202     ;
; -14.708 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 25.202     ;
; -14.665 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 25.158     ;
; -14.665 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 25.158     ;
; -14.654 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.035      ; 25.144     ;
; -14.654 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.035      ; 25.144     ;
; -14.619 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 25.113     ;
; -14.619 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 25.113     ;
; -14.616 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.027      ; 25.098     ;
; -14.616 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 25.110     ;
; -14.616 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.027      ; 25.098     ;
; -14.616 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 25.110     ;
; -14.573 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 25.066     ;
; -14.573 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 25.066     ;
; -14.528 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.033      ; 25.016     ;
; -14.528 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.033      ; 25.016     ;
; -14.516 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.007      ; 24.978     ;
; -14.516 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.007      ; 24.978     ;
; -14.515 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.040      ; 25.010     ;
; -14.515 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.040      ; 25.010     ;
; -14.512 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.033      ; 25.000     ;
; -14.512 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.033      ; 25.000     ;
; -14.512 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.033      ; 25.000     ;
; -14.512 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.033      ; 25.000     ;
; -14.498 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.034      ; 24.987     ;
; -14.498 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.034      ; 24.987     ;
; -14.482 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 24.949     ;
; -14.482 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 24.949     ;
; -14.477 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.032      ; 24.964     ;
; -14.477 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.032      ; 24.964     ;
; -14.470 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.964     ;
; -14.470 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.964     ;
; -14.467 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.961     ;
; -14.467 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.961     ;
; -14.459 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.034      ; 24.948     ;
; -14.459 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.034      ; 24.948     ;
; -14.458 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.034      ; 24.947     ;
; -14.458 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.034      ; 24.947     ;
; -14.440 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 24.926     ;
; -14.440 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 24.926     ;
; -14.439 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 24.925     ;
; -14.439 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 24.925     ;
; -14.437 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[17]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 24.922     ;
; -14.437 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[17]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 24.922     ;
; -14.434 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.013      ; 24.902     ;
; -14.434 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.013      ; 24.902     ;
; -14.431 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.013      ; 24.899     ;
; -14.431 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.013      ; 24.899     ;
; -14.425 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.919     ;
; -14.425 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.919     ;
; -14.424 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 24.917     ;
; -14.424 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.918     ;
; -14.424 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 24.917     ;
; -14.424 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.918     ;
; -14.423 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.040      ; 24.918     ;
; -14.423 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.040      ; 24.918     ;
; -14.419 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.032      ; 24.906     ;
; -14.419 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.029      ; 24.903     ;
; -14.419 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.032      ; 24.906     ;
; -14.419 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.029      ; 24.903     ;
; -14.418 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.912     ;
; -14.418 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.912     ;
; -14.415 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.909     ;
; -14.415 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.909     ;
; -14.390 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 24.857     ;
; -14.390 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 24.857     ;
; -14.389 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 24.882     ;
; -14.389 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 24.882     ;
; -14.388 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 24.855     ;
; -14.388 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 24.855     ;
; -14.385 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.032      ; 24.872     ;
; -14.385 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.032      ; 24.872     ;
; -14.382 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.033      ; 24.870     ;
; -14.382 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.034      ; 24.871     ;
; -14.382 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.033      ; 24.870     ;
; -14.382 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.034      ; 24.871     ;
; -14.379 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.033      ; 24.867     ;
; -14.379 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.033      ; 24.867     ;
; -14.376 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.014     ; 24.817     ;
; -14.376 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.014     ; 24.817     ;
; -14.373 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 24.866     ;
; -14.373 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 24.866     ;
; -14.373 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 24.866     ;
; -14.373 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 24.866     ;
; -14.372 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 24.865     ;
; -14.372 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 24.865     ;
; -14.359 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.853     ;
; -14.359 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.853     ;
; -14.348 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 24.841     ;
; -14.348 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.842     ;
; -14.348 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.038      ; 24.841     ;
; -14.348 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.039      ; 24.842     ;
+---------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                                                                                ;
+---------+------------------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                                    ; To Node                                           ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+---------+------------------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -12.179 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 33.034     ;
; -12.179 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 33.034     ;
; -12.147 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 33.002     ;
; -12.147 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 33.002     ;
; -12.106 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.961     ;
; -12.106 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.961     ;
; -11.985 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.840     ;
; -11.985 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.840     ;
; -11.907 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.762     ;
; -11.907 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.762     ;
; -11.829 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.684     ;
; -11.829 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.684     ;
; -11.725 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.601     ;
; -11.725 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.601     ;
; -11.698 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.553     ;
; -11.698 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.553     ;
; -11.693 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.569     ;
; -11.693 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.569     ;
; -11.652 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.528     ;
; -11.652 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.528     ;
; -11.627 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.482     ;
; -11.627 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.482     ;
; -11.621 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.471     ;
; -11.621 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.471     ;
; -11.604 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.459     ;
; -11.604 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.459     ;
; -11.589 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.439     ;
; -11.589 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.439     ;
; -11.548 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.398     ;
; -11.548 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.398     ;
; -11.531 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.407     ;
; -11.531 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.407     ;
; -11.499 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[26]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.018     ; 32.352     ;
; -11.499 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[26]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.018     ; 32.352     ;
; -11.496 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.351     ;
; -11.496 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.351     ;
; -11.453 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.329     ;
; -11.453 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.329     ;
; -11.427 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.277     ;
; -11.427 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.277     ;
; -11.417 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.272     ;
; -11.417 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.272     ;
; -11.385 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.235     ;
; -11.385 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.235     ;
; -11.375 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.251     ;
; -11.375 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.251     ;
; -11.353 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.203     ;
; -11.353 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.203     ;
; -11.349 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.199     ;
; -11.349 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.199     ;
; -11.312 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.162     ;
; -11.312 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.162     ;
; -11.271 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.121     ;
; -11.271 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.121     ;
; -11.269 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.119     ;
; -11.269 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.119     ;
; -11.266 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[21] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.009     ; 32.128     ;
; -11.266 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[21] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.009     ; 32.128     ;
; -11.253 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.108     ;
; -11.253 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.108     ;
; -11.244 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.120     ;
; -11.244 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.120     ;
; -11.237 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.087     ;
; -11.237 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.087     ;
; -11.208 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[25]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.018     ; 32.061     ;
; -11.208 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[25]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.018     ; 32.061     ;
; -11.198 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[14]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.053     ;
; -11.198 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[14]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 32.053     ;
; -11.196 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.046     ;
; -11.196 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.046     ;
; -11.191 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.041     ;
; -11.191 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.041     ;
; -11.180 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.030     ;
; -11.180 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 32.030     ;
; -11.173 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.049     ;
; -11.173 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.049     ;
; -11.150 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.026     ;
; -11.150 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; 0.005      ; 32.026     ;
; -11.148 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 31.998     ;
; -11.148 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 31.998     ;
; -11.147 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[20] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.009     ; 32.009     ;
; -11.147 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[20] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.009     ; 32.009     ;
; -11.145 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[17]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.018     ; 31.998     ;
; -11.145 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[17]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.018     ; 31.998     ;
; -11.140 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 31.990     ;
; -11.140 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 31.990     ;
; -11.119 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.010     ; 31.980     ;
; -11.119 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.010     ; 31.980     ;
; -11.113 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 31.963     ;
; -11.113 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 31.963     ;
; -11.107 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 31.957     ;
; -11.107 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 31.957     ;
; -11.087 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[15]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 31.942     ;
; -11.087 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.010     ; 31.948     ;
; -11.087 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[15]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.016     ; 31.942     ;
; -11.087 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.010     ; 31.948     ;
; -11.075 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 31.925     ;
; -11.075 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 31.925     ;
; -11.069 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 31.919     ;
; -11.069 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.021     ; 31.919     ;
+---------+------------------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                                                                                ;
+---------+------------------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                                    ; To Node                                           ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+------------------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -12.179 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 33.034     ;
; -12.179 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 33.034     ;
; -12.147 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 33.002     ;
; -12.147 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 33.002     ;
; -12.106 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.961     ;
; -12.106 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.961     ;
; -11.985 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.840     ;
; -11.985 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.840     ;
; -11.907 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.762     ;
; -11.907 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.762     ;
; -11.829 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.684     ;
; -11.829 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.684     ;
; -11.725 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.601     ;
; -11.725 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.601     ;
; -11.698 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.553     ;
; -11.698 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.553     ;
; -11.693 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.569     ;
; -11.693 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.569     ;
; -11.652 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.528     ;
; -11.652 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.528     ;
; -11.627 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.482     ;
; -11.627 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.482     ;
; -11.621 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.471     ;
; -11.621 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.471     ;
; -11.604 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.459     ;
; -11.604 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.459     ;
; -11.589 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.439     ;
; -11.589 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.439     ;
; -11.548 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.398     ;
; -11.548 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.398     ;
; -11.531 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.407     ;
; -11.531 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.407     ;
; -11.499 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[26]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.018     ; 32.352     ;
; -11.499 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[26]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.018     ; 32.352     ;
; -11.496 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.351     ;
; -11.496 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.351     ;
; -11.453 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.329     ;
; -11.453 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.329     ;
; -11.427 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.277     ;
; -11.427 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.277     ;
; -11.417 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.272     ;
; -11.417 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.272     ;
; -11.385 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.235     ;
; -11.385 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.235     ;
; -11.375 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.251     ;
; -11.375 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.251     ;
; -11.353 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.203     ;
; -11.353 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.203     ;
; -11.349 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.199     ;
; -11.349 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.199     ;
; -11.312 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.162     ;
; -11.312 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.162     ;
; -11.271 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.121     ;
; -11.271 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.121     ;
; -11.269 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.119     ;
; -11.269 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.119     ;
; -11.266 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[21] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.009     ; 32.128     ;
; -11.266 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[21] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.009     ; 32.128     ;
; -11.253 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.108     ;
; -11.253 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.108     ;
; -11.244 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.120     ;
; -11.244 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.120     ;
; -11.237 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.087     ;
; -11.237 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.087     ;
; -11.208 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[25]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.018     ; 32.061     ;
; -11.208 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[25]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.018     ; 32.061     ;
; -11.198 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[14]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.053     ;
; -11.198 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[14]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 32.053     ;
; -11.196 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.046     ;
; -11.196 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.046     ;
; -11.191 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.041     ;
; -11.191 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.041     ;
; -11.180 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.030     ;
; -11.180 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 32.030     ;
; -11.173 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.049     ;
; -11.173 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.049     ;
; -11.150 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.026     ;
; -11.150 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; 0.005      ; 32.026     ;
; -11.148 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 31.998     ;
; -11.148 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 31.998     ;
; -11.147 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[20] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.009     ; 32.009     ;
; -11.147 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[20] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.009     ; 32.009     ;
; -11.145 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[17]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.018     ; 31.998     ;
; -11.145 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[17]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.018     ; 31.998     ;
; -11.140 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 31.990     ;
; -11.140 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 31.990     ;
; -11.119 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.010     ; 31.980     ;
; -11.119 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.010     ; 31.980     ;
; -11.113 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 31.963     ;
; -11.113 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 31.963     ;
; -11.107 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 31.957     ;
; -11.107 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 31.957     ;
; -11.087 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[15]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 31.942     ;
; -11.087 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.010     ; 31.948     ;
; -11.087 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[15]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.016     ; 31.942     ;
; -11.087 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.010     ; 31.948     ;
; -11.075 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 31.925     ;
; -11.075 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 31.925     ;
; -11.069 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 31.919     ;
; -11.069 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.021     ; 31.919     ;
+---------+------------------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                          ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node             ; To Node               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 22.922 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 2.506      ;
; 22.961 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 2.467      ;
; 23.035 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 2.393      ;
; 23.513 ; CLK_24576             ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.915      ;
; 23.710 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.718      ;
; 23.749 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.679      ;
; 24.141 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.287      ;
; 24.181 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.247      ;
; 24.182 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.246      ;
; 24.697 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.731      ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'CODEC_SCLK'                                                                                                                              ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                   ; To Node                                        ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 30.318 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[207] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.067      ; 10.487     ;
; 30.389 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[236] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.061      ; 10.410     ;
; 30.405 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[234] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.067      ; 10.400     ;
; 30.415 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[207] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.829      ; 11.152     ;
; 30.486 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[236] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.823      ; 11.075     ;
; 30.502 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[234] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.829      ; 11.065     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[163] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[162] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[161] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[160] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[159] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[135] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[122] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[121] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[120] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[119] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[118] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[14]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[13]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[12]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[11]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.593 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[10]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.042     ; 10.103     ;
; 30.623 ; A4299:I_4299|BUFFER_IN[206] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[207] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.080      ; 10.195     ;
; 30.649 ; A4299:I_4299|BUFFER_IN[207] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[207] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.080      ; 10.169     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[163] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[162] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[161] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[160] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[159] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[135] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[122] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[121] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[120] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[119] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[118] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[14]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[13]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[12]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[11]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.690 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[10]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.720      ; 10.768     ;
; 30.694 ; A4299:I_4299|BUFFER_IN[206] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[236] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.074      ; 10.118     ;
; 30.696 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[215] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.009      ; 10.051     ;
; 30.701 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[134] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.033     ; 10.004     ;
; 30.701 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[133] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.033     ; 10.004     ;
; 30.701 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[132] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.033     ; 10.004     ;
; 30.701 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[131] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.033     ; 10.004     ;
; 30.701 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[55]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.033     ; 10.004     ;
; 30.701 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[49]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.033     ; 10.004     ;
; 30.701 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[41]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.033     ; 10.004     ;
; 30.701 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[40]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.033     ; 10.004     ;
; 30.710 ; A4299:I_4299|BUFFER_IN[206] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[234] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.080      ; 10.108     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[249] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[248] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[247] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[232] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[231] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[230] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[229] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[117] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[54]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[53]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[52]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[51]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[50]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[44]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[43]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.711 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[42]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.021     ; 10.006     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[165] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[164] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[130] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[129] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[128] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[127] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[126] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[125] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[124] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[123] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[48]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[9]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[8]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[7]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[6]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.713 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[5]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.024     ; 10.001     ;
; 30.720 ; A4299:I_4299|BUFFER_IN[207] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[236] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.074      ; 10.092     ;
; 30.736 ; A4299:I_4299|BUFFER_IN[207] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[234] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.080      ; 10.082     ;
; 30.765 ; A4299:I_4299|BUFFER_IN[205] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[207] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 1.112      ; 11.085     ;
; 30.770 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[228] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.009      ; 9.977      ;
; 30.770 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[227] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.009      ; 9.977      ;
; 30.770 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[226] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.009      ; 9.977      ;
; 30.770 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[225] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.009      ; 9.977      ;
; 30.770 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[224] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.009      ; 9.977      ;
; 30.770 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[223] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.009      ; 9.977      ;
; 30.770 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[222] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.009      ; 9.977      ;
; 30.770 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[221] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.009      ; 9.977      ;
; 30.770 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[220] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.009      ; 9.977      ;
; 30.770 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[219] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.009      ; 9.977      ;
; 30.770 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[218] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.009      ; 9.977      ;
; 30.770 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[217] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.009      ; 9.977      ;
; 30.770 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[216] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.009      ; 9.977      ;
; 30.770 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[214] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.009      ; 9.977      ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                  ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node           ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 38.203 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.897      ;
; 38.369 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.731      ;
; 38.369 ; SCLK_6M4          ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.731      ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'CLK_PLL1'                                                                                               ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 59.724 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.814      ;
; 59.724 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.814      ;
; 59.724 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.814      ;
; 59.724 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.814      ;
; 59.724 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.814      ;
; 59.874 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.664      ;
; 59.874 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.664      ;
; 59.874 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.664      ;
; 59.874 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.664      ;
; 59.874 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.664      ;
; 59.945 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.005      ; 2.598      ;
; 59.946 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.005      ; 2.597      ;
; 60.095 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.005      ; 2.448      ;
; 60.096 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.005      ; 2.447      ;
; 60.292 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.246      ;
; 60.292 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.246      ;
; 60.292 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.246      ;
; 60.292 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.246      ;
; 60.292 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.246      ;
; 60.513 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.005      ; 2.030      ;
; 60.514 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.005      ; 2.029      ;
; 60.577 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.961      ;
; 60.577 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.961      ;
; 60.577 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.961      ;
; 60.577 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.961      ;
; 60.577 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.961      ;
; 60.681 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.857      ;
; 60.681 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.857      ;
; 60.681 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.857      ;
; 60.681 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.857      ;
; 60.681 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.857      ;
; 60.798 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.005      ; 1.745      ;
; 60.799 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.005      ; 1.744      ;
; 60.902 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.005      ; 1.641      ;
; 60.903 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.005      ; 1.640      ;
; 61.637 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.901      ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 60.376 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 2.162      ;
; 60.416 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 2.122      ;
; 60.609 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.929      ;
; 60.750 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.788      ;
; 61.211 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.327      ;
; 61.213 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.325      ;
; 61.214 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.324      ;
; 61.216 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.322      ;
; 61.259 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.279      ;
; 61.260 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.278      ;
; 61.264 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.274      ;
; 61.621 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.917      ;
; 61.807 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; CLK_0M5              ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                                                                    ;
+-------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                              ; To Node                                                                                                                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.228 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[191]                                                                          ; A4299:I_4299|BUFFER_IN[192]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.394      ; 0.908      ;
; 0.241 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[201]                                                                          ; A4299:I_4299|BUFFER_IN[202]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.394      ; 0.921      ;
; 0.243 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[207]                                                                          ; A4299:I_4299|BUFFER_IN[208]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.394      ; 0.923      ;
; 0.364 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[173]                                                                          ; A4299:I_4299|BUFFER_IN[174]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.256      ; 0.906      ;
; 0.364 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[174]                                                                          ; A4299:I_4299|BUFFER_IN[175]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.256      ; 0.906      ;
; 0.371 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[221]                                                                          ; A4299:I_4299|BUFFER_IN[222]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.251      ; 0.908      ;
; 0.445 ; A4299:I_4299|INT                                                                                                       ; A4299:I_4299|INT                                                                                                                                          ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; A4299:I_4299|SYNC                                                                                                      ; A4299:I_4299|SYNC                                                                                                                                         ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.731      ;
; 0.481 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[0] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg0 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.987      ; 1.718      ;
; 0.490 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[7] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.987      ; 1.727      ;
; 0.494 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[2] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.987      ; 1.731      ;
; 0.496 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[3] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.987      ; 1.733      ;
; 0.510 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[1] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.987      ; 1.747      ;
; 0.517 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[0] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg0 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.951      ; 1.718      ;
; 0.519 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[222]                                                                          ; A4299:I_4299|BUFFER_IN[223]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.251      ; 1.056      ;
; 0.524 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[4] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.987      ; 1.761      ;
; 0.526 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[7] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.951      ; 1.727      ;
; 0.530 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[2] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.951      ; 1.731      ;
; 0.532 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[3] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.951      ; 1.733      ;
; 0.546 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[1] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.951      ; 1.747      ;
; 0.555 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[181]                                                                          ; A4299:I_4299|BUFFER_IN[182]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.068      ; 0.909      ;
; 0.557 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[198]                                                                          ; A4299:I_4299|BUFFER_IN[199]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.068      ; 0.911      ;
; 0.560 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[4] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.951      ; 1.761      ;
; 0.578 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[5] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.987      ; 1.815      ;
; 0.605 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[186]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[187]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.192      ; 1.083      ;
; 0.611 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[6] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.987      ; 1.848      ;
; 0.612 ; A4299:I_4299|\CODEC_TRANSMIT:BITCNT[7]                                                                                 ; A4299:I_4299|\CODEC_TRANSMIT:BITCNT[7]                                                                                                                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[94]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[95]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[92]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[93]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.898      ;
; 0.614 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[152]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[153]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[5] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.951      ; 1.815      ;
; 0.615 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[91]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[92]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.901      ;
; 0.616 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[89]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[90]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.902      ;
; 0.617 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[147]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[148]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.617 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[139]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[140]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.617 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[57]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[58]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.617 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[21]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[22]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.618 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[58]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[59]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.904      ;
; 0.619 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[93]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[94]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.905      ;
; 0.619 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[88]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[89]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.905      ;
; 0.619 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[11]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[12]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.905      ;
; 0.620 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[157]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[158]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[121]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[122]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[26]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[27]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[242]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[243]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[233]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[234]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[223]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[224]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[167]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[168]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[181]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[182]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[187]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[188]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.621 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[154]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[155]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[85]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[86]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[82]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[83]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[22]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[23]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[234]                                                                          ; A4299:I_4299|BUFFER_IN[235]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; -0.001     ; 0.906      ;
; 0.621 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[250]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[251]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[226]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[227]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[249]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[250]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.622 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[153]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[154]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[37]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[38]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[30]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[31]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[221]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[222]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[248]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[249]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[193]                                                                          ; A4299:I_4299|BUFFER_IN[194]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; -0.001     ; 0.907      ;
; 0.622 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[210]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[211]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[191]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[192]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.623 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[38]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[39]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[36]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[37]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[24]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[25]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[19]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[20]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.624 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[32]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[33]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.910      ;
; 0.624 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[25]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[26]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.910      ;
; 0.624 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[249]                                                                          ; A4299:I_4299|BUFFER_IN[250]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; -0.003     ; 0.907      ;
; 0.624 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[233]                                                                          ; A4299:I_4299|BUFFER_IN[234]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; -0.001     ; 0.909      ;
; 0.624 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[206]                                                                          ; A4299:I_4299|BUFFER_IN[207]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; -0.001     ; 0.909      ;
; 0.624 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[173]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[174]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.910      ;
; 0.624 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[176]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[177]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.910      ;
; 0.625 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[155]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[156]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.911      ;
; 0.625 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[78]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[79]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.911      ;
; 0.625 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[28]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[29]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.911      ;
; 0.625 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[17]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[18]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.911      ;
; 0.625 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[250]                                                                          ; A4299:I_4299|BUFFER_IN[251]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; -0.003     ; 0.908      ;
; 0.625 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[215]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[216]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.911      ;
; 0.625 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[184]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[185]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.911      ;
; 0.626 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[212]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[213]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.912      ;
; 0.626 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[166]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[167]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.912      ;
; 0.626 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[196]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[197]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.912      ;
; 0.627 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[238]                                                                          ; A4299:I_4299|BUFFER_IN[239]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.913      ;
; 0.627 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[248]                                                                          ; A4299:I_4299|BUFFER_IN[249]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; -0.003     ; 0.910      ;
; 0.627 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[239]                                                                          ; A4299:I_4299|BUFFER_IN[240]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.913      ;
; 0.627 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[216]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[217]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.913      ;
; 0.627 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[238]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[239]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.913      ;
; 0.628 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[243]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[244]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.914      ;
; 0.628 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[183]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[184]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.914      ;
; 0.629 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[235]                                                                          ; A4299:I_4299|BUFFER_IN[236]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.915      ;
; 0.630 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[252]                                                                          ; A4299:I_4299|BUFFER_IN[253]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.916      ;
; 0.630 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[229]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[230]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.916      ;
; 0.630 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[194]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[195]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.916      ;
; 0.630 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[176]                                                                          ; A4299:I_4299|BUFFER_IN[177]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; -0.003     ; 0.913      ;
; 0.630 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[165]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[166]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.916      ;
+-------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                              ;
+-------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                              ; To Node                                                                                ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|RETRY                                 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|RETRY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP                 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST               ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.IDLE                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.IDLE                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|BUS_CTRL_STATE.DATA_C1C4              ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|BUS_CTRL_STATE.DATA_C1C4              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[2]                  ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[2]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[0]                  ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[0]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[1]                  ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[1]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP          ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                          ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED              ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|ALU_BSY                                            ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|ALU_BSY                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|LOOP_BSY_I                   ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|LOOP_BSY_I                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                       ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                      ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0          ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE            ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RESET           ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|READ_CYCLE                                 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|READ_CYCLE                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_INT             ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_INT             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                   ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                   ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|EXEC_WB_STATE.IDLE                         ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|EXEC_WB_STATE.IDLE                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_PNTR[0]                ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_PNTR[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRACE                   ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRACE                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                     ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OW_RDY                                     ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OW_RDY                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[32]              ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[32]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|WRITE_CYCLE                                ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|WRITE_CYCLE                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                              ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[2]                                                                       ; \SLOW_CPU:TMP[2]                                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[1]                                                                       ; \SLOW_CPU:TMP[1]                                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[0]                                                                       ; \SLOW_CPU:TMP[0]                                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]            ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]            ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEM_FIRST_RD                             ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEM_FIRST_RD                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT                ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                     ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO                 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR                    ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL                 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT                  ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV                   ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET                   ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_VALID                            ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_VALID                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL                    ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXT~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXT~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR            ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                       ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVEA~reg0                ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVEA~reg0                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_2[3]                 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_2[3]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_1[3]                 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_1[3]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPA~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPA~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                            ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                            ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[1]               ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[1]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.PEA~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.PEA~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                         ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|FETCH_STATE.FETCH_IDATA_B2                 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|FETCH_STATE.FETCH_IDATA_B2                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PREFETCH_BUFFERS:RDY_VAR             ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PREFETCH_BUFFERS:RDY_VAR             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RTE             ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RTE             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NBCD~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NBCD~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|\STACK_CTRL:STACK_POS_VAR[0] ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|\STACK_CTRL:STACK_POS_VAR[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST               ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST               ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2              ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2              ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1              ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|ADR_LATCH[3]                                                         ; WF68K10_TOP:I_CPU|ADR_LATCH[3]                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|ADR_LATCH[2]                                                         ; WF68K10_TOP:I_CPU|ADR_LATCH[2]                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
+-------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                                                                              ;
+-------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                              ; To Node                                                                                ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|RETRY                                 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|RETRY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP                 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST               ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.IDLE                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.IDLE                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|BUS_CTRL_STATE.DATA_C1C4              ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|BUS_CTRL_STATE.DATA_C1C4              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[2]                  ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[2]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[0]                  ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[0]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[1]                  ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[1]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP          ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                          ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED              ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|ALU_BSY                                            ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|ALU_BSY                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|LOOP_BSY_I                   ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|LOOP_BSY_I                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                       ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                      ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0          ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE            ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RESET           ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|READ_CYCLE                                 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|READ_CYCLE                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_INT             ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_INT             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                   ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                   ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|EXEC_WB_STATE.IDLE                         ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|EXEC_WB_STATE.IDLE                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_PNTR[0]                ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_PNTR[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRACE                   ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRACE                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                     ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OW_RDY                                     ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OW_RDY                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[32]              ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[32]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|WRITE_CYCLE                                ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|WRITE_CYCLE                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                              ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[2]                                                                       ; \SLOW_CPU:TMP[2]                                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[1]                                                                       ; \SLOW_CPU:TMP[1]                                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[0]                                                                       ; \SLOW_CPU:TMP[0]                                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]            ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]            ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEM_FIRST_RD                             ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEM_FIRST_RD                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT                ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                     ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO                 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR                    ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL                 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT                  ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV                   ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET                   ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_VALID                            ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_VALID                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL                    ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXT~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXT~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR            ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                       ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVEA~reg0                ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVEA~reg0                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_2[3]                 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_2[3]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_1[3]                 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_1[3]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPA~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPA~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                            ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                            ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[1]               ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[1]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.PEA~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.PEA~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                         ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|FETCH_STATE.FETCH_IDATA_B2                 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|FETCH_STATE.FETCH_IDATA_B2                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PREFETCH_BUFFERS:RDY_VAR             ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PREFETCH_BUFFERS:RDY_VAR             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RTE             ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RTE             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NBCD~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NBCD~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|\STACK_CTRL:STACK_POS_VAR[0] ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|\STACK_CTRL:STACK_POS_VAR[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST               ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST               ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2              ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2              ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1              ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|ADR_LATCH[3]                                                         ; WF68K10_TOP:I_CPU|ADR_LATCH[3]                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K10_TOP:I_CPU|ADR_LATCH[2]                                                         ; WF68K10_TOP:I_CPU|ADR_LATCH[2]                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
+-------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.594 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.002        ; 0.034      ; 0.916      ;
; 0.597 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.002        ; 0.034      ; 0.919      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[59]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[60]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[43]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[44]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[28]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[59]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[60]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[43]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[44]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[28]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.614 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[13]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[14]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[4][1]                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[3][1]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.594 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.002        ; 0.034      ; 0.916      ;
; 0.597 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.002        ; 0.034      ; 0.919      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[59]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[60]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[43]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[44]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[28]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[59]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[60]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[43]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[44]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[28]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.614 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[13]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[14]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[4][1]                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[3][1]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.900      ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                                                                                                        ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                     ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[8]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[8]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                                                                                                        ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                     ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[8]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[8]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                  ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node           ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; SCLK_6M4          ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.611 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.897      ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                          ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node             ; To Node               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.960 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.246      ;
; 0.961 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.247      ;
; 1.001 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.287      ;
; 1.393 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.679      ;
; 1.432 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.718      ;
; 1.629 ; CLK_24576             ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.915      ;
; 2.107 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 2.393      ;
; 2.181 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 2.467      ;
; 2.220 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 2.506      ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; CLK_0M5              ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.631 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.917      ;
; 0.988 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.274      ;
; 0.992 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.278      ;
; 0.993 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.279      ;
; 1.036 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.322      ;
; 1.038 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.324      ;
; 1.039 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.325      ;
; 1.041 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.327      ;
; 1.502 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.788      ;
; 1.643 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.929      ;
; 1.836 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 2.122      ;
; 1.876 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 2.162      ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'CLK_PLL1'                                                                                               ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 0.615 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.901      ;
; 0.951 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.237      ;
; 0.981 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.267      ;
; 0.994 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.280      ;
; 1.026 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.312      ;
; 1.026 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.312      ;
; 1.349 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.005      ; 1.640      ;
; 1.350 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.005      ; 1.641      ;
; 1.413 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.699      ;
; 1.453 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.005      ; 1.744      ;
; 1.454 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.005      ; 1.745      ;
; 1.456 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.742      ;
; 1.456 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.742      ;
; 1.456 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.742      ;
; 1.493 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.779      ;
; 1.536 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.822      ;
; 1.536 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.822      ;
; 1.571 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.857      ;
; 1.571 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.857      ;
; 1.571 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.857      ;
; 1.573 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.859      ;
; 1.616 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.902      ;
; 1.675 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.961      ;
; 1.675 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.961      ;
; 1.675 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.961      ;
; 1.675 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.961      ;
; 1.696 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.982      ;
; 1.738 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.005      ; 2.029      ;
; 1.739 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.005      ; 2.030      ;
; 1.960 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.246      ;
; 1.960 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.246      ;
; 2.156 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.005      ; 2.447      ;
; 2.157 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.005      ; 2.448      ;
; 2.306 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.005      ; 2.597      ;
; 2.307 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.005      ; 2.598      ;
; 2.528 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.814      ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                        ;
+--------+--------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                        ; To Node                                                                                                   ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 10.633     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.029      ; 10.653     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[7]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 10.633     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.029      ; 10.653     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[7]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 10.639     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 10.630     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.008     ; 10.615     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.008     ; 10.615     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.029      ; 10.652     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 10.663     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 10.630     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.008     ; 10.615     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.008     ; 10.615     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.029      ; 10.652     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 10.663     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 10.632     ;
; 20.666 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 10.658     ;
; 20.666 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 10.658     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.034      ; 10.637     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.034      ; 10.637     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.034      ; 10.637     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.611     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.047      ; 10.650     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.047      ; 10.650     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.047      ; 10.650     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 10.623     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 10.623     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.611     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.034      ; 10.637     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.611     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[15]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.002      ; 10.605     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 10.623     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[11]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.611     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.047      ; 10.650     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.047      ; 10.650     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.047      ; 10.650     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 10.623     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.611     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.611     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[31]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.002      ; 10.605     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.034      ; 10.637     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.034      ; 10.637     ;
+--------+--------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                                                        ;
+--------+--------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                        ; To Node                                                                                                   ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 10.633     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.029      ; 10.653     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[7]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 10.633     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.029      ; 10.653     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 10.639     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[7]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.024      ; 10.648     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 10.639     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 10.630     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.008     ; 10.615     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.008     ; 10.615     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.029      ; 10.652     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 10.663     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 10.630     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.008     ; 10.615     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.008     ; 10.615     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.029      ; 10.652     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 10.663     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.019      ; 10.642     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 10.632     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.033      ; 10.656     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 10.632     ;
; 20.666 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 10.658     ;
; 20.666 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 10.658     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.034      ; 10.637     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.034      ; 10.637     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.034      ; 10.637     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.611     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.047      ; 10.650     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.047      ; 10.650     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.047      ; 10.650     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 10.623     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 10.623     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.611     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.034      ; 10.637     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.611     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[15]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.002      ; 10.605     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 10.623     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[11]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.611     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.047      ; 10.650     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.047      ; 10.650     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.047      ; 10.650     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 10.623     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.611     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.611     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[31]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.002      ; 10.605     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.034      ; 10.637     ;
; 20.685 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.034      ; 10.637     ;
+--------+--------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                        ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                        ; To Node                                                                                   ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[11]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[22]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[23]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[17]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[16]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[18]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[21]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[11]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[22]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[23]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[17]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[16]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[18]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[21]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[9]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[8]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[10]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[10]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[11]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.050      ; 10.673     ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                        ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                        ; To Node                                                                                   ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[11]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[22]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[23]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[17]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[16]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[18]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[21]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[11]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[22]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[23]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.049      ; 10.673     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[17]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[16]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[18]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.674     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[21]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.048      ; 10.672     ;
; 20.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.047      ; 10.671     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[9]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[8]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[10]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[10]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[11]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.673     ;
; 20.665 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.050      ; 10.673     ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                           ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                           ; To Node                                                                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 78.914 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|dffe4 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0 ; CODEC_SCLK   ; CODEC_SCLK  ; 81.400       ; 0.409      ; 2.855      ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                           ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                           ; To Node                                                                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 2.196 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|dffe4 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.409      ; 2.855      ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                               ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                      ; To Node                                                                            ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 2.424 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 2.758      ;
; 2.424 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 2.758      ;
; 2.424 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 2.758      ;
; 2.424 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 2.758      ;
; 2.424 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 2.758      ;
; 2.424 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 2.758      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.048      ; 3.056      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][12]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][2]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][7]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][10]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][0]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][10]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][0]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][12]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][2]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][7]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][10]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][0]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][10]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][0]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.016     ; 6.409      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.016     ; 6.409      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[29] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[28] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[26] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[25] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.016     ; 6.409      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.016     ; 6.409      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.017      ; 6.442      ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                               ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                      ; To Node                                                                            ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 2.424 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 2.758      ;
; 2.424 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 2.758      ;
; 2.424 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 2.758      ;
; 2.424 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 2.758      ;
; 2.424 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 2.758      ;
; 2.424 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 2.758      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 2.722 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.048      ; 3.056      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][12]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][2]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][7]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][10]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][0]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][10]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][0]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][12]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][2]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][7]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][10]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][0]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][10]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.138 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][0]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 6.404      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.016     ; 6.409      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.016     ; 6.409      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[29] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[28] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[26] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[25] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.016     ; 6.409      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.032     ; 6.393      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.016     ; 6.409      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
; 6.139 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.017      ; 6.442      ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                  ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                                ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 2.874      ;
; 2.850 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 3.152      ;
; 2.850 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 3.152      ;
; 2.850 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 3.152      ;
; 2.850 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 3.152      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.167      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.172      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.172      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.172      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.172      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.172      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.172      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.172      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.029      ; 3.172      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.022      ; 3.254      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.269      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.269      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.269      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.269      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.269      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.269      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.269      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.023      ; 3.269      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 3.701      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 3.722      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 3.749      ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                  ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                                ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 2.874      ;
; 2.574 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 2.874      ;
; 2.850 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 3.152      ;
; 2.850 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 3.152      ;
; 2.850 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 3.152      ;
; 2.850 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 3.152      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.167      ;
; 2.852 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.167      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.172      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.172      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.172      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.172      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.172      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.172      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.172      ;
; 2.857 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.029      ; 3.172      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 3.254      ;
; 2.946 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.022      ; 3.254      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.269      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.269      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.269      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.269      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.269      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.269      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.269      ;
; 2.960 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.023      ; 3.269      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.415 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 3.701      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 3.722      ;
; 3.428 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 3.722      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
; 3.472 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 3.749      ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                     ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg7  ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                                                                                     ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg7  ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 11.584 ; 12.695       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576                                           ;
; 11.584 ; 12.695       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576                                           ;
; 11.584 ; 12.695       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]                               ;
; 11.584 ; 12.695       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]                               ;
; 11.584 ; 12.695       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]                               ;
; 11.584 ; 12.695       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]                               ;
; 11.584 ; 12.695       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]                               ;
; 11.584 ; 12.695       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]                               ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576|clk                                       ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576|clk                                       ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|inclk[0] ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|inclk[0] ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|outclk   ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|outclk   ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                                                 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4                                            ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4                                            ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]                                   ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]                                   ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|inclk[0] ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|inclk[0] ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|outclk   ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|outclk   ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4|clk                                        ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4|clk                                        ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]|clk                               ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]|clk                               ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                   ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                   ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------+
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]               ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]               ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]               ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]               ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------+
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]               ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]               ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]               ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]               ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CLK_PLL1'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 59.869 ; 62.500       ; 2.631          ; Port Rate        ; CLK_PLL1 ; Rise       ; CLK_PLL1                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5                                             ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5                                             ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CLK_PLL2'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 59.869 ; 62.500       ; 2.631          ; Port Rate        ; CLK_PLL2 ; Rise       ; CLK_PLL2                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CRT_PIN4_CLK1'                                                                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock         ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 59.869 ; 62.500       ; 2.631          ; Port Rate        ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1                             ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CODEC_SCLK'                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock      ; Clock Edge ; Target                                                                                                                                                    ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0                    ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0                    ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg0 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg0 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg6 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg6 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_datain_reg0  ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_datain_reg0  ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_memory_reg0  ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_memory_reg0  ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg0 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg0 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[162]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[162]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[163]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[163]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[164]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[164]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[165]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[165]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[166]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[166]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[167]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[167]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[168]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[168]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[169]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[169]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[170]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[170]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[171]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[171]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[172]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[172]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[173]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[173]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[174]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[174]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[175]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[175]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[176]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[176]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[177]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[177]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[178]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[178]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[179]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[179]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[180]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[180]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[181]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[181]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[182]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[182]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[183]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[183]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[184]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[184]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[185]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[185]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[186]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[186]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[187]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[187]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[188]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[188]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[189]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[189]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[190]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[190]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[191]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[191]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[192]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[192]                                                                                                                               ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 0.802  ; 0.802  ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; 11.918 ; 11.918 ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; -0.403 ; -0.403 ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; 13.898 ; 13.898 ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; 27.034 ; 27.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 6.398  ; 6.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 10.854 ; 10.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 7.606  ; 7.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 11.786 ; 11.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 9.605  ; 9.605  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 10.493 ; 10.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 9.830  ; 9.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 10.372 ; 10.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 11.272 ; 11.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 11.032 ; 11.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 11.786 ; 11.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 11.199 ; 11.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 16.904 ; 16.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 16.883 ; 16.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 17.496 ; 17.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; 12.218 ; 12.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 37.095 ; 37.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 19.430 ; 19.430 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 18.145 ; 18.145 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[3]     ; CLK_PLL1      ; 37.095 ; 37.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 30.582 ; 30.582 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 20.491 ; 20.491 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 14.278 ; 14.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 13.088 ; 13.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 17.946 ; 17.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 16.731 ; 16.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 15.921 ; 15.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 17.578 ; 17.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 15.422 ; 15.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 16.110 ; 16.110 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 17.620 ; 17.620 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 17.763 ; 17.763 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 17.256 ; 17.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 17.946 ; 17.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 16.433 ; 16.433 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 16.982 ; 16.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 17.855 ; 17.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 16.453 ; 16.453 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 17.184 ; 17.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 11.783 ; 11.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 13.139 ; 13.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 8.581  ; 8.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 14.092 ; 14.092 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 28.790 ; 28.790 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 28.790 ; 28.790 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 28.085 ; 28.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 27.614 ; 27.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; 13.369 ; 13.369 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; 6.446  ; 6.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; 10.895 ; 10.895 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; 15.965 ; 15.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; 8.679  ; 8.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 9.660  ; 9.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 22.206 ; 22.206 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 11.368 ; 11.368 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 22.126 ; 22.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; 7.466  ; 7.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 27.878 ; 27.878 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 18.711 ; 18.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 18.530 ; 18.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 18.530 ; 18.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 17.765 ; 17.765 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 16.256 ; 16.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 17.083 ; 17.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 17.866 ; 17.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 17.599 ; 17.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 18.210 ; 18.210 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 18.483 ; 18.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; 5.903  ; 5.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; 4.587  ; 4.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; 5.158  ; 5.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; 5.723  ; 5.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; 6.122  ; 6.122  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; 4.198  ; 4.198  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 19.851 ; 19.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 19.066 ; 19.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 18.283 ; 18.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 17.962 ; 17.962 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 18.599 ; 18.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 17.095 ; 17.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 18.501 ; 18.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 17.558 ; 17.558 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 17.851 ; 17.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 19.851 ; 19.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 17.824 ; 17.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 18.045 ; 18.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 18.838 ; 18.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 18.055 ; 18.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 19.162 ; 19.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 19.473 ; 19.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 17.836 ; 17.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; 2.890  ; 2.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 8.494  ; 8.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 28.039 ; 28.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 13.388 ; 13.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 9.379  ; 9.379  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 10.597 ; 10.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 10.082 ; 10.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 10.172 ; 10.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 10.226 ; 10.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 10.597 ; 10.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 9.565  ; 9.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 9.082  ; 9.082  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 9.248  ; 9.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 10.327 ; 10.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 13.163 ; 13.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 11.793 ; 11.793 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 11.957 ; 11.957 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 13.717 ; 13.717 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 10.818 ; 10.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; 14.144 ; 14.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; 7.292  ; 7.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; 13.752 ; 13.752 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 24.832 ; 24.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; 7.496  ; 7.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; 9.558  ; 9.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; 8.977  ; 8.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; 8.604  ; 8.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; 8.693  ; 8.693  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; 8.977  ; 8.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; 9.057  ; 9.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; 9.494  ; 9.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; 10.885 ; 10.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 10.177 ; 10.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 25.807 ; 25.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; 8.443  ; 8.443  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 8.307  ; 8.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 25.332 ; 25.332 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 6.785  ; 6.785  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 6.797  ; 6.797  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 7.401  ; 7.401  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; 7.184  ; 7.184  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 16.263 ; 16.263 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 15.872 ; 15.872 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 15.682 ; 15.682 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 28.741 ; 28.741 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 17.629 ; 17.629 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 16.344 ; 16.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 28.741 ; 28.741 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 18.835 ; 18.835 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 12.477 ; 12.477 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 11.287 ; 11.287 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 16.937 ; 16.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 15.706 ; 15.706 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 14.910 ; 14.910 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 16.937 ; 16.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 14.168 ; 14.168 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 14.583 ; 14.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 15.566 ; 15.566 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 15.949 ; 15.949 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 15.455 ; 15.455 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 16.105 ; 16.105 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 14.249 ; 14.249 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 15.140 ; 15.140 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 15.530 ; 15.530 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 13.907 ; 13.907 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 14.938 ; 14.938 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 9.421  ; 9.421  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 10.849 ; 10.849 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 10.454 ; 10.454 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; 3.956  ; 3.956  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; 3.961  ; 3.961  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; 3.002  ; 3.002  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 26.428 ; 26.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 26.428 ; 26.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 25.850 ; 25.850 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 25.773 ; 25.773 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; 8.340  ; 8.340  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 6.906  ; 6.906  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 20.152 ; 20.152 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; 8.760  ; 8.760  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 20.072 ; 20.072 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 25.824 ; 25.824 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 17.686 ; 17.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 16.689 ; 16.689 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 16.689 ; 16.689 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 15.581 ; 15.581 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 14.414 ; 14.414 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 14.758 ; 14.758 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 15.320 ; 15.320 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 15.353 ; 15.353 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 15.848 ; 15.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 16.193 ; 16.193 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 18.041 ; 18.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 18.041 ; 18.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 17.272 ; 17.272 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 17.321 ; 17.321 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 17.345 ; 17.345 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 15.568 ; 15.568 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 16.447 ; 16.447 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 15.744 ; 15.744 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 16.050 ; 16.050 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 18.010 ; 18.010 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 15.640 ; 15.640 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 16.203 ; 16.203 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 16.513 ; 16.513 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 15.509 ; 15.509 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 16.916 ; 16.916 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 17.111 ; 17.111 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 15.546 ; 15.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 26.198 ; 26.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 23.807 ; 23.807 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 8.248  ; 8.248  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; 8.381  ; 8.381  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 24.499 ; 24.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; 27.034 ; 27.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 6.398  ; 6.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 10.854 ; 10.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 7.606  ; 7.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 11.786 ; 11.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 9.605  ; 9.605  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 10.493 ; 10.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 9.830  ; 9.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 10.372 ; 10.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 11.272 ; 11.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 11.032 ; 11.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 11.786 ; 11.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 11.199 ; 11.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 16.904 ; 16.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 16.883 ; 16.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 17.496 ; 17.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; 12.218 ; 12.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 37.095 ; 37.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 19.430 ; 19.430 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 18.145 ; 18.145 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[3]     ; CRT_PIN4_CLK1 ; 37.095 ; 37.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 30.582 ; 30.582 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 20.491 ; 20.491 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 14.278 ; 14.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 13.088 ; 13.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 17.946 ; 17.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 16.731 ; 16.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 15.921 ; 15.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 17.578 ; 17.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 15.422 ; 15.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 16.110 ; 16.110 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 17.620 ; 17.620 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 17.763 ; 17.763 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.256 ; 17.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 17.946 ; 17.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 16.433 ; 16.433 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 16.982 ; 16.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 17.855 ; 17.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 16.453 ; 16.453 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 17.184 ; 17.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 11.783 ; 11.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 13.139 ; 13.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 8.581  ; 8.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 14.092 ; 14.092 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 28.790 ; 28.790 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 28.790 ; 28.790 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 28.085 ; 28.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 27.614 ; 27.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; 13.369 ; 13.369 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; 6.446  ; 6.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; 10.895 ; 10.895 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; 15.965 ; 15.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; 8.679  ; 8.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 9.660  ; 9.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 22.206 ; 22.206 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 11.368 ; 11.368 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 22.126 ; 22.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; 7.466  ; 7.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 27.878 ; 27.878 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 18.711 ; 18.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 18.530 ; 18.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 18.530 ; 18.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 17.765 ; 17.765 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 16.256 ; 16.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 17.083 ; 17.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 17.866 ; 17.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 17.599 ; 17.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 18.210 ; 18.210 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 18.483 ; 18.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; 5.903  ; 5.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; 4.587  ; 4.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; 5.158  ; 5.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; 5.723  ; 5.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; 6.122  ; 6.122  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; 4.198  ; 4.198  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 19.851 ; 19.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 19.066 ; 19.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 18.283 ; 18.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 17.962 ; 17.962 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 18.599 ; 18.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 17.095 ; 17.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 18.501 ; 18.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 17.558 ; 17.558 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 17.851 ; 17.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 19.851 ; 19.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 17.824 ; 17.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 18.045 ; 18.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 18.838 ; 18.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 18.055 ; 18.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 19.162 ; 19.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 19.473 ; 19.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 17.836 ; 17.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; 2.890  ; 2.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 8.494  ; 8.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 28.039 ; 28.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 13.388 ; 13.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 9.379  ; 9.379  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 10.597 ; 10.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 10.082 ; 10.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 10.172 ; 10.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 10.226 ; 10.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 10.597 ; 10.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 9.565  ; 9.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 9.082  ; 9.082  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 9.248  ; 9.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 10.327 ; 10.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 13.163 ; 13.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 11.793 ; 11.793 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 11.957 ; 11.957 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 13.717 ; 13.717 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 10.818 ; 10.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; 14.144 ; 14.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; 7.292  ; 7.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; 13.752 ; 13.752 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 24.832 ; 24.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; 7.496  ; 7.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; 9.558  ; 9.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; 8.977  ; 8.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; 8.604  ; 8.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; 8.693  ; 8.693  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; 8.977  ; 8.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; 9.057  ; 9.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; 9.494  ; 9.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; 10.885 ; 10.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 10.177 ; 10.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 25.807 ; 25.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; 8.443  ; 8.443  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 8.307  ; 8.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 25.332 ; 25.332 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 6.785  ; 6.785  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 6.797  ; 6.797  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 7.401  ; 7.401  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; 7.184  ; 7.184  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 16.263 ; 16.263 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 15.872 ; 15.872 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 15.682 ; 15.682 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 28.741 ; 28.741 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 17.629 ; 17.629 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 16.344 ; 16.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 28.741 ; 28.741 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 18.835 ; 18.835 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 12.477 ; 12.477 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 11.287 ; 11.287 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 16.937 ; 16.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 15.706 ; 15.706 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 14.910 ; 14.910 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 16.937 ; 16.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 14.168 ; 14.168 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 14.583 ; 14.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 15.566 ; 15.566 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 15.949 ; 15.949 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 15.455 ; 15.455 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 16.105 ; 16.105 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 14.249 ; 14.249 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 15.140 ; 15.140 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 15.530 ; 15.530 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 13.907 ; 13.907 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 14.938 ; 14.938 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 9.421  ; 9.421  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 10.849 ; 10.849 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 10.454 ; 10.454 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; 3.956  ; 3.956  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; 3.961  ; 3.961  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; 3.002  ; 3.002  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 26.428 ; 26.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 26.428 ; 26.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 25.850 ; 25.850 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 25.773 ; 25.773 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; 8.340  ; 8.340  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 6.906  ; 6.906  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 20.152 ; 20.152 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; 8.760  ; 8.760  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 20.072 ; 20.072 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 25.824 ; 25.824 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 17.686 ; 17.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 16.689 ; 16.689 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 16.689 ; 16.689 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 15.581 ; 15.581 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 14.414 ; 14.414 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 14.758 ; 14.758 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 15.320 ; 15.320 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 15.353 ; 15.353 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 15.848 ; 15.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 16.193 ; 16.193 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 18.041 ; 18.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 18.041 ; 18.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 17.272 ; 17.272 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 17.321 ; 17.321 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 17.345 ; 17.345 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 15.568 ; 15.568 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 16.447 ; 16.447 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 15.744 ; 15.744 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 16.050 ; 16.050 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 18.010 ; 18.010 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 15.640 ; 15.640 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 16.203 ; 16.203 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 16.513 ; 16.513 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 15.509 ; 15.509 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 16.916 ; 16.916 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 17.111 ; 17.111 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 15.546 ; 15.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 26.198 ; 26.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 23.807 ; 23.807 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 8.248  ; 8.248  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; 8.381  ; 8.381  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 24.499 ; 24.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; 25.030 ; 25.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; 15.388 ; 15.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; 15.710 ; 15.710 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; 15.436 ; 15.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 28.925 ; 28.925 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; 17.485 ; 17.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; 16.200 ; 16.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; 11.543 ; 11.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; 28.925 ; 28.925 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; 18.587 ; 18.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; 12.333 ; 12.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 11.143 ; 11.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 16.289 ; 16.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 15.458 ; 15.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 14.748 ; 14.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 16.062 ; 16.062 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 13.879 ; 13.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 14.294 ; 14.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 15.549 ; 15.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 15.703 ; 15.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 15.311 ; 15.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 16.289 ; 16.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; 11.800 ; 11.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 26.363 ; 26.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 26.363 ; 26.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 26.034 ; 26.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 25.957 ; 25.957 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; 20.135 ; 20.135 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; 20.055 ; 20.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 25.807 ; 25.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; 17.438 ; 17.438 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; 16.873 ; 16.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; 16.873 ; 16.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 18.194 ; 18.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 17.793 ; 17.793 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 17.110 ; 17.110 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 16.446 ; 16.446 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 17.056 ; 17.056 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 15.279 ; 15.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 16.430 ; 16.430 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 15.498 ; 15.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 15.906 ; 15.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 18.194 ; 18.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 12.089 ; 12.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 11.953 ; 11.953 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 12.478 ; 12.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 13.375 ; 13.375 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 14.016 ; 14.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 14.041 ; 14.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 14.415 ; 14.415 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 26.382 ; 26.382 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 23.559 ; 23.559 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 24.197 ; 24.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 13.671 ; 13.671 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 18.261 ; 18.261 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; 18.261 ; 18.261 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 13.729 ; 13.729 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 13.729 ; 13.729 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 13.410 ; 13.410 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 13.327 ; 13.327 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 12.881 ; 12.881 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 14.426 ; 14.426 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; 25.030 ; 25.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 15.388 ; 15.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 15.710 ; 15.710 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 15.436 ; 15.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 28.925 ; 28.925 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 17.485 ; 17.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 16.200 ; 16.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; 11.543 ; 11.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 28.925 ; 28.925 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 18.587 ; 18.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 12.333 ; 12.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 11.143 ; 11.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 16.289 ; 16.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 15.458 ; 15.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 14.748 ; 14.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 16.062 ; 16.062 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 13.879 ; 13.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 14.294 ; 14.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 15.549 ; 15.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 15.703 ; 15.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 15.311 ; 15.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 16.289 ; 16.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 11.800 ; 11.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 26.363 ; 26.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 26.363 ; 26.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 26.034 ; 26.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 25.957 ; 25.957 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 20.135 ; 20.135 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 20.055 ; 20.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 25.807 ; 25.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 17.438 ; 17.438 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 16.873 ; 16.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 16.873 ; 16.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 18.194 ; 18.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 17.793 ; 17.793 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 17.110 ; 17.110 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 16.446 ; 16.446 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 17.056 ; 17.056 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 15.279 ; 15.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 16.430 ; 16.430 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 15.498 ; 15.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 15.906 ; 15.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 18.194 ; 18.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 12.089 ; 12.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 11.953 ; 11.953 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 12.478 ; 12.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 13.375 ; 13.375 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 14.016 ; 14.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 14.041 ; 14.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 14.415 ; 14.415 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 26.382 ; 26.382 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 23.559 ; 23.559 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 24.197 ; 24.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 13.671 ; 13.671 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 18.261 ; 18.261 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 18.261 ; 18.261 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 13.729 ; 13.729 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 13.729 ; 13.729 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 13.410 ; 13.410 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 13.327 ; 13.327 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 12.881 ; 12.881 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 14.426 ; 14.426 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; 24.440 ; 24.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; 13.819 ; 13.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; 13.804 ; 13.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; 13.847 ; 13.847 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; 28.335 ; 28.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; 15.919 ; 15.919 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; 14.634 ; 14.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[5]     ; CLK_PLL1      ; 28.335 ; 28.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; 18.871 ; 18.871 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; 10.767 ; 10.767 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 9.577  ; 9.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; 16.235 ; 16.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 13.581 ; 13.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 12.842 ; 12.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 14.493 ; 14.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 12.334 ; 12.334 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 12.734 ; 12.734 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 14.001 ; 14.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 14.114 ; 14.114 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 13.745 ; 13.745 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 15.699 ; 15.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 13.328 ; 13.328 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 15.331 ; 15.331 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 16.235 ; 16.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 14.364 ; 14.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 15.177 ; 15.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 8.265  ; 8.265  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 9.276  ; 9.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; 25.882 ; 25.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; 25.882 ; 25.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; 25.444 ; 25.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; 25.367 ; 25.367 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; 18.587 ; 18.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; 18.507 ; 18.507 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; 25.131 ; 25.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; 15.561 ; 15.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 18.223 ; 18.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; 16.283 ; 16.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; 14.660 ; 14.660 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; 14.605 ; 14.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 18.223 ; 18.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 17.155 ; 17.155 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 18.057 ; 18.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 17.280 ; 17.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; 16.021 ; 16.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 17.604 ; 17.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 15.916 ; 15.916 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 15.204 ; 15.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 14.877 ; 14.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 15.511 ; 15.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 13.719 ; 13.719 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 14.882 ; 14.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 13.909 ; 13.909 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 14.340 ; 14.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 17.604 ; 17.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 14.719 ; 14.719 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 16.394 ; 16.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 17.218 ; 17.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 15.966 ; 15.966 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 17.155 ; 17.155 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 16.565 ; 16.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 15.374 ; 15.374 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; 25.792 ; 25.792 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; 21.888 ; 21.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; 23.056 ; 23.056 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; 24.440 ; 24.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 13.819 ; 13.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 13.804 ; 13.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 13.847 ; 13.847 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 28.335 ; 28.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 15.919 ; 15.919 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 14.634 ; 14.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 28.335 ; 28.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 18.871 ; 18.871 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 10.767 ; 10.767 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 9.577  ; 9.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 16.235 ; 16.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 13.581 ; 13.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 12.842 ; 12.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 14.493 ; 14.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 12.334 ; 12.334 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 12.734 ; 12.734 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 14.001 ; 14.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 14.114 ; 14.114 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 13.745 ; 13.745 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 15.699 ; 15.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 13.328 ; 13.328 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 15.331 ; 15.331 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 16.235 ; 16.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 14.364 ; 14.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 15.177 ; 15.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 8.265  ; 8.265  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 9.276  ; 9.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 25.882 ; 25.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 25.882 ; 25.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 25.444 ; 25.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 25.367 ; 25.367 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 18.587 ; 18.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 18.507 ; 18.507 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 25.131 ; 25.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 15.561 ; 15.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 18.223 ; 18.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 16.283 ; 16.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 14.660 ; 14.660 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 14.605 ; 14.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 18.223 ; 18.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 17.155 ; 17.155 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 18.057 ; 18.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 17.280 ; 17.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 16.021 ; 16.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 17.604 ; 17.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 15.916 ; 15.916 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 15.204 ; 15.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 14.877 ; 14.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 15.511 ; 15.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 13.719 ; 13.719 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 14.882 ; 14.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 13.909 ; 13.909 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 14.340 ; 14.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 17.604 ; 17.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 14.719 ; 14.719 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 16.394 ; 16.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 17.218 ; 17.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 15.966 ; 15.966 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 17.155 ; 17.155 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 16.565 ; 16.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 15.374 ; 15.374 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 25.792 ; 25.792 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 21.888 ; 21.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 23.056 ; 23.056 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                   ;
+----------------+---------------+---------+---------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+---------+---------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; -0.551  ; -0.551  ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; -11.232 ; -11.232 ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; 0.651   ; 0.651   ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; -11.819 ; -11.819 ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; -5.874  ; -5.874  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -6.150  ; -6.150  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -6.545  ; -6.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -7.358  ; -7.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; -6.592  ; -6.592  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; -6.592  ; -6.592  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; -6.661  ; -6.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; -7.181  ; -7.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; -6.650  ; -6.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; -6.860  ; -6.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; -7.046  ; -7.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; -7.109  ; -7.109  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; -6.981  ; -6.981  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -6.447  ; -6.447  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -6.126  ; -6.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -7.477  ; -7.477  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; -8.594  ; -8.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -7.921  ; -7.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -10.706 ; -10.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -10.003 ; -10.003 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[3]     ; CLK_PLL1      ; -7.921  ; -7.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -13.005 ; -13.005 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -10.525 ; -10.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -6.136  ; -6.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -4.946  ; -4.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -6.593  ; -6.593  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -7.359  ; -7.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -7.359  ; -7.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -6.957  ; -6.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -7.358  ; -7.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -7.302  ; -7.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -7.032  ; -7.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -7.189  ; -7.189  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -8.016  ; -8.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -6.593  ; -6.593  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -8.058  ; -8.058  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -7.485  ; -7.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -9.371  ; -9.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -9.760  ; -9.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -8.664  ; -8.664  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -7.100  ; -7.100  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -8.318  ; -8.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; -8.333  ; -8.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -7.086  ; -7.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -9.788  ; -9.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -10.194 ; -10.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -9.865  ; -9.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -9.788  ; -9.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; -8.690  ; -8.690  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; -3.297  ; -3.297  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; -7.984  ; -7.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; -9.285  ; -9.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; -6.830  ; -6.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -7.287  ; -7.287  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -10.932 ; -10.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; -7.322  ; -7.322  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -10.852 ; -10.852 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; -7.218  ; -7.218  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -7.323  ; -7.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -8.601  ; -8.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -12.888 ; -12.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -15.715 ; -15.715 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -14.928 ; -14.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -12.888 ; -12.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -13.520 ; -13.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -13.862 ; -13.862 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -14.428 ; -14.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -14.708 ; -14.708 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -15.461 ; -15.461 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; -5.655  ; -5.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; -3.333  ; -3.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; -3.904  ; -3.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; -4.469  ; -4.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; -4.963  ; -4.963  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; -3.489  ; -3.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -7.086  ; -7.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -7.422  ; -7.422  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -7.319  ; -7.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -8.327  ; -8.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -8.302  ; -8.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -8.140  ; -8.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -7.894  ; -7.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -8.789  ; -8.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -9.177  ; -9.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -7.576  ; -7.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -8.055  ; -8.055  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -7.790  ; -7.790  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -7.398  ; -7.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -7.799  ; -7.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -7.549  ; -7.549  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -7.086  ; -7.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -7.107  ; -7.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; -2.642  ; -2.642  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; -8.246  ; -8.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -6.428  ; -6.428  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; -9.012  ; -9.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; -7.239  ; -7.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; -6.199  ; -6.199  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; -6.728  ; -6.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; -6.821  ; -6.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; -7.363  ; -7.363  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; -6.710  ; -6.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; -7.132  ; -7.132  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; -6.795  ; -6.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; -6.289  ; -6.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; -6.199  ; -6.199  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; -7.287  ; -7.287  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; -6.473  ; -6.473  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; -7.447  ; -7.447  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; -7.441  ; -7.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; -7.270  ; -7.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; -7.937  ; -7.937  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; -6.701  ; -6.701  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; -8.958  ; -8.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -8.904  ; -8.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; -7.240  ; -7.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; -9.302  ; -9.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; -6.860  ; -6.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; -6.961  ; -6.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; -6.860  ; -6.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; -7.630  ; -7.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; -8.466  ; -8.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; -9.238  ; -9.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; -10.629 ; -10.629 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -9.591  ; -9.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -9.022  ; -9.022  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; -8.192  ; -8.192  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; -6.852  ; -6.852  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; -9.849  ; -9.849  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -6.537  ; -6.537  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -6.549  ; -6.549  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -7.153  ; -7.153  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; -6.936  ; -6.936  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -15.045 ; -15.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -14.743 ; -14.743 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -14.783 ; -14.783 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -9.677  ; -9.677  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -16.984 ; -16.984 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -15.699 ; -15.699 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -12.479 ; -12.479 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -9.677  ; -9.677  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -11.832 ; -11.832 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -10.642 ; -10.642 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -8.186  ; -8.186  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -8.415  ; -8.415  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -9.071  ; -9.071  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -8.358  ; -8.358  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -8.212  ; -8.212  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -8.914  ; -8.914  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -9.400  ; -9.400  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -10.249 ; -10.249 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -11.156 ; -11.156 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -8.835  ; -8.835  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -8.186  ; -8.186  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -8.274  ; -8.274  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -9.986  ; -9.986  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -10.051 ; -10.051 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -9.034  ; -9.034  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -8.256  ; -8.256  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -9.760  ; -9.760  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -9.888  ; -9.888  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; -3.310  ; -3.310  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; -2.844  ; -2.844  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; -2.556  ; -2.556  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -9.505  ; -9.505  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -9.907  ; -9.907  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -9.588  ; -9.588  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -9.505  ; -9.505  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; -8.092  ; -8.092  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -6.658  ; -6.658  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -19.486 ; -19.486 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; -8.512  ; -8.512  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -19.406 ; -19.406 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -9.119  ; -9.119  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -16.849 ; -16.849 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -13.677 ; -13.677 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -15.620 ; -15.620 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -15.056 ; -15.056 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -13.677 ; -13.677 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -14.135 ; -14.135 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -14.153 ; -14.153 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -14.798 ; -14.798 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -14.683 ; -14.683 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -15.104 ; -15.104 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -14.342 ; -14.342 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -17.204 ; -17.204 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -16.143 ; -16.143 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -16.103 ; -16.103 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -16.430 ; -16.430 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -15.013 ; -15.013 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -15.781 ; -15.781 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -14.845 ; -14.845 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -15.405 ; -15.405 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -16.941 ; -16.941 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -15.115 ; -15.115 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -15.466 ; -15.466 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -15.890 ; -15.890 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -14.342 ; -14.342 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -16.361 ; -16.361 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -15.946 ; -15.946 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -14.457 ; -14.457 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -9.214  ; -9.214  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -11.876 ; -11.876 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -8.000  ; -8.000  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; -8.133  ; -8.133  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -11.895 ; -11.895 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; -5.874  ; -5.874  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -6.150  ; -6.150  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -6.545  ; -6.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -7.358  ; -7.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -6.592  ; -6.592  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -6.592  ; -6.592  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -6.661  ; -6.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -7.181  ; -7.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -6.650  ; -6.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -6.860  ; -6.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -7.046  ; -7.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -7.109  ; -7.109  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -6.981  ; -6.981  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -6.447  ; -6.447  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -6.126  ; -6.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -7.477  ; -7.477  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; -8.594  ; -8.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -7.921  ; -7.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -10.706 ; -10.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -10.003 ; -10.003 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[3]     ; CRT_PIN4_CLK1 ; -7.921  ; -7.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -13.005 ; -13.005 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -10.525 ; -10.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -6.136  ; -6.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -4.946  ; -4.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -6.593  ; -6.593  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -7.359  ; -7.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -7.359  ; -7.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -6.957  ; -6.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -7.358  ; -7.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -7.302  ; -7.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -7.032  ; -7.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -7.189  ; -7.189  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -8.016  ; -8.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -6.593  ; -6.593  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -8.058  ; -8.058  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -7.485  ; -7.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -9.371  ; -9.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -9.760  ; -9.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -8.664  ; -8.664  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -7.100  ; -7.100  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -8.318  ; -8.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; -8.333  ; -8.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -7.086  ; -7.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -9.788  ; -9.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -10.194 ; -10.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -9.865  ; -9.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -9.788  ; -9.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; -8.690  ; -8.690  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; -3.297  ; -3.297  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; -7.984  ; -7.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; -9.285  ; -9.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; -6.830  ; -6.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -7.287  ; -7.287  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -10.932 ; -10.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; -7.322  ; -7.322  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -10.852 ; -10.852 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; -7.218  ; -7.218  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -7.323  ; -7.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -8.601  ; -8.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -12.888 ; -12.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -15.715 ; -15.715 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -14.928 ; -14.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -12.888 ; -12.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -13.520 ; -13.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -13.862 ; -13.862 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -14.428 ; -14.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -14.708 ; -14.708 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -15.461 ; -15.461 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; -5.655  ; -5.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; -3.333  ; -3.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; -3.904  ; -3.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; -4.469  ; -4.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; -4.963  ; -4.963  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; -3.489  ; -3.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -7.086  ; -7.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -7.422  ; -7.422  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -7.319  ; -7.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -8.327  ; -8.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -8.302  ; -8.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -8.140  ; -8.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -7.894  ; -7.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -8.789  ; -8.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -9.177  ; -9.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -7.576  ; -7.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -8.055  ; -8.055  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -7.790  ; -7.790  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -7.398  ; -7.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -7.799  ; -7.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -7.549  ; -7.549  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -7.086  ; -7.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -7.107  ; -7.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; -2.642  ; -2.642  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; -8.246  ; -8.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -6.428  ; -6.428  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; -9.012  ; -9.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; -7.239  ; -7.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; -6.199  ; -6.199  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; -6.728  ; -6.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; -6.821  ; -6.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; -7.363  ; -7.363  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; -6.710  ; -6.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; -7.132  ; -7.132  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; -6.795  ; -6.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; -6.289  ; -6.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; -6.199  ; -6.199  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; -7.287  ; -7.287  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; -6.473  ; -6.473  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; -7.447  ; -7.447  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; -7.441  ; -7.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; -7.270  ; -7.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; -7.937  ; -7.937  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; -6.701  ; -6.701  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; -8.958  ; -8.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -8.904  ; -8.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; -7.240  ; -7.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; -9.302  ; -9.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; -6.860  ; -6.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; -6.961  ; -6.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; -6.860  ; -6.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; -7.630  ; -7.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; -8.466  ; -8.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; -9.238  ; -9.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; -10.629 ; -10.629 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -9.591  ; -9.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -9.022  ; -9.022  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; -8.192  ; -8.192  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; -6.852  ; -6.852  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -9.849  ; -9.849  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -6.537  ; -6.537  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -6.549  ; -6.549  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -7.153  ; -7.153  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; -6.936  ; -6.936  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -15.045 ; -15.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -14.743 ; -14.743 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -14.783 ; -14.783 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -9.677  ; -9.677  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -16.984 ; -16.984 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -15.699 ; -15.699 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -12.479 ; -12.479 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -9.677  ; -9.677  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -11.832 ; -11.832 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -10.642 ; -10.642 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -8.186  ; -8.186  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -8.415  ; -8.415  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -9.071  ; -9.071  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -8.358  ; -8.358  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -8.212  ; -8.212  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -8.914  ; -8.914  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -9.400  ; -9.400  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -10.249 ; -10.249 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -11.156 ; -11.156 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -8.835  ; -8.835  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -8.186  ; -8.186  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -8.274  ; -8.274  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -9.986  ; -9.986  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -10.051 ; -10.051 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -9.034  ; -9.034  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -8.256  ; -8.256  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -9.760  ; -9.760  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -9.888  ; -9.888  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; -3.310  ; -3.310  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; -2.844  ; -2.844  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; -2.556  ; -2.556  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -9.505  ; -9.505  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -9.907  ; -9.907  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -9.588  ; -9.588  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -9.505  ; -9.505  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; -8.092  ; -8.092  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -6.658  ; -6.658  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -19.486 ; -19.486 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; -8.512  ; -8.512  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -19.406 ; -19.406 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -9.119  ; -9.119  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -16.849 ; -16.849 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -13.677 ; -13.677 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -15.620 ; -15.620 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -15.056 ; -15.056 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -13.677 ; -13.677 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -14.135 ; -14.135 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -14.153 ; -14.153 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -14.798 ; -14.798 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -14.683 ; -14.683 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -15.104 ; -15.104 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -14.342 ; -14.342 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -17.204 ; -17.204 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -16.143 ; -16.143 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -16.103 ; -16.103 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -16.430 ; -16.430 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -15.013 ; -15.013 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -15.781 ; -15.781 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -14.845 ; -14.845 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -15.405 ; -15.405 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -16.941 ; -16.941 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -15.115 ; -15.115 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -15.466 ; -15.466 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -15.890 ; -15.890 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -14.342 ; -14.342 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -16.361 ; -16.361 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -15.946 ; -15.946 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -14.457 ; -14.457 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -9.214  ; -9.214  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -11.876 ; -11.876 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -8.000  ; -8.000  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; -8.133  ; -8.133  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -11.895 ; -11.895 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; -8.501  ; -8.501  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; -14.632 ; -14.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; -14.699 ; -14.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; -14.634 ; -14.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -8.888  ; -8.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; -8.888  ; -8.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; -9.310  ; -9.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; -10.351 ; -10.351 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; -10.671 ; -10.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; -10.802 ; -10.802 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; -4.638  ; -4.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -4.914  ; -4.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; -7.500  ; -7.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; -7.500  ; -7.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; -9.027  ; -9.027  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; -7.945  ; -7.945  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; -7.941  ; -7.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; -7.996  ; -7.996  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; -8.874  ; -8.874  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; -10.100 ; -10.100 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; -10.743 ; -10.743 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; -9.840  ; -9.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; -11.013 ; -11.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -10.220 ; -10.220 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -10.574 ; -10.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -10.220 ; -10.220 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -11.218 ; -11.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; -18.960 ; -18.960 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; -18.880 ; -18.880 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -8.508  ; -8.508  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; -15.934 ; -15.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; -16.625 ; -16.625 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; -16.625 ; -16.625 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -6.383  ; -6.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -6.823  ; -6.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -6.783  ; -6.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -6.946  ; -6.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -6.709  ; -6.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -6.623  ; -6.623  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -7.245  ; -7.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -6.383  ; -6.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -7.187  ; -7.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -6.935  ; -6.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -6.838  ; -6.838  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -6.853  ; -6.853  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -6.807  ; -6.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -6.964  ; -6.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -7.009  ; -7.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -6.727  ; -6.727  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -6.991  ; -6.991  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; -6.100  ; -6.100  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -11.318 ; -11.318 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; -9.947  ; -9.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; -11.253 ; -11.253 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -14.198 ; -14.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; -14.198 ; -14.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -12.675 ; -12.675 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -13.077 ; -13.077 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -12.758 ; -12.758 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -12.675 ; -12.675 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -12.097 ; -12.097 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -12.384 ; -12.384 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; -8.501  ; -8.501  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -14.632 ; -14.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -14.699 ; -14.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -14.634 ; -14.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -8.888  ; -8.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -8.888  ; -8.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -9.310  ; -9.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; -10.351 ; -10.351 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -10.671 ; -10.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -10.802 ; -10.802 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -4.638  ; -4.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -4.914  ; -4.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -7.500  ; -7.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -7.500  ; -7.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -9.027  ; -9.027  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -7.945  ; -7.945  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -7.941  ; -7.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -7.996  ; -7.996  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -8.874  ; -8.874  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -10.100 ; -10.100 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -10.743 ; -10.743 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -9.840  ; -9.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -11.013 ; -11.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -10.220 ; -10.220 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -10.574 ; -10.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -10.220 ; -10.220 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -11.218 ; -11.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -18.960 ; -18.960 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -18.880 ; -18.880 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -8.508  ; -8.508  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -15.934 ; -15.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -16.625 ; -16.625 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -16.625 ; -16.625 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -6.383  ; -6.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -6.823  ; -6.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -6.783  ; -6.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -6.946  ; -6.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -6.709  ; -6.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -6.623  ; -6.623  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -7.245  ; -7.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -6.383  ; -6.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -7.187  ; -7.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -6.935  ; -6.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -6.838  ; -6.838  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -6.853  ; -6.853  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -6.807  ; -6.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -6.964  ; -6.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -7.009  ; -7.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -6.727  ; -6.727  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -6.991  ; -6.991  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -6.100  ; -6.100  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -11.318 ; -11.318 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -9.947  ; -9.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -11.253 ; -11.253 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -14.198 ; -14.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -14.198 ; -14.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -12.675 ; -12.675 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -13.077 ; -13.077 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -12.758 ; -12.758 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -12.675 ; -12.675 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -12.097 ; -12.097 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -12.384 ; -12.384 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; -7.793  ; -7.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; -13.571 ; -13.571 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; -13.556 ; -13.556 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; -13.599 ; -13.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; -12.866 ; -12.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; -15.671 ; -15.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; -14.386 ; -14.386 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[5]     ; CLK_PLL1      ; -12.866 ; -12.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; -13.751 ; -13.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; -10.519 ; -10.519 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -9.329  ; -9.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; -6.864  ; -6.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; -6.879  ; -6.879  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; -7.884  ; -7.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; -6.884  ; -6.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; -7.045  ; -7.045  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; -7.372  ; -7.372  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; -8.253  ; -8.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; -9.065  ; -9.065  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; -9.843  ; -9.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; -8.190  ; -8.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; -6.956  ; -6.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; -6.864  ; -6.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; -8.749  ; -8.749  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; -9.136  ; -9.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; -7.605  ; -7.605  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; -7.781  ; -7.781  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; -8.211  ; -8.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; -9.578  ; -9.578  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; -9.578  ; -9.578  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; -9.644  ; -9.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; -13.240 ; -13.240 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; -18.339 ; -18.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; -18.259 ; -18.259 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; -12.198 ; -12.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; -15.313 ; -15.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; -7.202  ; -7.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; -14.975 ; -14.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; -13.826 ; -13.826 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; -12.267 ; -12.267 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; -7.618  ; -7.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; -7.428  ; -7.428  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; -7.202  ; -7.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; -7.389  ; -7.389  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; -14.372 ; -14.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -13.427 ; -13.427 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -15.668 ; -15.668 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -14.956 ; -14.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -14.629 ; -14.629 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -15.263 ; -15.263 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -13.471 ; -13.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -14.634 ; -14.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -13.661 ; -13.661 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -14.092 ; -14.092 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -16.296 ; -16.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -13.885 ; -13.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -14.056 ; -14.056 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -14.653 ; -14.653 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -13.427 ; -13.427 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -14.932 ; -14.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -15.471 ; -15.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -13.725 ; -13.725 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; -9.272  ; -9.272  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; -13.644 ; -13.644 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; -10.658 ; -10.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; -7.793  ; -7.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -13.571 ; -13.571 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -13.556 ; -13.556 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -13.599 ; -13.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -12.866 ; -12.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -15.671 ; -15.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -14.386 ; -14.386 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -12.866 ; -12.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -13.751 ; -13.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -10.519 ; -10.519 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -9.329  ; -9.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -6.864  ; -6.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -6.879  ; -6.879  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -7.884  ; -7.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -6.884  ; -6.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -7.045  ; -7.045  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -7.372  ; -7.372  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -8.253  ; -8.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -9.065  ; -9.065  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -9.843  ; -9.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -8.190  ; -8.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -6.956  ; -6.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -6.864  ; -6.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -8.749  ; -8.749  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -9.136  ; -9.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -7.605  ; -7.605  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -7.781  ; -7.781  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -8.211  ; -8.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -9.578  ; -9.578  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -9.578  ; -9.578  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -9.644  ; -9.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -13.240 ; -13.240 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -18.339 ; -18.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -18.259 ; -18.259 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -12.198 ; -12.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -15.313 ; -15.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -7.202  ; -7.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -14.975 ; -14.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -13.826 ; -13.826 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -12.267 ; -12.267 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -7.618  ; -7.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -7.428  ; -7.428  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -7.202  ; -7.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -7.389  ; -7.389  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -14.372 ; -14.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -13.427 ; -13.427 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -15.668 ; -15.668 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -14.956 ; -14.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -14.629 ; -14.629 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -15.263 ; -15.263 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -13.471 ; -13.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -14.634 ; -14.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -13.661 ; -13.661 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -14.092 ; -14.092 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -16.296 ; -16.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -13.885 ; -13.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -14.056 ; -14.056 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -14.653 ; -14.653 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -13.427 ; -13.427 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -14.932 ; -14.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -15.471 ; -15.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -13.725 ; -13.725 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -9.272  ; -9.272  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -13.644 ; -13.644 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -10.658 ; -10.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+---------+---------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                      ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 20.458 ; 20.458 ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 20.735 ; 20.735 ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 19.745 ; 19.745 ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 31.124 ; 31.124 ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 30.642 ; 30.642 ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 30.272 ; 30.272 ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 26.934 ; 26.934 ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 31.001 ; 31.001 ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 31.124 ; 31.124 ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 30.064 ; 30.064 ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 30.947 ; 30.947 ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 27.631 ; 27.631 ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 28.558 ; 28.558 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 27.156 ; 27.156 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 27.703 ; 27.703 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 27.270 ; 27.270 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 28.558 ; 28.558 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 27.647 ; 27.647 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 27.542 ; 27.542 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 25.694 ; 25.694 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 27.074 ; 27.074 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 25.997 ; 25.997 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 24.708 ; 24.708 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 23.156 ; 23.156 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 23.944 ; 23.944 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 23.856 ; 23.856 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 24.497 ; 24.497 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 25.807 ; 25.807 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 26.373 ; 26.373 ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 9.159  ; 9.159  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 30.053 ; 30.053 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 28.804 ; 28.804 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 28.235 ; 28.235 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 27.558 ; 27.558 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 28.509 ; 28.509 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 26.849 ; 26.849 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 30.053 ; 30.053 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 28.180 ; 28.180 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 29.495 ; 29.495 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 27.854 ; 27.854 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 24.860 ; 24.860 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 23.424 ; 23.424 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 25.105 ; 25.105 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 24.982 ; 24.982 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 24.733 ; 24.733 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 28.173 ; 28.173 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 26.695 ; 26.695 ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 13.616 ; 13.616 ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 7.985  ; 7.985  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 7.069  ; 7.069  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 20.261 ; 20.261 ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 20.261 ; 20.261 ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 22.682 ; 22.682 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 22.682 ; 22.682 ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 22.134 ; 22.134 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 19.661 ; 19.661 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 20.847 ; 20.847 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 19.335 ; 19.335 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 21.979 ; 21.979 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 20.719 ; 20.719 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 18.806 ; 18.806 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 19.149 ; 19.149 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 19.891 ; 19.891 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 21.237 ; 21.237 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 20.201 ; 20.201 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 18.583 ; 18.583 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 19.685 ; 19.685 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 19.686 ; 19.686 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 20.452 ; 20.452 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 22.134 ; 22.134 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 22.000 ; 22.000 ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 24.500 ; 24.500 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 21.309 ; 21.309 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 21.379 ; 21.379 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 19.623 ; 19.623 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 21.930 ; 21.930 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 19.921 ; 19.921 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 21.317 ; 21.317 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 21.635 ; 21.635 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 22.312 ; 22.312 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 23.094 ; 23.094 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 20.353 ; 20.353 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 18.851 ; 18.851 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 20.846 ; 20.846 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 20.812 ; 20.812 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 20.688 ; 20.688 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 24.500 ; 24.500 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 22.322 ; 22.322 ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 17.905 ; 17.905 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.905 ; 17.905 ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.746  ; 9.746  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 20.326 ; 20.326 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 20.326 ; 20.326 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 12.086 ; 12.086 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.524 ; 12.524 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.661 ; 12.661 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 11.152 ; 11.152 ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 9.442  ; 9.442  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 17.905 ; 17.905 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.905 ; 17.905 ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.746  ; 9.746  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 20.326 ; 20.326 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 20.326 ; 20.326 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 12.086 ; 12.086 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.524 ; 12.524 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.661 ; 12.661 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 11.152 ; 11.152 ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 9.442  ; 9.442  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 30.698 ; 30.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 30.975 ; 30.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 22.933 ; 22.933 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 19.626 ; 19.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 19.898 ; 19.898 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 19.702 ; 19.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 19.456 ; 19.456 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 19.630 ; 19.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 20.219 ; 20.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 18.990 ; 18.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 20.159 ; 20.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 19.749 ; 19.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 19.639 ; 19.639 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 19.672 ; 19.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 21.452 ; 21.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 21.851 ; 21.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 20.778 ; 20.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 22.731 ; 22.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 22.933 ; 22.933 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 21.435 ; 21.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 22.722 ; 22.722 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 21.687 ; 21.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 21.521 ; 21.521 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 21.831 ; 21.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 20.823 ; 20.823 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 20.729 ; 20.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 10.232 ; 10.232 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 4.042  ; 4.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 8.472  ; 8.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 7.095  ; 7.095  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 7.420  ; 7.420  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 28.273 ; 28.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 29.985 ; 29.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 41.364 ; 41.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 40.882 ; 40.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 40.512 ; 40.512 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 37.174 ; 37.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 41.241 ; 41.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 41.364 ; 41.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 40.304 ; 40.304 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 41.187 ; 41.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 37.871 ; 37.871 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 6.763  ; 6.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 6.175  ; 6.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 6.275  ; 6.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 7.903  ; 7.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 7.267  ; 7.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 6.570  ; 6.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 5.905  ; 5.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 8.079  ; 8.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 40.226 ; 40.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 38.634 ; 38.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 39.007 ; 39.007 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 38.679 ; 38.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 40.151 ; 40.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 39.625 ; 39.625 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 40.198 ; 40.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 38.215 ; 38.215 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 39.083 ; 39.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 40.226 ; 40.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 38.894 ; 38.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 37.269 ; 37.269 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 37.789 ; 37.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 37.640 ; 37.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 38.561 ; 38.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 38.589 ; 38.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 38.827 ; 38.827 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 9.481  ; 9.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 6.696  ; 6.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 9.835  ; 9.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 5.678  ; 5.678  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 5.903  ; 5.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 19.807 ; 19.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 19.807 ; 19.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 19.131 ; 19.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 19.487 ; 19.487 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 6.182  ; 6.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 6.505  ; 6.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 7.388  ; 7.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 8.074  ; 8.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 7.943  ; 7.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 7.889  ; 7.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 6.597  ; 6.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 7.967  ; 7.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 21.293 ; 21.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 21.205 ; 21.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 30.534 ; 30.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 30.464 ; 30.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 6.800  ; 6.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 5.246  ; 5.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 7.124  ; 7.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 10.449 ; 10.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 9.469  ; 9.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 8.269  ; 8.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 26.045 ; 26.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 26.986 ; 26.986 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 26.011 ; 26.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 26.357 ; 26.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 26.418 ; 26.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 27.822 ; 27.822 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 28.112 ; 28.112 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 30.703 ; 30.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 30.337 ; 30.337 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 27.012 ; 27.012 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 7.930  ; 7.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 10.376 ; 10.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 9.393  ; 9.393  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 9.331  ; 9.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 10.376 ; 10.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 9.938  ; 9.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 24.229 ; 24.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 7.751  ; 7.751  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 6.795  ; 6.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 9.568  ; 9.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 5.629  ; 5.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 6.850  ; 6.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.238  ; 6.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 8.974  ; 8.974  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 9.568  ; 9.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 9.339  ; 9.339  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 9.325  ; 9.325  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 5.952  ; 5.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 6.145  ; 6.145  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 9.769  ; 9.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 10.874 ; 10.874 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 31.123 ; 31.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 26.245 ; 26.245 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 24.218 ; 24.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 24.250 ; 24.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 25.329 ; 25.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 24.121 ; 24.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 27.176 ; 27.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 25.238 ; 25.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 25.471 ; 25.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 31.123 ; 31.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 25.816 ; 25.816 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 21.474 ; 21.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 22.660 ; 22.660 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 21.790 ; 21.790 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 29.480 ; 29.480 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 29.480 ; 29.480 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 27.458 ; 27.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 29.642 ; 29.642 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 29.638 ; 29.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 42.709 ; 42.709 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 40.282 ; 40.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 39.539 ; 39.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 38.967 ; 38.967 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 40.102 ; 40.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 38.827 ; 38.827 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 42.709 ; 42.709 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 40.701 ; 40.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 41.504 ; 41.504 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 42.083 ; 42.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 39.046 ; 39.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 37.537 ; 37.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 38.950 ; 38.950 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 38.766 ; 38.766 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 38.797 ; 38.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 40.955 ; 40.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 39.149 ; 39.149 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 30.828 ; 30.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 30.024 ; 30.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 29.076 ; 29.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 29.977 ; 29.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 30.543 ; 30.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 29.902 ; 29.902 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 11.501 ; 11.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 26.506 ; 26.506 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 26.125 ; 26.125 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 27.198 ; 27.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 26.777 ; 26.777 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 27.753 ; 27.753 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 26.639 ; 26.639 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 26.670 ; 26.670 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 12.811 ; 12.811 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 10.124 ; 10.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 7.581  ; 7.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 7.177  ; 7.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 13.257 ; 13.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 8.155  ; 8.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 7.804  ; 7.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 8.155  ; 8.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 7.487  ; 7.487  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 7.807  ; 7.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 7.133  ; 7.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 7.211  ; 7.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 7.181  ; 7.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 7.054  ; 7.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 6.130  ; 6.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 9.110  ; 9.110  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 5.120  ; 5.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 5.830  ; 5.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 9.641  ; 9.641  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 8.960  ; 8.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 7.918  ; 7.918  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 8.946  ; 8.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 10.869 ; 10.869 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 11.195 ; 11.195 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 6.829  ; 6.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 11.170 ; 11.170 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 7.951  ; 7.951  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 9.002  ; 9.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 9.071  ; 9.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 8.993  ; 8.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 9.071  ; 9.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 8.939  ; 8.939  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 9.039  ; 9.039  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 24.627 ; 24.627 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 7.107  ; 7.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 5.597  ; 5.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 8.344  ; 8.344  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 13.015 ; 13.015 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 14.385 ; 14.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 13.443 ; 13.443 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 17.872 ; 17.872 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 18.149 ; 18.149 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 8.089  ; 8.089  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 15.447 ; 14.770 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 17.159 ; 16.482 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 28.538 ; 28.538 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 28.056 ; 28.056 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 27.686 ; 27.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 24.348 ; 24.348 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 28.415 ; 28.415 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 28.538 ; 28.538 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 27.478 ; 27.478 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 28.361 ; 28.361 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 25.045 ; 25.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 27.372 ; 27.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 25.808 ; 25.808 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 26.181 ; 26.084 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 25.504 ; 25.853 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 27.325 ; 27.150 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 26.799 ; 26.630 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 27.372 ; 27.193 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 25.389 ; 25.268 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 26.257 ; 25.612 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 27.262 ; 27.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 25.645 ; 26.068 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 24.443 ; 24.057 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 24.963 ; 24.963 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 24.814 ; 24.346 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 25.735 ; 25.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 25.763 ; 25.763 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 26.001 ; 26.001 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 8.173  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 8.621  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 17.708 ; 17.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 17.638 ; 17.493 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 13.219 ; 12.975 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 14.160 ; 13.916 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 13.185 ; 12.941 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 13.531 ; 13.287 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 13.592 ; 13.348 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 14.996 ; 14.752 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 15.286 ; 14.609 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 17.877 ; 17.200 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 16.834 ; 17.511 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 13.509 ; 14.186 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 9.899  ; 9.899  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 17.268 ; 15.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 13.862 ; 13.862 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 13.018 ; 13.018 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 12.771 ; 12.771 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 12.594 ; 12.594 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 12.325 ; 12.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 15.518 ; 15.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 12.579 ; 12.579 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 12.982 ; 12.982 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 17.268 ; 13.639 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 13.967 ; 13.967 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 9.180  ; 9.180  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 9.914  ; 9.914  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 9.493  ; 9.493  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 15.625 ; 11.996 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 15.625 ; 11.996 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 13.603 ; 9.974  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 15.787 ; 12.158 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 12.154 ; 15.783 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 29.883 ; 29.704 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 27.456 ; 27.456 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 26.713 ; 26.616 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 25.792 ; 26.141 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 27.276 ; 27.101 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 26.001 ; 25.832 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 29.883 ; 29.704 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 27.875 ; 27.754 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 28.678 ; 28.033 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 29.119 ; 29.257 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 25.797 ; 26.220 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 24.711 ; 24.410 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 26.124 ; 26.124 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 25.940 ; 25.472 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 25.971 ; 25.810 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 28.129 ; 28.129 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 26.323 ; 26.323 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 16.973 ; 13.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 16.169 ; 12.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 11.592 ; 15.221 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 12.493 ; 16.122 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 16.688 ; 13.059 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 12.418 ; 16.047 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 12.879 ; 10.644 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 13.093 ; 10.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 14.372 ; 14.227 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 13.951 ; 8.140  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 14.927 ; 14.308 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 13.813 ; 12.627 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 13.844 ; 8.034  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 10.298 ; 10.298 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 30.698 ; 30.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 30.975 ; 30.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 22.933 ; 22.933 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 19.626 ; 19.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 19.898 ; 19.898 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 19.702 ; 19.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 19.456 ; 19.456 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 19.630 ; 19.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 20.219 ; 20.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 18.990 ; 18.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 20.159 ; 20.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 19.749 ; 19.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 19.639 ; 19.639 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 19.672 ; 19.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 21.452 ; 21.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 21.851 ; 21.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 20.778 ; 20.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 22.731 ; 22.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 22.933 ; 22.933 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 21.435 ; 21.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 22.722 ; 22.722 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 21.687 ; 21.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 21.521 ; 21.521 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 21.831 ; 21.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 20.823 ; 20.823 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 20.729 ; 20.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 10.232 ; 10.232 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 4.042  ; 4.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 8.472  ; 8.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 7.095  ; 7.095  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 7.420  ; 7.420  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 28.273 ; 28.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 29.985 ; 29.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 41.364 ; 41.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 40.882 ; 40.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 40.512 ; 40.512 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 37.174 ; 37.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 41.241 ; 41.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 41.364 ; 41.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 40.304 ; 40.304 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 41.187 ; 41.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 37.871 ; 37.871 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 6.763  ; 6.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 6.175  ; 6.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 6.275  ; 6.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 7.903  ; 7.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 7.267  ; 7.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 6.570  ; 6.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 5.905  ; 5.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 8.079  ; 8.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 40.226 ; 40.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 38.634 ; 38.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 39.007 ; 39.007 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 38.679 ; 38.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 40.151 ; 40.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 39.625 ; 39.625 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 40.198 ; 40.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 38.215 ; 38.215 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 39.083 ; 39.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 40.226 ; 40.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 38.894 ; 38.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 37.269 ; 37.269 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 37.789 ; 37.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 37.640 ; 37.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 38.561 ; 38.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 38.589 ; 38.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 38.827 ; 38.827 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 9.481  ; 9.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 6.696  ; 6.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 9.835  ; 9.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 5.678  ; 5.678  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 5.903  ; 5.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 19.807 ; 19.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 19.807 ; 19.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 19.131 ; 19.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 19.487 ; 19.487 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 6.182  ; 6.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 6.505  ; 6.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 7.388  ; 7.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 8.074  ; 8.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 7.943  ; 7.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 7.889  ; 7.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 6.597  ; 6.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 7.967  ; 7.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 21.293 ; 21.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 21.205 ; 21.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 30.534 ; 30.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 30.464 ; 30.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 6.800  ; 6.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 5.246  ; 5.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 7.124  ; 7.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 10.449 ; 10.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 9.469  ; 9.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 8.269  ; 8.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 26.045 ; 26.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 26.986 ; 26.986 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 26.011 ; 26.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 26.357 ; 26.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 26.418 ; 26.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 27.822 ; 27.822 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 28.112 ; 28.112 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 30.703 ; 30.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 30.337 ; 30.337 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 27.012 ; 27.012 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 7.930  ; 7.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 10.376 ; 10.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 9.393  ; 9.393  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 9.331  ; 9.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 10.376 ; 10.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 9.938  ; 9.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 24.229 ; 24.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 7.751  ; 7.751  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 6.795  ; 6.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 9.568  ; 9.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 5.629  ; 5.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 6.850  ; 6.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.238  ; 6.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 8.974  ; 8.974  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 9.568  ; 9.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 9.339  ; 9.339  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 9.325  ; 9.325  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 5.952  ; 5.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 6.145  ; 6.145  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 9.769  ; 9.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 10.874 ; 10.874 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 31.123 ; 31.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 26.245 ; 26.245 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 24.218 ; 24.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 24.250 ; 24.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 25.329 ; 25.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 24.121 ; 24.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 27.176 ; 27.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 25.238 ; 25.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 25.471 ; 25.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 31.123 ; 31.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 25.816 ; 25.816 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 21.474 ; 21.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 22.660 ; 22.660 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 21.790 ; 21.790 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 29.480 ; 29.480 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 29.480 ; 29.480 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 27.458 ; 27.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 29.642 ; 29.642 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 29.638 ; 29.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 42.709 ; 42.709 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 40.282 ; 40.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 39.539 ; 39.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 38.967 ; 38.967 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 40.102 ; 40.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 38.827 ; 38.827 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 42.709 ; 42.709 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 40.701 ; 40.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 41.504 ; 41.504 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 42.083 ; 42.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 39.046 ; 39.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 37.537 ; 37.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 38.950 ; 38.950 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 38.766 ; 38.766 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 38.797 ; 38.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 40.955 ; 40.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 39.149 ; 39.149 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 30.828 ; 30.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 30.024 ; 30.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 29.076 ; 29.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 29.977 ; 29.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 30.543 ; 30.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 29.902 ; 29.902 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 11.501 ; 11.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 26.506 ; 26.506 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 26.125 ; 26.125 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 27.198 ; 27.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 26.777 ; 26.777 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 27.753 ; 27.753 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 26.639 ; 26.639 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 26.670 ; 26.670 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 12.811 ; 12.811 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 10.124 ; 10.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 7.581  ; 7.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 7.177  ; 7.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 13.257 ; 13.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 8.155  ; 8.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 7.804  ; 7.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 8.155  ; 8.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 7.487  ; 7.487  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 7.807  ; 7.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 7.133  ; 7.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 7.211  ; 7.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 7.181  ; 7.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 7.054  ; 7.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 6.130  ; 6.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 9.110  ; 9.110  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 5.120  ; 5.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 5.830  ; 5.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 9.641  ; 9.641  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 8.960  ; 8.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 7.918  ; 7.918  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 8.946  ; 8.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 10.869 ; 10.869 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 11.195 ; 11.195 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 6.829  ; 6.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 11.170 ; 11.170 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 7.951  ; 7.951  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 9.002  ; 9.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 9.071  ; 9.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 8.993  ; 8.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 9.071  ; 9.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 8.939  ; 8.939  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 9.039  ; 9.039  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 24.627 ; 24.627 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 7.107  ; 7.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 5.597  ; 5.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 8.344  ; 8.344  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 13.015 ; 13.015 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 14.385 ; 14.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 13.443 ; 13.443 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 17.872 ; 17.872 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 18.149 ; 18.149 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 8.089  ; 8.089  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 15.447 ; 14.770 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 17.159 ; 16.482 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 28.538 ; 28.538 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 28.056 ; 28.056 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 27.686 ; 27.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 24.348 ; 24.348 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 28.415 ; 28.415 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 28.538 ; 28.538 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 27.478 ; 27.478 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 28.361 ; 28.361 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 25.045 ; 25.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 27.372 ; 27.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 25.808 ; 25.808 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 26.181 ; 26.084 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 25.504 ; 25.853 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 27.325 ; 27.150 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 26.799 ; 26.630 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 27.372 ; 27.193 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 25.389 ; 25.268 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 26.257 ; 25.612 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 27.262 ; 27.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 25.645 ; 26.068 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 24.443 ; 24.057 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 24.963 ; 24.963 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 24.814 ; 24.346 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 25.735 ; 25.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 25.763 ; 25.763 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 26.001 ; 26.001 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 8.173  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 8.621  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 17.708 ; 17.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 17.638 ; 17.493 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 13.219 ; 12.975 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 14.160 ; 13.916 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 13.185 ; 12.941 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 13.531 ; 13.287 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 13.592 ; 13.348 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 14.996 ; 14.752 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 15.286 ; 14.609 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 17.877 ; 17.200 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 16.834 ; 17.511 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 13.509 ; 14.186 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 9.899  ; 9.899  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 17.268 ; 15.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 13.862 ; 13.862 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 13.018 ; 13.018 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 12.771 ; 12.771 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 12.594 ; 12.594 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 12.325 ; 12.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 15.518 ; 15.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 12.579 ; 12.579 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 12.982 ; 12.982 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 17.268 ; 13.639 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 13.967 ; 13.967 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 9.180  ; 9.180  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 9.914  ; 9.914  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 9.493  ; 9.493  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 15.625 ; 11.996 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 15.625 ; 11.996 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 13.603 ; 9.974  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 15.787 ; 12.158 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 12.154 ; 15.783 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 29.883 ; 29.704 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 27.456 ; 27.456 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 26.713 ; 26.616 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 25.792 ; 26.141 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 27.276 ; 27.101 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 26.001 ; 25.832 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 29.883 ; 29.704 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 27.875 ; 27.754 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 28.678 ; 28.033 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 29.119 ; 29.257 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 25.797 ; 26.220 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 24.711 ; 24.410 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 26.124 ; 26.124 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 25.940 ; 25.472 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 25.971 ; 25.810 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 28.129 ; 28.129 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 26.323 ; 26.323 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 16.973 ; 13.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 16.169 ; 12.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 11.592 ; 15.221 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 12.493 ; 16.122 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 16.688 ; 13.059 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 12.418 ; 16.047 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 12.879 ; 10.644 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 13.093 ; 10.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 14.372 ; 14.227 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 13.951 ; 8.140  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 14.927 ; 14.308 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 13.813 ; 12.627 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 13.844 ; 8.034  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 10.298 ; 10.298 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 15.678 ; 15.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 15.955 ; 15.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 7.988  ; 7.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 6.667  ; 6.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 6.568  ; 6.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 14.965 ; 14.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 26.344 ; 26.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 25.862 ; 25.862 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 25.492 ; 25.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 22.154 ; 22.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 26.221 ; 26.221 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 26.344 ; 26.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 25.284 ; 25.284 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 26.167 ; 26.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 22.851 ; 22.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 8.525  ; 8.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 8.525  ; 8.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 7.094  ; 7.094  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 7.537  ; 7.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 6.895  ; 6.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 8.636  ; 8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 8.636  ; 8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 6.841  ; 6.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 7.405  ; 7.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 6.920  ; 6.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 15.471 ; 15.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 7.614  ; 7.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 7.614  ; 7.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 7.155  ; 7.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 6.332  ; 6.332  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 6.499  ; 6.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 23.778 ; 23.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 22.376 ; 22.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 22.923 ; 22.923 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 22.490 ; 22.490 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 23.778 ; 23.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 22.867 ; 22.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 22.762 ; 22.762 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 20.914 ; 20.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 22.294 ; 22.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 21.217 ; 21.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 19.928 ; 19.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 18.376 ; 18.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 19.164 ; 19.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 19.076 ; 19.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 19.717 ; 19.717 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 21.027 ; 21.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 21.593 ; 21.593 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 9.813  ; 9.813  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 8.354  ; 8.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 6.257  ; 6.257  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 6.421  ; 6.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 8.176  ; 8.176  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 16.272 ; 16.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 13.256 ; 13.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 13.114 ; 13.114 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 13.214 ; 13.214 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 13.117 ; 13.117 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 13.344 ; 13.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 16.272 ; 16.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 12.586 ; 12.586 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 12.879 ; 12.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 12.966 ; 12.966 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 14.270 ; 14.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 10.599 ; 10.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 11.393 ; 11.393 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 10.632 ; 10.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 10.391 ; 10.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 10.391 ; 10.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 6.869  ; 6.869  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 11.606 ; 11.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 11.594 ; 11.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 25.406 ; 25.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 24.024 ; 24.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 23.455 ; 23.455 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 22.778 ; 22.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 23.729 ; 23.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 22.069 ; 22.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 25.273 ; 25.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 23.408 ; 23.408 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 24.973 ; 24.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 25.406 ; 25.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 23.906 ; 23.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 22.974 ; 22.974 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 21.002 ; 21.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 23.188 ; 23.188 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 21.785 ; 21.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 23.965 ; 23.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 21.915 ; 21.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 12.780 ; 12.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 11.981 ; 11.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 11.027 ; 11.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 11.928 ; 11.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 12.531 ; 12.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 11.898 ; 11.898 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 10.873 ; 10.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 10.390 ; 10.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 9.386  ; 9.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 8.335  ; 8.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 8.429  ; 8.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 9.806  ; 9.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 8.843  ; 8.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 9.185  ; 9.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 11.034 ; 11.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 9.516  ; 9.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 7.088  ; 7.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 7.019  ; 7.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 7.088  ; 7.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 6.740  ; 6.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 6.843  ; 6.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 6.999  ; 6.999  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 15.678 ; 15.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 15.955 ; 15.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 7.988  ; 7.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 6.667  ; 6.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 6.568  ; 6.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 14.965 ; 14.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 26.344 ; 26.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 25.862 ; 25.862 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 25.492 ; 25.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 22.154 ; 22.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 26.221 ; 26.221 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 26.344 ; 26.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 25.284 ; 25.284 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 26.167 ; 26.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 22.851 ; 22.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 8.525  ; 8.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 8.525  ; 8.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 7.094  ; 7.094  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 7.537  ; 7.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 6.895  ; 6.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 8.636  ; 8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 8.636  ; 8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 6.841  ; 6.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 7.405  ; 7.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 6.920  ; 6.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 15.471 ; 15.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 7.614  ; 7.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 7.614  ; 7.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 7.155  ; 7.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 6.332  ; 6.332  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 6.499  ; 6.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 23.778 ; 23.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 22.376 ; 22.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 22.923 ; 22.923 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 22.490 ; 22.490 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 23.778 ; 23.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 22.867 ; 22.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 22.762 ; 22.762 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 20.914 ; 20.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 22.294 ; 22.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 21.217 ; 21.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 19.928 ; 19.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 18.376 ; 18.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 19.164 ; 19.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 19.076 ; 19.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 19.717 ; 19.717 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 21.027 ; 21.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 21.593 ; 21.593 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 9.813  ; 9.813  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 8.354  ; 8.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 6.257  ; 6.257  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 6.421  ; 6.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 8.176  ; 8.176  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 16.272 ; 16.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 13.256 ; 13.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 13.114 ; 13.114 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 13.214 ; 13.214 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 13.117 ; 13.117 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 13.344 ; 13.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 16.272 ; 16.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 12.586 ; 12.586 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 12.879 ; 12.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 12.966 ; 12.966 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 14.270 ; 14.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 10.599 ; 10.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 11.393 ; 11.393 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 10.632 ; 10.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 10.391 ; 10.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 10.391 ; 10.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 6.869  ; 6.869  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 11.606 ; 11.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 11.594 ; 11.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 25.406 ; 25.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 24.024 ; 24.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 23.455 ; 23.455 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 22.778 ; 22.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 23.729 ; 23.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 22.069 ; 22.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 25.273 ; 25.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 23.408 ; 23.408 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 24.973 ; 24.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 25.406 ; 25.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 23.906 ; 23.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 22.974 ; 22.974 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 21.002 ; 21.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 23.188 ; 23.188 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 21.785 ; 21.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 23.965 ; 23.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 21.915 ; 21.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 12.780 ; 12.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 11.981 ; 11.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 11.027 ; 11.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 11.928 ; 11.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 12.531 ; 12.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 11.898 ; 11.898 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 10.873 ; 10.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 10.390 ; 10.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 9.386  ; 9.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 8.335  ; 8.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 8.429  ; 8.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 9.806  ; 9.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 8.843  ; 8.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 9.185  ; 9.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 11.034 ; 11.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 9.516  ; 9.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 7.088  ; 7.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 7.019  ; 7.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 7.088  ; 7.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 6.740  ; 6.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 6.843  ; 6.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 6.999  ; 6.999  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 32.422 ; 32.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 30.802 ; 30.802 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 31.792 ; 31.792 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 31.018 ; 31.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 32.182 ; 32.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 32.422 ; 32.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 31.140 ; 31.140 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 29.656 ; 29.656 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 31.246 ; 31.246 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 31.557 ; 31.557 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 30.024 ; 30.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 29.122 ; 29.122 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 28.997 ; 28.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 28.481 ; 28.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 30.358 ; 30.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 27.666 ; 27.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 28.460 ; 28.460 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 13.657 ; 13.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 13.083 ; 13.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 13.129 ; 13.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 13.657 ; 13.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 13.638 ; 13.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 33.667 ; 33.667 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 32.450 ; 32.450 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 32.324 ; 32.324 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 31.306 ; 31.306 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 32.133 ; 32.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 31.624 ; 31.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 33.651 ; 33.651 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 32.142 ; 32.142 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 33.667 ; 33.667 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 33.414 ; 33.414 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 30.176 ; 30.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 29.390 ; 29.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 30.158 ; 30.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 29.607 ; 29.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 30.594 ; 30.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 30.032 ; 30.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 28.782 ; 28.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 32.422 ; 32.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 30.802 ; 30.802 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 31.792 ; 31.792 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 31.018 ; 31.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 32.182 ; 32.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 32.422 ; 32.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 31.140 ; 31.140 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 29.656 ; 29.656 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 31.246 ; 31.246 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 31.557 ; 31.557 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 30.024 ; 30.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 29.122 ; 29.122 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 28.997 ; 28.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 28.481 ; 28.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 30.358 ; 30.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 27.666 ; 27.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 28.460 ; 28.460 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 13.657 ; 13.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 13.083 ; 13.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 13.129 ; 13.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 13.657 ; 13.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 13.638 ; 13.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 33.667 ; 33.667 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 32.450 ; 32.450 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 32.324 ; 32.324 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 31.306 ; 31.306 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 32.133 ; 32.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 31.624 ; 31.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 33.651 ; 33.651 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 32.142 ; 32.142 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 33.667 ; 33.667 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 33.414 ; 33.414 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 30.176 ; 30.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 29.390 ; 29.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 30.158 ; 30.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 29.607 ; 29.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 30.594 ; 30.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 30.032 ; 30.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 28.782 ; 28.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.821  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.821  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 19.489 ; 19.489 ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 19.758 ; 19.758 ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 19.745 ; 19.745 ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 20.243 ; 20.243 ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 21.889 ; 21.889 ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 22.126 ; 22.126 ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 20.243 ; 20.243 ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 22.556 ; 22.556 ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 21.414 ; 21.414 ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 20.243 ; 20.243 ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 20.643 ; 20.643 ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 21.860 ; 21.860 ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 20.562 ; 20.562 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 22.813 ; 22.813 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 23.722 ; 23.722 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 22.262 ; 22.262 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 24.516 ; 24.516 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 24.115 ; 24.115 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 23.421 ; 23.421 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 21.405 ; 21.405 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 22.322 ; 22.322 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 24.596 ; 24.596 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 23.504 ; 23.504 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 22.217 ; 22.217 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 23.375 ; 23.375 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 23.111 ; 23.111 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 23.471 ; 23.471 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 20.562 ; 20.562 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 21.545 ; 21.545 ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 9.159  ; 9.159  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 21.867 ; 21.867 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 24.461 ; 24.461 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 24.254 ; 24.254 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 22.550 ; 22.550 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 24.467 ; 24.467 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 23.317 ; 23.317 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 25.932 ; 25.932 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 23.891 ; 23.891 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 24.743 ; 24.743 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 26.453 ; 26.453 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 23.656 ; 23.656 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 22.485 ; 22.485 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 24.536 ; 24.536 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 24.237 ; 24.237 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 23.707 ; 23.707 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 22.928 ; 22.928 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 21.867 ; 21.867 ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 13.616 ; 13.616 ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 7.985  ; 7.985  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 7.069  ; 7.069  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 20.261 ; 20.261 ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 20.261 ; 20.261 ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 22.682 ; 22.682 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 22.682 ; 22.682 ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 15.801 ; 15.801 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 17.064 ; 17.064 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 18.029 ; 18.029 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 16.673 ; 16.673 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 19.244 ; 19.244 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 17.998 ; 17.998 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 16.878 ; 16.878 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 15.921 ; 15.921 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 17.152 ; 17.152 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 18.994 ; 18.994 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 17.574 ; 17.574 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 15.801 ; 15.801 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 16.779 ; 16.779 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 16.265 ; 16.265 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 17.490 ; 17.490 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 18.926 ; 18.926 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 18.980 ; 18.980 ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 16.069 ; 16.069 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 18.712 ; 18.712 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 18.561 ; 18.561 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 16.961 ; 16.961 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 19.195 ; 19.195 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 17.200 ; 17.200 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 19.389 ; 19.389 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 18.407 ; 18.407 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 19.573 ; 19.573 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 20.851 ; 20.851 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 17.726 ; 17.726 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 16.069 ; 16.069 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 17.940 ; 17.940 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 17.391 ; 17.391 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 17.726 ; 17.726 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 21.292 ; 21.292 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 19.302 ; 19.302 ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 17.905 ; 17.905 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.905 ; 17.905 ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.746  ; 9.746  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 11.152 ; 11.152 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 20.326 ; 20.326 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 12.086 ; 12.086 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.524 ; 12.524 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.661 ; 12.661 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 11.152 ; 11.152 ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 9.442  ; 9.442  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 17.905 ; 17.905 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.905 ; 17.905 ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.746  ; 9.746  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 11.152 ; 11.152 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 20.326 ; 20.326 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 12.086 ; 12.086 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.524 ; 12.524 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.661 ; 12.661 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 11.152 ; 11.152 ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 9.442  ; 9.442  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 8.124  ; 8.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 8.394  ; 8.394  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 6.000  ; 6.000  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 9.653  ; 9.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 9.839  ; 9.839  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 9.564  ; 9.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 9.326  ; 9.326  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 8.779  ; 8.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 10.075 ; 10.075 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 9.146  ; 9.146  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 9.418  ; 9.418  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 9.442  ; 9.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 8.910  ; 8.910  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 9.135  ; 9.135  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 6.000  ; 6.000  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 7.409  ; 7.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 7.629  ; 7.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 7.988  ; 7.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 7.772  ; 7.772  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 7.599  ; 7.599  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 7.573  ; 7.573  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 7.539  ; 7.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 6.171  ; 6.171  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 9.726  ; 9.726  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 8.425  ; 8.425  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 8.176  ; 8.176  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 6.985  ; 6.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 4.042  ; 4.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 7.146  ; 7.146  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 6.871  ; 6.871  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 7.420  ; 7.420  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 12.018 ; 11.557 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 8.278  ; 8.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 7.076  ; 7.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 7.076  ; 7.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 7.296  ; 7.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 7.983  ; 7.983  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 7.540  ; 7.540  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 9.154  ; 9.154  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 7.983  ; 7.983  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 8.383  ; 8.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 8.858  ; 8.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 6.763  ; 6.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 6.175  ; 6.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 6.275  ; 6.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 4.697  ; 4.697  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 7.267  ; 7.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 6.570  ; 6.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 5.905  ; 5.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 7.931  ; 7.931  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 6.233  ; 6.233  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 7.009  ; 7.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 7.496  ; 7.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 7.155  ; 7.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 7.152  ; 7.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 7.697  ; 7.697  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 7.235  ; 7.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 6.530  ; 6.530  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 7.351  ; 7.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 6.545  ; 6.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 6.517  ; 6.517  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 6.753  ; 6.753  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 6.305  ; 6.305  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 6.822  ; 6.822  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 8.338  ; 8.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 6.233  ; 6.233  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 6.988  ; 6.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 9.238  ; 9.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 6.696  ; 6.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 7.599  ; 7.599  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 5.678  ; 5.678  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 5.903  ; 5.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 6.077  ; 6.077  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 7.394  ; 7.394  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 6.312  ; 6.312  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 6.077  ; 6.077  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 6.182  ; 6.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 6.505  ; 6.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 7.388  ; 7.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 8.074  ; 8.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 7.943  ; 7.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 7.889  ; 7.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 6.597  ; 6.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 7.967  ; 7.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 7.507  ; 7.507  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 7.768  ; 7.768  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 7.440  ; 7.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 7.370  ; 7.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 6.381  ; 6.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 5.246  ; 5.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 7.124  ; 7.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 7.332  ; 7.332  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 6.370  ; 6.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 8.269  ; 8.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 10.074 ; 10.909 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 11.851 ; 11.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 11.051 ; 11.263 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 11.397 ; 11.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 11.458 ; 11.670 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 12.862 ; 13.074 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 12.752 ; 12.029 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 15.343 ; 14.620 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 14.254 ; 14.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 9.881  ; 9.673  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 6.780  ; 6.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 6.746  ; 6.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 6.814  ; 6.814  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 6.746  ; 6.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 8.449  ; 8.449  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 7.588  ; 7.588  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 6.311  ; 6.311  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 7.751  ; 7.751  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 6.795  ; 6.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 5.629  ; 5.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 5.629  ; 5.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 6.850  ; 6.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.238  ; 6.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 8.647  ; 8.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 8.731  ; 8.731  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 9.141  ; 9.141  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 8.080  ; 8.080  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 5.952  ; 5.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 6.145  ; 6.145  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 8.270  ; 8.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 9.729  ; 9.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 9.180  ; 9.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 12.341 ; 12.341 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 11.948 ; 11.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 11.635 ; 11.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 11.566 ; 11.566 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 11.001 ; 11.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 13.213 ; 13.213 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 10.997 ; 10.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 11.108 ; 11.108 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 11.958 ; 13.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 13.967 ; 13.967 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 9.180  ; 9.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 9.914  ; 9.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 9.493  ; 9.493  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 9.160  ; 9.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 10.165 ; 10.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 9.160  ; 9.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 11.397 ; 11.700 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 11.696 ; 11.393 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 10.258 ; 10.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 12.187 ; 12.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 11.677 ; 11.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 11.984 ; 11.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 11.004 ; 11.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 11.525 ; 11.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 13.209 ; 13.209 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 12.358 ; 12.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 13.088 ; 13.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 12.755 ; 13.244 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 12.219 ; 12.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 10.258 ; 10.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 11.107 ; 11.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 10.969 ; 11.417 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 11.018 ; 11.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 11.545 ; 11.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 10.376 ; 10.644 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 12.583 ; 12.886 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 11.779 ; 12.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 11.134 ; 10.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 12.035 ; 11.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 12.298 ; 12.601 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 11.960 ; 11.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 9.982  ; 9.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 9.958  ; 9.623  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 9.236  ; 9.898  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 10.239 ; 10.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 8.140  ; 9.001  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 9.351  ; 9.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 9.267  ; 8.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 8.034  ; 8.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 8.442  ; 8.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 6.598  ; 6.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 7.581  ; 7.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 6.556  ; 6.556  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 6.337  ; 6.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 4.993  ; 4.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 5.726  ; 5.726  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 5.512  ; 5.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 5.447  ; 5.447  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 5.444  ; 5.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 5.281  ; 5.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 5.510  ; 5.510  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 5.182  ; 5.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 4.993  ; 4.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 6.130  ; 6.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 6.670  ; 6.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 5.120  ; 5.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 5.830  ; 5.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 7.810  ; 7.810  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 6.624  ; 6.624  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 7.203  ; 7.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 7.667  ; 7.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 9.045  ; 9.045  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 8.722  ; 8.722  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 6.829  ; 6.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 8.695  ; 8.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 7.951  ; 7.951  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 8.311  ; 8.311  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 6.324  ; 6.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 6.324  ; 6.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 7.054  ; 7.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 6.921  ; 6.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 6.827  ; 6.827  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 7.088  ; 7.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 7.107  ; 7.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 5.597  ; 5.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 8.344  ; 8.344  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 5.715  ; 5.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 6.581  ; 6.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 6.639  ; 6.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 12.928 ; 12.928 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 13.197 ; 13.197 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 6.648  ; 7.057  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 11.557 ; 12.018 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 13.751 ; 13.184 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 13.682 ; 13.682 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 15.328 ; 15.895 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 15.565 ; 16.132 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 13.682 ; 14.249 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 15.995 ; 16.562 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 14.853 ; 14.853 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 13.682 ; 13.682 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 14.082 ; 14.082 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 15.299 ; 15.299 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 13.018 ; 13.018 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 14.286 ; 14.012 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 14.813 ; 14.813 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 14.990 ; 14.990 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 16.397 ; 16.397 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 15.637 ; 15.637 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 14.456 ; 14.456 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 14.164 ; 14.059 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 15.239 ; 15.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 15.605 ; 15.605 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 14.755 ; 14.755 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 14.130 ; 14.130 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 13.615 ; 13.615 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 14.724 ; 15.158 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 16.514 ; 16.514 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 13.018 ; 13.018 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 13.117 ; 13.117 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 8.173  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 8.621  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 13.671 ; 13.575 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 13.601 ; 13.505 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 11.521 ; 10.074 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 11.016 ; 12.026 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 11.487 ; 11.051 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 11.833 ; 11.397 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 11.894 ; 11.458 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 13.298 ; 12.862 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 12.029 ; 12.752 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 14.620 ; 15.343 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 14.977 ; 14.254 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 9.673  ; 9.881  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 7.450  ; 8.721  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 9.180  ; 9.180  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 12.341 ; 12.341 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 11.948 ; 11.948 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 11.635 ; 11.635 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 11.566 ; 11.566 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 11.001 ; 11.001 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 13.213 ; 13.213 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 10.997 ; 10.997 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 11.108 ; 11.108 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 15.832 ; 11.958 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 13.967 ; 13.967 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 9.180  ; 9.180  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 9.914  ; 9.914  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 9.493  ; 9.493  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 12.167 ; 9.238  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 14.189 ; 10.165 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 12.167 ; 9.238  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 14.351 ; 11.397 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 11.393 ; 14.347 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 10.824 ; 10.376 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 12.187 ; 12.187 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 11.677 ; 11.677 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 12.366 ; 12.366 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 11.004 ; 11.004 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 11.525 ; 11.525 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 13.209 ; 13.209 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 12.358 ; 12.358 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 13.088 ; 13.088 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 13.244 ; 12.755 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 13.252 ; 12.804 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 11.904 ; 11.415 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 11.596 ; 11.107 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 11.417 ; 10.969 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 11.466 ; 11.018 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 11.993 ; 11.545 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 10.824 ; 10.376 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 15.537 ; 12.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 14.733 ; 11.779 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 10.831 ; 13.785 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 11.732 ; 14.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 15.252 ; 12.298 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 11.657 ; 14.611 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 9.623  ; 9.958  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 11.109 ; 9.236  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 10.335 ; 10.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 9.001  ; 8.140  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 9.079  ; 9.351  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 8.899  ; 9.536  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 8.351  ; 8.034  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 8.612  ; 9.120  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 8.124  ; 8.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 8.394  ; 8.394  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 6.000  ; 6.000  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 9.653  ; 9.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 9.839  ; 9.839  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 9.564  ; 9.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 9.326  ; 9.326  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 8.779  ; 8.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 10.075 ; 10.075 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 9.146  ; 9.146  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 9.418  ; 9.418  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 9.442  ; 9.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 8.910  ; 8.910  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 9.135  ; 9.135  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 6.000  ; 6.000  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 7.409  ; 7.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 7.629  ; 7.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 7.988  ; 7.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 7.772  ; 7.772  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 7.599  ; 7.599  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 7.573  ; 7.573  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 7.539  ; 7.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 6.171  ; 6.171  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 9.726  ; 9.726  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 8.425  ; 8.425  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 8.176  ; 8.176  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 6.985  ; 6.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 4.042  ; 4.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 7.146  ; 7.146  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 6.871  ; 6.871  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 7.420  ; 7.420  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 12.018 ; 11.557 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 8.278  ; 8.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 7.076  ; 7.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 7.076  ; 7.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 7.296  ; 7.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 7.983  ; 7.983  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 7.540  ; 7.540  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 9.154  ; 9.154  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 7.983  ; 7.983  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 8.383  ; 8.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 8.858  ; 8.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 6.763  ; 6.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 6.175  ; 6.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 6.275  ; 6.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 4.697  ; 4.697  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 7.267  ; 7.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 6.570  ; 6.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 5.905  ; 5.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 7.931  ; 7.931  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 6.233  ; 6.233  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 7.009  ; 7.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 7.496  ; 7.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 7.155  ; 7.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 7.152  ; 7.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 7.697  ; 7.697  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 7.235  ; 7.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.530  ; 6.530  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.351  ; 7.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.545  ; 6.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 6.517  ; 6.517  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 6.753  ; 6.753  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.305  ; 6.305  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 6.822  ; 6.822  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 8.338  ; 8.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 6.233  ; 6.233  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 6.988  ; 6.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 9.238  ; 9.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 6.696  ; 6.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 7.599  ; 7.599  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 5.678  ; 5.678  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 5.903  ; 5.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 6.077  ; 6.077  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 7.394  ; 7.394  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 6.312  ; 6.312  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 6.077  ; 6.077  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 6.182  ; 6.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 6.505  ; 6.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 7.388  ; 7.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 8.074  ; 8.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 7.943  ; 7.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 7.889  ; 7.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 6.597  ; 6.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 7.967  ; 7.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 7.507  ; 7.507  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 7.768  ; 7.768  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 7.440  ; 7.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 7.370  ; 7.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 6.381  ; 6.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 5.246  ; 5.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 7.124  ; 7.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 7.332  ; 7.332  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 6.370  ; 6.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 8.269  ; 8.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 10.074 ; 10.909 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 11.851 ; 11.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 11.051 ; 11.263 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 11.397 ; 11.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 11.458 ; 11.670 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 12.862 ; 13.074 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 12.752 ; 12.029 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 15.343 ; 14.620 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 14.254 ; 14.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 9.881  ; 9.673  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 6.780  ; 6.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 6.746  ; 6.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 6.814  ; 6.814  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 6.746  ; 6.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 8.449  ; 8.449  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 7.588  ; 7.588  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 6.311  ; 6.311  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 7.751  ; 7.751  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 6.795  ; 6.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 5.629  ; 5.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 5.629  ; 5.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 6.850  ; 6.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.238  ; 6.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 8.647  ; 8.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 8.731  ; 8.731  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 9.141  ; 9.141  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 8.080  ; 8.080  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 5.952  ; 5.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 6.145  ; 6.145  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 8.270  ; 8.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 9.729  ; 9.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 9.180  ; 9.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 12.341 ; 12.341 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 11.948 ; 11.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 11.635 ; 11.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 11.566 ; 11.566 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 11.001 ; 11.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 13.213 ; 13.213 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 10.997 ; 10.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 11.108 ; 11.108 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 11.958 ; 13.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 13.967 ; 13.967 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 9.180  ; 9.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 9.914  ; 9.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 9.493  ; 9.493  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 9.160  ; 9.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 10.165 ; 10.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 9.160  ; 9.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 11.397 ; 11.700 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 11.696 ; 11.393 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 10.258 ; 10.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 12.187 ; 12.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 11.677 ; 11.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 11.984 ; 11.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 11.004 ; 11.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 11.525 ; 11.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 13.209 ; 13.209 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 12.358 ; 12.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 13.088 ; 13.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 12.755 ; 13.244 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 12.219 ; 12.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 10.258 ; 10.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 11.107 ; 11.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 10.969 ; 11.417 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 11.018 ; 11.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 11.545 ; 11.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 10.376 ; 10.644 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 12.583 ; 12.886 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 11.779 ; 12.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 11.134 ; 10.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 12.035 ; 11.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 12.298 ; 12.601 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 11.960 ; 11.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 9.982  ; 9.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 9.958  ; 9.623  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 9.236  ; 9.898  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 10.239 ; 10.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 8.140  ; 9.001  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 9.351  ; 9.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 9.267  ; 8.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 8.034  ; 8.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 8.442  ; 8.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 6.598  ; 6.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 7.581  ; 7.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 6.556  ; 6.556  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 6.337  ; 6.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 4.993  ; 4.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 5.726  ; 5.726  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 5.512  ; 5.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 5.447  ; 5.447  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 5.444  ; 5.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 5.281  ; 5.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 5.510  ; 5.510  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 5.182  ; 5.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 4.993  ; 4.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 6.130  ; 6.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 6.670  ; 6.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 5.120  ; 5.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 5.830  ; 5.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 7.810  ; 7.810  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 6.624  ; 6.624  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 7.203  ; 7.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 7.667  ; 7.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 9.045  ; 9.045  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 8.722  ; 8.722  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 6.829  ; 6.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 8.695  ; 8.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 7.951  ; 7.951  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 8.311  ; 8.311  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 6.324  ; 6.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 6.324  ; 6.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 7.054  ; 7.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 6.921  ; 6.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 6.827  ; 6.827  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 7.088  ; 7.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 7.107  ; 7.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 5.597  ; 5.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 8.344  ; 8.344  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 5.715  ; 5.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 6.581  ; 6.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 6.639  ; 6.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 12.928 ; 12.928 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 13.197 ; 13.197 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 6.648  ; 7.057  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 11.557 ; 12.018 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 13.751 ; 13.184 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 13.682 ; 13.682 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 15.328 ; 15.895 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 15.565 ; 16.132 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 13.682 ; 14.249 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 15.995 ; 16.562 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 14.853 ; 14.853 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 13.682 ; 13.682 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 14.082 ; 14.082 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 15.299 ; 15.299 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 13.018 ; 13.018 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 14.286 ; 14.012 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 14.813 ; 14.813 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 14.990 ; 14.990 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 16.397 ; 16.397 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 15.637 ; 15.637 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 14.456 ; 14.456 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 14.164 ; 14.059 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 15.239 ; 15.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 15.605 ; 15.605 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 14.755 ; 14.755 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 14.130 ; 14.130 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 13.615 ; 13.615 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 14.724 ; 15.158 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 16.514 ; 16.514 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 13.018 ; 13.018 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 13.117 ; 13.117 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 8.173  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 8.621  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 13.671 ; 13.575 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 13.601 ; 13.505 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 11.521 ; 10.074 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 11.016 ; 12.026 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 11.487 ; 11.051 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 11.833 ; 11.397 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 11.894 ; 11.458 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 13.298 ; 12.862 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 12.029 ; 12.752 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 14.620 ; 15.343 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 14.977 ; 14.254 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 9.673  ; 9.881  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 7.450  ; 8.721  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 9.180  ; 9.180  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 12.341 ; 12.341 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 11.948 ; 11.948 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 11.635 ; 11.635 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 11.566 ; 11.566 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 11.001 ; 11.001 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 13.213 ; 13.213 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 10.997 ; 10.997 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 11.108 ; 11.108 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 15.832 ; 11.958 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 13.967 ; 13.967 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 9.180  ; 9.180  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 9.914  ; 9.914  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 9.493  ; 9.493  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 12.167 ; 9.238  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 14.189 ; 10.165 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 12.167 ; 9.238  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 14.351 ; 11.397 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 11.393 ; 14.347 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 10.824 ; 10.376 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 12.187 ; 12.187 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 11.677 ; 11.677 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 12.366 ; 12.366 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 11.004 ; 11.004 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 11.525 ; 11.525 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 13.209 ; 13.209 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 12.358 ; 12.358 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 13.088 ; 13.088 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 13.244 ; 12.755 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 13.252 ; 12.804 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 11.904 ; 11.415 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 11.596 ; 11.107 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 11.417 ; 10.969 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 11.466 ; 11.018 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 11.993 ; 11.545 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 10.824 ; 10.376 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 15.537 ; 12.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 14.733 ; 11.779 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 10.831 ; 13.785 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 11.732 ; 14.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 15.252 ; 12.298 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 11.657 ; 14.611 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 9.623  ; 9.958  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 11.109 ; 9.236  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 10.335 ; 10.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 9.001  ; 8.140  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 9.079  ; 9.351  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 8.899  ; 9.536  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 8.351  ; 8.034  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 8.612  ; 9.120  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 12.651 ; 12.651 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 12.920 ; 12.920 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 7.619  ; 7.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 6.667  ; 6.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 6.568  ; 6.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 12.907 ; 12.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 9.650  ; 9.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 9.650  ; 9.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 9.711  ; 9.711  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 12.706 ; 12.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 10.312 ; 10.312 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 14.576 ; 14.576 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 13.405 ; 13.405 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 13.805 ; 13.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 13.403 ; 13.403 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 6.763  ; 6.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 8.253  ; 8.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 7.086  ; 7.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 7.460  ; 7.460  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 6.763  ; 6.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 6.710  ; 6.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 8.222  ; 8.222  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 6.710  ; 6.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 6.844  ; 6.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 6.911  ; 6.911  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 7.284  ; 7.284  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 6.256  ; 6.256  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 7.341  ; 7.341  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 7.040  ; 7.040  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 6.256  ; 6.256  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 6.336  ; 6.336  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 9.613  ; 9.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 10.955 ; 10.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 11.817 ; 11.817 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 11.345 ; 11.345 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 14.447 ; 14.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 11.877 ; 11.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 11.762 ; 11.762 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 9.613  ; 9.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 10.627 ; 10.627 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 16.898 ; 16.898 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 15.609 ; 15.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 14.057 ; 14.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 14.845 ; 14.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 14.387 ; 14.387 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 15.398 ; 15.398 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 13.724 ; 13.724 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 14.707 ; 14.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 7.576  ; 7.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 7.705  ; 7.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 6.257  ; 6.257  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 6.421  ; 6.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 7.024  ; 7.024  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 7.015  ; 7.015  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 8.086  ; 8.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 8.048  ; 8.048  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 7.695  ; 7.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 8.100  ; 8.100  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 8.519  ; 8.519  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 8.481  ; 8.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 7.685  ; 7.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 7.653  ; 7.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 8.306  ; 8.306  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 8.556  ; 8.556  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 7.015  ; 7.015  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 7.870  ; 7.870  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 7.246  ; 7.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 6.869  ; 6.869  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 7.494  ; 7.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 6.869  ; 6.869  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 8.572  ; 8.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 8.560  ; 8.560  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 6.712  ; 6.712  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 9.705  ; 9.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 9.053  ; 9.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 8.300  ; 8.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 8.575  ; 8.575  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 7.101  ; 7.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 9.166  ; 9.166  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 8.316  ; 8.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 9.051  ; 9.051  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 9.407  ; 9.407  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 8.482  ; 8.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 7.798  ; 7.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 7.882  ; 7.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 8.308  ; 8.308  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 7.968  ; 7.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 8.456  ; 8.456  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 6.712  ; 6.712  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 9.746  ; 9.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 8.947  ; 8.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 7.993  ; 7.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 8.894  ; 8.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 9.149  ; 9.149  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 8.518  ; 8.518  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 7.733  ; 7.733  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 7.989  ; 7.989  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 9.386  ; 9.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 8.192  ; 8.192  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 8.227  ; 8.227  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 9.657  ; 9.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 8.461  ; 8.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 9.042  ; 9.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 10.885 ; 10.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 8.867  ; 8.867  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 2.964  ; 6.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 7.019  ; 7.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 7.088  ; 7.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 6.740  ; 6.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 6.843  ; 6.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 6.999  ; 6.999  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 12.651 ; 12.651 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 12.920 ; 12.920 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 7.619  ; 7.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 6.667  ; 6.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 6.568  ; 6.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 12.907 ; 12.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 9.650  ; 9.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 9.650  ; 9.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 9.711  ; 9.711  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 12.706 ; 12.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 10.312 ; 10.312 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 14.576 ; 14.576 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 13.405 ; 13.405 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 13.805 ; 13.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 13.403 ; 13.403 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 6.763  ; 6.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 8.253  ; 8.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 7.086  ; 7.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 7.460  ; 7.460  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 6.763  ; 6.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 6.710  ; 6.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 8.222  ; 8.222  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 6.710  ; 6.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 6.844  ; 6.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 6.911  ; 6.911  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 7.284  ; 7.284  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 6.256  ; 6.256  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 7.341  ; 7.341  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 7.040  ; 7.040  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 6.256  ; 6.256  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 6.336  ; 6.336  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 9.613  ; 9.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 10.955 ; 10.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 11.817 ; 11.817 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 11.345 ; 11.345 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 14.447 ; 14.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 11.877 ; 11.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 11.762 ; 11.762 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 9.613  ; 9.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 10.627 ; 10.627 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 16.898 ; 16.898 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 15.609 ; 15.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 14.057 ; 14.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 14.845 ; 14.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 14.387 ; 14.387 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 15.398 ; 15.398 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 13.724 ; 13.724 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 14.707 ; 14.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 7.576  ; 7.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 7.705  ; 7.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 6.257  ; 6.257  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 6.421  ; 6.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 7.024  ; 7.024  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 7.015  ; 7.015  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 8.086  ; 8.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 8.048  ; 8.048  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 7.695  ; 7.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 8.100  ; 8.100  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 8.519  ; 8.519  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 8.481  ; 8.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 7.685  ; 7.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 7.653  ; 7.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 8.306  ; 8.306  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 8.556  ; 8.556  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 7.015  ; 7.015  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 7.870  ; 7.870  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 7.246  ; 7.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 6.869  ; 6.869  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 7.494  ; 7.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 6.869  ; 6.869  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 8.572  ; 8.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 8.560  ; 8.560  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 6.712  ; 6.712  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 9.705  ; 9.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 9.053  ; 9.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 8.300  ; 8.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 8.575  ; 8.575  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 7.101  ; 7.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 9.166  ; 9.166  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 8.316  ; 8.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 9.051  ; 9.051  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 9.407  ; 9.407  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 8.482  ; 8.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 7.798  ; 7.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 7.882  ; 7.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 8.308  ; 8.308  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 7.968  ; 7.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 8.456  ; 8.456  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 6.712  ; 6.712  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 9.746  ; 9.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 8.947  ; 8.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 7.993  ; 7.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 8.894  ; 8.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 9.149  ; 9.149  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 8.518  ; 8.518  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 7.733  ; 7.733  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 7.989  ; 7.989  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 9.386  ; 9.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 8.192  ; 8.192  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 8.227  ; 8.227  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 9.657  ; 9.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 8.461  ; 8.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 9.042  ; 9.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 10.885 ; 10.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 8.867  ; 8.867  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 2.964  ; 6.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 7.019  ; 7.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 7.088  ; 7.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 6.740  ; 6.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 6.843  ; 6.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 6.999  ; 6.999  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 13.269 ; 13.269 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 16.147 ; 16.147 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 16.646 ; 16.646 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 16.213 ; 16.213 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 17.923 ; 17.923 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 16.143 ; 16.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 16.738 ; 16.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 15.014 ; 15.014 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 15.621 ; 15.621 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 16.196 ; 16.196 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 16.185 ; 16.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 14.870 ; 14.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 15.550 ; 15.550 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 14.685 ; 14.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 16.258 ; 16.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 13.269 ; 13.269 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 14.252 ; 14.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 6.978  ; 6.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 7.216  ; 7.216  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 6.978  ; 6.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 7.633  ; 7.633  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 7.572  ; 7.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 14.574 ; 14.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 17.795 ; 17.795 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 17.178 ; 17.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 16.501 ; 16.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 17.874 ; 17.874 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 15.345 ; 15.345 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 19.249 ; 19.249 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 17.500 ; 17.500 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 18.042 ; 18.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 18.053 ; 18.053 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 16.337 ; 16.337 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 15.138 ; 15.138 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 16.711 ; 16.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 15.811 ; 15.811 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 16.494 ; 16.494 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 15.635 ; 15.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 14.574 ; 14.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 13.269 ; 13.269 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 16.147 ; 16.147 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 16.646 ; 16.646 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 16.213 ; 16.213 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 17.923 ; 17.923 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 16.143 ; 16.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 16.738 ; 16.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 15.014 ; 15.014 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 15.621 ; 15.621 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 16.196 ; 16.196 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 16.185 ; 16.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 14.870 ; 14.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 15.550 ; 15.550 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 14.685 ; 14.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 16.258 ; 16.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 13.269 ; 13.269 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 14.252 ; 14.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 6.978  ; 6.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 7.216  ; 7.216  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 6.978  ; 6.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 7.633  ; 7.633  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 7.572  ; 7.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 14.574 ; 14.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 17.795 ; 17.795 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 17.178 ; 17.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 16.501 ; 16.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 17.874 ; 17.874 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 15.345 ; 15.345 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 19.249 ; 19.249 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 17.500 ; 17.500 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 18.042 ; 18.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 18.053 ; 18.053 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 16.337 ; 16.337 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 15.138 ; 15.138 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 16.711 ; 16.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 15.811 ; 15.811 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 16.494 ; 16.494 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 15.635 ; 15.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 14.574 ; 14.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.821  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.821  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------+
; Propagation Delay                                                ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 18.172 ; 18.172 ; 18.172 ; 18.172 ;
; ASn          ; ACSI_WRn      ; 18.449 ; 18.449 ; 18.449 ; 18.449 ;
; ASn          ; BUTTONn       ; 21.015 ;        ;        ; 21.015 ;
; ASn          ; CA1_OUT       ; 17.459 ;        ;        ; 17.459 ;
; ASn          ; CD[0]         ; 28.356 ; 28.356 ; 28.356 ; 28.356 ;
; ASn          ; CD[1]         ; 27.986 ; 27.986 ; 27.986 ; 27.986 ;
; ASn          ; CD[2]         ; 24.648 ; 24.648 ; 24.648 ; 24.648 ;
; ASn          ; CD[3]         ; 28.715 ; 28.715 ; 28.715 ; 28.715 ;
; ASn          ; CD[4]         ; 28.838 ; 28.838 ; 28.838 ; 28.838 ;
; ASn          ; CD[5]         ; 27.778 ; 27.778 ; 27.778 ; 27.778 ;
; ASn          ; CD[6]         ; 28.661 ; 28.661 ; 28.661 ; 28.661 ;
; ASn          ; CD[7]         ; 25.345 ; 25.345 ; 25.345 ; 25.345 ;
; ASn          ; DATA[0]       ; 30.522 ; 30.236 ; 30.236 ; 30.522 ;
; ASn          ; DATA[1]       ; 31.555 ; 31.049 ; 31.049 ; 31.555 ;
; ASn          ; DATA[2]       ; 31.130 ; 30.303 ; 30.303 ; 31.130 ;
; ASn          ; DATA[3]       ; 32.242 ; 31.313 ; 31.313 ; 32.242 ;
; ASn          ; DATA[4]       ; 31.638 ; 31.538 ; 31.538 ; 31.638 ;
; ASn          ; DATA[5]       ; 31.103 ; 32.076 ; 32.076 ; 31.103 ;
; ASn          ; DATA[6]       ; 30.216 ; 29.559 ; 29.559 ; 30.216 ;
; ASn          ; DATA[7]       ; 30.728 ; 29.794 ; 29.794 ; 30.728 ;
; ASn          ; DATA[8]       ; 30.595 ; 30.733 ; 30.733 ; 30.595 ;
; ASn          ; DATA[9]       ; 29.648 ; 30.039 ; 30.039 ; 29.648 ;
; ASn          ; DATA[10]      ; 28.439 ; 27.911 ; 27.911 ; 28.439 ;
; ASn          ; DATA[11]      ; 29.671 ; 29.671 ; 29.671 ; 29.671 ;
; ASn          ; DATA[12]      ; 29.007 ; 28.359 ; 28.359 ; 29.007 ;
; ASn          ; DATA[13]      ; 29.979 ; 29.979 ; 29.979 ; 29.979 ;
; ASn          ; DATA[14]      ; 30.003 ; 30.003 ; 30.003 ; 30.003 ;
; ASn          ; DATA[15]      ; 30.569 ; 30.569 ; 30.569 ; 30.569 ;
; ASn          ; DTACKn        ; 21.786 ; 21.786 ; 21.786 ; 21.786 ;
; ASn          ; FLASH_CEn     ; 18.663 ;        ;        ; 18.663 ;
; ASn          ; FLASH_OEn     ; 18.593 ;        ;        ; 18.593 ;
; ASn          ; IDE_CS0n      ; 13.444 ;        ;        ; 13.444 ;
; ASn          ; IDE_CS1n      ; 14.385 ;        ;        ; 14.385 ;
; ASn          ; IDE_D_EN_INn  ; 13.942 ;        ;        ; 13.942 ;
; ASn          ; IDE_D_EN_OUTn ; 13.756 ;        ;        ; 13.756 ;
; ASn          ; IDE_IORDn     ; 13.562 ;        ;        ; 13.562 ;
; ASn          ; IDE_IOWRn     ; 14.978 ;        ;        ; 14.978 ;
; ASn          ; JOY_RHn       ; 16.667 ;        ;        ; 16.667 ;
; ASn          ; JOY_RLn       ; 19.258 ;        ;        ; 19.258 ;
; ASn          ; JOY_WEn       ;        ; 18.892 ; 18.892 ;        ;
; ASn          ; JOY_WL        ;        ; 13.471 ; 13.471 ;        ;
; ASn          ; RAM_ADR[8]    ;        ; 18.145 ; 18.145 ;        ;
; ASn          ; RAM_BA[0]     ;        ; 16.502 ; 16.502 ;        ;
; ASn          ; RAM_BA[1]     ;        ; 14.480 ; 14.480 ;        ;
; ASn          ; RAM_CAS0n     ;        ; 16.664 ; 16.664 ;        ;
; ASn          ; RAM_CAS1n     ; 16.660 ;        ;        ; 16.660 ;
; ASn          ; RAM_DATA[0]   ; 32.170 ; 31.884 ; 31.884 ; 32.170 ;
; ASn          ; RAM_DATA[1]   ; 32.087 ; 31.581 ; 31.581 ; 32.087 ;
; ASn          ; RAM_DATA[2]   ; 31.418 ; 30.591 ; 30.591 ; 31.418 ;
; ASn          ; RAM_DATA[3]   ; 32.193 ; 31.264 ; 31.264 ; 32.193 ;
; ASn          ; RAM_DATA[4]   ; 30.840 ; 30.740 ; 30.740 ; 30.840 ;
; ASn          ; RAM_DATA[5]   ; 33.614 ; 34.587 ; 34.587 ; 33.614 ;
; ASn          ; RAM_DATA[6]   ; 32.702 ; 32.045 ; 32.045 ; 32.702 ;
; ASn          ; RAM_DATA[7]   ; 33.149 ; 32.215 ; 32.215 ; 33.149 ;
; ASn          ; RAM_DATA[8]   ; 32.452 ; 32.590 ; 32.590 ; 32.452 ;
; ASn          ; RAM_DATA[9]   ; 29.800 ; 30.191 ; 30.191 ; 29.800 ;
; ASn          ; RAM_DATA[10]  ; 28.707 ; 28.179 ; 28.179 ; 28.707 ;
; ASn          ; RAM_DATA[11]  ; 30.832 ; 30.832 ; 30.832 ; 30.832 ;
; ASn          ; RAM_DATA[12]  ; 30.133 ; 29.485 ; 29.485 ; 30.133 ;
; ASn          ; RAM_DATA[13]  ; 30.215 ; 30.215 ; 30.215 ; 30.215 ;
; ASn          ; RAM_DATA[14]  ; 32.369 ; 32.369 ; 32.369 ; 32.369 ;
; ASn          ; RAM_DATA[15]  ; 30.891 ; 30.891 ; 30.891 ; 30.891 ;
; ASn          ; RAM_DQM0H     ;        ; 17.850 ; 17.850 ;        ;
; ASn          ; RAM_DQM0L     ;        ; 17.046 ; 17.046 ;        ;
; ASn          ; RAM_DQM1H     ; 16.098 ;        ;        ; 16.098 ;
; ASn          ; RAM_DQM1L     ; 16.999 ;        ;        ; 16.999 ;
; ASn          ; RAM_RAS0n     ;        ; 17.565 ; 17.565 ;        ;
; ASn          ; RAM_RAS1n     ; 16.924 ;        ;        ; 16.924 ;
; ASn          ; ROM0n         ; 17.610 ;        ;        ; 17.610 ;
; ASn          ; ROM1n         ; 17.229 ;        ;        ; 17.229 ;
; ASn          ; ROM2n         ; 15.327 ;        ;        ; 15.327 ;
; ASn          ; ROM3n         ; 17.515 ;        ;        ; 17.515 ;
; ASn          ; ROM4n         ; 18.810 ;        ;        ; 18.810 ;
; ASn          ; ROM5n         ; 14.300 ;        ;        ; 14.300 ;
; ASn          ; ROM6n         ; 17.723 ;        ;        ; 17.723 ;
; COM_CTS      ; DATA[2]       ;        ; 22.061 ; 22.061 ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 22.349 ; 22.349 ;        ;
; COM_DCD      ; DATA[1]       ;        ; 22.235 ; 22.235 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 22.767 ; 22.767 ;        ;
; COM_RI       ; DATA[6]       ;        ; 21.072 ; 21.072 ;        ;
; COM_RI       ; RAM_DATA[6]   ;        ; 23.558 ; 23.558 ;        ;
; CONFIG[1]    ; DATA[7]       ; 24.247 ; 24.247 ; 24.247 ; 24.247 ;
; CONFIG[1]    ; HSYNC         ; 14.469 ; 14.469 ; 14.469 ; 14.469 ;
; CONFIG[1]    ; RAM_DATA[7]   ; 26.668 ; 26.668 ; 26.668 ; 26.668 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 16.363 ; 16.363 ; 16.363 ; 16.363 ;
; CONFIG[1]    ; RAM_DATA[13]  ; 16.801 ; 16.801 ; 16.801 ; 16.801 ;
; CONFIG[1]    ; RAM_DATA[14]  ; 16.938 ; 16.938 ; 16.938 ; 16.938 ;
; CONFIG[1]    ; RAM_DATA[15]  ; 15.429 ; 15.429 ; 15.429 ; 15.429 ;
; CONFIG[1]    ; VSYNC         ; 14.171 ; 14.171 ; 14.171 ; 14.171 ;
; CONFIG[2]    ; DATA[7]       ; 22.962 ; 22.962 ; 22.962 ; 22.962 ;
; CONFIG[2]    ; HSYNC         ; 14.304 ; 14.304 ; 14.304 ; 14.304 ;
; CONFIG[2]    ; RAM_DATA[7]   ; 25.383 ; 25.383 ; 25.383 ; 25.383 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 16.565 ; 16.565 ; 16.565 ; 16.565 ;
; CONFIG[2]    ; RAM_DATA[13]  ; 17.003 ; 17.003 ; 17.003 ; 17.003 ;
; CONFIG[2]    ; RAM_DATA[14]  ; 17.140 ; 17.140 ; 17.140 ; 17.140 ;
; CONFIG[2]    ; RAM_DATA[15]  ; 15.631 ; 15.631 ; 15.631 ; 15.631 ;
; CONFIG[2]    ; VSYNC         ; 14.001 ; 14.001 ; 14.001 ; 14.001 ;
; CONFIG[3]    ; LDSn          ; 23.789 ; 24.013 ; 24.013 ; 23.789 ;
; CONFIG[3]    ; UDSn          ; 24.187 ; 24.411 ; 24.411 ; 24.187 ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 16.269 ; 16.269 ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 14.226 ; 14.226 ;        ;
; CONFIG[5]    ; ACSI_RDn      ; 26.021 ; 26.021 ; 26.021 ; 26.021 ;
; CONFIG[5]    ; ACSI_WRn      ; 26.298 ; 26.298 ; 26.298 ; 26.298 ;
; CONFIG[5]    ; BUTTONn       ; 23.596 ; 21.361 ; 21.361 ; 23.596 ;
; CONFIG[5]    ; CA1_OUT       ; 25.308 ; 23.073 ; 23.073 ; 25.308 ;
; CONFIG[5]    ; CD[0]         ; 36.205 ; 36.205 ; 36.205 ; 36.205 ;
; CONFIG[5]    ; CD[1]         ; 35.835 ; 35.835 ; 35.835 ; 35.835 ;
; CONFIG[5]    ; CD[2]         ; 32.497 ; 32.497 ; 32.497 ; 32.497 ;
; CONFIG[5]    ; CD[3]         ; 36.564 ; 36.564 ; 36.564 ; 36.564 ;
; CONFIG[5]    ; CD[4]         ; 36.687 ; 36.687 ; 36.687 ; 36.687 ;
; CONFIG[5]    ; CD[5]         ; 35.627 ; 35.627 ; 35.627 ; 35.627 ;
; CONFIG[5]    ; CD[6]         ; 36.510 ; 36.510 ; 36.510 ; 36.510 ;
; CONFIG[5]    ; CD[7]         ; 33.194 ; 33.194 ; 33.194 ; 33.194 ;
; CONFIG[5]    ; DATA[0]       ; 33.957 ; 33.957 ; 33.957 ; 33.957 ;
; CONFIG[5]    ; DATA[1]       ; 34.330 ; 34.233 ; 34.233 ; 34.330 ;
; CONFIG[5]    ; DATA[2]       ; 33.653 ; 34.002 ; 34.002 ; 33.653 ;
; CONFIG[5]    ; DATA[3]       ; 35.474 ; 35.299 ; 35.299 ; 35.474 ;
; CONFIG[5]    ; DATA[4]       ; 34.948 ; 34.779 ; 34.779 ; 34.948 ;
; CONFIG[5]    ; DATA[5]       ; 35.521 ; 35.342 ; 35.342 ; 35.521 ;
; CONFIG[5]    ; DATA[6]       ; 33.538 ; 33.417 ; 33.417 ; 33.538 ;
; CONFIG[5]    ; DATA[7]       ; 34.406 ; 33.761 ; 33.761 ; 34.406 ;
; CONFIG[5]    ; DATA[8]       ; 35.411 ; 35.549 ; 35.549 ; 35.411 ;
; CONFIG[5]    ; DATA[9]       ; 33.794 ; 34.217 ; 34.217 ; 33.794 ;
; CONFIG[5]    ; DATA[10]      ; 32.592 ; 32.206 ; 32.206 ; 32.592 ;
; CONFIG[5]    ; DATA[11]      ; 33.112 ; 33.112 ; 33.112 ; 33.112 ;
; CONFIG[5]    ; DATA[12]      ; 32.963 ; 32.495 ; 32.495 ; 32.963 ;
; CONFIG[5]    ; DATA[13]      ; 33.884 ; 33.723 ; 33.723 ; 33.884 ;
; CONFIG[5]    ; DATA[14]      ; 33.912 ; 33.912 ; 33.912 ; 33.912 ;
; CONFIG[5]    ; DATA[15]      ; 34.150 ; 34.150 ; 34.150 ; 34.150 ;
; CONFIG[5]    ; DTACKn        ; 27.961 ; 27.961 ; 27.961 ; 27.961 ;
; CONFIG[5]    ; FLASH_CEn     ; 25.857 ; 25.712 ; 25.712 ; 25.857 ;
; CONFIG[5]    ; FLASH_OEn     ; 25.787 ; 25.642 ; 25.642 ; 25.787 ;
; CONFIG[5]    ; IDE_CS0n      ; 21.368 ; 19.133 ; 19.133 ; 21.368 ;
; CONFIG[5]    ; IDE_CS1n      ; 22.309 ; 20.074 ; 20.074 ; 22.309 ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 21.334 ; 19.099 ; 19.099 ; 21.334 ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 21.680 ; 19.445 ; 19.445 ; 21.680 ;
; CONFIG[5]    ; IDE_IORDn     ; 21.741 ; 19.506 ; 19.506 ; 21.741 ;
; CONFIG[5]    ; IDE_IOWRn     ; 23.145 ; 20.910 ; 20.910 ; 23.145 ;
; CONFIG[5]    ; JOY_RHn       ; 23.435 ; 21.200 ; 21.200 ; 23.435 ;
; CONFIG[5]    ; JOY_RLn       ; 26.026 ; 23.791 ; 23.791 ; 26.026 ;
; CONFIG[5]    ; JOY_WEn       ; 23.425 ; 25.660 ; 25.660 ; 23.425 ;
; CONFIG[5]    ; JOY_WL        ; 20.100 ; 22.335 ; 22.335 ; 20.100 ;
; CONFIG[5]    ; RAM_ADR[8]    ; 25.841 ; 24.211 ; 24.211 ; 25.841 ;
; CONFIG[5]    ; RAM_BA[0]     ; 24.198 ; 22.568 ; 22.568 ; 24.198 ;
; CONFIG[5]    ; RAM_BA[1]     ; 22.176 ; 20.546 ; 20.546 ; 22.176 ;
; CONFIG[5]    ; RAM_CAS0n     ; 24.360 ; 22.730 ; 22.730 ; 24.360 ;
; CONFIG[5]    ; RAM_CAS1n     ; 22.726 ; 24.356 ; 24.356 ; 22.726 ;
; CONFIG[5]    ; RAM_DATA[0]   ; 35.605 ; 35.605 ; 35.605 ; 35.605 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 34.862 ; 34.765 ; 34.765 ; 34.862 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 33.941 ; 34.290 ; 34.290 ; 33.941 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 35.425 ; 35.250 ; 35.250 ; 35.425 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 34.150 ; 33.981 ; 33.981 ; 34.150 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 38.032 ; 37.853 ; 37.853 ; 38.032 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 36.024 ; 35.903 ; 35.903 ; 36.024 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 36.827 ; 36.182 ; 36.182 ; 36.827 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 37.268 ; 37.406 ; 37.406 ; 37.268 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 33.946 ; 34.369 ; 34.369 ; 33.946 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 32.860 ; 32.474 ; 32.474 ; 32.860 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 34.273 ; 34.273 ; 34.273 ; 34.273 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 34.089 ; 33.621 ; 33.621 ; 34.089 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 34.120 ; 33.959 ; 33.959 ; 34.120 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 36.278 ; 36.278 ; 36.278 ; 36.278 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 34.472 ; 34.472 ; 34.472 ; 34.472 ;
; CONFIG[5]    ; RAM_DQM0H     ; 25.546 ; 23.916 ; 23.916 ; 25.546 ;
; CONFIG[5]    ; RAM_DQM0L     ; 24.742 ; 23.112 ; 23.112 ; 24.742 ;
; CONFIG[5]    ; RAM_DQM1H     ; 22.164 ; 23.794 ; 23.794 ; 22.164 ;
; CONFIG[5]    ; RAM_DQM1L     ; 23.065 ; 24.695 ; 24.695 ; 23.065 ;
; CONFIG[5]    ; RAM_RAS0n     ; 25.261 ; 23.631 ; 23.631 ; 25.261 ;
; CONFIG[5]    ; RAM_RAS1n     ; 22.990 ; 24.620 ; 24.620 ; 22.990 ;
; CONFIG[5]    ; ROM0n         ; 21.025 ; 19.594 ; 19.594 ; 21.025 ;
; CONFIG[5]    ; ROM1n         ; 21.242 ; 19.213 ; 19.213 ; 21.242 ;
; CONFIG[5]    ; ROM2n         ; 22.521 ; 22.376 ; 22.376 ; 22.521 ;
; CONFIG[5]    ; ROM3n         ; 22.100 ; 19.865 ; 19.865 ; 22.100 ;
; CONFIG[5]    ; ROM4n         ; 23.076 ; 22.457 ; 22.457 ; 23.076 ;
; CONFIG[5]    ; ROM5n         ; 21.962 ; 20.776 ; 20.776 ; 21.962 ;
; CONFIG[5]    ; ROM6n         ; 21.993 ; 19.758 ; 19.758 ; 21.993 ;
; CONFIG[6]    ; DATA[0]       ; 24.513 ; 24.513 ; 24.513 ; 24.513 ;
; CONFIG[6]    ; DATA[1]       ; 23.547 ; 23.547 ; 23.547 ; 23.547 ;
; CONFIG[6]    ; DATA[2]       ; 24.567 ; 24.567 ; 24.567 ; 24.567 ;
; CONFIG[6]    ; DATA[3]       ; 24.087 ; 24.087 ; 24.087 ; 24.087 ;
; CONFIG[6]    ; DATA[4]       ; 24.297 ; 24.297 ; 24.297 ; 24.297 ;
; CONFIG[6]    ; DATA[5]       ; 25.485 ; 25.485 ; 25.485 ; 25.485 ;
; CONFIG[6]    ; DATA[6]       ; 23.780 ; 23.780 ; 23.780 ; 23.780 ;
; CONFIG[6]    ; DATA[7]       ; 22.437 ; 22.437 ; 22.437 ; 22.437 ;
; CONFIG[6]    ; DATA[8]       ; 24.693 ; 24.693 ; 24.693 ; 24.693 ;
; CONFIG[6]    ; DATA[9]       ; 24.521 ; 24.521 ; 24.521 ; 24.521 ;
; CONFIG[6]    ; DATA[10]      ; 23.556 ; 23.556 ; 23.556 ; 23.556 ;
; CONFIG[6]    ; DATA[11]      ; 24.102 ; 24.102 ; 24.102 ; 24.102 ;
; CONFIG[6]    ; DATA[12]      ; 22.932 ; 22.932 ; 22.932 ; 22.932 ;
; CONFIG[6]    ; DATA[13]      ; 23.958 ; 23.958 ; 23.958 ; 23.958 ;
; CONFIG[6]    ; DATA[14]      ; 21.231 ; 21.231 ; 21.231 ; 21.231 ;
; CONFIG[6]    ; DATA[15]      ; 22.214 ; 22.214 ; 22.214 ; 22.214 ;
; CONFIG[6]    ; DTACKn        ; 18.868 ; 18.868 ; 18.868 ; 18.868 ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 15.059 ; 15.059 ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 14.809 ; 14.809 ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 18.045 ; 18.045 ; 18.045 ; 18.045 ;
; CONFIG[6]    ; FLASH_OEn     ; 17.975 ; 17.975 ; 17.975 ; 17.975 ;
; CONFIG[6]    ; RAM_DATA[0]   ; 26.161 ; 26.161 ; 26.161 ; 26.161 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 24.079 ; 24.079 ; 24.079 ; 24.079 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 24.855 ; 24.855 ; 24.855 ; 24.855 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 24.038 ; 24.038 ; 24.038 ; 24.038 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 23.499 ; 23.499 ; 23.499 ; 23.499 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 27.996 ; 27.996 ; 27.996 ; 27.996 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 26.266 ; 26.266 ; 26.266 ; 26.266 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 24.858 ; 24.858 ; 24.858 ; 24.858 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 26.550 ; 26.550 ; 26.550 ; 26.550 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 24.673 ; 24.673 ; 24.673 ; 24.673 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 23.824 ; 23.824 ; 23.824 ; 23.824 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 25.263 ; 25.263 ; 25.263 ; 25.263 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 24.058 ; 24.058 ; 24.058 ; 24.058 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 24.194 ; 24.194 ; 24.194 ; 24.194 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 23.597 ; 23.597 ; 23.597 ; 23.597 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 22.536 ; 22.536 ; 22.536 ; 22.536 ;
; CONFIG[6]    ; ROM2n         ; 14.709 ; 14.709 ; 14.709 ; 14.709 ;
; CRT_PIN3     ; DATA[7]       ; 19.095 ; 19.095 ; 19.095 ; 19.095 ;
; CRT_PIN3     ; RAM_DATA[7]   ; 21.516 ; 21.516 ; 21.516 ; 21.516 ;
; CRT_PIN3     ; RAM_DATA[12]  ; 11.813 ; 11.813 ; 11.813 ; 11.813 ;
; CRT_PIN3     ; RAM_DATA[13]  ; 12.251 ; 12.251 ; 12.251 ; 12.251 ;
; CRT_PIN3     ; RAM_DATA[14]  ; 12.388 ; 12.388 ; 12.388 ; 12.388 ;
; CRT_PIN3     ; RAM_DATA[15]  ; 10.879 ; 10.879 ; 10.879 ; 10.879 ;
; DATA[0]      ; DATA[0]       ; 21.384 ;        ;        ; 21.384 ;
; DATA[0]      ; RAM_DATA[0]   ; 23.032 ;        ;        ; 23.032 ;
; DATA[1]      ; DATA[1]       ; 21.273 ;        ;        ; 21.273 ;
; DATA[1]      ; RAM_DATA[1]   ; 21.805 ;        ;        ; 21.805 ;
; DATA[2]      ; DATA[2]       ; 22.735 ;        ;        ; 22.735 ;
; DATA[2]      ; RAM_DATA[2]   ; 23.023 ;        ;        ; 23.023 ;
; DATA[3]      ; DATA[3]       ; 21.749 ;        ;        ; 21.749 ;
; DATA[3]      ; RAM_DATA[3]   ; 21.700 ;        ;        ; 21.700 ;
; DATA[4]      ; DATA[4]       ; 21.917 ;        ;        ; 21.917 ;
; DATA[4]      ; RAM_DATA[4]   ; 21.119 ;        ;        ; 21.119 ;
; DATA[5]      ; DATA[5]       ; 22.662 ;        ;        ; 22.662 ;
; DATA[5]      ; RAM_DATA[5]   ; 25.173 ;        ;        ; 25.173 ;
; DATA[6]      ; DATA[6]       ; 21.339 ;        ;        ; 21.339 ;
; DATA[6]      ; RAM_DATA[6]   ; 23.825 ;        ;        ; 23.825 ;
; DATA[7]      ; DATA[7]       ; 22.073 ;        ;        ; 22.073 ;
; DATA[7]      ; RAM_DATA[7]   ; 24.494 ;        ;        ; 24.494 ;
; DATA[8]      ; DATA[8]       ; 22.913 ;        ;        ; 22.913 ;
; DATA[8]      ; RAM_DATA[8]   ; 24.770 ;        ;        ; 24.770 ;
; DATA[9]      ; DATA[9]       ; 21.317 ;        ;        ; 21.317 ;
; DATA[9]      ; RAM_DATA[9]   ; 21.469 ;        ;        ; 21.469 ;
; DATA[10]     ; DATA[10]      ; 20.498 ;        ;        ; 20.498 ;
; DATA[10]     ; RAM_DATA[10]  ; 20.766 ;        ;        ; 20.766 ;
; DATA[11]     ; DATA[11]      ; 21.466 ;        ;        ; 21.466 ;
; DATA[11]     ; RAM_DATA[11]  ; 22.627 ;        ;        ; 22.627 ;
; DATA[12]     ; DATA[12]      ; 19.550 ;        ;        ; 19.550 ;
; DATA[12]     ; RAM_DATA[12]  ; 20.676 ;        ;        ; 20.676 ;
; DATA[13]     ; DATA[13]      ; 22.129 ;        ;        ; 22.129 ;
; DATA[13]     ; RAM_DATA[13]  ; 22.365 ;        ;        ; 22.365 ;
; DATA[14]     ; DATA[14]      ; 15.246 ;        ;        ; 15.246 ;
; DATA[14]     ; RAM_DATA[14]  ; 17.612 ;        ;        ; 17.612 ;
; DATA[15]     ; DATA[15]      ; 17.491 ;        ;        ; 17.491 ;
; DATA[15]     ; RAM_DATA[15]  ; 17.813 ;        ;        ; 17.813 ;
; FC[0]        ; ACSI_RDn      ; 20.971 ; 20.971 ; 20.971 ; 20.971 ;
; FC[0]        ; ACSI_WRn      ; 21.248 ; 21.248 ; 21.248 ; 21.248 ;
; FC[0]        ; BUTTONn       ; 18.528 ; 18.528 ; 18.528 ; 18.528 ;
; FC[0]        ; CA1_OUT       ; 20.258 ; 20.258 ; 20.258 ; 20.258 ;
; FC[0]        ; CD[0]         ; 31.155 ; 31.155 ; 31.155 ; 31.155 ;
; FC[0]        ; CD[1]         ; 30.785 ; 30.785 ; 30.785 ; 30.785 ;
; FC[0]        ; CD[2]         ; 27.447 ; 27.447 ; 27.447 ; 27.447 ;
; FC[0]        ; CD[3]         ; 31.514 ; 31.514 ; 31.514 ; 31.514 ;
; FC[0]        ; CD[4]         ; 31.637 ; 31.637 ; 31.637 ; 31.637 ;
; FC[0]        ; CD[5]         ; 30.577 ; 30.577 ; 30.577 ; 30.577 ;
; FC[0]        ; CD[6]         ; 31.460 ; 31.460 ; 31.460 ; 31.460 ;
; FC[0]        ; CD[7]         ; 28.144 ; 28.144 ; 28.144 ; 28.144 ;
; FC[0]        ; DATA[0]       ; 31.941 ; 31.941 ; 31.941 ; 31.941 ;
; FC[0]        ; DATA[1]       ; 32.357 ; 32.357 ; 32.357 ; 32.357 ;
; FC[0]        ; DATA[2]       ; 31.385 ; 31.385 ; 31.385 ; 31.385 ;
; FC[0]        ; DATA[3]       ; 33.681 ; 33.681 ; 33.681 ; 33.681 ;
; FC[0]        ; DATA[4]       ; 32.488 ; 32.488 ; 32.488 ; 32.488 ;
; FC[0]        ; DATA[5]       ; 32.262 ; 32.262 ; 32.262 ; 32.262 ;
; FC[0]        ; DATA[6]       ; 30.857 ; 30.857 ; 30.857 ; 30.857 ;
; FC[0]        ; DATA[7]       ; 32.025 ; 32.025 ; 32.025 ; 32.025 ;
; FC[0]        ; DATA[8]       ; 32.987 ; 32.987 ; 32.987 ; 32.987 ;
; FC[0]        ; DATA[9]       ; 31.946 ; 31.946 ; 31.946 ; 31.946 ;
; FC[0]        ; DATA[10]      ; 30.164 ; 30.164 ; 30.164 ; 30.164 ;
; FC[0]        ; DATA[11]      ; 30.957 ; 30.957 ; 30.957 ; 30.957 ;
; FC[0]        ; DATA[12]      ; 30.371 ; 30.371 ; 30.371 ; 30.371 ;
; FC[0]        ; DATA[13]      ; 31.448 ; 31.448 ; 31.448 ; 31.448 ;
; FC[0]        ; DATA[14]      ; 32.253 ; 32.253 ; 32.253 ; 32.253 ;
; FC[0]        ; DATA[15]      ; 32.536 ; 32.536 ; 32.536 ; 32.536 ;
; FC[0]        ; DTACKn        ; 24.337 ; 24.337 ; 24.337 ; 24.337 ;
; FC[0]        ; FLASH_CEn     ; 18.470 ; 18.470 ; 18.470 ; 18.470 ;
; FC[0]        ; FLASH_OEn     ; 18.400 ; 18.400 ; 18.400 ; 18.400 ;
; FC[0]        ; JOY_RHn       ; 21.012 ; 21.012 ; 21.012 ; 21.012 ;
; FC[0]        ; JOY_RLn       ; 23.603 ; 23.603 ; 23.603 ; 23.603 ;
; FC[0]        ; JOY_WEn       ; 23.237 ; 23.237 ; 23.237 ; 23.237 ;
; FC[0]        ; JOY_WL        ; 17.816 ; 17.816 ; 17.816 ; 17.816 ;
; FC[0]        ; RAM_ADR[8]    ; 17.955 ; 17.955 ; 17.955 ; 17.955 ;
; FC[0]        ; RAM_BA[0]     ; 16.312 ; 16.312 ; 16.312 ; 16.312 ;
; FC[0]        ; RAM_BA[1]     ; 14.290 ; 14.290 ; 14.290 ; 14.290 ;
; FC[0]        ; RAM_CAS0n     ; 16.474 ; 16.474 ; 16.474 ; 16.474 ;
; FC[0]        ; RAM_CAS1n     ; 16.470 ; 16.470 ; 16.470 ; 16.470 ;
; FC[0]        ; RAM_DATA[0]   ; 33.589 ; 33.589 ; 33.589 ; 33.589 ;
; FC[0]        ; RAM_DATA[1]   ; 32.889 ; 32.889 ; 32.889 ; 32.889 ;
; FC[0]        ; RAM_DATA[2]   ; 31.673 ; 31.673 ; 31.673 ; 31.673 ;
; FC[0]        ; RAM_DATA[3]   ; 33.632 ; 33.632 ; 33.632 ; 33.632 ;
; FC[0]        ; RAM_DATA[4]   ; 31.690 ; 31.690 ; 31.690 ; 31.690 ;
; FC[0]        ; RAM_DATA[5]   ; 34.773 ; 34.773 ; 34.773 ; 34.773 ;
; FC[0]        ; RAM_DATA[6]   ; 33.343 ; 33.343 ; 33.343 ; 33.343 ;
; FC[0]        ; RAM_DATA[7]   ; 34.446 ; 34.446 ; 34.446 ; 34.446 ;
; FC[0]        ; RAM_DATA[8]   ; 34.844 ; 34.844 ; 34.844 ; 34.844 ;
; FC[0]        ; RAM_DATA[9]   ; 32.098 ; 32.098 ; 32.098 ; 32.098 ;
; FC[0]        ; RAM_DATA[10]  ; 30.432 ; 30.432 ; 30.432 ; 30.432 ;
; FC[0]        ; RAM_DATA[11]  ; 32.118 ; 32.118 ; 32.118 ; 32.118 ;
; FC[0]        ; RAM_DATA[12]  ; 31.497 ; 31.497 ; 31.497 ; 31.497 ;
; FC[0]        ; RAM_DATA[13]  ; 31.684 ; 31.684 ; 31.684 ; 31.684 ;
; FC[0]        ; RAM_DATA[14]  ; 34.619 ; 34.619 ; 34.619 ; 34.619 ;
; FC[0]        ; RAM_DATA[15]  ; 32.858 ; 32.858 ; 32.858 ; 32.858 ;
; FC[0]        ; RAM_DQM0H     ; 17.660 ; 17.660 ; 17.660 ; 17.660 ;
; FC[0]        ; RAM_DQM0L     ; 16.856 ; 16.856 ; 16.856 ; 16.856 ;
; FC[0]        ; RAM_DQM1H     ; 15.908 ; 15.908 ; 15.908 ; 15.908 ;
; FC[0]        ; RAM_DQM1L     ; 16.809 ; 16.809 ; 16.809 ; 16.809 ;
; FC[0]        ; RAM_RAS0n     ; 17.375 ; 17.375 ; 17.375 ; 17.375 ;
; FC[0]        ; RAM_RAS1n     ; 16.734 ; 16.734 ; 16.734 ; 16.734 ;
; FC[0]        ; ROM0n         ; 17.417 ; 17.417 ; 17.417 ; 17.417 ;
; FC[0]        ; ROM1n         ; 17.036 ; 17.036 ; 17.036 ; 17.036 ;
; FC[0]        ; ROM2n         ; 15.134 ; 15.134 ; 15.134 ; 15.134 ;
; FC[0]        ; ROM3n         ; 17.322 ; 17.322 ; 17.322 ; 17.322 ;
; FC[0]        ; ROM4n         ; 18.617 ; 18.617 ; 18.617 ; 18.617 ;
; FC[0]        ; ROM5n         ; 14.107 ; 14.107 ; 14.107 ; 14.107 ;
; FC[0]        ; ROM6n         ; 17.530 ; 17.530 ; 17.530 ; 17.530 ;
; FC[1]        ; ACSI_RDn      ; 20.652 ; 20.652 ; 20.652 ; 20.652 ;
; FC[1]        ; ACSI_WRn      ; 20.929 ; 20.929 ; 20.929 ; 20.929 ;
; FC[1]        ; BUTTONn       ; 18.231 ; 18.231 ; 18.231 ; 18.231 ;
; FC[1]        ; CA1_OUT       ; 19.939 ; 19.939 ; 19.939 ; 19.939 ;
; FC[1]        ; CD[0]         ; 30.836 ; 30.836 ; 30.836 ; 30.836 ;
; FC[1]        ; CD[1]         ; 30.466 ; 30.466 ; 30.466 ; 30.466 ;
; FC[1]        ; CD[2]         ; 27.128 ; 27.128 ; 27.128 ; 27.128 ;
; FC[1]        ; CD[3]         ; 31.195 ; 31.195 ; 31.195 ; 31.195 ;
; FC[1]        ; CD[4]         ; 31.318 ; 31.318 ; 31.318 ; 31.318 ;
; FC[1]        ; CD[5]         ; 30.258 ; 30.258 ; 30.258 ; 30.258 ;
; FC[1]        ; CD[6]         ; 31.141 ; 31.141 ; 31.141 ; 31.141 ;
; FC[1]        ; CD[7]         ; 27.825 ; 27.825 ; 27.825 ; 27.825 ;
; FC[1]        ; DATA[0]       ; 31.236 ; 31.236 ; 31.236 ; 31.236 ;
; FC[1]        ; DATA[1]       ; 31.652 ; 31.652 ; 31.652 ; 31.652 ;
; FC[1]        ; DATA[2]       ; 30.680 ; 30.680 ; 30.680 ; 30.680 ;
; FC[1]        ; DATA[3]       ; 32.976 ; 32.976 ; 32.976 ; 32.976 ;
; FC[1]        ; DATA[4]       ; 31.783 ; 31.783 ; 31.783 ; 31.783 ;
; FC[1]        ; DATA[5]       ; 31.943 ; 31.943 ; 31.943 ; 31.943 ;
; FC[1]        ; DATA[6]       ; 30.152 ; 30.152 ; 30.152 ; 30.152 ;
; FC[1]        ; DATA[7]       ; 31.320 ; 31.320 ; 31.320 ; 31.320 ;
; FC[1]        ; DATA[8]       ; 32.658 ; 32.658 ; 32.658 ; 32.658 ;
; FC[1]        ; DATA[9]       ; 31.326 ; 31.326 ; 31.326 ; 31.326 ;
; FC[1]        ; DATA[10]      ; 29.459 ; 29.459 ; 29.459 ; 29.459 ;
; FC[1]        ; DATA[11]      ; 30.252 ; 30.252 ; 30.252 ; 30.252 ;
; FC[1]        ; DATA[12]      ; 29.695 ; 29.695 ; 29.695 ; 29.695 ;
; FC[1]        ; DATA[13]      ; 30.993 ; 30.993 ; 30.993 ; 30.993 ;
; FC[1]        ; DATA[14]      ; 31.548 ; 31.548 ; 31.548 ; 31.548 ;
; FC[1]        ; DATA[15]      ; 31.831 ; 31.831 ; 31.831 ; 31.831 ;
; FC[1]        ; DTACKn        ; 23.632 ; 23.632 ; 23.632 ; 23.632 ;
; FC[1]        ; FLASH_CEn     ; 18.103 ; 18.103 ; 18.103 ; 18.103 ;
; FC[1]        ; FLASH_OEn     ; 18.033 ; 18.033 ; 18.033 ; 18.033 ;
; FC[1]        ; JOY_RHn       ; 20.693 ; 20.693 ; 20.693 ; 20.693 ;
; FC[1]        ; JOY_RLn       ; 23.284 ; 23.284 ; 23.284 ; 23.284 ;
; FC[1]        ; JOY_WEn       ; 22.918 ; 22.918 ; 22.918 ; 22.918 ;
; FC[1]        ; JOY_WL        ; 17.497 ; 17.497 ; 17.497 ; 17.497 ;
; FC[1]        ; RAM_ADR[8]    ; 17.601 ; 17.601 ; 17.601 ; 17.601 ;
; FC[1]        ; RAM_BA[0]     ; 15.958 ; 15.958 ; 15.958 ; 15.958 ;
; FC[1]        ; RAM_BA[1]     ; 13.936 ; 13.936 ; 13.936 ; 13.936 ;
; FC[1]        ; RAM_CAS0n     ; 16.120 ; 16.120 ; 16.120 ; 16.120 ;
; FC[1]        ; RAM_CAS1n     ; 16.116 ; 16.116 ; 16.116 ; 16.116 ;
; FC[1]        ; RAM_DATA[0]   ; 32.884 ; 32.884 ; 32.884 ; 32.884 ;
; FC[1]        ; RAM_DATA[1]   ; 32.184 ; 32.184 ; 32.184 ; 32.184 ;
; FC[1]        ; RAM_DATA[2]   ; 30.968 ; 30.968 ; 30.968 ; 30.968 ;
; FC[1]        ; RAM_DATA[3]   ; 32.927 ; 32.927 ; 32.927 ; 32.927 ;
; FC[1]        ; RAM_DATA[4]   ; 30.985 ; 30.985 ; 30.985 ; 30.985 ;
; FC[1]        ; RAM_DATA[5]   ; 34.454 ; 34.454 ; 34.454 ; 34.454 ;
; FC[1]        ; RAM_DATA[6]   ; 32.638 ; 32.638 ; 32.638 ; 32.638 ;
; FC[1]        ; RAM_DATA[7]   ; 33.741 ; 33.741 ; 33.741 ; 33.741 ;
; FC[1]        ; RAM_DATA[8]   ; 34.515 ; 34.515 ; 34.515 ; 34.515 ;
; FC[1]        ; RAM_DATA[9]   ; 31.478 ; 31.478 ; 31.478 ; 31.478 ;
; FC[1]        ; RAM_DATA[10]  ; 29.727 ; 29.727 ; 29.727 ; 29.727 ;
; FC[1]        ; RAM_DATA[11]  ; 31.413 ; 31.413 ; 31.413 ; 31.413 ;
; FC[1]        ; RAM_DATA[12]  ; 30.821 ; 30.821 ; 30.821 ; 30.821 ;
; FC[1]        ; RAM_DATA[13]  ; 31.229 ; 31.229 ; 31.229 ; 31.229 ;
; FC[1]        ; RAM_DATA[14]  ; 33.914 ; 33.914 ; 33.914 ; 33.914 ;
; FC[1]        ; RAM_DATA[15]  ; 32.153 ; 32.153 ; 32.153 ; 32.153 ;
; FC[1]        ; RAM_DQM0H     ; 17.306 ; 17.306 ; 17.306 ; 17.306 ;
; FC[1]        ; RAM_DQM0L     ; 16.502 ; 16.502 ; 16.502 ; 16.502 ;
; FC[1]        ; RAM_DQM1H     ; 15.554 ; 15.554 ; 15.554 ; 15.554 ;
; FC[1]        ; RAM_DQM1L     ; 16.455 ; 16.455 ; 16.455 ; 16.455 ;
; FC[1]        ; RAM_RAS0n     ; 17.021 ; 17.021 ; 17.021 ; 17.021 ;
; FC[1]        ; RAM_RAS1n     ; 16.380 ; 16.380 ; 16.380 ; 16.380 ;
; FC[1]        ; ROM0n         ; 17.050 ; 17.050 ; 17.050 ; 17.050 ;
; FC[1]        ; ROM1n         ; 16.669 ; 16.669 ; 16.669 ; 16.669 ;
; FC[1]        ; ROM2n         ; 14.767 ; 14.767 ; 14.767 ; 14.767 ;
; FC[1]        ; ROM3n         ; 16.955 ; 16.955 ; 16.955 ; 16.955 ;
; FC[1]        ; ROM4n         ; 18.250 ; 18.250 ; 18.250 ; 18.250 ;
; FC[1]        ; ROM5n         ; 13.740 ; 13.740 ; 13.740 ; 13.740 ;
; FC[1]        ; ROM6n         ; 17.163 ; 17.163 ; 17.163 ; 17.163 ;
; FC[2]        ; ACSI_RDn      ; 20.571 ; 20.571 ; 20.571 ; 20.571 ;
; FC[2]        ; ACSI_WRn      ; 20.848 ; 20.848 ; 20.848 ; 20.848 ;
; FC[2]        ; CA1_OUT       ;        ; 19.858 ; 19.858 ;        ;
; FC[2]        ; CD[0]         ; 30.755 ; 30.755 ; 30.755 ; 30.755 ;
; FC[2]        ; CD[1]         ; 30.385 ; 30.385 ; 30.385 ; 30.385 ;
; FC[2]        ; CD[2]         ; 27.047 ; 27.047 ; 27.047 ; 27.047 ;
; FC[2]        ; CD[3]         ; 31.114 ; 31.114 ; 31.114 ; 31.114 ;
; FC[2]        ; CD[4]         ; 31.237 ; 31.237 ; 31.237 ; 31.237 ;
; FC[2]        ; CD[5]         ; 30.177 ; 30.177 ; 30.177 ; 30.177 ;
; FC[2]        ; CD[6]         ; 31.060 ; 31.060 ; 31.060 ; 31.060 ;
; FC[2]        ; CD[7]         ; 27.744 ; 27.744 ; 27.744 ; 27.744 ;
; FC[2]        ; DATA[0]       ; 29.920 ; 30.798 ; 30.798 ; 29.920 ;
; FC[2]        ; DATA[1]       ; 30.879 ; 31.507 ; 31.507 ; 30.879 ;
; FC[2]        ; DATA[2]       ; 30.089 ; 29.842 ; 29.842 ; 30.089 ;
; FC[2]        ; DATA[3]       ; 31.759 ; 32.651 ; 32.651 ; 31.759 ;
; FC[2]        ; DATA[4]       ; 31.324 ; 31.424 ; 31.424 ; 31.324 ;
; FC[2]        ; DATA[5]       ; 31.862 ; 31.037 ; 31.037 ; 31.862 ;
; FC[2]        ; DATA[6]       ; 29.345 ; 29.245 ; 29.245 ; 29.345 ;
; FC[2]        ; DATA[7]       ; 29.580 ; 30.139 ; 30.139 ; 29.580 ;
; FC[2]        ; DATA[8]       ; 32.581 ; 32.443 ; 32.443 ; 32.581 ;
; FC[2]        ; DATA[9]       ; 31.249 ; 30.784 ; 30.784 ; 31.249 ;
; FC[2]        ; DATA[10]      ; 29.238 ; 29.238 ; 29.238 ; 29.238 ;
; FC[2]        ; DATA[11]      ; 30.144 ; 30.144 ; 30.144 ; 30.144 ;
; FC[2]        ; DATA[12]      ; 29.461 ; 29.618 ; 29.618 ; 29.461 ;
; FC[2]        ; DATA[13]      ; 30.755 ; 30.916 ; 30.916 ; 30.755 ;
; FC[2]        ; DATA[14]      ; 30.981 ; 30.981 ; 30.981 ; 30.981 ;
; FC[2]        ; DATA[15]      ; 31.182 ; 31.182 ; 31.182 ; 31.182 ;
; FC[2]        ; DTACKn        ; 23.053 ; 23.053 ; 23.053 ; 23.053 ;
; FC[2]        ; JOY_RHn       ;        ; 20.612 ; 20.612 ;        ;
; FC[2]        ; JOY_RLn       ;        ; 23.203 ; 23.203 ;        ;
; FC[2]        ; JOY_WEn       ; 22.837 ;        ;        ; 22.837 ;
; FC[2]        ; JOY_WL        ; 17.416 ;        ;        ; 17.416 ;
; FC[2]        ; RAM_DATA[0]   ; 31.568 ; 32.446 ; 32.446 ; 31.568 ;
; FC[2]        ; RAM_DATA[1]   ; 31.411 ; 32.039 ; 32.039 ; 31.411 ;
; FC[2]        ; RAM_DATA[2]   ; 30.377 ; 30.130 ; 30.130 ; 30.377 ;
; FC[2]        ; RAM_DATA[3]   ; 31.710 ; 32.602 ; 32.602 ; 31.710 ;
; FC[2]        ; RAM_DATA[4]   ; 30.526 ; 30.626 ; 30.626 ; 30.526 ;
; FC[2]        ; RAM_DATA[5]   ; 34.373 ; 33.548 ; 33.548 ; 34.373 ;
; FC[2]        ; RAM_DATA[6]   ; 31.831 ; 31.731 ; 31.731 ; 31.831 ;
; FC[2]        ; RAM_DATA[7]   ; 32.001 ; 32.560 ; 32.560 ; 32.001 ;
; FC[2]        ; RAM_DATA[8]   ; 34.438 ; 34.300 ; 34.300 ; 34.438 ;
; FC[2]        ; RAM_DATA[9]   ; 31.401 ; 30.936 ; 30.936 ; 31.401 ;
; FC[2]        ; RAM_DATA[10]  ; 29.506 ; 29.506 ; 29.506 ; 29.506 ;
; FC[2]        ; RAM_DATA[11]  ; 31.305 ; 31.305 ; 31.305 ; 31.305 ;
; FC[2]        ; RAM_DATA[12]  ; 30.587 ; 30.744 ; 30.744 ; 30.587 ;
; FC[2]        ; RAM_DATA[13]  ; 30.991 ; 31.152 ; 31.152 ; 30.991 ;
; FC[2]        ; RAM_DATA[14]  ; 33.347 ; 33.347 ; 33.347 ; 33.347 ;
; FC[2]        ; RAM_DATA[15]  ; 31.504 ; 31.504 ; 31.504 ; 31.504 ;
; HDINTn       ; DATA[5]       ; 27.248 ;        ;        ; 27.248 ;
; HDINTn       ; RAM_DATA[5]   ; 29.759 ;        ;        ; 29.759 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 27.168 ; 27.168 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 29.679 ; 29.679 ;        ;
; IDE_IORDY    ; DTACKn        ; 17.327 ; 17.327 ; 17.327 ; 17.327 ;
; LDSn         ; ACSI_RDn      ; 18.887 ; 18.887 ; 18.887 ; 18.887 ;
; LDSn         ; ACSI_WRn      ; 19.164 ; 19.164 ; 19.164 ; 19.164 ;
; LDSn         ; BUTTONn       ; 21.706 ;        ;        ; 21.706 ;
; LDSn         ; CA1_OUT       ; 18.174 ;        ;        ; 18.174 ;
; LDSn         ; CD[0]         ; 29.071 ; 29.071 ; 29.071 ; 29.071 ;
; LDSn         ; CD[1]         ; 28.701 ; 28.701 ; 28.701 ; 28.701 ;
; LDSn         ; CD[2]         ; 25.363 ; 25.363 ; 25.363 ; 25.363 ;
; LDSn         ; CD[3]         ; 29.430 ; 29.430 ; 29.430 ; 29.430 ;
; LDSn         ; CD[4]         ; 29.553 ; 29.553 ; 29.553 ; 29.553 ;
; LDSn         ; CD[5]         ; 28.493 ; 28.493 ; 28.493 ; 28.493 ;
; LDSn         ; CD[6]         ; 29.376 ; 29.376 ; 29.376 ; 29.376 ;
; LDSn         ; CD[7]         ; 26.060 ; 26.060 ; 26.060 ; 26.060 ;
; LDSn         ; DATA[0]       ; 30.265 ; 30.978 ; 30.978 ; 30.265 ;
; LDSn         ; DATA[1]       ; 30.974 ; 31.893 ; 31.893 ; 30.974 ;
; LDSn         ; DATA[2]       ; 30.834 ; 31.147 ; 31.147 ; 30.834 ;
; LDSn         ; DATA[3]       ; 32.439 ; 32.157 ; 32.157 ; 32.439 ;
; LDSn         ; DATA[4]       ; 32.482 ; 32.382 ; 32.382 ; 32.482 ;
; LDSn         ; DATA[5]       ; 31.947 ; 32.920 ; 32.920 ; 31.947 ;
; LDSn         ; DATA[6]       ; 30.303 ; 30.403 ; 30.403 ; 30.303 ;
; LDSn         ; DATA[7]       ; 31.197 ; 30.638 ; 30.638 ; 31.197 ;
; LDSn         ; DATA[8]       ; 31.177 ; 31.177 ; 31.177 ; 31.177 ;
; LDSn         ; DATA[9]       ; 30.339 ; 30.339 ; 30.339 ; 30.339 ;
; LDSn         ; DATA[10]      ; 29.150 ; 28.601 ; 28.601 ; 29.150 ;
; LDSn         ; DATA[11]      ; 30.362 ; 30.362 ; 30.362 ; 30.362 ;
; LDSn         ; DATA[12]      ; 29.718 ; 29.070 ; 29.070 ; 29.718 ;
; LDSn         ; DATA[13]      ; 30.670 ; 30.670 ; 30.670 ; 30.670 ;
; LDSn         ; DATA[14]      ; 30.847 ; 30.847 ; 30.847 ; 30.847 ;
; LDSn         ; DATA[15]      ; 31.413 ; 31.413 ; 31.413 ; 31.413 ;
; LDSn         ; DTACKn        ; 22.378 ; 22.378 ; 22.378 ; 22.378 ;
; LDSn         ; IDE_IORDn     ; 13.198 ;        ;        ; 13.198 ;
; LDSn         ; IDE_IOWRn     ; 14.606 ;        ;        ; 14.606 ;
; LDSn         ; JOY_RLn       ; 17.474 ;        ;        ; 17.474 ;
; LDSn         ; JOY_WEn       ;        ; 17.108 ; 17.108 ;        ;
; LDSn         ; JOY_WL        ;        ; 14.997 ; 14.997 ;        ;
; LDSn         ; RAM_CAS0n     ; 14.682 ;        ;        ; 14.682 ;
; LDSn         ; RAM_CAS1n     ; 14.667 ;        ;        ; 14.667 ;
; LDSn         ; RAM_DATA[0]   ; 31.913 ; 32.626 ; 32.626 ; 31.913 ;
; LDSn         ; RAM_DATA[1]   ; 31.506 ; 32.425 ; 32.425 ; 31.506 ;
; LDSn         ; RAM_DATA[2]   ; 31.122 ; 31.435 ; 31.435 ; 31.122 ;
; LDSn         ; RAM_DATA[3]   ; 32.390 ; 32.108 ; 32.108 ; 32.390 ;
; LDSn         ; RAM_DATA[4]   ; 31.684 ; 31.584 ; 31.584 ; 31.684 ;
; LDSn         ; RAM_DATA[5]   ; 34.458 ; 35.431 ; 35.431 ; 34.458 ;
; LDSn         ; RAM_DATA[6]   ; 32.789 ; 32.889 ; 32.889 ; 32.789 ;
; LDSn         ; RAM_DATA[7]   ; 33.618 ; 33.059 ; 33.059 ; 33.618 ;
; LDSn         ; RAM_DATA[8]   ; 33.034 ; 33.034 ; 33.034 ; 33.034 ;
; LDSn         ; RAM_DATA[9]   ; 30.491 ; 30.491 ; 30.491 ; 30.491 ;
; LDSn         ; RAM_DATA[10]  ; 29.418 ; 28.869 ; 28.869 ; 29.418 ;
; LDSn         ; RAM_DATA[11]  ; 31.523 ; 31.523 ; 31.523 ; 31.523 ;
; LDSn         ; RAM_DATA[12]  ; 30.844 ; 30.196 ; 30.196 ; 30.844 ;
; LDSn         ; RAM_DATA[13]  ; 30.906 ; 30.906 ; 30.906 ; 30.906 ;
; LDSn         ; RAM_DATA[14]  ; 33.213 ; 33.213 ; 33.213 ; 33.213 ;
; LDSn         ; RAM_DATA[15]  ; 31.735 ; 31.735 ; 31.735 ; 31.735 ;
; LDSn         ; RAM_DQM0L     ; 15.935 ;        ;        ; 15.935 ;
; LDSn         ; RAM_DQM1L     ; 15.885 ;        ;        ; 15.885 ;
; LPT_BSY      ; DATA[0]       ; 23.364 ;        ;        ; 23.364 ;
; LPT_BSY      ; RAM_DATA[0]   ; 25.012 ;        ;        ; 25.012 ;
; LPT_D[0]     ; DATA[8]       ; 23.497 ;        ;        ; 23.497 ;
; LPT_D[0]     ; RAM_DATA[8]   ; 25.354 ;        ;        ; 25.354 ;
; LPT_D[1]     ; DATA[9]       ; 22.649 ;        ;        ; 22.649 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 22.801 ;        ;        ; 22.801 ;
; LPT_D[2]     ; DATA[10]      ; 19.772 ;        ;        ; 19.772 ;
; LPT_D[2]     ; RAM_DATA[10]  ; 20.040 ;        ;        ; 20.040 ;
; LPT_D[3]     ; DATA[11]      ; 20.694 ;        ;        ; 20.694 ;
; LPT_D[3]     ; RAM_DATA[11]  ; 21.855 ;        ;        ; 21.855 ;
; LPT_D[4]     ; DATA[12]      ; 20.963 ;        ;        ; 20.963 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 22.089 ;        ;        ; 22.089 ;
; LPT_D[5]     ; DATA[13]      ; 22.544 ;        ;        ; 22.544 ;
; LPT_D[5]     ; RAM_DATA[13]  ; 22.780 ;        ;        ; 22.780 ;
; LPT_D[6]     ; DATA[14]      ; 21.673 ; 21.673 ; 21.673 ; 21.673 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 24.039 ; 24.039 ; 24.039 ; 24.039 ;
; LPT_D[7]     ; DATA[15]      ; 22.835 ; 22.835 ; 22.835 ; 22.835 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 23.157 ; 23.157 ; 23.157 ; 23.157 ;
; MIDI_IN      ; MIDI_TLR      ; 8.871  ;        ;        ; 8.871  ;
; RAM_DATA[0]  ; DATA[0]       ; 23.719 ;        ;        ; 23.719 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 25.367 ;        ;        ; 25.367 ;
; RAM_DATA[1]  ; DATA[1]       ; 23.635 ;        ;        ; 23.635 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 24.167 ;        ;        ; 24.167 ;
; RAM_DATA[2]  ; DATA[2]       ; 23.119 ;        ;        ; 23.119 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 23.407 ;        ;        ; 23.407 ;
; RAM_DATA[3]  ; DATA[3]       ; 24.926 ;        ;        ; 24.926 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 24.877 ;        ;        ; 24.877 ;
; RAM_DATA[4]  ; DATA[4]       ; 22.902 ;        ;        ; 22.902 ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 22.104 ;        ;        ; 22.104 ;
; RAM_DATA[5]  ; DATA[5]       ; 23.543 ;        ;        ; 23.543 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 26.054 ;        ;        ; 26.054 ;
; RAM_DATA[6]  ; DATA[6]       ; 21.134 ;        ;        ; 21.134 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 23.620 ;        ;        ; 23.620 ;
; RAM_DATA[7]  ; DATA[7]       ; 22.668 ;        ;        ; 22.668 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 25.089 ;        ;        ; 25.089 ;
; RAM_DATA[8]  ; DATA[8]       ; 24.818 ;        ;        ; 24.818 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 26.675 ;        ;        ; 26.675 ;
; RAM_DATA[9]  ; DATA[9]       ; 22.708 ;        ;        ; 22.708 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 22.860 ;        ;        ; 22.860 ;
; RAM_DATA[10] ; DATA[10]      ; 21.561 ;        ;        ; 21.561 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 21.829 ;        ;        ; 21.829 ;
; RAM_DATA[11] ; DATA[11]      ; 22.449 ;        ;        ; 22.449 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 23.610 ;        ;        ; 23.610 ;
; RAM_DATA[12] ; DATA[12]      ; 21.152 ;        ;        ; 21.152 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 22.278 ;        ;        ; 22.278 ;
; RAM_DATA[13] ; DATA[13]      ; 24.107 ;        ;        ; 24.107 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 24.343 ;        ;        ; 24.343 ;
; RAM_DATA[14] ; DATA[14]      ; 22.936 ; 22.936 ; 22.936 ; 22.936 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 25.302 ; 25.302 ; 25.302 ; 25.302 ;
; RAM_DATA[15] ; DATA[15]      ; 22.188 ; 22.188 ; 22.188 ; 22.188 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 22.510 ; 22.510 ; 22.510 ; 22.510 ;
; RWn          ; ACSI_RDn      ; 20.996 ; 20.996 ; 20.996 ; 20.996 ;
; RWn          ; ACSI_WRn      ; 21.273 ; 21.273 ; 21.273 ; 21.273 ;
; RWn          ; BUTTONn       ;        ; 21.438 ; 21.438 ;        ;
; RWn          ; CA1_OUT       ;        ; 20.283 ; 20.283 ;        ;
; RWn          ; CD[0]         ; 31.180 ; 31.180 ; 31.180 ; 31.180 ;
; RWn          ; CD[1]         ; 30.810 ; 30.810 ; 30.810 ; 30.810 ;
; RWn          ; CD[2]         ; 27.472 ; 27.472 ; 27.472 ; 27.472 ;
; RWn          ; CD[3]         ; 31.539 ; 31.539 ; 31.539 ; 31.539 ;
; RWn          ; CD[4]         ; 31.662 ; 31.662 ; 31.662 ; 31.662 ;
; RWn          ; CD[5]         ; 30.602 ; 30.602 ; 30.602 ; 30.602 ;
; RWn          ; CD[6]         ; 31.485 ; 31.485 ; 31.485 ; 31.485 ;
; RWn          ; CD[7]         ; 28.169 ; 28.169 ; 28.169 ; 28.169 ;
; RWn          ; DATA[0]       ; 30.659 ; 31.223 ; 31.223 ; 30.659 ;
; RWn          ; DATA[1]       ; 31.304 ; 31.978 ; 31.978 ; 31.304 ;
; RWn          ; DATA[2]       ; 30.514 ; 31.553 ; 31.553 ; 30.514 ;
; RWn          ; DATA[3]       ; 32.184 ; 33.076 ; 33.076 ; 32.184 ;
; RWn          ; DATA[4]       ; 31.749 ; 31.849 ; 31.849 ; 31.749 ;
; RWn          ; DATA[5]       ; 32.287 ; 31.462 ; 31.462 ; 32.287 ;
; RWn          ; DATA[6]       ; 29.897 ; 30.639 ; 30.639 ; 29.897 ;
; RWn          ; DATA[7]       ; 30.005 ; 31.151 ; 31.151 ; 30.005 ;
; RWn          ; DATA[8]       ; 32.868 ; 33.006 ; 33.006 ; 32.868 ;
; RWn          ; DATA[9]       ; 31.209 ; 31.674 ; 31.674 ; 31.209 ;
; RWn          ; DATA[10]      ; 29.663 ; 29.663 ; 29.663 ; 29.663 ;
; RWn          ; DATA[11]      ; 30.569 ; 30.569 ; 30.569 ; 30.569 ;
; RWn          ; DATA[12]      ; 30.043 ; 29.886 ; 29.886 ; 30.043 ;
; RWn          ; DATA[13]      ; 31.341 ; 31.180 ; 31.180 ; 31.341 ;
; RWn          ; DATA[14]      ; 31.406 ; 31.406 ; 31.406 ; 31.406 ;
; RWn          ; DATA[15]      ; 31.607 ; 31.607 ; 31.607 ; 31.607 ;
; RWn          ; DTACKn        ; 23.478 ; 23.478 ; 23.478 ; 23.478 ;
; RWn          ; FLASH_CEn     ;        ; 18.490 ; 18.490 ;        ;
; RWn          ; FLASH_OEn     ;        ; 18.420 ; 18.420 ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 13.832 ; 13.832 ;        ;
; RWn          ; IDE_D_EN_OUTn ; 13.848 ;        ;        ; 13.848 ;
; RWn          ; IDE_IORDn     ;        ; 13.909 ; 13.909 ;        ;
; RWn          ; IDE_IOWRn     ; 15.313 ;        ;        ; 15.313 ;
; RWn          ; JOY_RHn       ;        ; 21.037 ; 21.037 ;        ;
; RWn          ; JOY_RLn       ;        ; 23.628 ; 23.628 ;        ;
; RWn          ; JOY_WEn       ; 23.262 ;        ;        ; 23.262 ;
; RWn          ; JOY_WL        ; 17.841 ; 14.857 ; 14.857 ; 17.841 ;
; RWn          ; RAM_DATA[0]   ; 32.307 ; 32.871 ; 32.871 ; 32.307 ;
; RWn          ; RAM_DATA[1]   ; 31.836 ; 32.510 ; 32.510 ; 31.836 ;
; RWn          ; RAM_DATA[2]   ; 30.802 ; 31.841 ; 31.841 ; 30.802 ;
; RWn          ; RAM_DATA[3]   ; 32.135 ; 33.027 ; 33.027 ; 32.135 ;
; RWn          ; RAM_DATA[4]   ; 30.951 ; 31.051 ; 31.051 ; 30.951 ;
; RWn          ; RAM_DATA[5]   ; 34.798 ; 33.973 ; 33.973 ; 34.798 ;
; RWn          ; RAM_DATA[6]   ; 32.383 ; 33.125 ; 33.125 ; 32.383 ;
; RWn          ; RAM_DATA[7]   ; 32.426 ; 33.572 ; 33.572 ; 32.426 ;
; RWn          ; RAM_DATA[8]   ; 34.725 ; 34.863 ; 34.863 ; 34.725 ;
; RWn          ; RAM_DATA[9]   ; 31.361 ; 31.826 ; 31.826 ; 31.361 ;
; RWn          ; RAM_DATA[10]  ; 29.931 ; 29.931 ; 29.931 ; 29.931 ;
; RWn          ; RAM_DATA[11]  ; 31.730 ; 31.730 ; 31.730 ; 31.730 ;
; RWn          ; RAM_DATA[12]  ; 31.169 ; 31.012 ; 31.012 ; 31.169 ;
; RWn          ; RAM_DATA[13]  ; 31.577 ; 31.416 ; 31.416 ; 31.577 ;
; RWn          ; RAM_DATA[14]  ; 33.772 ; 33.772 ; 33.772 ; 33.772 ;
; RWn          ; RAM_DATA[15]  ; 31.929 ; 31.929 ; 31.929 ; 31.929 ;
; RWn          ; RAM_WEn       ; 13.866 ;        ;        ; 13.866 ;
; RWn          ; ROM0n         ;        ; 17.437 ; 17.437 ;        ;
; RWn          ; ROM1n         ;        ; 17.056 ; 17.056 ;        ;
; RWn          ; ROM2n         ;        ; 15.154 ; 15.154 ;        ;
; RWn          ; ROM3n         ;        ; 17.342 ; 17.342 ;        ;
; RWn          ; ROM4n         ;        ; 18.637 ; 18.637 ;        ;
; RWn          ; ROM5n         ;        ; 14.127 ; 14.127 ;        ;
; RWn          ; ROM6n         ;        ; 17.550 ; 17.550 ;        ;
; SCSI_ACKn    ; CD[0]         ; 17.133 ; 17.133 ; 17.133 ; 17.133 ;
; SCSI_ATNn    ; CD[1]         ; 17.985 ; 17.985 ; 17.985 ; 17.985 ;
; SCSI_BSYn    ; CD[6]         ; 21.530 ; 21.530 ; 21.530 ; 21.530 ;
; SCSI_D[0]    ; CD[0]         ; 17.625 ; 17.625 ; 17.625 ; 17.625 ;
; SCSI_D[1]    ; CD[1]         ; 17.839 ; 17.839 ; 17.839 ; 17.839 ;
; SCSI_D[2]    ; CD[2]         ;        ; 18.295 ; 18.295 ;        ;
; SCSI_D[3]    ; CD[3]         ; 18.504 ; 18.504 ; 18.504 ; 18.504 ;
; SCSI_D[4]    ; CD[4]         ; 20.605 ; 20.605 ; 20.605 ; 20.605 ;
; SCSI_D[5]    ; CD[5]         ; 20.094 ; 20.094 ; 20.094 ; 20.094 ;
; SCSI_D[6]    ; CD[6]         ; 21.308 ; 21.308 ; 21.308 ; 21.308 ;
; SCSI_D[7]    ; CD[7]         ; 18.404 ; 18.404 ; 18.404 ; 18.404 ;
; SCSI_DCn     ; CD[3]         ; 21.336 ; 21.336 ; 21.336 ; 21.336 ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 18.920 ; 18.920 ; 18.920 ; 18.920 ;
; SCSI_DCn     ; SCSI_D[0]     ; 18.404 ; 18.404 ; 18.404 ; 18.404 ;
; SCSI_DCn     ; SCSI_D[1]     ; 18.404 ; 18.404 ; 18.404 ; 18.404 ;
; SCSI_DCn     ; SCSI_D[2]     ; 17.579 ; 17.579 ; 17.579 ; 17.579 ;
; SCSI_DCn     ; SCSI_D[3]     ; 17.579 ; 17.579 ; 17.579 ; 17.579 ;
; SCSI_DCn     ; SCSI_D[4]     ; 17.262 ; 17.262 ; 17.262 ; 17.262 ;
; SCSI_DCn     ; SCSI_D[5]     ; 17.262 ; 17.262 ; 17.262 ; 17.262 ;
; SCSI_DCn     ; SCSI_D[6]     ; 17.255 ; 17.255 ; 17.255 ; 17.255 ;
; SCSI_DCn     ; SCSI_D[7]     ; 17.255 ; 17.255 ; 17.255 ; 17.255 ;
; SCSI_DCn     ; SCSI_DP       ; 18.414 ; 18.414 ; 18.414 ; 18.414 ;
; SCSI_DP      ; CD[0]         ; 17.137 ; 17.137 ; 17.137 ; 17.137 ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 13.580 ; 13.580 ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 13.568 ;        ;        ; 13.568 ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 13.123 ; 13.123 ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 13.304 ;        ;        ; 13.304 ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 13.259 ; 13.259 ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 13.095 ;        ;        ; 13.095 ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 13.163 ; 13.163 ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 13.245 ;        ;        ; 13.245 ;
; SCSI_IDn[1]  ; SCSI_DP       ; 14.948 ; 14.948 ; 14.948 ; 14.948 ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 13.143 ; 13.143 ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 13.119 ; 13.119 ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 12.685 ;        ;        ; 12.685 ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 12.864 ;        ;        ; 12.864 ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 12.816 ; 12.816 ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 12.644 ; 12.644 ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 12.710 ;        ;        ; 12.710 ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 12.800 ;        ;        ; 12.800 ;
; SCSI_IDn[2]  ; SCSI_DP       ; 14.503 ; 14.503 ; 14.503 ; 14.503 ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 13.816 ; 13.816 ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 13.780 ; 13.780 ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 13.390 ; 13.390 ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 13.568 ; 13.568 ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 13.421 ;        ;        ; 13.421 ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 13.238 ;        ;        ; 13.238 ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 13.351 ;        ;        ; 13.351 ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 13.437 ;        ;        ; 13.437 ;
; SCSI_IDn[3]  ; SCSI_DP       ; 15.140 ; 15.140 ; 15.140 ; 15.140 ;
; SCSI_IOn     ; CD[2]         ;        ; 17.794 ; 17.794 ;        ;
; SCSI_IOn     ; CD[3]         ; 19.966 ; 19.966 ; 19.966 ; 19.966 ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 17.550 ; 17.550 ; 17.550 ; 17.550 ;
; SCSI_IOn     ; SCSI_D[0]     ; 17.034 ; 17.034 ; 17.034 ; 17.034 ;
; SCSI_IOn     ; SCSI_D[1]     ; 17.034 ; 17.034 ; 17.034 ; 17.034 ;
; SCSI_IOn     ; SCSI_D[2]     ; 16.209 ; 16.209 ; 16.209 ; 16.209 ;
; SCSI_IOn     ; SCSI_D[3]     ; 16.209 ; 16.209 ; 16.209 ; 16.209 ;
; SCSI_IOn     ; SCSI_D[4]     ; 15.892 ; 15.892 ; 15.892 ; 15.892 ;
; SCSI_IOn     ; SCSI_D[5]     ; 15.892 ; 15.892 ; 15.892 ; 15.892 ;
; SCSI_IOn     ; SCSI_D[6]     ; 15.885 ; 15.885 ; 15.885 ; 15.885 ;
; SCSI_IOn     ; SCSI_D[7]     ; 15.885 ; 15.885 ; 15.885 ; 15.885 ;
; SCSI_IOn     ; SCSI_DP       ; 17.044 ; 17.044 ; 17.044 ; 17.044 ;
; SCSI_IOn     ; SCSI_RDn      ; 12.732 ;        ;        ; 12.732 ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 13.954 ; 13.954 ;        ;
; SCSI_MSGn    ; CD[3]         ; 20.130 ; 20.130 ; 20.130 ; 20.130 ;
; SCSI_MSGn    ; CD[4]         ; 21.135 ; 21.135 ; 21.135 ; 21.135 ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 17.714 ; 17.714 ; 17.714 ; 17.714 ;
; SCSI_MSGn    ; SCSI_D[0]     ; 17.198 ; 17.198 ; 17.198 ; 17.198 ;
; SCSI_MSGn    ; SCSI_D[1]     ; 17.198 ; 17.198 ; 17.198 ; 17.198 ;
; SCSI_MSGn    ; SCSI_D[2]     ; 16.373 ; 16.373 ; 16.373 ; 16.373 ;
; SCSI_MSGn    ; SCSI_D[3]     ; 16.373 ; 16.373 ; 16.373 ; 16.373 ;
; SCSI_MSGn    ; SCSI_D[4]     ; 16.056 ; 16.056 ; 16.056 ; 16.056 ;
; SCSI_MSGn    ; SCSI_D[5]     ; 16.056 ; 16.056 ; 16.056 ; 16.056 ;
; SCSI_MSGn    ; SCSI_D[6]     ; 16.049 ; 16.049 ; 16.049 ; 16.049 ;
; SCSI_MSGn    ; SCSI_D[7]     ; 16.049 ; 16.049 ; 16.049 ; 16.049 ;
; SCSI_MSGn    ; SCSI_DP       ; 17.208 ; 17.208 ; 17.208 ; 17.208 ;
; SCSI_REQn    ; CD[3]         ; 20.296 ; 20.296 ; 20.296 ; 20.296 ;
; SCSI_REQn    ; CD[5]         ; 20.609 ; 20.609 ; 20.609 ; 20.609 ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 17.880 ;        ;        ; 17.880 ;
; SCSI_REQn    ; SCSI_D[0]     ; 17.364 ; 17.364 ; 17.364 ; 17.364 ;
; SCSI_REQn    ; SCSI_D[1]     ; 17.364 ; 17.364 ; 17.364 ; 17.364 ;
; SCSI_REQn    ; SCSI_D[2]     ; 16.539 ; 16.539 ; 16.539 ; 16.539 ;
; SCSI_REQn    ; SCSI_D[3]     ; 16.539 ; 16.539 ; 16.539 ; 16.539 ;
; SCSI_REQn    ; SCSI_D[4]     ; 16.222 ; 16.222 ; 16.222 ; 16.222 ;
; SCSI_REQn    ; SCSI_D[5]     ; 16.222 ; 16.222 ; 16.222 ; 16.222 ;
; SCSI_REQn    ; SCSI_D[6]     ; 16.215 ; 16.215 ; 16.215 ; 16.215 ;
; SCSI_REQn    ; SCSI_D[7]     ; 16.215 ; 16.215 ; 16.215 ; 16.215 ;
; SCSI_REQn    ; SCSI_DP       ; 17.374 ; 17.374 ; 17.374 ; 17.374 ;
; SCSI_RSTn    ; CD[7]         ;        ; 19.202 ; 19.202 ;        ;
; SCSI_SELn    ; CD[1]         ; 16.732 ; 16.732 ; 16.732 ; 16.732 ;
; SD_AVR_ENn   ; RESETn        ;        ; 16.240 ; 16.240 ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 14.339 ; 14.339 ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 11.944 ; 11.944 ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 14.344 ;        ;        ; 14.344 ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 13.070 ;        ;        ; 13.070 ;
; SD_RESETn    ; ACSI_RDn      ; 22.787 ; 22.787 ; 22.787 ; 22.787 ;
; SD_RESETn    ; ACSI_WRn      ; 23.064 ; 23.064 ; 23.064 ; 23.064 ;
; SD_RESETn    ; CA1_OUT       ; 22.074 ;        ;        ; 22.074 ;
; SD_RESETn    ; CD[0]         ; 32.971 ; 32.971 ; 32.971 ; 32.971 ;
; SD_RESETn    ; CD[1]         ; 32.601 ; 32.601 ; 32.601 ; 32.601 ;
; SD_RESETn    ; CD[2]         ; 29.263 ; 29.263 ; 29.263 ; 29.263 ;
; SD_RESETn    ; CD[3]         ; 33.330 ; 33.330 ; 33.330 ; 33.330 ;
; SD_RESETn    ; CD[4]         ; 33.453 ; 33.453 ; 33.453 ; 33.453 ;
; SD_RESETn    ; CD[5]         ; 32.393 ; 32.393 ; 32.393 ; 32.393 ;
; SD_RESETn    ; CD[6]         ; 33.276 ; 33.276 ; 33.276 ; 33.276 ;
; SD_RESETn    ; CD[7]         ; 29.960 ; 29.960 ; 29.960 ; 29.960 ;
; SD_RESETn    ; COM_TxD       ; 17.159 ; 17.159 ; 17.159 ; 17.159 ;
; SD_RESETn    ; DATA[0]       ; 29.485 ; 29.485 ; 29.485 ; 29.485 ;
; SD_RESETn    ; DATA[1]       ; 30.032 ; 30.032 ; 30.032 ; 30.032 ;
; SD_RESETn    ; DATA[2]       ; 29.599 ; 29.599 ; 29.599 ; 29.599 ;
; SD_RESETn    ; DATA[3]       ; 30.887 ; 30.887 ; 30.887 ; 30.887 ;
; SD_RESETn    ; DATA[4]       ; 29.894 ; 29.976 ; 29.976 ; 29.894 ;
; SD_RESETn    ; DATA[5]       ; 29.871 ; 29.871 ; 29.871 ; 29.871 ;
; SD_RESETn    ; DATA[6]       ; 28.023 ; 28.023 ; 28.023 ; 28.023 ;
; SD_RESETn    ; DATA[7]       ; 29.403 ; 29.403 ; 29.403 ; 29.403 ;
; SD_RESETn    ; DATA[8]       ; 26.925 ; 28.326 ; 28.326 ; 26.925 ;
; SD_RESETn    ; DATA[9]       ; 25.833 ; 27.037 ; 27.037 ; 25.833 ;
; SD_RESETn    ; DATA[10]      ; 24.546 ; 25.485 ; 25.485 ; 24.546 ;
; SD_RESETn    ; DATA[11]      ; 25.704 ; 26.273 ; 26.273 ; 25.704 ;
; SD_RESETn    ; DATA[12]      ; 25.440 ; 26.185 ; 26.185 ; 25.440 ;
; SD_RESETn    ; DATA[13]      ; 25.800 ; 26.826 ; 26.826 ; 25.800 ;
; SD_RESETn    ; DATA[14]      ; 28.136 ; 28.136 ; 28.136 ; 28.136 ;
; SD_RESETn    ; DATA[15]      ; 28.702 ; 28.702 ; 28.702 ; 28.702 ;
; SD_RESETn    ; DTACKn        ; 21.951 ; 21.951 ; 21.951 ; 21.951 ;
; SD_RESETn    ; RAM_DATA[0]   ; 31.133 ; 31.133 ; 31.133 ; 31.133 ;
; SD_RESETn    ; RAM_DATA[1]   ; 30.564 ; 30.564 ; 30.564 ; 30.564 ;
; SD_RESETn    ; RAM_DATA[2]   ; 29.887 ; 29.887 ; 29.887 ; 29.887 ;
; SD_RESETn    ; RAM_DATA[3]   ; 30.838 ; 30.838 ; 30.838 ; 30.838 ;
; SD_RESETn    ; RAM_DATA[4]   ; 29.096 ; 29.178 ; 29.178 ; 29.096 ;
; SD_RESETn    ; RAM_DATA[5]   ; 32.382 ; 32.382 ; 32.382 ; 32.382 ;
; SD_RESETn    ; RAM_DATA[6]   ; 30.509 ; 30.509 ; 30.509 ; 30.509 ;
; SD_RESETn    ; RAM_DATA[7]   ; 31.824 ; 31.824 ; 31.824 ; 31.824 ;
; SD_RESETn    ; RAM_DATA[8]   ; 28.782 ; 30.183 ; 30.183 ; 28.782 ;
; SD_RESETn    ; RAM_DATA[9]   ; 25.985 ; 27.189 ; 27.189 ; 25.985 ;
; SD_RESETn    ; RAM_DATA[10]  ; 24.814 ; 25.753 ; 25.753 ; 24.814 ;
; SD_RESETn    ; RAM_DATA[11]  ; 26.865 ; 27.434 ; 27.434 ; 26.865 ;
; SD_RESETn    ; RAM_DATA[12]  ; 26.566 ; 27.311 ; 27.311 ; 26.566 ;
; SD_RESETn    ; RAM_DATA[13]  ; 26.036 ; 27.062 ; 27.062 ; 26.036 ;
; SD_RESETn    ; RAM_DATA[14]  ; 30.502 ; 30.502 ; 30.502 ; 30.502 ;
; SD_RESETn    ; RAM_DATA[15]  ; 29.024 ; 29.024 ; 29.024 ; 29.024 ;
; UDSn         ; ACSI_RDn      ; 18.525 ; 18.525 ; 18.525 ; 18.525 ;
; UDSn         ; ACSI_WRn      ; 18.802 ; 18.802 ; 18.802 ; 18.802 ;
; UDSn         ; CA1_OUT       ; 17.812 ;        ;        ; 17.812 ;
; UDSn         ; CD[0]         ; 28.709 ; 28.709 ; 28.709 ; 28.709 ;
; UDSn         ; CD[1]         ; 28.339 ; 28.339 ; 28.339 ; 28.339 ;
; UDSn         ; CD[2]         ; 25.001 ; 25.001 ; 25.001 ; 25.001 ;
; UDSn         ; CD[3]         ; 29.068 ; 29.068 ; 29.068 ; 29.068 ;
; UDSn         ; CD[4]         ; 29.191 ; 29.191 ; 29.191 ; 29.191 ;
; UDSn         ; CD[5]         ; 28.131 ; 28.131 ; 28.131 ; 28.131 ;
; UDSn         ; CD[6]         ; 29.014 ; 29.014 ; 29.014 ; 29.014 ;
; UDSn         ; CD[7]         ; 25.698 ; 25.698 ; 25.698 ; 25.698 ;
; UDSn         ; DATA[0]       ; 29.689 ; 28.502 ; 28.502 ; 29.689 ;
; UDSn         ; DATA[1]       ; 30.722 ; 28.998 ; 28.998 ; 30.722 ;
; UDSn         ; DATA[2]       ; 30.297 ; 28.460 ; 28.460 ; 30.297 ;
; UDSn         ; DATA[3]       ; 31.409 ; 30.196 ; 30.196 ; 31.409 ;
; UDSn         ; DATA[4]       ; 29.440 ; 29.440 ; 29.440 ; 29.440 ;
; UDSn         ; DATA[5]       ; 29.788 ; 29.788 ; 29.788 ; 29.788 ;
; UDSn         ; DATA[6]       ; 29.383 ; 28.632 ; 28.632 ; 29.383 ;
; UDSn         ; DATA[7]       ; 29.895 ; 28.540 ; 28.540 ; 29.895 ;
; UDSn         ; DATA[8]       ; 29.800 ; 29.938 ; 29.938 ; 29.800 ;
; UDSn         ; DATA[9]       ; 28.747 ; 29.206 ; 29.206 ; 28.747 ;
; UDSn         ; DATA[10]      ; 27.610 ; 27.078 ; 27.078 ; 27.610 ;
; UDSn         ; DATA[11]      ; 27.634 ; 28.287 ; 28.287 ; 27.634 ;
; UDSn         ; DATA[12]      ; 28.178 ; 27.530 ; 27.530 ; 28.178 ;
; UDSn         ; DATA[13]      ; 28.742 ; 28.664 ; 28.664 ; 28.742 ;
; UDSn         ; DATA[14]      ; 28.768 ; 28.768 ; 28.768 ; 28.768 ;
; UDSn         ; DATA[15]      ; 29.051 ; 29.051 ; 29.051 ; 29.051 ;
; UDSn         ; DTACKn        ; 20.852 ; 20.852 ; 20.852 ; 20.852 ;
; UDSn         ; JOY_RHn       ; 14.422 ;        ;        ; 14.422 ;
; UDSn         ; RAM_CAS0n     ; 14.288 ;        ;        ; 14.288 ;
; UDSn         ; RAM_CAS1n     ; 14.273 ;        ;        ; 14.273 ;
; UDSn         ; RAM_DATA[0]   ; 31.337 ; 30.150 ; 30.150 ; 31.337 ;
; UDSn         ; RAM_DATA[1]   ; 31.254 ; 29.530 ; 29.530 ; 31.254 ;
; UDSn         ; RAM_DATA[2]   ; 30.585 ; 28.748 ; 28.748 ; 30.585 ;
; UDSn         ; RAM_DATA[3]   ; 31.360 ; 30.147 ; 30.147 ; 31.360 ;
; UDSn         ; RAM_DATA[4]   ; 28.642 ; 28.642 ; 28.642 ; 28.642 ;
; UDSn         ; RAM_DATA[5]   ; 32.299 ; 32.299 ; 32.299 ; 32.299 ;
; UDSn         ; RAM_DATA[6]   ; 31.869 ; 31.118 ; 31.118 ; 31.869 ;
; UDSn         ; RAM_DATA[7]   ; 32.316 ; 30.961 ; 30.961 ; 32.316 ;
; UDSn         ; RAM_DATA[8]   ; 31.657 ; 31.795 ; 31.795 ; 31.657 ;
; UDSn         ; RAM_DATA[9]   ; 28.899 ; 29.358 ; 29.358 ; 28.899 ;
; UDSn         ; RAM_DATA[10]  ; 27.878 ; 27.346 ; 27.346 ; 27.878 ;
; UDSn         ; RAM_DATA[11]  ; 28.795 ; 29.448 ; 29.448 ; 28.795 ;
; UDSn         ; RAM_DATA[12]  ; 29.304 ; 28.656 ; 28.656 ; 29.304 ;
; UDSn         ; RAM_DATA[13]  ; 28.978 ; 28.900 ; 28.900 ; 28.978 ;
; UDSn         ; RAM_DATA[14]  ; 31.134 ; 31.134 ; 31.134 ; 31.134 ;
; UDSn         ; RAM_DATA[15]  ; 29.373 ; 29.373 ; 29.373 ; 29.373 ;
; UDSn         ; RAM_DQM0H     ; 15.397 ;        ;        ; 15.397 ;
; UDSn         ; RAM_DQM1H     ; 13.646 ;        ;        ; 13.646 ;
+--------------+---------------+--------+--------+--------+--------+


+------------------------------------------------------------------+
; Minimum Propagation Delay                                        ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 17.203 ; 17.203 ; 17.203 ; 17.203 ;
; ASn          ; ACSI_WRn      ; 17.472 ; 17.472 ; 17.472 ; 17.472 ;
; ASn          ; BUTTONn       ; 21.015 ;        ;        ; 21.015 ;
; ASn          ; CA1_OUT       ; 17.459 ;        ;        ; 17.459 ;
; ASn          ; CD[0]         ; 20.418 ; 19.603 ; 19.603 ; 20.418 ;
; ASn          ; CD[1]         ; 20.601 ; 19.840 ; 19.840 ; 20.601 ;
; ASn          ; CD[2]         ; 18.768 ; 17.957 ; 17.957 ; 18.768 ;
; ASn          ; CD[3]         ; 20.601 ; 20.270 ; 20.270 ; 20.601 ;
; ASn          ; CD[4]         ; 19.128 ; 19.128 ; 19.128 ; 19.128 ;
; ASn          ; CD[5]         ; 17.957 ; 17.957 ; 17.957 ; 17.957 ;
; ASn          ; CD[6]         ; 18.357 ; 18.357 ; 18.357 ; 18.357 ;
; ASn          ; CD[7]         ; 19.574 ; 19.574 ; 19.574 ; 19.574 ;
; ASn          ; DATA[0]       ; 19.281 ; 19.281 ; 19.281 ; 19.281 ;
; ASn          ; DATA[1]       ; 19.281 ; 19.281 ; 19.281 ; 19.281 ;
; ASn          ; DATA[2]       ; 19.266 ; 19.266 ; 19.266 ; 19.266 ;
; ASn          ; DATA[3]       ; 19.266 ; 19.266 ; 19.266 ; 19.266 ;
; ASn          ; DATA[4]       ; 19.251 ; 19.251 ; 19.251 ; 19.251 ;
; ASn          ; DATA[5]       ; 19.251 ; 19.251 ; 19.251 ; 19.251 ;
; ASn          ; DATA[6]       ; 19.209 ; 19.209 ; 19.209 ; 19.209 ;
; ASn          ; DATA[7]       ; 19.199 ; 19.199 ; 19.199 ; 19.199 ;
; ASn          ; DATA[8]       ; 19.266 ; 19.266 ; 19.266 ; 19.266 ;
; ASn          ; DATA[9]       ; 19.266 ; 19.266 ; 19.266 ; 19.266 ;
; ASn          ; DATA[10]      ; 19.628 ; 19.628 ; 19.628 ; 19.628 ;
; ASn          ; DATA[11]      ; 19.628 ; 19.283 ; 19.283 ; 19.628 ;
; ASn          ; DATA[12]      ; 19.223 ; 19.596 ; 19.596 ; 19.223 ;
; ASn          ; DATA[13]      ; 19.596 ; 19.596 ; 19.596 ; 19.596 ;
; ASn          ; DATA[14]      ; 19.536 ; 19.536 ; 19.536 ; 19.536 ;
; ASn          ; DATA[15]      ; 19.964 ; 19.964 ; 19.964 ; 19.964 ;
; ASn          ; DTACKn        ; 14.937 ; 14.937 ; 14.937 ; 14.937 ;
; ASn          ; FLASH_CEn     ; 18.663 ;        ;        ; 18.663 ;
; ASn          ; FLASH_OEn     ; 18.593 ;        ;        ; 18.593 ;
; ASn          ; IDE_CS0n      ; 13.444 ;        ;        ; 13.444 ;
; ASn          ; IDE_CS1n      ; 14.385 ;        ;        ; 14.385 ;
; ASn          ; IDE_D_EN_INn  ; 13.942 ;        ;        ; 13.942 ;
; ASn          ; IDE_D_EN_OUTn ; 13.756 ;        ;        ; 13.756 ;
; ASn          ; IDE_IORDn     ; 13.562 ;        ;        ; 13.562 ;
; ASn          ; IDE_IOWRn     ; 14.978 ;        ;        ; 14.978 ;
; ASn          ; JOY_RHn       ; 16.667 ;        ;        ; 16.667 ;
; ASn          ; JOY_RLn       ; 19.258 ;        ;        ; 19.258 ;
; ASn          ; JOY_WEn       ;        ; 18.892 ; 18.892 ;        ;
; ASn          ; JOY_WL        ;        ; 13.471 ; 13.471 ;        ;
; ASn          ; RAM_ADR[8]    ;        ; 18.145 ; 18.145 ;        ;
; ASn          ; RAM_BA[0]     ;        ; 16.502 ; 16.502 ;        ;
; ASn          ; RAM_BA[1]     ;        ; 14.480 ; 14.480 ;        ;
; ASn          ; RAM_CAS0n     ;        ; 16.664 ; 16.664 ;        ;
; ASn          ; RAM_CAS1n     ; 16.660 ;        ;        ; 16.660 ;
; ASn          ; RAM_DATA[0]   ; 22.405 ; 22.405 ; 22.405 ; 22.405 ;
; ASn          ; RAM_DATA[1]   ; 21.421 ; 21.461 ; 21.461 ; 21.421 ;
; ASn          ; RAM_DATA[2]   ; 21.228 ; 22.243 ; 22.243 ; 21.228 ;
; ASn          ; RAM_DATA[3]   ; 21.617 ; 22.589 ; 22.589 ; 21.617 ;
; ASn          ; RAM_DATA[4]   ; 20.645 ; 21.587 ; 21.587 ; 20.645 ;
; ASn          ; RAM_DATA[5]   ; 24.615 ; 24.615 ; 24.615 ; 24.615 ;
; ASn          ; RAM_DATA[6]   ; 22.180 ; 22.440 ; 22.440 ; 22.180 ;
; ASn          ; RAM_DATA[7]   ; 22.821 ; 23.437 ; 23.437 ; 22.821 ;
; ASn          ; RAM_DATA[8]   ; 23.822 ; 24.200 ; 24.200 ; 23.822 ;
; ASn          ; RAM_DATA[9]   ; 20.548 ; 21.781 ; 21.781 ; 20.548 ;
; ASn          ; RAM_DATA[10]  ; 19.911 ; 20.738 ; 20.738 ; 19.911 ;
; ASn          ; RAM_DATA[11]  ; 21.978 ; 20.444 ; 20.444 ; 21.978 ;
; ASn          ; RAM_DATA[12]  ; 20.349 ; 21.737 ; 21.737 ; 20.349 ;
; ASn          ; RAM_DATA[13]  ; 21.447 ; 21.667 ; 21.667 ; 21.447 ;
; ASn          ; RAM_DATA[14]  ; 21.902 ; 21.902 ; 21.902 ; 21.902 ;
; ASn          ; RAM_DATA[15]  ; 20.841 ; 20.841 ; 20.841 ; 20.841 ;
; ASn          ; RAM_DQM0H     ;        ; 17.850 ; 17.850 ;        ;
; ASn          ; RAM_DQM0L     ;        ; 17.046 ; 17.046 ;        ;
; ASn          ; RAM_DQM1H     ; 16.098 ;        ;        ; 16.098 ;
; ASn          ; RAM_DQM1L     ; 16.999 ;        ;        ; 16.999 ;
; ASn          ; RAM_RAS0n     ;        ; 17.565 ; 17.565 ;        ;
; ASn          ; RAM_RAS1n     ; 16.924 ;        ;        ; 16.924 ;
; ASn          ; ROM0n         ; 17.610 ;        ;        ; 17.610 ;
; ASn          ; ROM1n         ; 17.229 ;        ;        ; 17.229 ;
; ASn          ; ROM2n         ; 15.327 ;        ;        ; 15.327 ;
; ASn          ; ROM3n         ; 17.515 ;        ;        ; 17.515 ;
; ASn          ; ROM4n         ; 18.810 ;        ;        ; 18.810 ;
; ASn          ; ROM5n         ; 14.300 ;        ;        ; 14.300 ;
; ASn          ; ROM6n         ; 17.723 ;        ;        ; 17.723 ;
; COM_CTS      ; DATA[2]       ;        ; 22.061 ; 22.061 ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 22.349 ; 22.349 ;        ;
; COM_DCD      ; DATA[1]       ;        ; 22.235 ; 22.235 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 22.767 ; 22.767 ;        ;
; COM_RI       ; DATA[6]       ;        ; 21.072 ; 21.072 ;        ;
; COM_RI       ; RAM_DATA[6]   ;        ; 23.558 ; 23.558 ;        ;
; CONFIG[1]    ; DATA[7]       ; 24.247 ; 24.247 ; 24.247 ; 24.247 ;
; CONFIG[1]    ; HSYNC         ; 14.469 ; 14.469 ; 14.469 ; 14.469 ;
; CONFIG[1]    ; RAM_DATA[7]   ; 26.668 ; 26.668 ; 26.668 ; 26.668 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 16.363 ; 16.363 ; 16.363 ; 16.363 ;
; CONFIG[1]    ; RAM_DATA[13]  ; 16.801 ; 16.801 ; 16.801 ; 16.801 ;
; CONFIG[1]    ; RAM_DATA[14]  ; 16.938 ; 16.938 ; 16.938 ; 16.938 ;
; CONFIG[1]    ; RAM_DATA[15]  ; 15.429 ; 15.429 ; 15.429 ; 15.429 ;
; CONFIG[1]    ; VSYNC         ; 14.171 ; 14.171 ; 14.171 ; 14.171 ;
; CONFIG[2]    ; DATA[7]       ; 22.962 ; 22.962 ; 22.962 ; 22.962 ;
; CONFIG[2]    ; HSYNC         ; 14.304 ; 14.304 ; 14.304 ; 14.304 ;
; CONFIG[2]    ; RAM_DATA[7]   ; 25.383 ; 25.383 ; 25.383 ; 25.383 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 16.565 ; 16.565 ; 16.565 ; 16.565 ;
; CONFIG[2]    ; RAM_DATA[13]  ; 17.003 ; 17.003 ; 17.003 ; 17.003 ;
; CONFIG[2]    ; RAM_DATA[14]  ; 17.140 ; 17.140 ; 17.140 ; 17.140 ;
; CONFIG[2]    ; RAM_DATA[15]  ; 15.631 ; 15.631 ; 15.631 ; 15.631 ;
; CONFIG[2]    ; VSYNC         ; 14.001 ; 14.001 ; 14.001 ; 14.001 ;
; CONFIG[3]    ; LDSn          ; 23.789 ; 23.896 ; 23.896 ; 23.789 ;
; CONFIG[3]    ; UDSn          ; 24.187 ; 24.294 ; 24.294 ; 24.187 ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 16.269 ; 16.269 ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 14.226 ; 14.226 ;        ;
; CONFIG[5]    ; ACSI_RDn      ; 22.301 ; 22.301 ; 22.301 ; 22.301 ;
; CONFIG[5]    ; ACSI_WRn      ; 22.570 ; 22.570 ; 22.570 ; 22.570 ;
; CONFIG[5]    ; BUTTONn       ; 20.845 ; 20.845 ; 20.845 ; 20.845 ;
; CONFIG[5]    ; CA1_OUT       ; 22.557 ; 22.557 ; 22.557 ; 22.557 ;
; CONFIG[5]    ; CD[0]         ; 24.701 ; 24.701 ; 24.701 ; 24.701 ;
; CONFIG[5]    ; CD[1]         ; 24.938 ; 24.938 ; 24.938 ; 24.938 ;
; CONFIG[5]    ; CD[2]         ; 23.055 ; 23.055 ; 23.055 ; 23.055 ;
; CONFIG[5]    ; CD[3]         ; 25.368 ; 25.368 ; 25.368 ; 25.368 ;
; CONFIG[5]    ; CD[4]         ; 24.226 ; 24.226 ; 24.226 ; 24.226 ;
; CONFIG[5]    ; CD[5]         ; 23.055 ; 23.055 ; 23.055 ; 23.055 ;
; CONFIG[5]    ; CD[6]         ; 23.455 ; 23.455 ; 23.455 ; 23.455 ;
; CONFIG[5]    ; CD[7]         ; 24.672 ; 24.672 ; 24.672 ; 24.672 ;
; CONFIG[5]    ; DATA[0]       ; 19.034 ; 19.034 ; 19.034 ; 19.034 ;
; CONFIG[5]    ; DATA[1]       ; 19.034 ; 19.034 ; 19.034 ; 19.034 ;
; CONFIG[5]    ; DATA[2]       ; 19.019 ; 19.019 ; 19.019 ; 19.019 ;
; CONFIG[5]    ; DATA[3]       ; 19.019 ; 19.019 ; 19.019 ; 19.019 ;
; CONFIG[5]    ; DATA[4]       ; 19.004 ; 19.004 ; 19.004 ; 19.004 ;
; CONFIG[5]    ; DATA[5]       ; 19.004 ; 19.004 ; 19.004 ; 19.004 ;
; CONFIG[5]    ; DATA[6]       ; 18.962 ; 18.962 ; 18.962 ; 18.962 ;
; CONFIG[5]    ; DATA[7]       ; 18.952 ; 18.952 ; 18.952 ; 18.952 ;
; CONFIG[5]    ; DATA[8]       ; 19.019 ; 19.019 ; 19.019 ; 19.019 ;
; CONFIG[5]    ; DATA[9]       ; 19.019 ; 19.019 ; 19.019 ; 19.019 ;
; CONFIG[5]    ; DATA[10]      ; 19.381 ; 19.381 ; 19.381 ; 19.381 ;
; CONFIG[5]    ; DATA[11]      ; 19.381 ; 19.381 ; 19.381 ; 19.381 ;
; CONFIG[5]    ; DATA[12]      ; 19.349 ; 19.349 ; 19.349 ; 19.349 ;
; CONFIG[5]    ; DATA[13]      ; 19.349 ; 19.349 ; 19.349 ; 19.349 ;
; CONFIG[5]    ; DATA[14]      ; 19.727 ; 19.727 ; 19.727 ; 19.727 ;
; CONFIG[5]    ; DATA[15]      ; 19.717 ; 19.717 ; 19.717 ; 19.717 ;
; CONFIG[5]    ; DTACKn        ; 20.035 ; 20.035 ; 20.035 ; 20.035 ;
; CONFIG[5]    ; FLASH_CEn     ; 20.894 ; 20.894 ; 20.894 ; 20.894 ;
; CONFIG[5]    ; FLASH_OEn     ; 20.824 ; 20.824 ; 20.824 ; 20.824 ;
; CONFIG[5]    ; IDE_CS0n      ; 18.598 ; 18.598 ; 18.598 ; 18.598 ;
; CONFIG[5]    ; IDE_CS1n      ; 19.539 ; 19.539 ; 19.539 ; 19.539 ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 18.564 ; 18.564 ; 18.564 ; 18.564 ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 18.910 ; 18.910 ; 18.910 ; 18.910 ;
; CONFIG[5]    ; IDE_IORDn     ; 18.971 ; 18.971 ; 18.971 ; 18.971 ;
; CONFIG[5]    ; IDE_IOWRn     ; 20.375 ; 20.375 ; 20.375 ; 20.375 ;
; CONFIG[5]    ; JOY_RHn       ; 20.684 ; 20.684 ; 20.684 ; 20.684 ;
; CONFIG[5]    ; JOY_RLn       ; 23.275 ; 23.275 ; 23.275 ; 23.275 ;
; CONFIG[5]    ; JOY_WEn       ; 22.909 ; 22.909 ; 22.909 ; 22.909 ;
; CONFIG[5]    ; JOY_WL        ; 19.584 ; 19.584 ; 19.584 ; 19.584 ;
; CONFIG[5]    ; RAM_ADR[8]    ; 20.275 ; 18.052 ; 18.052 ; 20.275 ;
; CONFIG[5]    ; RAM_BA[0]     ; 18.632 ; 16.409 ; 16.409 ; 18.632 ;
; CONFIG[5]    ; RAM_BA[1]     ; 16.254 ; 14.387 ; 14.387 ; 16.254 ;
; CONFIG[5]    ; RAM_CAS0n     ; 18.362 ; 16.571 ; 16.571 ; 18.362 ;
; CONFIG[5]    ; RAM_CAS1n     ; 16.567 ; 18.358 ; 18.358 ; 16.567 ;
; CONFIG[5]    ; RAM_DATA[0]   ; 24.416 ; 24.416 ; 24.416 ; 24.416 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 24.189 ; 24.189 ; 24.189 ; 24.189 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 24.173 ; 24.173 ; 24.173 ; 24.173 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 25.543 ; 25.543 ; 25.543 ; 25.543 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 23.665 ; 23.665 ; 23.665 ; 23.665 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 25.930 ; 25.930 ; 25.930 ; 25.930 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 25.301 ; 25.301 ; 25.301 ; 25.301 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 26.819 ; 26.819 ; 26.819 ; 26.819 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 26.431 ; 26.431 ; 26.431 ; 26.431 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 24.735 ; 24.735 ; 24.735 ; 24.735 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 23.664 ; 23.664 ; 23.664 ; 23.664 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 24.634 ; 24.634 ; 24.634 ; 24.634 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 24.606 ; 24.606 ; 24.606 ; 24.606 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 25.596 ; 25.596 ; 25.596 ; 25.596 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 26.446 ; 26.446 ; 26.446 ; 26.446 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 25.021 ; 25.021 ; 25.021 ; 25.021 ;
; CONFIG[5]    ; RAM_DQM0H     ; 19.548 ; 17.757 ; 17.757 ; 19.548 ;
; CONFIG[5]    ; RAM_DQM0L     ; 18.744 ; 16.953 ; 16.953 ; 18.744 ;
; CONFIG[5]    ; RAM_DQM1H     ; 16.005 ; 17.796 ; 17.796 ; 16.005 ;
; CONFIG[5]    ; RAM_DQM1L     ; 16.906 ; 18.697 ; 18.697 ; 16.906 ;
; CONFIG[5]    ; RAM_RAS0n     ; 19.263 ; 17.472 ; 17.472 ; 19.263 ;
; CONFIG[5]    ; RAM_RAS1n     ; 16.831 ; 18.622 ; 18.622 ; 16.831 ;
; CONFIG[5]    ; ROM0n         ; 18.191 ; 18.191 ; 18.191 ; 18.191 ;
; CONFIG[5]    ; ROM1n         ; 17.726 ; 17.467 ; 17.467 ; 17.726 ;
; CONFIG[5]    ; ROM2n         ; 17.558 ; 17.558 ; 17.558 ; 17.558 ;
; CONFIG[5]    ; ROM3n         ; 19.499 ; 19.405 ; 19.405 ; 19.499 ;
; CONFIG[5]    ; ROM4n         ; 19.762 ; 19.947 ; 19.947 ; 19.762 ;
; CONFIG[5]    ; ROM5n         ; 18.266 ; 18.266 ; 18.266 ; 18.266 ;
; CONFIG[5]    ; ROM6n         ; 19.483 ; 19.298 ; 19.298 ; 19.483 ;
; CONFIG[6]    ; DATA[0]       ; 24.513 ; 24.513 ; 24.513 ; 24.513 ;
; CONFIG[6]    ; DATA[1]       ; 23.547 ; 23.547 ; 23.547 ; 23.547 ;
; CONFIG[6]    ; DATA[2]       ; 24.567 ; 24.567 ; 24.567 ; 24.567 ;
; CONFIG[6]    ; DATA[3]       ; 24.087 ; 24.087 ; 24.087 ; 24.087 ;
; CONFIG[6]    ; DATA[4]       ; 24.297 ; 24.297 ; 24.297 ; 24.297 ;
; CONFIG[6]    ; DATA[5]       ; 25.485 ; 25.485 ; 25.485 ; 25.485 ;
; CONFIG[6]    ; DATA[6]       ; 23.780 ; 23.780 ; 23.780 ; 23.780 ;
; CONFIG[6]    ; DATA[7]       ; 22.437 ; 22.437 ; 22.437 ; 22.437 ;
; CONFIG[6]    ; DATA[8]       ; 24.693 ; 24.693 ; 24.693 ; 24.693 ;
; CONFIG[6]    ; DATA[9]       ; 24.521 ; 24.521 ; 24.521 ; 24.521 ;
; CONFIG[6]    ; DATA[10]      ; 23.217 ; 23.217 ; 23.217 ; 23.217 ;
; CONFIG[6]    ; DATA[11]      ; 24.102 ; 24.102 ; 24.102 ; 24.102 ;
; CONFIG[6]    ; DATA[12]      ; 22.656 ; 22.656 ; 22.656 ; 22.656 ;
; CONFIG[6]    ; DATA[13]      ; 23.958 ; 23.958 ; 23.958 ; 23.958 ;
; CONFIG[6]    ; DATA[14]      ; 21.231 ; 21.231 ; 21.231 ; 21.231 ;
; CONFIG[6]    ; DATA[15]      ; 22.214 ; 22.214 ; 22.214 ; 22.214 ;
; CONFIG[6]    ; DTACKn        ; 18.868 ; 18.868 ; 18.868 ; 18.868 ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 15.059 ; 15.059 ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 14.809 ; 14.809 ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 18.045 ; 18.045 ; 18.045 ; 18.045 ;
; CONFIG[6]    ; FLASH_OEn     ; 17.975 ; 17.975 ; 17.975 ; 17.975 ;
; CONFIG[6]    ; RAM_DATA[0]   ; 26.161 ; 26.161 ; 26.161 ; 26.161 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 24.079 ; 24.079 ; 24.079 ; 24.079 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 24.855 ; 24.855 ; 24.855 ; 24.855 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 24.038 ; 24.038 ; 24.038 ; 24.038 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 23.499 ; 23.499 ; 23.499 ; 23.499 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 27.996 ; 27.996 ; 27.996 ; 27.996 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 26.266 ; 26.266 ; 26.266 ; 26.266 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 24.858 ; 24.858 ; 24.858 ; 24.858 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 26.550 ; 26.550 ; 26.550 ; 26.550 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 24.673 ; 24.673 ; 24.673 ; 24.673 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 23.485 ; 23.485 ; 23.485 ; 23.485 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 25.263 ; 25.263 ; 25.263 ; 25.263 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 23.782 ; 23.782 ; 23.782 ; 23.782 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 24.194 ; 24.194 ; 24.194 ; 24.194 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 23.597 ; 23.597 ; 23.597 ; 23.597 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 22.536 ; 22.536 ; 22.536 ; 22.536 ;
; CONFIG[6]    ; ROM2n         ; 14.709 ; 14.709 ; 14.709 ; 14.709 ;
; CRT_PIN3     ; DATA[7]       ; 19.095 ; 19.095 ; 19.095 ; 19.095 ;
; CRT_PIN3     ; RAM_DATA[7]   ; 21.516 ; 21.516 ; 21.516 ; 21.516 ;
; CRT_PIN3     ; RAM_DATA[12]  ; 11.813 ; 11.813 ; 11.813 ; 11.813 ;
; CRT_PIN3     ; RAM_DATA[13]  ; 12.251 ; 12.251 ; 12.251 ; 12.251 ;
; CRT_PIN3     ; RAM_DATA[14]  ; 12.388 ; 12.388 ; 12.388 ; 12.388 ;
; CRT_PIN3     ; RAM_DATA[15]  ; 10.879 ; 10.879 ; 10.879 ; 10.879 ;
; DATA[0]      ; DATA[0]       ; 14.930 ;        ;        ; 14.930 ;
; DATA[0]      ; RAM_DATA[0]   ; 16.578 ;        ;        ; 16.578 ;
; DATA[1]      ; DATA[1]       ; 16.563 ;        ;        ; 16.563 ;
; DATA[1]      ; RAM_DATA[1]   ; 17.095 ;        ;        ; 17.095 ;
; DATA[2]      ; DATA[2]       ; 15.374 ;        ;        ; 15.374 ;
; DATA[2]      ; RAM_DATA[2]   ; 15.662 ;        ;        ; 15.662 ;
; DATA[3]      ; DATA[3]       ; 16.708 ;        ;        ; 16.708 ;
; DATA[3]      ; RAM_DATA[3]   ; 16.659 ;        ;        ; 16.659 ;
; DATA[4]      ; DATA[4]       ; 16.803 ;        ;        ; 16.803 ;
; DATA[4]      ; RAM_DATA[4]   ; 16.005 ;        ;        ; 16.005 ;
; DATA[5]      ; DATA[5]       ; 17.162 ;        ;        ; 17.162 ;
; DATA[5]      ; RAM_DATA[5]   ; 19.673 ;        ;        ; 19.673 ;
; DATA[6]      ; DATA[6]       ; 16.538 ;        ;        ; 16.538 ;
; DATA[6]      ; RAM_DATA[6]   ; 19.024 ;        ;        ; 19.024 ;
; DATA[7]      ; DATA[7]       ; 18.419 ;        ;        ; 18.419 ;
; DATA[7]      ; RAM_DATA[7]   ; 20.840 ;        ;        ; 20.840 ;
; DATA[8]      ; DATA[8]       ; 16.712 ;        ;        ; 16.712 ;
; DATA[8]      ; RAM_DATA[8]   ; 18.569 ;        ;        ; 18.569 ;
; DATA[9]      ; DATA[9]       ; 15.779 ;        ;        ; 15.779 ;
; DATA[9]      ; RAM_DATA[9]   ; 15.931 ;        ;        ; 15.931 ;
; DATA[10]     ; DATA[10]      ; 14.369 ;        ;        ; 14.369 ;
; DATA[10]     ; RAM_DATA[10]  ; 14.637 ;        ;        ; 14.637 ;
; DATA[11]     ; DATA[11]      ; 16.545 ;        ;        ; 16.545 ;
; DATA[11]     ; RAM_DATA[11]  ; 17.706 ;        ;        ; 17.706 ;
; DATA[12]     ; DATA[12]      ; 16.861 ;        ;        ; 16.861 ;
; DATA[12]     ; RAM_DATA[12]  ; 17.987 ;        ;        ; 17.987 ;
; DATA[13]     ; DATA[13]      ; 16.780 ;        ;        ; 16.780 ;
; DATA[13]     ; RAM_DATA[13]  ; 17.016 ;        ;        ; 17.016 ;
; DATA[14]     ; DATA[14]      ; 15.246 ;        ;        ; 15.246 ;
; DATA[14]     ; RAM_DATA[14]  ; 17.612 ;        ;        ; 17.612 ;
; DATA[15]     ; DATA[15]      ; 17.491 ;        ;        ; 17.491 ;
; DATA[15]     ; RAM_DATA[15]  ; 17.813 ;        ;        ; 17.813 ;
; FC[0]        ; ACSI_RDn      ; 20.002 ; 20.002 ; 20.002 ; 20.002 ;
; FC[0]        ; ACSI_WRn      ; 20.271 ; 20.271 ; 20.271 ; 20.271 ;
; FC[0]        ; BUTTONn       ; 18.528 ; 18.528 ; 18.528 ; 18.528 ;
; FC[0]        ; CA1_OUT       ; 20.258 ; 20.258 ; 20.258 ; 20.258 ;
; FC[0]        ; CD[0]         ; 22.402 ; 22.402 ; 22.402 ; 22.402 ;
; FC[0]        ; CD[1]         ; 22.639 ; 22.639 ; 22.639 ; 22.639 ;
; FC[0]        ; CD[2]         ; 20.756 ; 20.756 ; 20.756 ; 20.756 ;
; FC[0]        ; CD[3]         ; 23.069 ; 23.069 ; 23.069 ; 23.069 ;
; FC[0]        ; CD[4]         ; 21.927 ; 21.927 ; 21.927 ; 21.927 ;
; FC[0]        ; CD[5]         ; 20.756 ; 20.756 ; 20.756 ; 20.756 ;
; FC[0]        ; CD[6]         ; 21.156 ; 21.156 ; 21.156 ; 21.156 ;
; FC[0]        ; CD[7]         ; 22.373 ; 22.373 ; 22.373 ; 22.373 ;
; FC[0]        ; DATA[0]       ; 19.750 ; 19.750 ; 19.750 ; 19.750 ;
; FC[0]        ; DATA[1]       ; 19.253 ; 19.253 ; 19.253 ; 19.253 ;
; FC[0]        ; DATA[2]       ; 19.020 ; 19.020 ; 19.020 ; 19.020 ;
; FC[0]        ; DATA[3]       ; 19.746 ; 19.746 ; 19.746 ; 19.746 ;
; FC[0]        ; DATA[4]       ; 19.523 ; 19.523 ; 19.523 ; 19.523 ;
; FC[0]        ; DATA[5]       ; 22.933 ; 22.933 ; 22.933 ; 22.933 ;
; FC[0]        ; DATA[6]       ; 17.774 ; 17.774 ; 17.774 ; 17.774 ;
; FC[0]        ; DATA[7]       ; 18.480 ; 18.480 ; 18.480 ; 18.480 ;
; FC[0]        ; DATA[8]       ; 20.318 ; 20.318 ; 20.318 ; 20.318 ;
; FC[0]        ; DATA[9]       ; 18.476 ; 18.476 ; 18.476 ; 18.476 ;
; FC[0]        ; DATA[10]      ; 17.723 ; 17.723 ; 17.723 ; 17.723 ;
; FC[0]        ; DATA[11]      ; 18.907 ; 18.907 ; 18.907 ; 18.907 ;
; FC[0]        ; DATA[12]      ; 17.303 ; 17.303 ; 17.303 ; 17.303 ;
; FC[0]        ; DATA[13]      ; 19.291 ; 19.291 ; 19.291 ; 19.291 ;
; FC[0]        ; DATA[14]      ; 18.590 ; 18.590 ; 18.590 ; 18.590 ;
; FC[0]        ; DATA[15]      ; 18.621 ; 18.621 ; 18.621 ; 18.621 ;
; FC[0]        ; DTACKn        ; 15.645 ; 15.645 ; 15.645 ; 15.645 ;
; FC[0]        ; FLASH_CEn     ; 18.470 ; 18.470 ; 18.470 ; 18.470 ;
; FC[0]        ; FLASH_OEn     ; 18.400 ; 18.400 ; 18.400 ; 18.400 ;
; FC[0]        ; JOY_RHn       ; 21.012 ; 21.012 ; 21.012 ; 21.012 ;
; FC[0]        ; JOY_RLn       ; 23.603 ; 23.603 ; 23.603 ; 23.603 ;
; FC[0]        ; JOY_WEn       ; 23.237 ; 23.237 ; 23.237 ; 23.237 ;
; FC[0]        ; JOY_WL        ; 17.816 ; 17.816 ; 17.816 ; 17.816 ;
; FC[0]        ; RAM_ADR[8]    ; 17.955 ; 17.955 ; 17.955 ; 17.955 ;
; FC[0]        ; RAM_BA[0]     ; 16.312 ; 16.312 ; 16.312 ; 16.312 ;
; FC[0]        ; RAM_BA[1]     ; 14.290 ; 14.290 ; 14.290 ; 14.290 ;
; FC[0]        ; RAM_CAS0n     ; 16.474 ; 16.474 ; 16.474 ; 16.474 ;
; FC[0]        ; RAM_CAS1n     ; 16.470 ; 16.470 ; 16.470 ; 16.470 ;
; FC[0]        ; RAM_DATA[0]   ; 21.398 ; 21.398 ; 21.398 ; 21.398 ;
; FC[0]        ; RAM_DATA[1]   ; 19.785 ; 19.785 ; 19.785 ; 19.785 ;
; FC[0]        ; RAM_DATA[2]   ; 19.308 ; 19.308 ; 19.308 ; 19.308 ;
; FC[0]        ; RAM_DATA[3]   ; 19.697 ; 19.697 ; 19.697 ; 19.697 ;
; FC[0]        ; RAM_DATA[4]   ; 18.725 ; 18.725 ; 18.725 ; 18.725 ;
; FC[0]        ; RAM_DATA[5]   ; 25.444 ; 25.444 ; 25.444 ; 25.444 ;
; FC[0]        ; RAM_DATA[6]   ; 20.260 ; 20.260 ; 20.260 ; 20.260 ;
; FC[0]        ; RAM_DATA[7]   ; 20.901 ; 20.901 ; 20.901 ; 20.901 ;
; FC[0]        ; RAM_DATA[8]   ; 22.175 ; 22.175 ; 22.175 ; 22.175 ;
; FC[0]        ; RAM_DATA[9]   ; 18.628 ; 18.628 ; 18.628 ; 18.628 ;
; FC[0]        ; RAM_DATA[10]  ; 17.991 ; 17.991 ; 17.991 ; 17.991 ;
; FC[0]        ; RAM_DATA[11]  ; 20.068 ; 20.068 ; 20.068 ; 20.068 ;
; FC[0]        ; RAM_DATA[12]  ; 18.429 ; 18.429 ; 18.429 ; 18.429 ;
; FC[0]        ; RAM_DATA[13]  ; 19.527 ; 19.527 ; 19.527 ; 19.527 ;
; FC[0]        ; RAM_DATA[14]  ; 20.956 ; 20.956 ; 20.956 ; 20.956 ;
; FC[0]        ; RAM_DATA[15]  ; 18.943 ; 18.943 ; 18.943 ; 18.943 ;
; FC[0]        ; RAM_DQM0H     ; 17.660 ; 17.660 ; 17.660 ; 17.660 ;
; FC[0]        ; RAM_DQM0L     ; 16.856 ; 16.856 ; 16.856 ; 16.856 ;
; FC[0]        ; RAM_DQM1H     ; 15.908 ; 15.908 ; 15.908 ; 15.908 ;
; FC[0]        ; RAM_DQM1L     ; 16.809 ; 16.809 ; 16.809 ; 16.809 ;
; FC[0]        ; RAM_RAS0n     ; 17.375 ; 17.375 ; 17.375 ; 17.375 ;
; FC[0]        ; RAM_RAS1n     ; 16.734 ; 16.734 ; 16.734 ; 16.734 ;
; FC[0]        ; ROM0n         ; 17.417 ; 17.417 ; 17.417 ; 17.417 ;
; FC[0]        ; ROM1n         ; 17.036 ; 17.036 ; 17.036 ; 17.036 ;
; FC[0]        ; ROM2n         ; 15.134 ; 15.134 ; 15.134 ; 15.134 ;
; FC[0]        ; ROM3n         ; 17.322 ; 17.322 ; 17.322 ; 17.322 ;
; FC[0]        ; ROM4n         ; 18.617 ; 18.617 ; 18.617 ; 18.617 ;
; FC[0]        ; ROM5n         ; 14.107 ; 14.107 ; 14.107 ; 14.107 ;
; FC[0]        ; ROM6n         ; 17.530 ; 17.530 ; 17.530 ; 17.530 ;
; FC[1]        ; ACSI_RDn      ; 19.683 ; 19.683 ; 19.683 ; 19.683 ;
; FC[1]        ; ACSI_WRn      ; 19.952 ; 19.952 ; 19.952 ; 19.952 ;
; FC[1]        ; BUTTONn       ; 18.231 ; 18.231 ; 18.231 ; 18.231 ;
; FC[1]        ; CA1_OUT       ; 19.939 ; 19.939 ; 19.939 ; 19.939 ;
; FC[1]        ; CD[0]         ; 22.083 ; 22.083 ; 22.083 ; 22.083 ;
; FC[1]        ; CD[1]         ; 22.320 ; 22.320 ; 22.320 ; 22.320 ;
; FC[1]        ; CD[2]         ; 20.437 ; 20.437 ; 20.437 ; 20.437 ;
; FC[1]        ; CD[3]         ; 22.750 ; 22.750 ; 22.750 ; 22.750 ;
; FC[1]        ; CD[4]         ; 21.608 ; 21.608 ; 21.608 ; 21.608 ;
; FC[1]        ; CD[5]         ; 20.437 ; 20.437 ; 20.437 ; 20.437 ;
; FC[1]        ; CD[6]         ; 20.837 ; 20.837 ; 20.837 ; 20.837 ;
; FC[1]        ; CD[7]         ; 22.054 ; 22.054 ; 22.054 ; 22.054 ;
; FC[1]        ; DATA[0]       ; 19.816 ; 19.816 ; 19.816 ; 19.816 ;
; FC[1]        ; DATA[1]       ; 19.319 ; 19.319 ; 19.319 ; 19.319 ;
; FC[1]        ; DATA[2]       ; 19.086 ; 19.086 ; 19.086 ; 19.086 ;
; FC[1]        ; DATA[3]       ; 19.812 ; 19.812 ; 19.812 ; 19.812 ;
; FC[1]        ; DATA[4]       ; 19.589 ; 19.589 ; 19.589 ; 19.589 ;
; FC[1]        ; DATA[5]       ; 22.636 ; 22.636 ; 22.636 ; 22.636 ;
; FC[1]        ; DATA[6]       ; 17.840 ; 17.840 ; 17.840 ; 17.840 ;
; FC[1]        ; DATA[7]       ; 18.546 ; 18.546 ; 18.546 ; 18.546 ;
; FC[1]        ; DATA[8]       ; 20.384 ; 20.384 ; 20.384 ; 20.384 ;
; FC[1]        ; DATA[9]       ; 18.542 ; 18.542 ; 18.542 ; 18.542 ;
; FC[1]        ; DATA[10]      ; 17.789 ; 17.789 ; 17.789 ; 17.789 ;
; FC[1]        ; DATA[11]      ; 18.973 ; 18.973 ; 18.973 ; 18.973 ;
; FC[1]        ; DATA[12]      ; 17.369 ; 17.369 ; 17.369 ; 17.369 ;
; FC[1]        ; DATA[13]      ; 19.357 ; 19.357 ; 19.357 ; 19.357 ;
; FC[1]        ; DATA[14]      ; 18.656 ; 18.656 ; 18.656 ; 18.656 ;
; FC[1]        ; DATA[15]      ; 18.687 ; 18.687 ; 18.687 ; 18.687 ;
; FC[1]        ; DTACKn        ; 15.348 ; 15.348 ; 15.348 ; 15.348 ;
; FC[1]        ; FLASH_CEn     ; 18.103 ; 18.103 ; 18.103 ; 18.103 ;
; FC[1]        ; FLASH_OEn     ; 18.033 ; 18.033 ; 18.033 ; 18.033 ;
; FC[1]        ; JOY_RHn       ; 20.693 ; 20.693 ; 20.693 ; 20.693 ;
; FC[1]        ; JOY_RLn       ; 23.284 ; 23.284 ; 23.284 ; 23.284 ;
; FC[1]        ; JOY_WEn       ; 22.918 ; 22.918 ; 22.918 ; 22.918 ;
; FC[1]        ; JOY_WL        ; 17.497 ; 17.497 ; 17.497 ; 17.497 ;
; FC[1]        ; RAM_ADR[8]    ; 17.601 ; 17.601 ; 17.601 ; 17.601 ;
; FC[1]        ; RAM_BA[0]     ; 15.958 ; 15.958 ; 15.958 ; 15.958 ;
; FC[1]        ; RAM_BA[1]     ; 13.936 ; 13.936 ; 13.936 ; 13.936 ;
; FC[1]        ; RAM_CAS0n     ; 16.120 ; 16.120 ; 16.120 ; 16.120 ;
; FC[1]        ; RAM_CAS1n     ; 16.116 ; 16.116 ; 16.116 ; 16.116 ;
; FC[1]        ; RAM_DATA[0]   ; 21.464 ; 21.464 ; 21.464 ; 21.464 ;
; FC[1]        ; RAM_DATA[1]   ; 19.851 ; 19.851 ; 19.851 ; 19.851 ;
; FC[1]        ; RAM_DATA[2]   ; 19.374 ; 19.374 ; 19.374 ; 19.374 ;
; FC[1]        ; RAM_DATA[3]   ; 19.763 ; 19.763 ; 19.763 ; 19.763 ;
; FC[1]        ; RAM_DATA[4]   ; 18.791 ; 18.791 ; 18.791 ; 18.791 ;
; FC[1]        ; RAM_DATA[5]   ; 25.147 ; 25.147 ; 25.147 ; 25.147 ;
; FC[1]        ; RAM_DATA[6]   ; 20.326 ; 20.326 ; 20.326 ; 20.326 ;
; FC[1]        ; RAM_DATA[7]   ; 20.967 ; 20.967 ; 20.967 ; 20.967 ;
; FC[1]        ; RAM_DATA[8]   ; 22.241 ; 22.241 ; 22.241 ; 22.241 ;
; FC[1]        ; RAM_DATA[9]   ; 18.694 ; 18.694 ; 18.694 ; 18.694 ;
; FC[1]        ; RAM_DATA[10]  ; 18.057 ; 18.057 ; 18.057 ; 18.057 ;
; FC[1]        ; RAM_DATA[11]  ; 20.134 ; 20.134 ; 20.134 ; 20.134 ;
; FC[1]        ; RAM_DATA[12]  ; 18.495 ; 18.495 ; 18.495 ; 18.495 ;
; FC[1]        ; RAM_DATA[13]  ; 19.593 ; 19.593 ; 19.593 ; 19.593 ;
; FC[1]        ; RAM_DATA[14]  ; 21.022 ; 21.022 ; 21.022 ; 21.022 ;
; FC[1]        ; RAM_DATA[15]  ; 19.009 ; 19.009 ; 19.009 ; 19.009 ;
; FC[1]        ; RAM_DQM0H     ; 17.306 ; 17.306 ; 17.306 ; 17.306 ;
; FC[1]        ; RAM_DQM0L     ; 16.502 ; 16.502 ; 16.502 ; 16.502 ;
; FC[1]        ; RAM_DQM1H     ; 15.554 ; 15.554 ; 15.554 ; 15.554 ;
; FC[1]        ; RAM_DQM1L     ; 16.455 ; 16.455 ; 16.455 ; 16.455 ;
; FC[1]        ; RAM_RAS0n     ; 17.021 ; 17.021 ; 17.021 ; 17.021 ;
; FC[1]        ; RAM_RAS1n     ; 16.380 ; 16.380 ; 16.380 ; 16.380 ;
; FC[1]        ; ROM0n         ; 17.050 ; 17.050 ; 17.050 ; 17.050 ;
; FC[1]        ; ROM1n         ; 16.669 ; 16.669 ; 16.669 ; 16.669 ;
; FC[1]        ; ROM2n         ; 14.767 ; 14.767 ; 14.767 ; 14.767 ;
; FC[1]        ; ROM3n         ; 16.955 ; 16.955 ; 16.955 ; 16.955 ;
; FC[1]        ; ROM4n         ; 18.250 ; 18.250 ; 18.250 ; 18.250 ;
; FC[1]        ; ROM5n         ; 13.740 ; 13.740 ; 13.740 ; 13.740 ;
; FC[1]        ; ROM6n         ; 17.163 ; 17.163 ; 17.163 ; 17.163 ;
; FC[2]        ; ACSI_RDn      ; 19.602 ; 19.602 ; 19.602 ; 19.602 ;
; FC[2]        ; ACSI_WRn      ; 19.871 ; 19.871 ; 19.871 ; 19.871 ;
; FC[2]        ; CA1_OUT       ;        ; 19.858 ; 19.858 ;        ;
; FC[2]        ; CD[0]         ; 22.002 ; 22.817 ; 22.817 ; 22.002 ;
; FC[2]        ; CD[1]         ; 22.239 ; 23.000 ; 23.000 ; 22.239 ;
; FC[2]        ; CD[2]         ; 20.356 ; 21.167 ; 21.167 ; 20.356 ;
; FC[2]        ; CD[3]         ; 22.669 ; 23.000 ; 23.000 ; 22.669 ;
; FC[2]        ; CD[4]         ; 21.527 ; 21.527 ; 21.527 ; 21.527 ;
; FC[2]        ; CD[5]         ; 20.356 ; 20.356 ; 20.356 ; 20.356 ;
; FC[2]        ; CD[6]         ; 20.756 ; 20.756 ; 20.756 ; 20.756 ;
; FC[2]        ; CD[7]         ; 21.973 ; 21.973 ; 21.973 ; 21.973 ;
; FC[2]        ; DATA[0]       ; 21.937 ; 21.937 ; 21.937 ; 21.937 ;
; FC[2]        ; DATA[1]       ; 22.109 ; 22.109 ; 22.109 ; 22.109 ;
; FC[2]        ; DATA[2]       ; 24.527 ; 22.682 ; 22.682 ; 24.527 ;
; FC[2]        ; DATA[3]       ; 25.746 ; 23.408 ; 23.408 ; 25.746 ;
; FC[2]        ; DATA[4]       ; 25.345 ; 23.185 ; 23.185 ; 25.345 ;
; FC[2]        ; DATA[5]       ; 24.922 ; 23.570 ; 23.570 ; 24.922 ;
; FC[2]        ; DATA[6]       ; 22.772 ; 21.011 ; 21.011 ; 22.772 ;
; FC[2]        ; DATA[7]       ; 23.815 ; 22.142 ; 22.142 ; 23.815 ;
; FC[2]        ; DATA[8]       ; 26.226 ; 23.498 ; 23.498 ; 26.226 ;
; FC[2]        ; DATA[9]       ; 25.357 ; 22.138 ; 22.138 ; 25.357 ;
; FC[2]        ; DATA[10]      ; 23.960 ; 21.385 ; 21.385 ; 23.960 ;
; FC[2]        ; DATA[11]      ; 24.748 ; 22.202 ; 22.202 ; 24.748 ;
; FC[2]        ; DATA[12]      ; 24.339 ; 20.965 ; 20.965 ; 24.339 ;
; FC[2]        ; DATA[13]      ; 25.159 ; 22.953 ; 22.953 ; 25.159 ;
; FC[2]        ; DATA[14]      ; 21.435 ; 21.435 ; 21.435 ; 21.435 ;
; FC[2]        ; DATA[15]      ; 22.149 ; 22.149 ; 22.149 ; 22.149 ;
; FC[2]        ; DTACKn        ; 17.137 ; 17.137 ; 17.137 ; 17.137 ;
; FC[2]        ; JOY_RHn       ;        ; 20.612 ; 20.612 ;        ;
; FC[2]        ; JOY_RLn       ;        ; 23.203 ; 23.203 ;        ;
; FC[2]        ; JOY_WEn       ; 22.837 ;        ;        ; 22.837 ;
; FC[2]        ; JOY_WL        ; 17.416 ;        ;        ; 17.416 ;
; FC[2]        ; RAM_DATA[0]   ; 23.585 ; 23.585 ; 23.585 ; 23.585 ;
; FC[2]        ; RAM_DATA[1]   ; 22.641 ; 22.641 ; 22.641 ; 22.641 ;
; FC[2]        ; RAM_DATA[2]   ; 24.815 ; 22.970 ; 22.970 ; 24.815 ;
; FC[2]        ; RAM_DATA[3]   ; 25.697 ; 23.359 ; 23.359 ; 25.697 ;
; FC[2]        ; RAM_DATA[4]   ; 24.547 ; 22.387 ; 22.387 ; 24.547 ;
; FC[2]        ; RAM_DATA[5]   ; 27.433 ; 26.081 ; 26.081 ; 27.433 ;
; FC[2]        ; RAM_DATA[6]   ; 25.258 ; 23.497 ; 23.497 ; 25.258 ;
; FC[2]        ; RAM_DATA[7]   ; 26.236 ; 24.563 ; 24.563 ; 26.236 ;
; FC[2]        ; RAM_DATA[8]   ; 28.083 ; 25.355 ; 25.355 ; 28.083 ;
; FC[2]        ; RAM_DATA[9]   ; 25.509 ; 22.290 ; 22.290 ; 25.509 ;
; FC[2]        ; RAM_DATA[10]  ; 24.228 ; 21.653 ; 21.653 ; 24.228 ;
; FC[2]        ; RAM_DATA[11]  ; 25.909 ; 23.363 ; 23.363 ; 25.909 ;
; FC[2]        ; RAM_DATA[12]  ; 25.465 ; 22.091 ; 22.091 ; 25.465 ;
; FC[2]        ; RAM_DATA[13]  ; 25.395 ; 23.189 ; 23.189 ; 25.395 ;
; FC[2]        ; RAM_DATA[14]  ; 23.801 ; 23.801 ; 23.801 ; 23.801 ;
; FC[2]        ; RAM_DATA[15]  ; 22.471 ; 22.471 ; 22.471 ; 22.471 ;
; HDINTn       ; DATA[5]       ; 27.248 ;        ;        ; 27.248 ;
; HDINTn       ; RAM_DATA[5]   ; 29.759 ;        ;        ; 29.759 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 27.168 ; 27.168 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 29.679 ; 29.679 ;        ;
; IDE_IORDY    ; DTACKn        ; 17.327 ; 17.327 ; 17.327 ; 17.327 ;
; LDSn         ; ACSI_RDn      ; 17.918 ; 17.918 ; 17.918 ; 17.918 ;
; LDSn         ; ACSI_WRn      ; 18.187 ; 18.187 ; 18.187 ; 18.187 ;
; LDSn         ; BUTTONn       ; 21.706 ;        ;        ; 21.706 ;
; LDSn         ; CA1_OUT       ; 18.174 ;        ;        ; 18.174 ;
; LDSn         ; CD[0]         ; 21.133 ; 20.318 ; 20.318 ; 21.133 ;
; LDSn         ; CD[1]         ; 21.316 ; 20.555 ; 20.555 ; 21.316 ;
; LDSn         ; CD[2]         ; 19.483 ; 18.672 ; 18.672 ; 19.483 ;
; LDSn         ; CD[3]         ; 21.316 ; 20.985 ; 20.985 ; 21.316 ;
; LDSn         ; CD[4]         ; 19.843 ; 19.843 ; 19.843 ; 19.843 ;
; LDSn         ; CD[5]         ; 18.672 ; 18.672 ; 18.672 ; 18.672 ;
; LDSn         ; CD[6]         ; 19.072 ; 19.072 ; 19.072 ; 19.072 ;
; LDSn         ; CD[7]         ; 20.289 ; 20.289 ; 20.289 ; 20.289 ;
; LDSn         ; DATA[0]       ; 19.992 ; 19.992 ; 19.992 ; 19.992 ;
; LDSn         ; DATA[1]       ; 19.992 ; 19.992 ; 19.992 ; 19.992 ;
; LDSn         ; DATA[2]       ; 19.977 ; 19.977 ; 19.977 ; 19.977 ;
; LDSn         ; DATA[3]       ; 19.977 ; 19.977 ; 19.977 ; 19.977 ;
; LDSn         ; DATA[4]       ; 19.962 ; 19.962 ; 19.962 ; 19.962 ;
; LDSn         ; DATA[5]       ; 19.962 ; 19.962 ; 19.962 ; 19.962 ;
; LDSn         ; DATA[6]       ; 19.920 ; 19.920 ; 19.920 ; 19.920 ;
; LDSn         ; DATA[7]       ; 19.910 ; 19.910 ; 19.910 ; 19.910 ;
; LDSn         ; DATA[8]       ; 19.977 ; 19.977 ; 19.977 ; 19.977 ;
; LDSn         ; DATA[9]       ; 19.977 ; 19.977 ; 19.977 ; 19.977 ;
; LDSn         ; DATA[10]      ; 20.339 ; 20.339 ; 20.339 ; 20.339 ;
; LDSn         ; DATA[11]      ; 20.339 ; 19.994 ; 19.994 ; 20.339 ;
; LDSn         ; DATA[12]      ; 20.307 ; 20.307 ; 20.307 ; 20.307 ;
; LDSn         ; DATA[13]      ; 20.307 ; 20.307 ; 20.307 ; 20.307 ;
; LDSn         ; DATA[14]      ; 20.685 ; 20.685 ; 20.685 ; 20.685 ;
; LDSn         ; DATA[15]      ; 20.675 ; 20.675 ; 20.675 ; 20.675 ;
; LDSn         ; DTACKn        ; 15.652 ; 15.652 ; 15.652 ; 15.652 ;
; LDSn         ; IDE_IORDn     ; 13.198 ;        ;        ; 13.198 ;
; LDSn         ; IDE_IOWRn     ; 14.606 ;        ;        ; 14.606 ;
; LDSn         ; JOY_RLn       ; 17.474 ;        ;        ; 17.474 ;
; LDSn         ; JOY_WEn       ;        ; 17.108 ; 17.108 ;        ;
; LDSn         ; JOY_WL        ;        ; 14.997 ; 14.997 ;        ;
; LDSn         ; RAM_CAS0n     ; 14.682 ;        ;        ; 14.682 ;
; LDSn         ; RAM_CAS1n     ; 14.667 ;        ;        ; 14.667 ;
; LDSn         ; RAM_DATA[0]   ; 23.224 ; 23.519 ; 23.519 ; 23.224 ;
; LDSn         ; RAM_DATA[1]   ; 22.132 ; 22.965 ; 22.965 ; 22.132 ;
; LDSn         ; RAM_DATA[2]   ; 22.699 ; 22.954 ; 22.954 ; 22.699 ;
; LDSn         ; RAM_DATA[3]   ; 23.158 ; 23.300 ; 23.300 ; 23.158 ;
; LDSn         ; RAM_DATA[4]   ; 22.298 ; 22.298 ; 22.298 ; 22.298 ;
; LDSn         ; RAM_DATA[5]   ; 25.459 ; 25.459 ; 25.459 ; 25.459 ;
; LDSn         ; RAM_DATA[6]   ; 23.284 ; 23.284 ; 23.284 ; 23.284 ;
; LDSn         ; RAM_DATA[7]   ; 24.281 ; 24.281 ; 24.281 ; 24.281 ;
; LDSn         ; RAM_DATA[8]   ; 24.533 ; 24.911 ; 24.911 ; 24.533 ;
; LDSn         ; RAM_DATA[9]   ; 22.876 ; 22.629 ; 22.629 ; 22.876 ;
; LDSn         ; RAM_DATA[10]  ; 21.377 ; 21.377 ; 21.377 ; 21.377 ;
; LDSn         ; RAM_DATA[11]  ; 22.689 ; 21.155 ; 21.155 ; 22.689 ;
; LDSn         ; RAM_DATA[12]  ; 22.189 ; 22.228 ; 22.228 ; 22.189 ;
; LDSn         ; RAM_DATA[13]  ; 23.414 ; 23.414 ; 23.414 ; 23.414 ;
; LDSn         ; RAM_DATA[14]  ; 23.359 ; 23.359 ; 23.359 ; 23.359 ;
; LDSn         ; RAM_DATA[15]  ; 22.298 ; 22.298 ; 22.298 ; 22.298 ;
; LDSn         ; RAM_DQM0L     ; 15.935 ;        ;        ; 15.935 ;
; LDSn         ; RAM_DQM1L     ; 15.885 ;        ;        ; 15.885 ;
; LPT_BSY      ; DATA[0]       ; 23.364 ;        ;        ; 23.364 ;
; LPT_BSY      ; RAM_DATA[0]   ; 25.012 ;        ;        ; 25.012 ;
; LPT_D[0]     ; DATA[8]       ; 23.497 ;        ;        ; 23.497 ;
; LPT_D[0]     ; RAM_DATA[8]   ; 25.354 ;        ;        ; 25.354 ;
; LPT_D[1]     ; DATA[9]       ; 22.649 ;        ;        ; 22.649 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 22.801 ;        ;        ; 22.801 ;
; LPT_D[2]     ; DATA[10]      ; 19.772 ;        ;        ; 19.772 ;
; LPT_D[2]     ; RAM_DATA[10]  ; 20.040 ;        ;        ; 20.040 ;
; LPT_D[3]     ; DATA[11]      ; 20.694 ;        ;        ; 20.694 ;
; LPT_D[3]     ; RAM_DATA[11]  ; 21.855 ;        ;        ; 21.855 ;
; LPT_D[4]     ; DATA[12]      ; 20.963 ;        ;        ; 20.963 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 22.089 ;        ;        ; 22.089 ;
; LPT_D[5]     ; DATA[13]      ; 22.544 ;        ;        ; 22.544 ;
; LPT_D[5]     ; RAM_DATA[13]  ; 22.780 ;        ;        ; 22.780 ;
; LPT_D[6]     ; DATA[14]      ; 21.673 ; 21.673 ; 21.673 ; 21.673 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 24.039 ; 24.039 ; 24.039 ; 24.039 ;
; LPT_D[7]     ; DATA[15]      ; 22.835 ; 22.835 ; 22.835 ; 22.835 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 23.157 ; 23.157 ; 23.157 ; 23.157 ;
; MIDI_IN      ; MIDI_TLR      ; 8.871  ;        ;        ; 8.871  ;
; RAM_DATA[0]  ; DATA[0]       ; 23.719 ;        ;        ; 23.719 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 25.367 ;        ;        ; 25.367 ;
; RAM_DATA[1]  ; DATA[1]       ; 23.635 ;        ;        ; 23.635 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 24.167 ;        ;        ; 24.167 ;
; RAM_DATA[2]  ; DATA[2]       ; 23.119 ;        ;        ; 23.119 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 23.407 ;        ;        ; 23.407 ;
; RAM_DATA[3]  ; DATA[3]       ; 24.926 ;        ;        ; 24.926 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 24.877 ;        ;        ; 24.877 ;
; RAM_DATA[4]  ; DATA[4]       ; 22.902 ;        ;        ; 22.902 ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 22.104 ;        ;        ; 22.104 ;
; RAM_DATA[5]  ; DATA[5]       ; 23.543 ;        ;        ; 23.543 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 26.054 ;        ;        ; 26.054 ;
; RAM_DATA[6]  ; DATA[6]       ; 21.134 ;        ;        ; 21.134 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 23.620 ;        ;        ; 23.620 ;
; RAM_DATA[7]  ; DATA[7]       ; 22.668 ;        ;        ; 22.668 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 25.089 ;        ;        ; 25.089 ;
; RAM_DATA[8]  ; DATA[8]       ; 24.818 ;        ;        ; 24.818 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 26.675 ;        ;        ; 26.675 ;
; RAM_DATA[9]  ; DATA[9]       ; 22.708 ;        ;        ; 22.708 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 22.860 ;        ;        ; 22.860 ;
; RAM_DATA[10] ; DATA[10]      ; 21.561 ;        ;        ; 21.561 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 21.829 ;        ;        ; 21.829 ;
; RAM_DATA[11] ; DATA[11]      ; 22.449 ;        ;        ; 22.449 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 23.610 ;        ;        ; 23.610 ;
; RAM_DATA[12] ; DATA[12]      ; 21.152 ;        ;        ; 21.152 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 22.278 ;        ;        ; 22.278 ;
; RAM_DATA[13] ; DATA[13]      ; 24.107 ;        ;        ; 24.107 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 24.343 ;        ;        ; 24.343 ;
; RAM_DATA[14] ; DATA[14]      ; 22.936 ; 22.936 ; 22.936 ; 22.936 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 25.302 ; 25.302 ; 25.302 ; 25.302 ;
; RAM_DATA[15] ; DATA[15]      ; 22.188 ; 22.188 ; 22.188 ; 22.188 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 22.510 ; 22.510 ; 22.510 ; 22.510 ;
; RWn          ; ACSI_RDn      ; 20.027 ; 13.468 ; 13.468 ; 20.027 ;
; RWn          ; ACSI_WRn      ; 13.734 ; 20.296 ; 20.296 ; 13.734 ;
; RWn          ; BUTTONn       ;        ; 21.438 ; 21.438 ;        ;
; RWn          ; CA1_OUT       ;        ; 20.283 ; 20.283 ;        ;
; RWn          ; CD[0]         ; 16.682 ; 15.867 ; 15.867 ; 16.682 ;
; RWn          ; CD[1]         ; 16.865 ; 16.104 ; 16.104 ; 16.865 ;
; RWn          ; CD[2]         ; 15.032 ; 14.221 ; 14.221 ; 15.032 ;
; RWn          ; CD[3]         ; 16.865 ; 16.534 ; 16.534 ; 16.865 ;
; RWn          ; CD[4]         ; 15.392 ; 15.392 ; 15.392 ; 15.392 ;
; RWn          ; CD[5]         ; 14.221 ; 14.221 ; 14.221 ; 14.221 ;
; RWn          ; CD[6]         ; 14.621 ; 14.621 ; 14.621 ; 14.621 ;
; RWn          ; CD[7]         ; 15.838 ; 15.838 ; 15.838 ; 15.838 ;
; RWn          ; DATA[0]       ; 19.048 ; 18.860 ; 18.860 ; 19.048 ;
; RWn          ; DATA[1]       ; 19.642 ; 19.717 ; 19.717 ; 19.642 ;
; RWn          ; DATA[2]       ; 19.287 ; 17.849 ; 17.849 ; 19.287 ;
; RWn          ; DATA[3]       ; 19.702 ; 19.702 ; 19.702 ; 19.702 ;
; RWn          ; DATA[4]       ; 19.687 ; 19.664 ; 19.664 ; 19.687 ;
; RWn          ; DATA[5]       ; 19.008 ; 19.008 ; 19.008 ; 19.008 ;
; RWn          ; DATA[6]       ; 16.992 ; 16.992 ; 16.992 ; 16.992 ;
; RWn          ; DATA[7]       ; 17.909 ; 17.909 ; 17.909 ; 17.909 ;
; RWn          ; DATA[8]       ; 19.702 ; 19.506 ; 19.506 ; 19.702 ;
; RWn          ; DATA[9]       ; 19.605 ; 18.291 ; 18.291 ; 19.605 ;
; RWn          ; DATA[10]      ; 18.471 ; 17.804 ; 17.804 ; 18.471 ;
; RWn          ; DATA[11]      ; 19.200 ; 18.962 ; 18.962 ; 19.200 ;
; RWn          ; DATA[12]      ; 18.832 ; 18.496 ; 18.496 ; 18.832 ;
; RWn          ; DATA[13]      ; 20.032 ; 19.058 ; 19.058 ; 20.032 ;
; RWn          ; DATA[14]      ; 16.912 ; 16.912 ; 16.912 ; 16.912 ;
; RWn          ; DATA[15]      ; 17.895 ; 17.895 ; 17.895 ; 17.895 ;
; RWn          ; DTACKn        ; 17.562 ; 17.562 ; 17.562 ; 17.562 ;
; RWn          ; FLASH_CEn     ;        ; 18.490 ; 18.490 ;        ;
; RWn          ; FLASH_OEn     ;        ; 18.420 ; 18.420 ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 13.832 ; 13.832 ;        ;
; RWn          ; IDE_D_EN_OUTn ; 13.848 ;        ;        ; 13.848 ;
; RWn          ; IDE_IORDn     ;        ; 13.909 ; 13.909 ;        ;
; RWn          ; IDE_IOWRn     ; 15.313 ;        ;        ; 15.313 ;
; RWn          ; JOY_RHn       ;        ; 15.527 ; 15.527 ;        ;
; RWn          ; JOY_RLn       ;        ; 18.118 ; 18.118 ;        ;
; RWn          ; JOY_WEn       ; 17.752 ;        ;        ; 17.752 ;
; RWn          ; JOY_WL        ; 17.841 ; 14.857 ; 14.857 ; 17.841 ;
; RWn          ; RAM_DATA[0]   ; 16.136 ; 16.136 ; 16.136 ; 16.136 ;
; RWn          ; RAM_DATA[1]   ; 15.624 ; 15.624 ; 15.624 ; 15.624 ;
; RWn          ; RAM_DATA[2]   ; 14.731 ; 14.731 ; 14.731 ; 14.731 ;
; RWn          ; RAM_DATA[3]   ; 15.006 ; 15.006 ; 15.006 ; 15.006 ;
; RWn          ; RAM_DATA[4]   ; 14.808 ; 14.808 ; 14.808 ; 14.808 ;
; RWn          ; RAM_DATA[5]   ; 16.419 ; 16.419 ; 16.419 ; 16.419 ;
; RWn          ; RAM_DATA[6]   ; 16.101 ; 16.101 ; 16.101 ; 16.101 ;
; RWn          ; RAM_DATA[7]   ; 16.419 ; 16.419 ; 16.419 ; 16.419 ;
; RWn          ; RAM_DATA[8]   ; 15.838 ; 15.838 ; 15.838 ; 15.838 ;
; RWn          ; RAM_DATA[9]   ; 14.913 ; 14.913 ; 14.913 ; 14.913 ;
; RWn          ; RAM_DATA[10]  ; 14.229 ; 14.229 ; 14.229 ; 14.229 ;
; RWn          ; RAM_DATA[11]  ; 14.540 ; 14.540 ; 14.540 ; 14.540 ;
; RWn          ; RAM_DATA[12]  ; 14.739 ; 14.739 ; 14.739 ; 14.739 ;
; RWn          ; RAM_DATA[13]  ; 14.399 ; 14.399 ; 14.399 ; 14.399 ;
; RWn          ; RAM_DATA[14]  ; 15.315 ; 15.315 ; 15.315 ; 15.315 ;
; RWn          ; RAM_DATA[15]  ; 14.144 ; 14.144 ; 14.144 ; 14.144 ;
; RWn          ; RAM_WEn       ; 13.866 ;        ;        ; 13.866 ;
; RWn          ; ROM0n         ;        ; 17.437 ; 17.437 ;        ;
; RWn          ; ROM1n         ;        ; 17.056 ; 17.056 ;        ;
; RWn          ; ROM2n         ;        ; 15.154 ; 15.154 ;        ;
; RWn          ; ROM3n         ;        ; 17.342 ; 17.342 ;        ;
; RWn          ; ROM4n         ;        ; 18.637 ; 18.637 ;        ;
; RWn          ; ROM5n         ;        ; 14.127 ; 14.127 ;        ;
; RWn          ; ROM6n         ;        ; 17.550 ; 17.550 ;        ;
; SCSI_ACKn    ; CD[0]         ; 17.133 ; 17.133 ; 17.133 ; 17.133 ;
; SCSI_ATNn    ; CD[1]         ; 17.985 ; 17.985 ; 17.985 ; 17.985 ;
; SCSI_BSYn    ; CD[6]         ; 21.530 ; 21.530 ; 21.530 ; 21.530 ;
; SCSI_D[0]    ; CD[0]         ; 17.625 ; 17.625 ; 17.625 ; 17.625 ;
; SCSI_D[1]    ; CD[1]         ; 17.839 ; 17.839 ; 17.839 ; 17.839 ;
; SCSI_D[2]    ; CD[2]         ;        ; 18.295 ; 18.295 ;        ;
; SCSI_D[3]    ; CD[3]         ; 18.504 ; 18.504 ; 18.504 ; 18.504 ;
; SCSI_D[4]    ; CD[4]         ; 20.605 ; 20.605 ; 20.605 ; 20.605 ;
; SCSI_D[5]    ; CD[5]         ; 20.094 ; 20.094 ; 20.094 ; 20.094 ;
; SCSI_D[6]    ; CD[6]         ; 21.308 ; 21.308 ; 21.308 ; 21.308 ;
; SCSI_D[7]    ; CD[7]         ; 18.404 ; 18.404 ; 18.404 ; 18.404 ;
; SCSI_DCn     ; CD[3]         ; 17.878 ; 17.878 ; 17.878 ; 17.878 ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 18.920 ; 18.920 ; 18.920 ; 18.920 ;
; SCSI_DCn     ; SCSI_D[0]     ; 18.404 ; 18.404 ; 18.404 ; 18.404 ;
; SCSI_DCn     ; SCSI_D[1]     ; 18.404 ; 18.404 ; 18.404 ; 18.404 ;
; SCSI_DCn     ; SCSI_D[2]     ; 17.579 ; 17.579 ; 17.579 ; 17.579 ;
; SCSI_DCn     ; SCSI_D[3]     ; 17.579 ; 17.579 ; 17.579 ; 17.579 ;
; SCSI_DCn     ; SCSI_D[4]     ; 17.262 ; 17.262 ; 17.262 ; 17.262 ;
; SCSI_DCn     ; SCSI_D[5]     ; 17.262 ; 17.262 ; 17.262 ; 17.262 ;
; SCSI_DCn     ; SCSI_D[6]     ; 17.255 ; 17.255 ; 17.255 ; 17.255 ;
; SCSI_DCn     ; SCSI_D[7]     ; 17.255 ; 17.255 ; 17.255 ; 17.255 ;
; SCSI_DCn     ; SCSI_DP       ; 18.414 ; 18.414 ; 18.414 ; 18.414 ;
; SCSI_DP      ; CD[0]         ; 17.137 ; 17.137 ; 17.137 ; 17.137 ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 13.580 ; 13.580 ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 13.568 ;        ;        ; 13.568 ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 13.123 ; 13.123 ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 13.304 ;        ;        ; 13.304 ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 13.259 ; 13.259 ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 13.095 ;        ;        ; 13.095 ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 13.163 ; 13.163 ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 13.245 ;        ;        ; 13.245 ;
; SCSI_IDn[1]  ; SCSI_DP       ; 14.221 ; 14.221 ; 14.221 ; 14.221 ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 13.143 ; 13.143 ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 13.119 ; 13.119 ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 12.685 ;        ;        ; 12.685 ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 12.864 ;        ;        ; 12.864 ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 12.816 ; 12.816 ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 12.644 ; 12.644 ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 12.710 ;        ;        ; 12.710 ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 12.800 ;        ;        ; 12.800 ;
; SCSI_IDn[2]  ; SCSI_DP       ; 13.772 ; 13.772 ; 13.772 ; 13.772 ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 13.816 ; 13.816 ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 13.780 ; 13.780 ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 13.390 ; 13.390 ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 13.568 ; 13.568 ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 13.421 ;        ;        ; 13.421 ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 13.238 ;        ;        ; 13.238 ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 13.351 ;        ;        ; 13.351 ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 13.437 ;        ;        ; 13.437 ;
; SCSI_IDn[3]  ; SCSI_DP       ; 14.433 ; 14.433 ; 14.433 ; 14.433 ;
; SCSI_IOn     ; CD[2]         ;        ; 17.794 ; 17.794 ;        ;
; SCSI_IOn     ; CD[3]         ; 19.966 ; 19.966 ; 19.966 ; 19.966 ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 14.609 ; 17.550 ; 17.550 ; 14.609 ;
; SCSI_IOn     ; SCSI_D[0]     ; 14.093 ; 14.093 ; 14.093 ; 14.093 ;
; SCSI_IOn     ; SCSI_D[1]     ; 14.093 ; 14.093 ; 14.093 ; 14.093 ;
; SCSI_IOn     ; SCSI_D[2]     ; 13.268 ; 13.268 ; 13.268 ; 13.268 ;
; SCSI_IOn     ; SCSI_D[3]     ; 13.268 ; 13.268 ; 13.268 ; 13.268 ;
; SCSI_IOn     ; SCSI_D[4]     ; 12.951 ; 12.951 ; 12.951 ; 12.951 ;
; SCSI_IOn     ; SCSI_D[5]     ; 12.951 ; 12.951 ; 12.951 ; 12.951 ;
; SCSI_IOn     ; SCSI_D[6]     ; 12.944 ; 12.944 ; 12.944 ; 12.944 ;
; SCSI_IOn     ; SCSI_D[7]     ; 12.944 ; 12.944 ; 12.944 ; 12.944 ;
; SCSI_IOn     ; SCSI_DP       ; 14.103 ; 14.103 ; 14.103 ; 14.103 ;
; SCSI_IOn     ; SCSI_RDn      ; 12.732 ;        ;        ; 12.732 ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 13.954 ; 13.954 ;        ;
; SCSI_MSGn    ; CD[3]         ; 20.130 ; 20.130 ; 20.130 ; 20.130 ;
; SCSI_MSGn    ; CD[4]         ; 21.135 ; 21.135 ; 21.135 ; 21.135 ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 17.714 ; 17.714 ; 17.714 ; 17.714 ;
; SCSI_MSGn    ; SCSI_D[0]     ; 17.198 ; 17.198 ; 17.198 ; 17.198 ;
; SCSI_MSGn    ; SCSI_D[1]     ; 17.198 ; 17.198 ; 17.198 ; 17.198 ;
; SCSI_MSGn    ; SCSI_D[2]     ; 16.373 ; 16.373 ; 16.373 ; 16.373 ;
; SCSI_MSGn    ; SCSI_D[3]     ; 16.373 ; 16.373 ; 16.373 ; 16.373 ;
; SCSI_MSGn    ; SCSI_D[4]     ; 16.056 ; 16.056 ; 16.056 ; 16.056 ;
; SCSI_MSGn    ; SCSI_D[5]     ; 16.056 ; 16.056 ; 16.056 ; 16.056 ;
; SCSI_MSGn    ; SCSI_D[6]     ; 16.049 ; 16.049 ; 16.049 ; 16.049 ;
; SCSI_MSGn    ; SCSI_D[7]     ; 16.049 ; 16.049 ; 16.049 ; 16.049 ;
; SCSI_MSGn    ; SCSI_DP       ; 17.208 ; 17.208 ; 17.208 ; 17.208 ;
; SCSI_REQn    ; CD[3]         ; 20.296 ; 20.296 ; 20.296 ; 20.296 ;
; SCSI_REQn    ; CD[5]         ; 20.609 ; 20.609 ; 20.609 ; 20.609 ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 17.880 ;        ;        ; 17.880 ;
; SCSI_REQn    ; SCSI_D[0]     ; 17.364 ; 17.364 ; 17.364 ; 17.364 ;
; SCSI_REQn    ; SCSI_D[1]     ; 17.364 ; 17.364 ; 17.364 ; 17.364 ;
; SCSI_REQn    ; SCSI_D[2]     ; 16.539 ; 16.539 ; 16.539 ; 16.539 ;
; SCSI_REQn    ; SCSI_D[3]     ; 16.539 ; 16.539 ; 16.539 ; 16.539 ;
; SCSI_REQn    ; SCSI_D[4]     ; 16.222 ; 16.222 ; 16.222 ; 16.222 ;
; SCSI_REQn    ; SCSI_D[5]     ; 16.222 ; 16.222 ; 16.222 ; 16.222 ;
; SCSI_REQn    ; SCSI_D[6]     ; 16.215 ; 16.215 ; 16.215 ; 16.215 ;
; SCSI_REQn    ; SCSI_D[7]     ; 16.215 ; 16.215 ; 16.215 ; 16.215 ;
; SCSI_REQn    ; SCSI_DP       ; 17.374 ; 17.374 ; 17.374 ; 17.374 ;
; SCSI_RSTn    ; CD[7]         ;        ; 19.202 ; 19.202 ;        ;
; SCSI_SELn    ; CD[1]         ; 16.732 ; 16.732 ; 16.732 ; 16.732 ;
; SD_AVR_ENn   ; RESETn        ;        ; 16.240 ; 16.240 ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 14.339 ; 14.339 ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 11.944 ; 11.944 ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 14.344 ;        ;        ; 14.344 ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 13.070 ;        ;        ; 13.070 ;
; SD_RESETn    ; ACSI_RDn      ; 21.818 ; 21.818 ; 21.818 ; 21.818 ;
; SD_RESETn    ; ACSI_WRn      ; 22.087 ; 22.087 ; 22.087 ; 22.087 ;
; SD_RESETn    ; CA1_OUT       ; 22.074 ;        ;        ; 22.074 ;
; SD_RESETn    ; CD[0]         ; 25.033 ; 24.218 ; 24.218 ; 25.033 ;
; SD_RESETn    ; CD[1]         ; 25.216 ; 24.455 ; 24.455 ; 25.216 ;
; SD_RESETn    ; CD[2]         ; 23.383 ; 22.572 ; 22.572 ; 23.383 ;
; SD_RESETn    ; CD[3]         ; 25.216 ; 24.885 ; 24.885 ; 25.216 ;
; SD_RESETn    ; CD[4]         ; 23.743 ; 23.743 ; 23.743 ; 23.743 ;
; SD_RESETn    ; CD[5]         ; 22.572 ; 22.572 ; 22.572 ; 22.572 ;
; SD_RESETn    ; CD[6]         ; 22.972 ; 22.972 ; 22.972 ; 22.972 ;
; SD_RESETn    ; CD[7]         ; 24.189 ; 24.189 ; 24.189 ; 24.189 ;
; SD_RESETn    ; COM_TxD       ; 17.159 ; 17.159 ; 17.159 ; 17.159 ;
; SD_RESETn    ; DATA[0]       ; 25.142 ; 25.142 ; 25.142 ; 25.142 ;
; SD_RESETn    ; DATA[1]       ; 26.051 ; 26.384 ; 26.384 ; 26.051 ;
; SD_RESETn    ; DATA[2]       ; 24.591 ; 25.816 ; 25.816 ; 24.591 ;
; SD_RESETn    ; DATA[3]       ; 26.845 ; 26.845 ; 26.845 ; 26.845 ;
; SD_RESETn    ; DATA[4]       ; 26.444 ; 26.444 ; 26.444 ; 26.444 ;
; SD_RESETn    ; DATA[5]       ; 25.750 ; 25.750 ; 25.750 ; 25.750 ;
; SD_RESETn    ; DATA[6]       ; 23.734 ; 23.734 ; 23.734 ; 23.734 ;
; SD_RESETn    ; DATA[7]       ; 24.651 ; 24.651 ; 24.651 ; 24.651 ;
; SD_RESETn    ; DATA[8]       ; 26.925 ; 28.090 ; 28.090 ; 26.925 ;
; SD_RESETn    ; DATA[9]       ; 25.833 ; 26.801 ; 26.801 ; 25.833 ;
; SD_RESETn    ; DATA[10]      ; 24.546 ; 25.249 ; 25.249 ; 24.546 ;
; SD_RESETn    ; DATA[11]      ; 25.704 ; 26.037 ; 26.037 ; 25.704 ;
; SD_RESETn    ; DATA[12]      ; 25.440 ; 25.949 ; 25.949 ; 25.440 ;
; SD_RESETn    ; DATA[13]      ; 25.800 ; 26.590 ; 26.590 ; 25.800 ;
; SD_RESETn    ; DATA[14]      ; 22.891 ; 22.891 ; 22.891 ; 22.891 ;
; SD_RESETn    ; DATA[15]      ; 23.874 ; 23.874 ; 23.874 ; 23.874 ;
; SD_RESETn    ; DTACKn        ; 17.550 ; 17.550 ; 17.550 ; 17.550 ;
; SD_RESETn    ; RAM_DATA[0]   ; 26.790 ; 26.790 ; 26.790 ; 26.790 ;
; SD_RESETn    ; RAM_DATA[1]   ; 26.583 ; 26.916 ; 26.916 ; 26.583 ;
; SD_RESETn    ; RAM_DATA[2]   ; 24.879 ; 26.104 ; 26.104 ; 24.879 ;
; SD_RESETn    ; RAM_DATA[3]   ; 26.796 ; 26.796 ; 26.796 ; 26.796 ;
; SD_RESETn    ; RAM_DATA[4]   ; 25.646 ; 25.646 ; 25.646 ; 25.646 ;
; SD_RESETn    ; RAM_DATA[5]   ; 28.261 ; 28.261 ; 28.261 ; 28.261 ;
; SD_RESETn    ; RAM_DATA[6]   ; 26.220 ; 26.220 ; 26.220 ; 26.220 ;
; SD_RESETn    ; RAM_DATA[7]   ; 27.072 ; 27.072 ; 27.072 ; 27.072 ;
; SD_RESETn    ; RAM_DATA[8]   ; 28.782 ; 29.947 ; 29.947 ; 28.782 ;
; SD_RESETn    ; RAM_DATA[9]   ; 25.985 ; 26.953 ; 26.953 ; 25.985 ;
; SD_RESETn    ; RAM_DATA[10]  ; 24.814 ; 25.517 ; 25.517 ; 24.814 ;
; SD_RESETn    ; RAM_DATA[11]  ; 26.865 ; 27.198 ; 27.198 ; 26.865 ;
; SD_RESETn    ; RAM_DATA[12]  ; 26.566 ; 27.075 ; 27.075 ; 26.566 ;
; SD_RESETn    ; RAM_DATA[13]  ; 26.036 ; 26.826 ; 26.826 ; 26.036 ;
; SD_RESETn    ; RAM_DATA[14]  ; 25.257 ; 25.257 ; 25.257 ; 25.257 ;
; SD_RESETn    ; RAM_DATA[15]  ; 24.196 ; 24.196 ; 24.196 ; 24.196 ;
; UDSn         ; ACSI_RDn      ; 17.556 ; 17.556 ; 17.556 ; 17.556 ;
; UDSn         ; ACSI_WRn      ; 17.825 ; 17.825 ; 17.825 ; 17.825 ;
; UDSn         ; CA1_OUT       ; 17.812 ;        ;        ; 17.812 ;
; UDSn         ; CD[0]         ; 20.771 ; 19.956 ; 19.956 ; 20.771 ;
; UDSn         ; CD[1]         ; 20.954 ; 20.193 ; 20.193 ; 20.954 ;
; UDSn         ; CD[2]         ; 19.121 ; 18.310 ; 18.310 ; 19.121 ;
; UDSn         ; CD[3]         ; 20.954 ; 20.623 ; 20.623 ; 20.954 ;
; UDSn         ; CD[4]         ; 19.481 ; 19.481 ; 19.481 ; 19.481 ;
; UDSn         ; CD[5]         ; 18.310 ; 18.310 ; 18.310 ; 18.310 ;
; UDSn         ; CD[6]         ; 18.710 ; 18.710 ; 18.710 ; 18.710 ;
; UDSn         ; CD[7]         ; 19.927 ; 19.927 ; 19.927 ; 19.927 ;
; UDSn         ; DATA[0]       ; 18.452 ; 18.452 ; 18.452 ; 18.452 ;
; UDSn         ; DATA[1]       ; 18.452 ; 18.452 ; 18.452 ; 18.452 ;
; UDSn         ; DATA[2]       ; 18.437 ; 18.437 ; 18.437 ; 18.437 ;
; UDSn         ; DATA[3]       ; 18.437 ; 18.437 ; 18.437 ; 18.437 ;
; UDSn         ; DATA[4]       ; 18.422 ; 18.422 ; 18.422 ; 18.422 ;
; UDSn         ; DATA[5]       ; 18.422 ; 18.422 ; 18.422 ; 18.422 ;
; UDSn         ; DATA[6]       ; 18.380 ; 18.380 ; 18.380 ; 18.380 ;
; UDSn         ; DATA[7]       ; 18.370 ; 18.370 ; 18.370 ; 18.370 ;
; UDSn         ; DATA[8]       ; 18.437 ; 18.437 ; 18.437 ; 18.437 ;
; UDSn         ; DATA[9]       ; 18.437 ; 18.437 ; 18.437 ; 18.437 ;
; UDSn         ; DATA[10]      ; 18.799 ; 18.799 ; 18.799 ; 18.799 ;
; UDSn         ; DATA[11]      ; 18.799 ; 18.454 ; 18.454 ; 18.799 ;
; UDSn         ; DATA[12]      ; 18.767 ; 18.767 ; 18.767 ; 18.767 ;
; UDSn         ; DATA[13]      ; 18.767 ; 18.767 ; 18.767 ; 18.767 ;
; UDSn         ; DATA[14]      ; 19.145 ; 19.145 ; 19.145 ; 19.145 ;
; UDSn         ; DATA[15]      ; 19.135 ; 19.135 ; 19.135 ; 19.135 ;
; UDSn         ; DTACKn        ; 15.290 ; 15.290 ; 15.290 ; 15.290 ;
; UDSn         ; JOY_RHn       ; 14.422 ;        ;        ; 14.422 ;
; UDSn         ; RAM_CAS0n     ; 14.288 ;        ;        ; 14.288 ;
; UDSn         ; RAM_CAS1n     ; 14.273 ;        ;        ; 14.273 ;
; UDSn         ; RAM_DATA[0]   ; 21.979 ; 21.979 ; 21.979 ; 21.979 ;
; UDSn         ; RAM_DATA[1]   ; 20.592 ; 21.425 ; 21.425 ; 20.592 ;
; UDSn         ; RAM_DATA[2]   ; 21.159 ; 21.414 ; 21.414 ; 21.159 ;
; UDSn         ; RAM_DATA[3]   ; 21.618 ; 21.760 ; 21.760 ; 21.618 ;
; UDSn         ; RAM_DATA[4]   ; 20.758 ; 20.758 ; 20.758 ; 20.758 ;
; UDSn         ; RAM_DATA[5]   ; 24.247 ; 24.257 ; 24.257 ; 24.247 ;
; UDSn         ; RAM_DATA[6]   ; 21.832 ; 22.364 ; 22.364 ; 21.832 ;
; UDSn         ; RAM_DATA[7]   ; 23.037 ; 23.291 ; 23.291 ; 23.037 ;
; UDSn         ; RAM_DATA[8]   ; 22.993 ; 23.371 ; 23.371 ; 22.993 ;
; UDSn         ; RAM_DATA[9]   ; 21.424 ; 21.089 ; 21.089 ; 21.424 ;
; UDSn         ; RAM_DATA[10]  ; 19.909 ; 19.909 ; 19.909 ; 19.909 ;
; UDSn         ; RAM_DATA[11]  ; 21.149 ; 19.615 ; 19.615 ; 21.149 ;
; UDSn         ; RAM_DATA[12]  ; 21.225 ; 21.246 ; 21.246 ; 21.225 ;
; UDSn         ; RAM_DATA[13]  ; 21.977 ; 21.977 ; 21.977 ; 21.977 ;
; UDSn         ; RAM_DATA[14]  ; 21.922 ; 21.922 ; 21.922 ; 21.922 ;
; UDSn         ; RAM_DATA[15]  ; 20.861 ; 20.861 ; 20.861 ; 20.861 ;
; UDSn         ; RAM_DQM0H     ; 15.397 ;        ;        ; 15.397 ;
; UDSn         ; RAM_DQM1H     ; 13.646 ;        ;        ; 13.646 ;
+--------------+---------------+--------+--------+--------+--------+


+-------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                     ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise   ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 25.581 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 25.735 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 25.725 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 25.731 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 25.725 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 25.581 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 25.581 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 25.732 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 25.732 ;      ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 14.830 ;      ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 19.622 ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 11.437 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 12.793 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 12.793 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 12.757 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 12.757 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 12.771 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 12.761 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 11.989 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 11.989 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 11.437 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 11.437 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 11.714 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 11.704 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 12.079 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 12.069 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 12.644 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 12.644 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 11.698 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 12.272 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 12.272 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 13.074 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 12.737 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 12.747 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 13.074 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 8.900  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 35.821 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 35.975 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 35.965 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 35.971 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 35.965 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 35.821 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 35.821 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 35.972 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 35.972 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 12.165 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 28.606 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 28.688 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 28.688 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 28.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 28.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 28.658 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 28.658 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 28.616 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 28.606 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 28.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 28.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 29.035 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 29.035 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 29.003 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 29.003 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 29.381 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 29.371 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 9.173  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 32.638 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 8.351  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 8.359  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 8.351  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 8.351  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 7.866  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 8.729  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 7.286  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 7.423  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 7.286  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 7.286  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 8.686  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 8.686  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 8.709  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 8.709  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 8.422  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 27.822 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 28.709 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 28.406 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 27.822 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 28.587 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 28.587 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 28.617 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 28.611 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 28.617 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 28.184 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 28.184 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 28.184 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 28.174 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 27.832 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 27.832 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 28.703 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 28.428 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 9.066  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 8.017  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.109  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.535  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 11.592 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 12.741 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 12.741 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 11.916 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 11.916 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 11.599 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 11.599 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 11.592 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 11.592 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.634  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 12.751 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.638  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.624  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.634  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 8.618  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 8.800  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 8.729  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 8.713  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 7.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 8.058  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 9.414  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 9.414  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 9.378  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 9.378  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 9.392  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 9.382  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 8.610  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 8.610  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 8.058  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 8.058  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 8.335  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 8.325  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.700  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.690  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 9.265  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 9.265  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 8.319  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 8.893  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 8.893  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 9.695  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 9.358  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 9.368  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 9.695  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 22.995 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 23.149 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 23.139 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 23.145 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 23.139 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 22.995 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 22.995 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 23.146 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 23.146 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 15.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 15.920 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 15.920 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 15.905 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 15.905 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 15.890 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 15.890 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 15.848 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 15.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 15.905 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 15.905 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 16.267 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 16.267 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 16.235 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 16.235 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 16.613 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 16.603 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 19.812 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 16.761 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 17.648 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 17.345 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 16.761 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 17.526 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 17.526 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 17.556 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 17.550 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 17.556 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 17.123 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 17.123 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 17.123 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 17.113 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 16.771 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 16.771 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 17.642 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 17.367 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 11.437 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 12.793 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 12.793 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 12.757 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 12.757 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 12.771 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 12.761 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 11.989 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 11.989 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 11.437 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 11.437 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 11.714 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 11.704 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 12.079 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 12.069 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 12.644 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 12.644 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 11.698 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 12.272 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 12.272 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 13.074 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 12.737 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 12.747 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 13.074 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 8.900  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 35.821 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 35.975 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 35.965 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 35.971 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 35.965 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 35.821 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 35.821 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 35.972 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 35.972 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 12.165 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 28.606 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 28.688 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 28.688 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 28.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 28.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 28.658 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 28.658 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 28.616 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 28.606 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 28.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 28.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 29.035 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 29.035 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 29.003 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 29.003 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 29.381 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 29.371 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 9.173  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 32.638 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 8.351  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 8.359  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 8.351  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 8.351  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 7.866  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.729  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 7.286  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 7.423  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 7.286  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 7.286  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 8.686  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 8.686  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 8.709  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 8.709  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 8.422  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 27.822 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 28.709 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 28.406 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 27.822 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 28.587 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 28.587 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 28.617 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 28.611 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 28.617 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 28.184 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 28.184 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 28.184 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 28.174 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 27.832 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 27.832 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 28.703 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 28.428 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 9.066  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 8.017  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.109  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.535  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 11.592 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 12.741 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 12.741 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 11.916 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 11.916 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 11.599 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 11.599 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 11.592 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 11.592 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.634  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 12.751 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.638  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.624  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.634  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 8.618  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 8.800  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.729  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 8.713  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 8.058  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 9.414  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 9.414  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 9.378  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 9.378  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 9.392  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 9.382  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 8.610  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 8.610  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 8.058  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 8.058  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 8.335  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 8.325  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.700  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.690  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 9.265  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 9.265  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 8.319  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 8.893  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 8.893  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 9.695  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 9.358  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 9.368  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 9.695  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 22.995 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 23.149 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 23.139 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 23.145 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 23.139 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 22.995 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 22.995 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 23.146 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 23.146 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 15.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 15.920 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 15.920 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 15.905 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 15.905 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 15.890 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 15.890 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 15.848 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 15.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 15.905 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 15.905 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 16.267 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 16.267 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 16.235 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 16.235 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 16.613 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 16.603 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 19.812 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 16.761 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 17.648 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 17.345 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 16.761 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 17.526 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 17.526 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 17.556 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 17.550 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 17.556 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 17.123 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 17.123 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 17.123 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 17.113 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 16.771 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 16.771 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 17.642 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 17.367 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 6.206  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 20.801 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 20.955 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 20.945 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 20.951 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 20.945 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 20.801 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 20.801 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 20.952 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 20.952 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 10.050 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 14.842 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 7.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 7.648  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 7.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 7.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 8.018  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 13.735 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 14.622 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 14.319 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 13.735 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 14.500 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 14.500 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 14.530 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 14.524 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 14.530 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 14.097 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 14.097 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 14.097 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 14.087 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 13.745 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 13.745 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 14.616 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 14.341 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 8.355  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 8.480  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.348  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.774  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 7.616  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 8.765  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 8.765  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 7.940  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 7.940  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 7.623  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 7.623  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 7.616  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 7.616  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.799  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 8.775  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.803  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.789  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.799  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 9.512  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 9.263  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 8.018  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 12.576 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 6.206  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 20.801 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 20.955 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 20.945 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 20.951 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 20.945 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 20.801 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 20.801 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 20.952 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 20.952 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 10.050 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 14.842 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 7.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 7.648  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 7.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 7.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.018  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 13.735 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 14.622 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 14.319 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 13.735 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 14.500 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 14.500 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 14.530 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 14.524 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 14.530 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 14.097 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 14.097 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 14.097 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 14.087 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 13.745 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 13.745 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 14.616 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 14.341 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 8.355  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 8.480  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.348  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.774  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 7.616  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 8.765  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 8.765  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 7.940  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 7.940  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 7.623  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 7.623  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 7.616  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 7.616  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.799  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 8.775  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.803  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.789  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.799  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 9.512  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 9.263  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.018  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 12.576 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 13.306 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 13.306 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 13.306 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 13.556 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 13.556 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 13.306 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 13.306 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 13.306 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 13.556 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 13.556 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                             ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise   ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 22.743 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 22.897 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 22.887 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 22.893 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 22.887 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 22.743 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 22.743 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 22.894 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 22.894 ;      ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 14.830 ;      ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 15.221 ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 7.488  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 8.844  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 8.844  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 8.808  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 8.808  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 8.822  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 8.812  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 8.040  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 8.040  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 7.488  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 7.488  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 7.765  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 7.755  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.130  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.120  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 8.695  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 8.695  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 7.749  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 8.323  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 8.323  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 9.125  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 8.788  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 8.798  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 9.125  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 6.535  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 8.055  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 8.209  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 8.199  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 8.205  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 8.199  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 8.055  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 8.055  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 8.206  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 8.206  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 5.074  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 9.154  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 9.236  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 9.236  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 9.221  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 9.221  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 9.206  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 9.206  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 9.164  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 9.154  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 9.221  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 9.221  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 9.583  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 9.583  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 9.551  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 9.551  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 9.929  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 9.919  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 8.718  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 9.251  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 7.741  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 7.749  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 7.741  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 7.741  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 7.866  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 8.119  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 7.286  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 7.423  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 7.286  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 7.286  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 8.686  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 8.686  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 8.709  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 8.709  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 8.422  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 11.156 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 12.043 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 11.740 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 11.156 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.921 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.921 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 11.951 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 11.945 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 11.951 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 11.518 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 11.518 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 11.518 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 11.508 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 11.166 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 11.166 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 12.037 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 11.762 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 8.456  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 6.613  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.109  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.535  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 5.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 7.124  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 7.124  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 6.299  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 6.299  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 5.982  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 5.982  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 5.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 5.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.634  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 7.134  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.638  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.624  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.634  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 7.412  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 7.396  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 8.119  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 8.561  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 7.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 8.058  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 9.414  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 9.414  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 9.378  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 9.378  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 9.392  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 9.382  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 8.610  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 8.610  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 8.058  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 8.058  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 8.335  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 8.325  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.700  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.690  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 9.265  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 9.265  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 8.319  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 8.893  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 8.893  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 9.695  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 9.358  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 9.368  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 9.695  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 16.182 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 16.336 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 16.326 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 16.332 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 16.326 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 16.182 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 16.182 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 16.333 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 16.333 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 10.196 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 10.278 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 10.278 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 10.263 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 10.263 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 10.248 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 10.248 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 10.206 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 10.196 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 10.263 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 10.263 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 10.625 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 10.625 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 10.593 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 10.593 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 10.971 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 10.961 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 10.662 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 11.156 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 12.043 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 11.740 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 11.156 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.921 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.921 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 11.951 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 11.945 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 11.951 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 11.518 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 11.518 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 11.518 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 11.508 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 11.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 11.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 12.037 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 11.762 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 7.488  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 8.844  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 8.844  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 8.808  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 8.808  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 8.822  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 8.812  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 8.040  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 8.040  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 7.488  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 7.488  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 7.765  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 7.755  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.130  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.120  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 8.695  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 8.695  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 7.749  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 8.323  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 8.323  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 9.125  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 8.788  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 8.798  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 9.125  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 6.535  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 8.055  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 8.209  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 8.199  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 8.205  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 8.199  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 8.055  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 8.055  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 8.206  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 8.206  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 5.074  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 9.154  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 9.236  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 9.236  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 9.221  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 9.221  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 9.206  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 9.206  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 9.164  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 9.154  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 9.221  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 9.221  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 9.583  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 9.583  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 9.551  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 9.551  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 9.929  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 9.919  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 8.718  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 9.251  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 7.741  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 7.749  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 7.741  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 7.741  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 7.866  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.119  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 7.286  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 7.423  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 7.286  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 7.286  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 8.686  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 8.686  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 8.709  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 8.709  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 8.422  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 11.156 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 12.043 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 11.740 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 11.156 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.921 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.921 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 11.951 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 11.945 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 11.951 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 11.518 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 11.518 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 11.518 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 11.508 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 11.166 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 11.166 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 12.037 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 11.762 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 8.456  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 6.613  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.109  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.535  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 5.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 7.124  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 7.124  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 6.299  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 6.299  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 5.982  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 5.982  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 5.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 5.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.634  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 7.134  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.638  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.624  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.634  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 7.412  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 7.396  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.119  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 8.561  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.883  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 8.058  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 9.414  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 9.414  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 9.378  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 9.378  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 9.392  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 9.382  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 8.610  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 8.610  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 8.058  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 8.058  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 8.335  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 8.325  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.700  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.690  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 9.265  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 9.265  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 8.319  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 8.893  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 8.893  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 9.695  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 9.358  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 9.368  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 9.695  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 16.182 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 16.336 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 16.326 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 16.332 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 16.326 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 16.182 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 16.182 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 16.333 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 16.333 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 10.196 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 10.278 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 10.278 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 10.263 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 10.263 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 10.248 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 10.248 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 10.206 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 10.196 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 10.263 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 10.263 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 10.625 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 10.625 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 10.593 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 10.593 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 10.971 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 10.961 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 10.662 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 11.156 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 12.043 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 11.740 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 11.156 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.921 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.921 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 11.951 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 11.945 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 11.951 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 11.518 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 11.518 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 11.518 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 11.508 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 11.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 11.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 12.037 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 11.762 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 6.206  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 9.717  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 9.871  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 9.861  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 9.867  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 9.861  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 9.717  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 9.717  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 9.868  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 9.868  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 7.992  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 8.383  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 7.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 7.648  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 7.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 7.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 8.018  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 9.193  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 10.080 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 9.777  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 9.193  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 9.958  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 9.958  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 9.988  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 9.982  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 9.988  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 9.555  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 9.555  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 9.555  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 9.545  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 9.203  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 9.203  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 10.074 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 9.799  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 8.355  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 8.113  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.205  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.631  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 7.469  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 8.618  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 8.618  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 7.793  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 7.793  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 7.476  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 7.476  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 7.469  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 7.469  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.650  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 8.628  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.654  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.650  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 9.129  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 8.896  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 8.018  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 12.576 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 6.206  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 9.717  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 9.871  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 9.861  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 9.867  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 9.861  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 9.717  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 9.717  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 9.868  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 9.868  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 7.992  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 8.383  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 7.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 7.648  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 7.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 7.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.018  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 9.193  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 10.080 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 9.777  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 9.193  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 9.958  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 9.958  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 9.988  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 9.982  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 9.988  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 9.555  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 9.555  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 9.555  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 9.545  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 9.203  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 9.203  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 10.074 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 9.799  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 8.355  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 8.113  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.205  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.631  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 7.469  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 8.618  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 8.618  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 7.793  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 7.793  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 7.476  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 7.476  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 7.469  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 7.469  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.650  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 8.628  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.654  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.650  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 9.129  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 8.896  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.018  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 12.576 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 7.439  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 7.439  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 7.439  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 7.532  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 7.532  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 7.439  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 7.439  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 7.439  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 7.532  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 7.532  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 25.581    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 25.735    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 25.725    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 25.731    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 25.725    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 25.581    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 25.581    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 25.732    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 25.732    ;           ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 14.830    ;           ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 19.622    ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 11.437    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 12.793    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 12.793    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 12.757    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 12.757    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 12.771    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 12.761    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 11.989    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 11.989    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 11.437    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 11.437    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 11.714    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 11.704    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 12.079    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 12.069    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 12.644    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 12.644    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 11.698    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 12.272    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 12.272    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 13.074    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 12.737    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 12.747    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 13.074    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 8.900     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 35.821    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 35.975    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 35.965    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 35.971    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 35.965    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 35.821    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 35.821    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 35.972    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 35.972    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 12.165    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 28.606    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 28.688    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 28.688    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 28.673    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 28.673    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 28.658    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 28.658    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 28.616    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 28.606    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 28.673    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 28.673    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 29.035    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 29.035    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 29.003    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 29.003    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 29.381    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 29.371    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 9.173     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 32.638    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 8.351     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 8.359     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 8.351     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 8.351     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 7.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 8.729     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 7.286     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 7.423     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 7.286     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 7.286     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 8.686     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 8.686     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 8.709     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 8.709     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 8.422     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 27.822    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 28.709    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 28.406    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 27.822    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 28.587    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 28.587    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 28.617    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 28.611    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 28.617    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 28.184    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 28.184    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 28.184    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 28.174    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 27.832    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 27.832    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 28.703    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 28.428    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 9.066     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 8.017     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.109     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.535     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 11.592    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 12.741    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 12.741    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 11.916    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 11.916    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 11.599    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 11.599    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 11.592    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 11.592    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.634     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 12.751    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.638     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.624     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.634     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 8.618     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 8.800     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 8.729     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 8.713     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 7.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 8.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 9.414     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 9.414     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 9.378     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 9.378     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 9.392     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 9.382     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 8.610     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 8.610     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 8.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 8.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 8.335     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 8.325     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.700     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.690     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 9.265     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 9.265     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 8.319     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 8.893     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 8.893     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 9.695     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 9.358     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 9.368     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 9.695     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 22.995    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 23.149    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 23.139    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 23.145    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 23.139    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 22.995    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 22.995    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 23.146    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 23.146    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 15.838    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 15.920    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 15.920    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 15.905    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 15.905    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 15.890    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 15.890    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 15.848    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 15.838    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 15.905    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 15.905    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 16.267    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 16.267    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 16.235    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 16.235    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 16.613    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 16.603    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 19.812    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 16.761    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 17.648    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 17.345    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 16.761    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 17.526    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 17.526    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 17.556    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 17.550    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 17.556    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 17.123    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 17.123    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 17.123    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 17.113    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 16.771    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 16.771    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 17.642    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 17.367    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 11.437    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 12.793    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 12.793    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 12.757    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 12.757    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 12.771    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 12.761    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 11.989    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 11.989    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 11.437    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 11.437    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 11.714    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 11.704    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 12.079    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 12.069    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 12.644    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 12.644    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 11.698    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 12.272    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 12.272    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 13.074    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 12.737    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 12.747    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 13.074    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 8.900     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 35.821    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 35.975    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 35.965    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 35.971    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 35.965    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 35.821    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 35.821    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 35.972    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 35.972    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 12.165    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 28.606    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 28.688    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 28.688    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 28.673    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 28.673    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 28.658    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 28.658    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 28.616    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 28.606    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 28.673    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 28.673    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 29.035    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 29.035    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 29.003    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 29.003    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 29.381    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 29.371    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 9.173     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 32.638    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 8.351     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 8.359     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 8.351     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 8.351     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 7.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.729     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 7.286     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 7.423     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 7.286     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 7.286     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 8.686     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 8.686     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 8.709     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 8.709     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 8.422     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 27.822    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 28.709    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 28.406    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 27.822    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 28.587    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 28.587    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 28.617    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 28.611    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 28.617    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 28.184    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 28.184    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 28.184    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 28.174    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 27.832    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 27.832    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 28.703    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 28.428    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 9.066     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 8.017     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.109     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.535     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 11.592    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 12.741    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 12.741    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 11.916    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 11.916    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 11.599    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 11.599    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 11.592    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 11.592    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.634     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 12.751    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.638     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.624     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.634     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 8.618     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 8.800     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.729     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 8.713     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 8.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 9.414     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 9.414     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 9.378     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 9.378     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 9.392     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 9.382     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 8.610     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 8.610     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 8.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 8.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 8.335     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 8.325     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.700     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.690     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 9.265     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 9.265     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 8.319     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 8.893     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 8.893     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 9.695     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 9.358     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 9.368     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 9.695     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 22.995    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 23.149    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 23.139    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 23.145    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 23.139    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 22.995    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 22.995    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 23.146    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 23.146    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 15.838    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 15.920    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 15.920    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 15.905    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 15.905    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 15.890    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 15.890    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 15.848    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 15.838    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 15.905    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 15.905    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 16.267    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 16.267    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 16.235    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 16.235    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 16.613    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 16.603    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 19.812    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 16.761    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 17.648    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 17.345    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 16.761    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 17.526    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 17.526    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 17.556    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 17.550    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 17.556    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 17.123    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 17.123    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 17.123    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 17.113    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 16.771    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 16.771    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 17.642    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 17.367    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 6.206     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 20.801    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 20.955    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 20.945    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 20.951    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 20.945    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 20.801    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 20.801    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 20.952    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 20.952    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 10.050    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 14.842    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 7.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 7.648     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 7.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 7.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 8.018     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 13.735    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 14.622    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 14.319    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 13.735    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 14.500    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 14.500    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 14.530    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 14.524    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 14.530    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 14.097    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 14.097    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 14.097    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 14.087    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 13.745    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 13.745    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 14.616    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 14.341    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 8.355     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 8.480     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.348     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.774     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 7.616     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 8.765     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 8.765     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 7.940     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 7.940     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 7.623     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 7.623     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 7.616     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 7.616     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.799     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 8.775     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.803     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.789     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.799     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 9.512     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 9.263     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 8.018     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 12.576    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 6.206     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 20.801    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 20.955    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 20.945    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 20.951    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 20.945    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 20.801    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 20.801    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 20.952    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 20.952    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 10.050    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 14.842    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 7.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 7.648     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 7.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 7.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.018     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 13.735    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 14.622    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 14.319    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 13.735    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 14.500    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 14.500    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 14.530    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 14.524    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 14.530    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 14.097    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 14.097    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 14.097    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 14.087    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 13.745    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 13.745    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 14.616    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 14.341    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 8.355     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 8.480     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.348     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.774     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 7.616     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 8.765     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 8.765     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 7.940     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 7.940     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 7.623     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 7.623     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 7.616     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 7.616     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.799     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 8.775     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.803     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.789     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.799     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 9.512     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 9.263     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.018     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 12.576    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 13.306    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 13.306    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 13.306    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 13.556    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 13.556    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 13.306    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 13.306    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 13.306    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 13.556    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 13.556    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                    ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 22.743    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 22.897    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 22.887    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 22.893    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 22.887    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 22.743    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 22.743    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 22.894    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 22.894    ;           ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 14.830    ;           ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 15.221    ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 7.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 8.844     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 8.844     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 8.808     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 8.808     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 8.822     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 8.812     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 8.040     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 8.040     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 7.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 7.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 7.765     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 7.755     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.130     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.120     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 8.695     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 8.695     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 7.749     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 8.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 8.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 9.125     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 8.788     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 8.798     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 9.125     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 6.535     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 8.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 8.209     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 8.199     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 8.205     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 8.199     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 8.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 8.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 8.206     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 8.206     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 5.074     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 9.154     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 9.236     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 9.236     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 9.221     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 9.221     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 9.206     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 9.206     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 9.164     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 9.154     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 9.221     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 9.221     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 9.583     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 9.583     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 9.551     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 9.551     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 9.929     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 9.919     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 8.718     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 9.251     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 7.741     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 7.749     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 7.741     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 7.741     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 7.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 8.119     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 7.286     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 7.423     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 7.286     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 7.286     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 8.686     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 8.686     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 8.709     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 8.709     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 8.422     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 11.156    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 12.043    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 11.740    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 11.156    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.921    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.921    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 11.951    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 11.945    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 11.951    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 11.518    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 11.518    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 11.518    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 11.508    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 11.166    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 11.166    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 12.037    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 11.762    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 8.456     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 6.613     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.109     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.535     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 5.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 7.124     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 7.124     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 6.299     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 6.299     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 5.982     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 5.982     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 5.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 5.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.634     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 7.134     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.638     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.624     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.634     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 7.412     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 7.396     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 8.119     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 8.561     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 7.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 8.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 9.414     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 9.414     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 9.378     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 9.378     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 9.392     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 9.382     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 8.610     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 8.610     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 8.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 8.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 8.335     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 8.325     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.700     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.690     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 9.265     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 9.265     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 8.319     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 8.893     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 8.893     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 9.695     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 9.358     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 9.368     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 9.695     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 16.182    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 16.336    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 16.326    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 16.332    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 16.326    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 16.182    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 16.182    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 16.333    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 16.333    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 10.196    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 10.278    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 10.278    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 10.263    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 10.263    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 10.248    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 10.248    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 10.206    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 10.196    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 10.263    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 10.263    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 10.625    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 10.625    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 10.593    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 10.593    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 10.971    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 10.961    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 10.662    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 11.156    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 12.043    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 11.740    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 11.156    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.921    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.921    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 11.951    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 11.945    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 11.951    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 11.518    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 11.518    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 11.518    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 11.508    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 11.166    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 11.166    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 12.037    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 11.762    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 7.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 8.844     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 8.844     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 8.808     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 8.808     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 8.822     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 8.812     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 8.040     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 8.040     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 7.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 7.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 7.765     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 7.755     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.130     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.120     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 8.695     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 8.695     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 7.749     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 8.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 8.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 9.125     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 8.788     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 8.798     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 9.125     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 6.535     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 8.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 8.209     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 8.199     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 8.205     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 8.199     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 8.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 8.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 8.206     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 8.206     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 5.074     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 9.154     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 9.236     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 9.236     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 9.221     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 9.221     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 9.206     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 9.206     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 9.164     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 9.154     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 9.221     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 9.221     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 9.583     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 9.583     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 9.551     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 9.551     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 9.929     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 9.919     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 8.718     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 9.251     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 7.741     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 7.749     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 7.741     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 7.741     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 7.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.119     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 7.286     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 7.423     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 7.286     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 7.286     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 8.686     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 8.686     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 8.709     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 8.709     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 8.422     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 11.156    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 12.043    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 11.740    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 11.156    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.921    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.921    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 11.951    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 11.945    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 11.951    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 11.518    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 11.518    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 11.518    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 11.508    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 11.166    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 11.166    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 12.037    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 11.762    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 8.456     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 6.613     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.109     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.535     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 5.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 7.124     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 7.124     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 6.299     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 6.299     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 5.982     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 5.982     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 5.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 5.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.634     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 7.134     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.638     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.624     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.634     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 7.412     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 7.396     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.119     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 8.561     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.883     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 8.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 9.414     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 9.414     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 9.378     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 9.378     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 9.392     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 9.382     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 8.610     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 8.610     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 8.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 8.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 8.335     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 8.325     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.700     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.690     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 9.265     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 9.265     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 8.319     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 8.893     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 8.893     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 9.695     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 9.358     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 9.368     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 9.695     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 16.182    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 16.336    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 16.326    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 16.332    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 16.326    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 16.182    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 16.182    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 16.333    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 16.333    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 10.196    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 10.278    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 10.278    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 10.263    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 10.263    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 10.248    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 10.248    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 10.206    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 10.196    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 10.263    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 10.263    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 10.625    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 10.625    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 10.593    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 10.593    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 10.971    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 10.961    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 10.662    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 11.156    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 12.043    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 11.740    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 11.156    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.921    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.921    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 11.951    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 11.945    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 11.951    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 11.518    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 11.518    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 11.518    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 11.508    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 11.166    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 11.166    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 12.037    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 11.762    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 6.206     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 9.717     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 9.871     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 9.861     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 9.867     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 9.861     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 9.717     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 9.717     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 9.868     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 9.868     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 7.992     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 8.383     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 7.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 7.648     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 7.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 7.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 8.018     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 9.193     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 10.080    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 9.777     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 9.193     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 9.958     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 9.958     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 9.988     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 9.982     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 9.988     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 9.555     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 9.555     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 9.555     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 9.545     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 9.203     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 9.203     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 10.074    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 9.799     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 8.355     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 8.113     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.205     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.631     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 7.469     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 8.618     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 8.618     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 7.793     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 7.793     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 7.476     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 7.476     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 7.469     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 7.469     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.650     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 8.628     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.654     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.650     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 9.129     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 8.896     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 8.018     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 12.576    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 6.206     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 9.717     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 9.871     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 9.861     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 9.867     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 9.861     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 9.717     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 9.717     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 9.868     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 9.868     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 7.992     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 8.383     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 7.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 7.648     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 7.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 7.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.018     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 9.193     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 10.080    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 9.777     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 9.193     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 9.958     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 9.958     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 9.988     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 9.982     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 9.988     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 9.555     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 9.555     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 9.555     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 9.545     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 9.203     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 9.203     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 10.074    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 9.799     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 8.355     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 8.113     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.205     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.631     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 7.469     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 8.618     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 8.618     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 7.793     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 7.793     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 7.476     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 7.476     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 7.469     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 7.469     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.650     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 8.628     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.654     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.650     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 9.129     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 8.896     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.018     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 12.576    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 7.439     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 7.439     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 7.439     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 7.532     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 7.532     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 7.439     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 7.439     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 7.439     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 7.532     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 7.532     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------+
; Fast Model Setup Summary                                                            ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1.069  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1.069  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 1.138  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 1.138  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 3.048  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 3.048  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 24.422 ; 0.000         ;
; CODEC_SCLK                                                 ; 36.626 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 38.707 ; 0.000         ;
; CLK_PLL1                                                   ; 61.367 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 61.685 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------+
; Fast Model Hold Summary                                                            ;
+------------------------------------------------------------+-------+---------------+
; Clock                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------+-------+---------------+
; CODEC_SCLK                                                 ; 0.073 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 0.215 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.215 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 0.215 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.215 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 0.215 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.215 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 0.215 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 0.215 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 0.215 ; 0.000         ;
; CLK_PLL1                                                   ; 0.239 ; 0.000         ;
+------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------+
; Fast Model Recovery Summary                                                         ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 26.724 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 26.724 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 26.726 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 26.726 ; 0.000         ;
; CODEC_SCLK                                                 ; 80.188 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------+
; Fast Model Removal Summary                                                         ;
+------------------------------------------------------------+-------+---------------+
; Clock                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------+-------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 1.063 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 1.063 ; 0.000         ;
; CODEC_SCLK                                                 ; 1.073 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1.088 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1.088 ; 0.000         ;
+------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width Summary                                              ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 8.289  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 8.289  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 11.695 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 13.498 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 13.498 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 18.531 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 29.231 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 29.231 ; 0.000         ;
; CLK_PLL1                                                   ; 30.250 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 30.250 ; 0.000         ;
; CLK_PLL2                                                   ; 31.250 ; 0.000         ;
; CRT_PIN4_CLK1                                              ; 31.250 ; 0.000         ;
; CODEC_SCLK                                                 ; 38.573 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                  ;
+-------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                         ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 1.069 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.025      ; 9.405      ;
; 1.069 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.025      ; 9.405      ;
; 1.073 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.025      ; 9.401      ;
; 1.073 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.025      ; 9.401      ;
; 1.122 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 9.338      ;
; 1.122 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 9.338      ;
; 1.156 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.001     ; 9.292      ;
; 1.156 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.001     ; 9.292      ;
; 1.162 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.019      ; 9.306      ;
; 1.162 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.019      ; 9.306      ;
; 1.183 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.006     ; 9.260      ;
; 1.183 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.006     ; 9.260      ;
; 1.184 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.291      ;
; 1.184 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.291      ;
; 1.188 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.287      ;
; 1.188 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.287      ;
; 1.192 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.283      ;
; 1.192 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.283      ;
; 1.195 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.005      ; 9.259      ;
; 1.195 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.005      ; 9.259      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.005      ; 9.258      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.245      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.012      ; 9.265      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.279      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.005      ; 9.258      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.008     ; 9.245      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.012      ; 9.265      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.279      ;
; 1.204 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.012      ; 9.257      ;
; 1.204 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.012      ; 9.257      ;
; 1.205 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.011     ; 9.233      ;
; 1.205 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.011     ; 9.233      ;
; 1.228 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 9.227      ;
; 1.228 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 9.227      ;
; 1.230 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.020     ; 9.199      ;
; 1.230 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.000      ; 9.219      ;
; 1.230 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.020     ; 9.199      ;
; 1.230 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.000      ; 9.219      ;
; 1.232 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 9.223      ;
; 1.232 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 9.223      ;
; 1.238 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.000      ; 9.211      ;
; 1.238 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.000      ; 9.211      ;
; 1.255 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.019      ; 9.213      ;
; 1.255 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.019      ; 9.213      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.206      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.014     ; 9.166      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 9.186      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.206      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.014     ; 9.166      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 9.186      ;
; 1.270 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.014     ; 9.165      ;
; 1.270 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 9.185      ;
; 1.270 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.014     ; 9.165      ;
; 1.270 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 9.185      ;
; 1.273 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.202      ;
; 1.273 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.202      ;
; 1.275 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.200      ;
; 1.275 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.200      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.020      ; 9.192      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 9.178      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.020      ; 9.192      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 9.178      ;
; 1.278 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 9.177      ;
; 1.278 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 9.177      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.196      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.030     ; 9.140      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.010     ; 9.160      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.196      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.030     ; 9.140      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.010     ; 9.160      ;
; 1.280 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.005      ; 9.174      ;
; 1.280 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.005      ; 9.174      ;
; 1.281 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.012      ; 9.180      ;
; 1.281 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.012      ; 9.180      ;
; 1.285 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.020      ; 9.184      ;
; 1.285 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.020      ; 9.184      ;
; 1.287 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.012      ; 9.174      ;
; 1.287 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.010     ; 9.152      ;
; 1.287 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.012      ; 9.174      ;
; 1.287 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.010     ; 9.152      ;
; 1.298 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.012     ; 9.139      ;
; 1.298 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.005     ; 9.146      ;
; 1.298 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.012     ; 9.139      ;
; 1.298 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.005     ; 9.146      ;
; 1.306 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.005     ; 9.138      ;
; 1.306 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.005     ; 9.138      ;
; 1.315 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.000      ; 9.134      ;
; 1.315 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.000      ; 9.134      ;
; 1.319 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.005      ; 9.135      ;
; 1.319 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.005      ; 9.135      ;
; 1.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 9.139      ;
; 1.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.000      ; 9.128      ;
; 1.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.000      ; 9.128      ;
; 1.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 9.139      ;
; 1.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.000      ; 9.128      ;
; 1.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.000      ; 9.128      ;
; 1.326 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.149      ;
; 1.326 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.026      ; 9.149      ;
; 1.329 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.000      ; 9.120      ;
; 1.329 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.020      ; 9.140      ;
+-------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                  ;
+-------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                         ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 1.069 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.025      ; 9.405      ;
; 1.069 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.025      ; 9.405      ;
; 1.073 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.025      ; 9.401      ;
; 1.073 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.025      ; 9.401      ;
; 1.122 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 9.338      ;
; 1.122 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 9.338      ;
; 1.156 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.001     ; 9.292      ;
; 1.156 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.001     ; 9.292      ;
; 1.162 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.019      ; 9.306      ;
; 1.162 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.019      ; 9.306      ;
; 1.183 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.006     ; 9.260      ;
; 1.183 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.006     ; 9.260      ;
; 1.184 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.291      ;
; 1.184 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.291      ;
; 1.188 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.287      ;
; 1.188 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.287      ;
; 1.192 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.283      ;
; 1.192 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.283      ;
; 1.195 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.005      ; 9.259      ;
; 1.195 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.005      ; 9.259      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.005      ; 9.258      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.245      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.012      ; 9.265      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.279      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.005      ; 9.258      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.008     ; 9.245      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.012      ; 9.265      ;
; 1.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.279      ;
; 1.204 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.012      ; 9.257      ;
; 1.204 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.012      ; 9.257      ;
; 1.205 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.011     ; 9.233      ;
; 1.205 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.011     ; 9.233      ;
; 1.228 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 9.227      ;
; 1.228 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 9.227      ;
; 1.230 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.020     ; 9.199      ;
; 1.230 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.000      ; 9.219      ;
; 1.230 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.020     ; 9.199      ;
; 1.230 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.000      ; 9.219      ;
; 1.232 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 9.223      ;
; 1.232 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 9.223      ;
; 1.238 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.000      ; 9.211      ;
; 1.238 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.000      ; 9.211      ;
; 1.255 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.019      ; 9.213      ;
; 1.255 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.019      ; 9.213      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.206      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.014     ; 9.166      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 9.186      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.206      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.014     ; 9.166      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 9.186      ;
; 1.270 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.014     ; 9.165      ;
; 1.270 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 9.185      ;
; 1.270 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.014     ; 9.165      ;
; 1.270 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 9.185      ;
; 1.273 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.202      ;
; 1.273 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.202      ;
; 1.275 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.200      ;
; 1.275 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.200      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.020      ; 9.192      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 9.178      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.020      ; 9.192      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 9.178      ;
; 1.278 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 9.177      ;
; 1.278 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 9.177      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.196      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.030     ; 9.140      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.010     ; 9.160      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.196      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.030     ; 9.140      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.010     ; 9.160      ;
; 1.280 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.005      ; 9.174      ;
; 1.280 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.005      ; 9.174      ;
; 1.281 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.012      ; 9.180      ;
; 1.281 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.012      ; 9.180      ;
; 1.285 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.020      ; 9.184      ;
; 1.285 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.020      ; 9.184      ;
; 1.287 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.012      ; 9.174      ;
; 1.287 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.010     ; 9.152      ;
; 1.287 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.012      ; 9.174      ;
; 1.287 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.010     ; 9.152      ;
; 1.298 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.012     ; 9.139      ;
; 1.298 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.005     ; 9.146      ;
; 1.298 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.012     ; 9.139      ;
; 1.298 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.005     ; 9.146      ;
; 1.306 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.005     ; 9.138      ;
; 1.306 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.005     ; 9.138      ;
; 1.315 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.000      ; 9.134      ;
; 1.315 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.000      ; 9.134      ;
; 1.319 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.005      ; 9.135      ;
; 1.319 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.005      ; 9.135      ;
; 1.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 9.139      ;
; 1.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.000      ; 9.128      ;
; 1.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.000      ; 9.128      ;
; 1.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 9.139      ;
; 1.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.000      ; 9.128      ;
; 1.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.000      ; 9.128      ;
; 1.326 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.149      ;
; 1.326 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.026      ; 9.149      ;
; 1.329 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.000      ; 9.120      ;
; 1.329 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.020      ; 9.140      ;
+-------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                          ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                         ; To Node                                                                                  ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 1.138 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.341      ;
; 1.138 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.341      ;
; 1.143 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.336      ;
; 1.143 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.336      ;
; 1.156 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.029      ; 9.322      ;
; 1.156 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.029      ; 9.322      ;
; 1.195 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.284      ;
; 1.195 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.284      ;
; 1.195 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.284      ;
; 1.195 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.284      ;
; 1.252 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.228      ;
; 1.252 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.228      ;
; 1.253 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.227      ;
; 1.253 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.227      ;
; 1.258 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.222      ;
; 1.258 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.222      ;
; 1.261 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.219      ;
; 1.261 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.219      ;
; 1.266 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.028      ; 9.211      ;
; 1.266 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.214      ;
; 1.266 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.028      ; 9.211      ;
; 1.266 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.214      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.191      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.191      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.211      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.211      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.191      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.191      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.211      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.211      ;
; 1.271 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.208      ;
; 1.271 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.208      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.203      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.203      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.203      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.203      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.024      ; 9.194      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.200      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.024      ; 9.194      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.200      ;
; 1.282 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.029      ; 9.196      ;
; 1.282 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.029      ; 9.196      ;
; 1.297 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.163      ;
; 1.297 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.163      ;
; 1.302 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.158      ;
; 1.302 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.158      ;
; 1.304 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.027      ; 9.172      ;
; 1.304 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.028      ; 9.173      ;
; 1.304 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.027      ; 9.172      ;
; 1.304 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.028      ; 9.173      ;
; 1.307 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.027      ; 9.169      ;
; 1.307 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.027      ; 9.169      ;
; 1.310 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[17]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.027      ; 9.166      ;
; 1.310 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[17]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.027      ; 9.166      ;
; 1.312 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.028      ; 9.165      ;
; 1.312 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.028      ; 9.165      ;
; 1.315 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.010      ; 9.144      ;
; 1.315 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.010      ; 9.144      ;
; 1.318 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.028      ; 9.159      ;
; 1.318 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.028      ; 9.159      ;
; 1.327 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.006      ; 9.128      ;
; 1.327 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.006      ; 9.128      ;
; 1.328 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[16]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.027      ; 9.148      ;
; 1.328 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[16]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.027      ; 9.148      ;
; 1.329 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.026      ; 9.146      ;
; 1.329 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.026      ; 9.146      ;
; 1.330 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.029      ; 9.148      ;
; 1.330 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.029      ; 9.148      ;
; 1.333 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.029      ; 9.145      ;
; 1.333 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.146      ;
; 1.333 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.029      ; 9.145      ;
; 1.333 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.146      ;
; 1.338 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.142      ;
; 1.338 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.142      ;
; 1.343 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.137      ;
; 1.343 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.137      ;
; 1.344 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.136      ;
; 1.344 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.136      ;
; 1.349 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.131      ;
; 1.349 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.131      ;
; 1.354 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.126      ;
; 1.354 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.126      ;
; 1.354 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.126      ;
; 1.354 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.126      ;
; 1.356 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.123      ;
; 1.356 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.123      ;
; 1.360 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.120      ;
; 1.360 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.120      ;
; 1.360 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.120      ;
; 1.360 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.031      ; 9.120      ;
; 1.362 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.117      ;
; 1.362 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.030      ; 9.117      ;
; 1.367 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.032      ; 9.114      ;
; 1.367 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.032      ; 9.114      ;
; 1.375 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.032      ; 9.106      ;
; 1.375 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.032      ; 9.106      ;
; 1.381 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[17]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.028      ; 9.096      ;
; 1.381 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[9]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.027      ; 9.095      ;
; 1.381 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.029      ; 9.097      ;
; 1.381 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[17]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.028      ; 9.096      ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                          ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                         ; To Node                                                                                  ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 1.138 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.341      ;
; 1.138 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.341      ;
; 1.143 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.336      ;
; 1.143 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.336      ;
; 1.156 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.029      ; 9.322      ;
; 1.156 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.029      ; 9.322      ;
; 1.195 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.284      ;
; 1.195 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.284      ;
; 1.195 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.284      ;
; 1.195 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.284      ;
; 1.252 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.228      ;
; 1.252 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.228      ;
; 1.253 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.227      ;
; 1.253 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.227      ;
; 1.258 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.222      ;
; 1.258 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.222      ;
; 1.261 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.219      ;
; 1.261 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.219      ;
; 1.266 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.028      ; 9.211      ;
; 1.266 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.214      ;
; 1.266 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.028      ; 9.211      ;
; 1.266 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.214      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.191      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.191      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.211      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.211      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.191      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.191      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.211      ;
; 1.269 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.211      ;
; 1.271 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.208      ;
; 1.271 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.208      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.203      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.203      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.203      ;
; 1.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.203      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.024      ; 9.194      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.200      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.024      ; 9.194      ;
; 1.279 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.200      ;
; 1.282 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.029      ; 9.196      ;
; 1.282 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.029      ; 9.196      ;
; 1.297 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.163      ;
; 1.297 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.163      ;
; 1.302 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.158      ;
; 1.302 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.158      ;
; 1.304 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.027      ; 9.172      ;
; 1.304 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.028      ; 9.173      ;
; 1.304 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.027      ; 9.172      ;
; 1.304 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.028      ; 9.173      ;
; 1.307 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.027      ; 9.169      ;
; 1.307 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.027      ; 9.169      ;
; 1.310 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[17]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.027      ; 9.166      ;
; 1.310 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[17]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.027      ; 9.166      ;
; 1.312 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.028      ; 9.165      ;
; 1.312 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.028      ; 9.165      ;
; 1.315 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.010      ; 9.144      ;
; 1.315 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.010      ; 9.144      ;
; 1.318 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.028      ; 9.159      ;
; 1.318 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.028      ; 9.159      ;
; 1.327 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.006      ; 9.128      ;
; 1.327 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.006      ; 9.128      ;
; 1.328 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[16]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.027      ; 9.148      ;
; 1.328 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[16]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.027      ; 9.148      ;
; 1.329 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.026      ; 9.146      ;
; 1.329 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.026      ; 9.146      ;
; 1.330 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.029      ; 9.148      ;
; 1.330 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.029      ; 9.148      ;
; 1.333 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.029      ; 9.145      ;
; 1.333 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.146      ;
; 1.333 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.029      ; 9.145      ;
; 1.333 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.146      ;
; 1.338 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.142      ;
; 1.338 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.142      ;
; 1.343 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.137      ;
; 1.343 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.137      ;
; 1.344 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.136      ;
; 1.344 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.136      ;
; 1.349 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.131      ;
; 1.349 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.131      ;
; 1.354 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.126      ;
; 1.354 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.126      ;
; 1.354 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.126      ;
; 1.354 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.126      ;
; 1.356 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.123      ;
; 1.356 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.123      ;
; 1.360 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.120      ;
; 1.360 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.120      ;
; 1.360 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.120      ;
; 1.360 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.031      ; 9.120      ;
; 1.362 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.117      ;
; 1.362 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.030      ; 9.117      ;
; 1.367 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.032      ; 9.114      ;
; 1.367 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.032      ; 9.114      ;
; 1.375 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.032      ; 9.106      ;
; 1.375 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.032      ; 9.106      ;
; 1.381 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[17]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.028      ; 9.096      ;
; 1.381 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[9]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.027      ; 9.095      ;
; 1.381 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.029      ; 9.097      ;
; 1.381 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[17]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.028      ; 9.096      ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                                                 ;
+-------+-------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                       ; To Node                                           ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 3.048 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.702      ; 9.102      ;
; 3.048 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.702      ; 9.102      ;
; 3.131 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.720      ; 9.037      ;
; 3.131 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.720      ; 9.037      ;
; 3.305 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.700      ; 8.843      ;
; 3.305 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.700      ; 8.843      ;
; 3.325 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.700      ; 8.823      ;
; 3.325 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.700      ; 8.823      ;
; 3.378 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.700      ; 8.770      ;
; 3.378 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.700      ; 8.770      ;
; 3.386 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.700      ; 8.762      ;
; 3.386 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.700      ; 8.762      ;
; 3.520 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.700      ; 8.628      ;
; 3.520 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.700      ; 8.628      ;
; 3.521 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.707      ; 8.634      ;
; 3.521 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.707      ; 8.634      ;
; 3.695 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.729      ; 8.482      ;
; 3.695 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.729      ; 8.482      ;
; 3.708 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.679      ; 8.419      ;
; 3.708 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.679      ; 8.419      ;
; 3.810 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.726      ; 8.364      ;
; 3.810 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.726      ; 8.364      ;
; 3.878 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.724      ; 8.294      ;
; 3.878 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.724      ; 8.294      ;
; 3.880 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.701      ; 8.269      ;
; 3.880 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.701      ; 8.269      ;
; 3.920 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.724      ; 8.252      ;
; 3.920 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.724      ; 8.252      ;
; 3.944 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.681      ; 8.185      ;
; 3.944 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.681      ; 8.185      ;
; 3.988 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.723      ; 8.183      ;
; 3.988 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.723      ; 8.183      ;
; 3.995 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.730      ; 8.183      ;
; 3.995 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.730      ; 8.183      ;
; 4.071 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.706      ; 8.083      ;
; 4.071 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.706      ; 8.083      ;
; 4.097 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.701      ; 8.052      ;
; 4.097 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.701      ; 8.052      ;
; 4.149 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.725      ; 8.024      ;
; 4.149 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.725      ; 8.024      ;
; 4.166 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.702      ; 7.984      ;
; 4.166 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.702      ; 7.984      ;
; 4.204 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.727      ; 7.971      ;
; 4.204 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.727      ; 7.971      ;
; 4.247 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.701      ; 7.902      ;
; 4.247 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.701      ; 7.902      ;
; 4.327 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.700      ; 7.821      ;
; 4.327 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.700      ; 7.821      ;
; 4.819 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.601      ;
; 4.819 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.601      ;
; 4.860 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.560      ;
; 4.860 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.560      ;
; 4.897 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.523      ;
; 4.897 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.523      ;
; 4.910 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.510      ;
; 4.910 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.510      ;
; 4.938 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.482      ;
; 4.938 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.482      ;
; 4.951 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.469      ;
; 4.951 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.469      ;
; 5.018 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.402      ;
; 5.018 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.402      ;
; 5.019 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.026     ; 5.403      ;
; 5.019 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.026     ; 5.403      ;
; 5.022 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.398      ;
; 5.022 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.398      ;
; 5.027 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.002      ; 5.423      ;
; 5.027 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.002      ; 5.423      ;
; 5.035 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.385      ;
; 5.035 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.385      ;
; 5.036 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.384      ;
; 5.036 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.384      ;
; 5.055 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.008     ; 5.385      ;
; 5.055 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.008     ; 5.385      ;
; 5.059 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.361      ;
; 5.059 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.361      ;
; 5.059 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.361      ;
; 5.059 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.361      ;
; 5.063 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.357      ;
; 5.063 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.357      ;
; 5.063 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.357      ;
; 5.063 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.357      ;
; 5.065 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.004     ; 5.379      ;
; 5.065 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.004     ; 5.379      ;
; 5.076 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.344      ;
; 5.076 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.344      ;
; 5.077 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.343      ;
; 5.077 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.343      ;
; 5.079 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.341      ;
; 5.079 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.341      ;
; 5.097 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.026     ; 5.325      ;
; 5.097 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.026     ; 5.325      ;
; 5.100 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.320      ;
; 5.100 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.028     ; 5.320      ;
; 5.105 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.002      ; 5.345      ;
; 5.105 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.002      ; 5.345      ;
; 5.109 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.002     ; 5.337      ;
; 5.109 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.002     ; 5.337      ;
; 5.110 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.026     ; 5.312      ;
; 5.110 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; -0.026     ; 5.312      ;
+-------+-------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                                                 ;
+-------+-------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                       ; To Node                                           ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 3.048 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.702      ; 9.102      ;
; 3.048 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.702      ; 9.102      ;
; 3.131 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.720      ; 9.037      ;
; 3.131 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.720      ; 9.037      ;
; 3.305 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.700      ; 8.843      ;
; 3.305 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.700      ; 8.843      ;
; 3.325 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.700      ; 8.823      ;
; 3.325 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.700      ; 8.823      ;
; 3.378 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.700      ; 8.770      ;
; 3.378 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.700      ; 8.770      ;
; 3.386 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.700      ; 8.762      ;
; 3.386 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.700      ; 8.762      ;
; 3.520 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.700      ; 8.628      ;
; 3.520 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.700      ; 8.628      ;
; 3.521 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.707      ; 8.634      ;
; 3.521 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.707      ; 8.634      ;
; 3.695 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.729      ; 8.482      ;
; 3.695 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.729      ; 8.482      ;
; 3.708 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.679      ; 8.419      ;
; 3.708 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.679      ; 8.419      ;
; 3.810 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.726      ; 8.364      ;
; 3.810 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.726      ; 8.364      ;
; 3.878 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.724      ; 8.294      ;
; 3.878 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.724      ; 8.294      ;
; 3.880 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.701      ; 8.269      ;
; 3.880 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.701      ; 8.269      ;
; 3.920 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.724      ; 8.252      ;
; 3.920 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.724      ; 8.252      ;
; 3.944 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.681      ; 8.185      ;
; 3.944 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.681      ; 8.185      ;
; 3.988 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.723      ; 8.183      ;
; 3.988 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.723      ; 8.183      ;
; 3.995 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.730      ; 8.183      ;
; 3.995 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.730      ; 8.183      ;
; 4.071 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.706      ; 8.083      ;
; 4.071 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.706      ; 8.083      ;
; 4.097 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.701      ; 8.052      ;
; 4.097 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.701      ; 8.052      ;
; 4.149 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.725      ; 8.024      ;
; 4.149 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.725      ; 8.024      ;
; 4.166 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.702      ; 7.984      ;
; 4.166 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.702      ; 7.984      ;
; 4.204 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.727      ; 7.971      ;
; 4.204 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.727      ; 7.971      ;
; 4.247 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.701      ; 7.902      ;
; 4.247 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.701      ; 7.902      ;
; 4.327 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.700      ; 7.821      ;
; 4.327 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.700      ; 7.821      ;
; 4.819 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.601      ;
; 4.819 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.601      ;
; 4.860 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.560      ;
; 4.860 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.560      ;
; 4.897 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.523      ;
; 4.897 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.523      ;
; 4.910 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.510      ;
; 4.910 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.510      ;
; 4.938 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.482      ;
; 4.938 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.482      ;
; 4.951 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.469      ;
; 4.951 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.469      ;
; 5.018 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.402      ;
; 5.018 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.402      ;
; 5.019 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.026     ; 5.403      ;
; 5.019 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.026     ; 5.403      ;
; 5.022 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.398      ;
; 5.022 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.398      ;
; 5.027 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.002      ; 5.423      ;
; 5.027 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.002      ; 5.423      ;
; 5.035 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.385      ;
; 5.035 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.385      ;
; 5.036 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.384      ;
; 5.036 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.384      ;
; 5.055 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.008     ; 5.385      ;
; 5.055 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.008     ; 5.385      ;
; 5.059 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.361      ;
; 5.059 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.361      ;
; 5.059 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.361      ;
; 5.059 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.361      ;
; 5.063 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.357      ;
; 5.063 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.357      ;
; 5.063 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.357      ;
; 5.063 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.357      ;
; 5.065 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.004     ; 5.379      ;
; 5.065 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.004     ; 5.379      ;
; 5.076 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.344      ;
; 5.076 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.344      ;
; 5.077 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.343      ;
; 5.077 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.343      ;
; 5.079 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.341      ;
; 5.079 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.341      ;
; 5.097 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.026     ; 5.325      ;
; 5.097 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.026     ; 5.325      ;
; 5.100 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.320      ;
; 5.100 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.028     ; 5.320      ;
; 5.105 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.002      ; 5.345      ;
; 5.105 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.002      ; 5.345      ;
; 5.109 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.002     ; 5.337      ;
; 5.109 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.002     ; 5.337      ;
; 5.110 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.026     ; 5.312      ;
; 5.110 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; -0.026     ; 5.312      ;
+-------+-------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                          ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node             ; To Node               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 24.422 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.000      ;
; 24.434 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.988      ;
; 24.474 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.948      ;
; 24.651 ; CLK_24576             ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.771      ;
; 24.765 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.657      ;
; 24.777 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.645      ;
; 24.905 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.517      ;
; 24.912 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.510      ;
; 24.916 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.506      ;
; 25.055 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.367      ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'CODEC_SCLK'                                                                                                                              ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                   ; To Node                                        ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[163] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[162] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[161] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[160] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[159] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[135] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[122] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[121] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[120] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[119] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[118] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[14]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[13]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[12]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[11]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.626 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[10]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.116     ; 3.990      ;
; 36.667 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[207] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.051     ; 4.014      ;
; 36.682 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[134] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.109     ; 3.941      ;
; 36.682 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[133] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.109     ; 3.941      ;
; 36.682 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[132] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.109     ; 3.941      ;
; 36.682 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[131] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.109     ; 3.941      ;
; 36.682 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[55]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.109     ; 3.941      ;
; 36.682 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[49]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.109     ; 3.941      ;
; 36.682 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[41]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.109     ; 3.941      ;
; 36.682 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[40]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.109     ; 3.941      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[249] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[248] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[247] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[232] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[231] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[230] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[229] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[117] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[54]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[53]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[52]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[51]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[50]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[44]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[43]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.688 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[42]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.101     ; 3.943      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[165] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[164] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[130] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[129] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[128] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[127] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[126] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[125] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[124] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[123] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[48]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[9]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[8]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[7]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[6]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.689 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[5]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.105     ; 3.938      ;
; 36.695 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[236] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.050     ; 3.987      ;
; 36.701 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[234] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.051     ; 3.980      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[163] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[162] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[161] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[160] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[159] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[135] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[122] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[121] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[120] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[119] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[118] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[14]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[13]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[12]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[11]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.707 ; A4299:I_4299|BUFFER_IN[254] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[10]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.283      ; 4.308      ;
; 36.733 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[228] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.082     ; 3.917      ;
; 36.733 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[227] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.082     ; 3.917      ;
; 36.733 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[226] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.082     ; 3.917      ;
; 36.733 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[225] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.082     ; 3.917      ;
; 36.733 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[224] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.082     ; 3.917      ;
; 36.733 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[223] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.082     ; 3.917      ;
; 36.733 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[222] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.082     ; 3.917      ;
; 36.733 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[221] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.082     ; 3.917      ;
; 36.733 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[220] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.082     ; 3.917      ;
; 36.733 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[219] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.082     ; 3.917      ;
; 36.733 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[218] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.082     ; 3.917      ;
; 36.733 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[217] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.082     ; 3.917      ;
; 36.733 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[216] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.082     ; 3.917      ;
; 36.733 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[215] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.082     ; 3.917      ;
; 36.733 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[214] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.082     ; 3.917      ;
; 36.735 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[158] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.118     ; 3.879      ;
; 36.735 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[157] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.118     ; 3.879      ;
; 36.735 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[156] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.118     ; 3.879      ;
; 36.735 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[155] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.118     ; 3.879      ;
; 36.735 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[154] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.118     ; 3.879      ;
; 36.735 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[153] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.118     ; 3.879      ;
; 36.735 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[152] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.118     ; 3.879      ;
; 36.735 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[23]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.118     ; 3.879      ;
; 36.735 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[22]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.118     ; 3.879      ;
; 36.735 ; A4299:I_4299|BUFFER_IN[236] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[21]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; -0.118     ; 3.879      ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                  ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node           ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 38.707 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.387      ;
; 38.727 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.367      ;
; 38.727 ; SCLK_6M4          ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.367      ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'CLK_PLL1'                                                                                               ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 61.367 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.165      ;
; 61.367 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.165      ;
; 61.367 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.165      ;
; 61.367 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.165      ;
; 61.367 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.165      ;
; 61.419 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.113      ;
; 61.419 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.113      ;
; 61.419 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.113      ;
; 61.419 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.113      ;
; 61.419 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.113      ;
; 61.530 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.001      ; 1.003      ;
; 61.550 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.001      ; 0.983      ;
; 61.566 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.966      ;
; 61.566 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.966      ;
; 61.566 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.966      ;
; 61.566 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.966      ;
; 61.566 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.966      ;
; 61.582 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.001      ; 0.951      ;
; 61.602 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.001      ; 0.931      ;
; 61.646 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.886      ;
; 61.646 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.886      ;
; 61.646 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.886      ;
; 61.646 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.886      ;
; 61.646 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.886      ;
; 61.694 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.838      ;
; 61.694 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.838      ;
; 61.694 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.838      ;
; 61.694 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.838      ;
; 61.694 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.838      ;
; 61.729 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.001      ; 0.804      ;
; 61.749 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.001      ; 0.784      ;
; 61.809 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.001      ; 0.724      ;
; 61.829 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.001      ; 0.704      ;
; 61.857 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.001      ; 0.676      ;
; 61.877 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.001      ; 0.656      ;
; 62.141 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.391      ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 61.685 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.847      ;
; 61.697 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.835      ;
; 61.759 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.773      ;
; 61.831 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.701      ;
; 61.990 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.542      ;
; 61.991 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.541      ;
; 61.994 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.538      ;
; 61.996 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.536      ;
; 62.006 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.526      ;
; 62.007 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.525      ;
; 62.011 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.521      ;
; 62.133 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.399      ;
; 62.165 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; CLK_0M5              ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                                                                    ;
+-------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                              ; To Node                                                                                                                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.073 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[191]                                                                          ; A4299:I_4299|BUFFER_IN[192]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.169      ; 0.394      ;
; 0.080 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[201]                                                                          ; A4299:I_4299|BUFFER_IN[202]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.169      ; 0.401      ;
; 0.082 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[207]                                                                          ; A4299:I_4299|BUFFER_IN[208]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.169      ; 0.403      ;
; 0.100 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[221]                                                                          ; A4299:I_4299|BUFFER_IN[222]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.142      ; 0.394      ;
; 0.153 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[174]                                                                          ; A4299:I_4299|BUFFER_IN[175]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.085      ; 0.390      ;
; 0.155 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[173]                                                                          ; A4299:I_4299|BUFFER_IN[174]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.085      ; 0.392      ;
; 0.156 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[0] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg0 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.415      ; 0.709      ;
; 0.159 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[7] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.415      ; 0.712      ;
; 0.160 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[0] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg0 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.411      ; 0.709      ;
; 0.161 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[2] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.415      ; 0.714      ;
; 0.162 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[3] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.415      ; 0.715      ;
; 0.163 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[7] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.411      ; 0.712      ;
; 0.165 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[2] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.411      ; 0.714      ;
; 0.166 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[3] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.411      ; 0.715      ;
; 0.170 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[1] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.415      ; 0.723      ;
; 0.174 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[1] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.411      ; 0.723      ;
; 0.183 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[4] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.415      ; 0.736      ;
; 0.187 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[4] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.411      ; 0.736      ;
; 0.188 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[222]                                                                          ; A4299:I_4299|BUFFER_IN[223]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.142      ; 0.482      ;
; 0.213 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[5] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.415      ; 0.766      ;
; 0.214 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[198]                                                                          ; A4299:I_4299|BUFFER_IN[199]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.026      ; 0.392      ;
; 0.215 ; A4299:I_4299|INT                                                                                                       ; A4299:I_4299|INT                                                                                                                                          ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; A4299:I_4299|SYNC                                                                                                      ; A4299:I_4299|SYNC                                                                                                                                         ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.367      ;
; 0.217 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[181]                                                                          ; A4299:I_4299|BUFFER_IN[182]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.026      ; 0.395      ;
; 0.217 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[5] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.411      ; 0.766      ;
; 0.220 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[224]                                                                          ; A4299:I_4299|BUFFER_IN[225]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.190      ; 0.562      ;
; 0.229 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[6] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.415      ; 0.782      ;
; 0.233 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[6] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg6 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.411      ; 0.782      ;
; 0.236 ; A4299:I_4299|\CODEC_TRANSMIT:BITCNT[7]                                                                                 ; A4299:I_4299|\CODEC_TRANSMIT:BITCNT[7]                                                                                                                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[92]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[93]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.388      ;
; 0.237 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[94]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[95]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[91]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[92]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.389      ;
; 0.238 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[152]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[153]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[89]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[90]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[242]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[243]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[234]                                                                          ; A4299:I_4299|BUFFER_IN[235]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[223]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[224]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.239 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[147]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[148]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[139]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[140]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[58]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[59]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[57]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[58]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[21]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[22]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[226]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[227]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[193]                                                                          ; A4299:I_4299|BUFFER_IN[194]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[187]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[188]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.240 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[88]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[89]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[26]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[27]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[11]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[12]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[210]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[211]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[233]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[234]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[167]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[168]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[181]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[182]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.241 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[154]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[155]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[153]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[154]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[93]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[94]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[85]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[86]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[82]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[83]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[37]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[38]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[30]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[31]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[22]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[23]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[249]                                                                          ; A4299:I_4299|BUFFER_IN[250]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[250]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[251]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[249]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[250]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[206]                                                                          ; A4299:I_4299|BUFFER_IN[207]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[212]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[213]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[215]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[216]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.242 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[121]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[122]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[38]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[39]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[24]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[25]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[19]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[20]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[250]                                                                          ; A4299:I_4299|BUFFER_IN[251]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[221]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[222]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[239]                                                                          ; A4299:I_4299|BUFFER_IN[240]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[248]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[249]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[216]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[217]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[191]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[192]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[196]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[197]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.243 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[157]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[158]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[36]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[37]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[32]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[33]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[25]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[26]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[248]                                                                          ; A4299:I_4299|BUFFER_IN[249]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[233]                                                                          ; A4299:I_4299|BUFFER_IN[234]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[243]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[244]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[229]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[230]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[184]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[185]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[173]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[174]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[176]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[177]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[165]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[166]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.244 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[155]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[156]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.396      ;
; 0.244 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[78]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[79]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.396      ;
; 0.244 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[28]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[29]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.396      ;
; 0.244 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[17]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[18]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.396      ;
; 0.244 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[252]                                                                          ; A4299:I_4299|BUFFER_IN[253]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.396      ;
; 0.244 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[253]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[254]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.396      ;
; 0.244 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[194]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[195]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.396      ;
; 0.244 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[166]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[167]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.396      ;
; 0.244 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[176]                                                                          ; A4299:I_4299|BUFFER_IN[177]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.001      ; 0.397      ;
; 0.245 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[238]                                                                          ; A4299:I_4299|BUFFER_IN[239]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.397      ;
; 0.245 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[235]                                                                          ; A4299:I_4299|BUFFER_IN[236]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.397      ;
+-------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                              ;
+-------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                              ; To Node                                                                                ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|RETRY                                 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|RETRY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP                 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST               ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.IDLE                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.IDLE                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|BUS_CTRL_STATE.DATA_C1C4              ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|BUS_CTRL_STATE.DATA_C1C4              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[2]                  ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[2]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[0]                  ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[0]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[1]                  ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[1]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP          ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                          ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED              ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|ALU_BSY                                            ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|ALU_BSY                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|LOOP_BSY_I                   ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|LOOP_BSY_I                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                       ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                      ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0          ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE            ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RESET           ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|READ_CYCLE                                 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|READ_CYCLE                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_INT             ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_INT             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                   ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                   ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|EXEC_WB_STATE.IDLE                         ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|EXEC_WB_STATE.IDLE                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_PNTR[0]                ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_PNTR[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRACE                   ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRACE                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                     ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OW_RDY                                     ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OW_RDY                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[32]              ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[32]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|WRITE_CYCLE                                ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|WRITE_CYCLE                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                              ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \SLOW_CPU:TMP[2]                                                                       ; \SLOW_CPU:TMP[2]                                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \SLOW_CPU:TMP[1]                                                                       ; \SLOW_CPU:TMP[1]                                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \SLOW_CPU:TMP[0]                                                                       ; \SLOW_CPU:TMP[0]                                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]            ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]            ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEM_FIRST_RD                             ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEM_FIRST_RD                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT                ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                     ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO                 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR                    ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL                 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT                  ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV                   ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET                   ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_VALID                            ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_VALID                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL                    ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXT~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXT~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR            ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                       ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVEA~reg0                ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVEA~reg0                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_2[3]                 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_2[3]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_1[3]                 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_1[3]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPA~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPA~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                            ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                            ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[1]               ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[1]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.PEA~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.PEA~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                         ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|FETCH_STATE.FETCH_IDATA_B2                 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|FETCH_STATE.FETCH_IDATA_B2                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PREFETCH_BUFFERS:RDY_VAR             ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PREFETCH_BUFFERS:RDY_VAR             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RTE             ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RTE             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NBCD~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NBCD~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|\STACK_CTRL:STACK_POS_VAR[0] ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|\STACK_CTRL:STACK_POS_VAR[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST               ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST               ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2              ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2              ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1              ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|ADR_LATCH[3]                                                         ; WF68K10_TOP:I_CPU|ADR_LATCH[3]                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|ADR_LATCH[2]                                                         ; WF68K10_TOP:I_CPU|ADR_LATCH[2]                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
+-------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                                                                              ;
+-------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                              ; To Node                                                                                ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|RETRY                                 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|RETRY                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP                 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST               ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.IDLE                     ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.IDLE                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|BUS_CTRL_STATE.DATA_C1C4              ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|BUS_CTRL_STATE.DATA_C1C4              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[2]                  ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[2]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[0]                  ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[0]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[1]                  ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[1]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP          ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                          ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED              ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|ALU_BSY                                            ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|ALU_BSY                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|LOOP_BSY_I                   ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|LOOP_BSY_I                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                       ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                      ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0          ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE            ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RESET           ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|READ_CYCLE                                 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|READ_CYCLE                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_INT             ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_INT             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                   ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                   ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|EXEC_WB_STATE.IDLE                         ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|EXEC_WB_STATE.IDLE                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_PNTR[0]                ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_PNTR[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRACE                   ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRACE                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                     ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OW_RDY                                     ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OW_RDY                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[32]              ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[32]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|WRITE_CYCLE                                ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|WRITE_CYCLE                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                              ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \SLOW_CPU:TMP[2]                                                                       ; \SLOW_CPU:TMP[2]                                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \SLOW_CPU:TMP[1]                                                                       ; \SLOW_CPU:TMP[1]                                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \SLOW_CPU:TMP[0]                                                                       ; \SLOW_CPU:TMP[0]                                                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]            ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]            ; WF68K10_TOP:I_CPU|WF68K10_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEM_FIRST_RD                             ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEM_FIRST_RD                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT                ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                     ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO                 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR                    ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL                 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT                  ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV                   ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET                   ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_VALID                            ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|DATA_VALID                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL                    ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXT~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXT~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                           ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                          ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR            ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                       ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVEA~reg0                ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVEA~reg0                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_2[3]                 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_2[3]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_1[3]                 ; WF68K10_TOP:I_CPU|WF68K10_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_1[3]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPA~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPA~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                            ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                            ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[1]               ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[1]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.PEA~reg0                  ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.PEA~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                         ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|FETCH_STATE.FETCH_IDATA_B2                 ; WF68K10_TOP:I_CPU|WF68K10_CONTROL:I_CONTROL|FETCH_STATE.FETCH_IDATA_B2                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PREFETCH_BUFFERS:RDY_VAR             ; WF68K10_TOP:I_CPU|WF68K10_BUS_INTERFACE:I_BUS_IF|\PREFETCH_BUFFERS:RDY_VAR             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RTE             ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_RTE             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NBCD~reg0                 ; WF68K10_TOP:I_CPU|WF68K10_OPCODE_DECODER:I_OPCODE_DECODER|OP.NBCD~reg0                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|\STACK_CTRL:STACK_POS_VAR[0] ; WF68K10_TOP:I_CPU|WF68K10_EXCEPTION_HANDLER:I_EXC_HANDLER|\STACK_CTRL:STACK_POS_VAR[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST               ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST               ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2              ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2              ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1              ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|ADR_LATCH[3]                                                         ; WF68K10_TOP:I_CPU|ADR_LATCH[3]                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K10_TOP:I_CPU|ADR_LATCH[2]                                                         ; WF68K10_TOP:I_CPU|ADR_LATCH[2]                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
+-------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.222 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.002        ; 0.022      ; 0.398      ;
; 0.225 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.002        ; 0.022      ; 0.401      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[59]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[60]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[43]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[44]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[28]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[13]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[14]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[4][1]                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[3][1]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[59]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[60]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[43]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[44]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[28]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[5]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.222 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.002        ; 0.022      ; 0.398      ;
; 0.225 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.002        ; 0.022      ; 0.401      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[59]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[60]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[43]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[44]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[28]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[13]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[14]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[4][1]                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[3][1]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[59]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[60]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[43]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[44]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[28]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.389      ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                                                                                                        ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                     ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[8]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[8]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                                                                                                        ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                     ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[8]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[8]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_LO                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                  ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node           ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; SCLK_6M4          ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.235 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.387      ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                          ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node             ; To Node               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.354 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.506      ;
; 0.358 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.510      ;
; 0.365 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.517      ;
; 0.493 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.645      ;
; 0.505 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.657      ;
; 0.619 ; CLK_24576             ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.771      ;
; 0.796 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.948      ;
; 0.836 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.988      ;
; 0.848 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.000      ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; CLK_0M5              ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.247 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.399      ;
; 0.369 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.521      ;
; 0.373 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.525      ;
; 0.374 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.526      ;
; 0.384 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.536      ;
; 0.386 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.538      ;
; 0.389 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.541      ;
; 0.390 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.542      ;
; 0.549 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.701      ;
; 0.621 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.773      ;
; 0.683 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.835      ;
; 0.695 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.847      ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'CLK_PLL1'                                                                                               ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 0.239 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.391      ;
; 0.366 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.518      ;
; 0.366 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.518      ;
; 0.378 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.530      ;
; 0.378 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.530      ;
; 0.378 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.530      ;
; 0.503 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.001      ; 0.656      ;
; 0.504 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.656      ;
; 0.518 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.670      ;
; 0.518 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.670      ;
; 0.518 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.670      ;
; 0.523 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.001      ; 0.676      ;
; 0.539 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.691      ;
; 0.551 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.001      ; 0.704      ;
; 0.553 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.705      ;
; 0.553 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.705      ;
; 0.571 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.001      ; 0.724      ;
; 0.574 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.726      ;
; 0.588 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.740      ;
; 0.623 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.775      ;
; 0.631 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.001      ; 0.784      ;
; 0.651 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.001      ; 0.804      ;
; 0.686 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.838      ;
; 0.686 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.838      ;
; 0.686 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.838      ;
; 0.734 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.886      ;
; 0.734 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.886      ;
; 0.734 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.886      ;
; 0.734 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.886      ;
; 0.778 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.001      ; 0.931      ;
; 0.798 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.001      ; 0.951      ;
; 0.814 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.966      ;
; 0.814 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.966      ;
; 0.830 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.001      ; 0.983      ;
; 0.850 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.001      ; 1.003      ;
; 1.013 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.165      ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                ;
+--------+--------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                        ; To Node                                                           ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 26.724 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.006      ; 4.564      ;
; 26.724 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.006      ; 4.564      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 4.562      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.008     ; 4.549      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.008     ; 4.549      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 4.562      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.008     ; 4.549      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.008     ; 4.549      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 4.571      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.026      ; 4.582      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 4.592      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.027      ; 4.583      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.026      ; 4.582      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 4.592      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.027      ; 4.583      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.565      ;
; 26.735 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.006      ; 4.553      ;
; 26.735 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.006      ; 4.553      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 4.560      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.005      ; 4.551      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.008     ; 4.538      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.008     ; 4.538      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 4.560      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 4.560      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.561      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.561      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.561      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.561      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.014      ; 4.560      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.561      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.015      ; 4.561      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.020      ; 4.566      ;
+--------+--------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                ;
+--------+--------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                        ; To Node                                                           ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 26.724 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.006      ; 4.564      ;
; 26.724 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.006      ; 4.564      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 4.562      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.008     ; 4.549      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.008     ; 4.549      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 4.562      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.008     ; 4.549      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.008     ; 4.549      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 4.571      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.572      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.577      ;
; 26.725 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 4.571      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.026      ; 4.582      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 4.592      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.027      ; 4.583      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.026      ; 4.582      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 4.592      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.027      ; 4.583      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.565      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.029      ; 4.585      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.565      ;
; 26.735 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.006      ; 4.553      ;
; 26.735 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.006      ; 4.553      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 4.560      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.005      ; 4.551      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.008     ; 4.538      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.008     ; 4.538      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 4.560      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 4.560      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.561      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.561      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.561      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.561      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.014      ; 4.560      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.561      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.015      ; 4.561      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.566      ;
; 26.736 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ   ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.020      ; 4.566      ;
+--------+--------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                        ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                        ; To Node                                                                                   ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[1]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.040      ; 4.596      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[1]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.003      ; 4.559      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[1]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.040      ; 4.596      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[1]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.003      ; 4.559      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[22]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.034      ; 4.589      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[23]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.034      ; 4.589      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[20]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.034      ; 4.589      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[14]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[15]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[12]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[19]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.034      ; 4.589      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[18]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.040      ; 4.595      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[21]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.040      ; 4.595      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.046      ; 4.601      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.040      ; 4.595      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[11]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[10]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[17]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[16]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[8]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[5]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[22]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.039      ; 4.594      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[20]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.046      ; 4.601      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[9]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.040      ; 4.595      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[6]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[14]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.046      ; 4.601      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[15]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[7]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.040      ; 4.595      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.040      ; 4.595      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[12]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[19]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[18]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[9]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[8]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[14]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[15]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[11]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[10]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[10]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[11]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[12]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[13]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[17]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[16]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[18]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[19]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[21]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[20]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[23]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[22]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.044      ; 4.599      ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                        ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                        ; To Node                                                                                   ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[1]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.040      ; 4.596      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[1]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.003      ; 4.559      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[1]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.040      ; 4.596      ;
; 26.726 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[1]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.003      ; 4.559      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[22]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.034      ; 4.589      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[23]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.034      ; 4.589      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[20]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.034      ; 4.589      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[14]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[15]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[12]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[19]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.034      ; 4.589      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[18]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.040      ; 4.595      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[21]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.040      ; 4.595      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.046      ; 4.601      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.040      ; 4.595      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[11]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[10]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[17]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[16]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[8]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[5]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[22]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.039      ; 4.594      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[20]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.046      ; 4.601      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[9]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.040      ; 4.595      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[6]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[14]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.046      ; 4.601      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[15]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[7]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.040      ; 4.595      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.040      ; 4.595      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[12]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[19]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[18]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 4.597      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.045      ; 4.600      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[9]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[8]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[14]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[15]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[11]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.043      ; 4.598      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[10]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[10]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[11]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[12]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[13]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[17]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[16]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[18]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[19]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[21]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[20]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[23]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[22]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.041      ; 4.596      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_ADR[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
; 26.727 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.044      ; 4.599      ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                           ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                           ; To Node                                                                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 80.188 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|dffe4 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0 ; CODEC_SCLK   ; CODEC_SCLK  ; 81.400       ; 0.170      ; 1.381      ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                         ;
+-------+------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                      ; To Node                                                                      ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 1.063 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.257      ;
; 1.063 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.257      ;
; 1.063 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.257      ;
; 1.063 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.257      ;
; 1.063 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.257      ;
; 1.063 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.257      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.042      ; 1.372      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[12]                                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 3.008      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[9]                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 3.008      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[15]                                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 3.008      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[14]                                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.020     ; 3.008      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.025     ; 3.003      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.025     ; 3.003      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.025     ; 3.003      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.024     ; 3.004      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.024     ; 3.004      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[1][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.036     ; 2.992      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[1][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.036     ; 2.992      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.024     ; 3.004      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.024     ; 3.004      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.024     ; 3.004      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[1][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.036     ; 2.992      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.036     ; 2.992      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.036     ; 2.992      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.036     ; 2.992      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.024     ; 3.004      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.036     ; 2.992      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.012     ; 3.016      ;
+-------+------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                         ;
+-------+------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                      ; To Node                                                                      ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 1.063 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.257      ;
; 1.063 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.257      ;
; 1.063 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.257      ;
; 1.063 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.257      ;
; 1.063 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.257      ;
; 1.063 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.257      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 1.178 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.042      ; 1.372      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[12]                                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 3.008      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[9]                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 3.008      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[15]                                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 3.008      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[14]                                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.020     ; 3.008      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.025     ; 3.003      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.025     ; 3.003      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.025     ; 3.003      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.024     ; 3.004      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.024     ; 3.004      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[1][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.036     ; 2.992      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[1][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.036     ; 2.992      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.024     ; 3.004      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.024     ; 3.004      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.024     ; 3.004      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[1][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.036     ; 2.992      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.036     ; 2.992      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 2.998      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.036     ; 2.992      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.036     ; 2.992      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 2.999      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 3.016      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.024     ; 3.004      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.036     ; 2.992      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.017     ; 3.011      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.023     ; 3.005      ;
; 2.876 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.012     ; 3.016      ;
+-------+------------------------------------------------+------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                           ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                           ; To Node                                                                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 1.073 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|dffe4 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.170      ; 1.381      ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                  ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                                ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.250      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 1.359      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 1.359      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 1.359      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 1.359      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 1.359      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 1.359      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 1.359      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.027      ; 1.359      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.026      ; 1.361      ;
; 1.185 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 1.351      ;
; 1.185 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 1.351      ;
; 1.185 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 1.351      ;
; 1.185 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.014      ; 1.351      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.020      ; 1.427      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.021      ; 1.434      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.021      ; 1.434      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.021      ; 1.434      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.021      ; 1.434      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.021      ; 1.434      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.021      ; 1.434      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.021      ; 1.434      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.021      ; 1.434      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 1.626      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.009     ; 1.627      ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                  ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                                ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.250      ;
; 1.088 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.250      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 1.359      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 1.359      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 1.359      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 1.359      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 1.359      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 1.359      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 1.359      ;
; 1.180 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.027      ; 1.359      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.361      ;
; 1.183 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.026      ; 1.361      ;
; 1.185 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 1.351      ;
; 1.185 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 1.351      ;
; 1.185 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 1.351      ;
; 1.185 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.014      ; 1.351      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.020      ; 1.427      ;
; 1.255 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.020      ; 1.427      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.021      ; 1.434      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.021      ; 1.434      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.021      ; 1.434      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.021      ; 1.434      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.021      ; 1.434      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.021      ; 1.434      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.021      ; 1.434      ;
; 1.261 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.021      ; 1.434      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.474 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 1.626      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.644      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
; 1.484 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.009     ; 1.627      ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                     ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg7  ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                                                                                     ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg7  ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 11.695 ; 12.695       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576                                           ;
; 11.695 ; 12.695       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576                                           ;
; 11.695 ; 12.695       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]                               ;
; 11.695 ; 12.695       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]                               ;
; 11.695 ; 12.695       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]                               ;
; 11.695 ; 12.695       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]                               ;
; 11.695 ; 12.695       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]                               ;
; 11.695 ; 12.695       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]                               ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576|clk                                       ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576|clk                                       ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|inclk[0] ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|inclk[0] ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|outclk   ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|outclk   ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                                                 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4                                            ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4                                            ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]                                   ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]                                   ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|inclk[0] ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|inclk[0] ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|outclk   ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|outclk   ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4|clk                                        ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4|clk                                        ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]|clk                               ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]|clk                               ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                   ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                   ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------+
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]               ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]               ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]               ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]               ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------+
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]               ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]               ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]               ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]               ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K10_TOP:I_CPU|WF68K10_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CLK_PLL1'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 60.120 ; 62.500       ; 2.380          ; Port Rate        ; CLK_PLL1 ; Rise       ; CLK_PLL1                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5                                             ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5                                             ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CLK_PLL2'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 60.120 ; 62.500       ; 2.380          ; Port Rate        ; CLK_PLL2 ; Rise       ; CLK_PLL2                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CRT_PIN4_CLK1'                                                                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock         ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 60.120 ; 62.500       ; 2.380          ; Port Rate        ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1                             ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CODEC_SCLK'                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock      ; Clock Edge ; Target                                                                                                                                                    ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0                    ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0                    ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg0 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg0 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg6 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg6 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_datain_reg0  ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_datain_reg0  ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_memory_reg0  ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_memory_reg0  ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg0 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg0 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[162]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[162]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[163]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[163]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[164]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[164]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[165]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[165]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[166]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[166]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[167]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[167]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[168]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[168]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[169]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[169]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[170]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[170]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[171]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[171]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[172]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[172]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[173]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[173]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[174]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[174]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[175]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[175]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[176]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[176]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[177]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[177]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[178]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[178]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[179]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[179]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[180]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[180]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[181]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[181]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[182]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[182]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[183]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[183]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[184]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[184]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[185]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[185]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[186]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[186]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[187]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[187]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[188]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[188]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[189]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[189]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[190]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[190]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[191]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[191]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[192]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[192]                                                                                                                               ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 0.043  ; 0.043  ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; 5.476  ; 5.476  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; -0.247 ; -0.247 ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; 6.190  ; 6.190  ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; 11.355 ; 11.355 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 3.559  ; 3.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 5.272  ; 5.272  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 4.005  ; 4.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 5.728  ; 5.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 4.821  ; 4.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 5.168  ; 5.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 4.846  ; 4.846  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 5.130  ; 5.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 5.540  ; 5.540  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 5.475  ; 5.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 5.728  ; 5.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 5.545  ; 5.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 7.381  ; 7.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 7.387  ; 7.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 7.661  ; 7.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; 5.618  ; 5.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 15.296 ; 15.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 8.534  ; 8.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 8.087  ; 8.087  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[3]     ; CLK_PLL1      ; 15.296 ; 15.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 12.686 ; 12.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 9.079  ; 9.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 5.703  ; 5.703  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 5.242  ; 5.242  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 7.935  ; 7.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 7.524  ; 7.524  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 7.144  ; 7.144  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 7.844  ; 7.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 6.977  ; 6.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 7.226  ; 7.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 7.896  ; 7.896  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 7.911  ; 7.911  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 7.747  ; 7.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 7.935  ; 7.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 7.380  ; 7.380  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 7.552  ; 7.552  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 7.885  ; 7.885  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 7.315  ; 7.315  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 7.594  ; 7.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 5.825  ; 5.825  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 6.415  ; 6.415  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 4.541  ; 4.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 6.467  ; 6.467  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 12.137 ; 12.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 12.137 ; 12.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 11.839 ; 11.839 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 11.676 ; 11.676 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; 6.384  ; 6.384  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; 2.904  ; 2.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; 5.327  ; 5.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; 7.262  ; 7.262  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; 4.449  ; 4.449  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 4.764  ; 4.764  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 9.580  ; 9.580  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 5.748  ; 5.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 9.515  ; 9.515  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; 4.002  ; 4.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 11.752 ; 11.752 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 8.193  ; 8.193  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 8.120  ; 8.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 7.864  ; 7.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 7.262  ; 7.262  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 7.572  ; 7.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 7.832  ; 7.832  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 7.740  ; 7.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 8.068  ; 8.068  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; 3.324  ; 3.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; 2.052  ; 2.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; 2.335  ; 2.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; 2.637  ; 2.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; 2.677  ; 2.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; 2.125  ; 2.125  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 8.730  ; 8.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 8.291  ; 8.291  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 8.013  ; 8.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 7.903  ; 7.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 8.189  ; 8.189  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 7.493  ; 7.493  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 8.044  ; 8.044  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 7.727  ; 7.727  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 7.851  ; 7.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 8.730  ; 8.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 7.802  ; 7.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 7.851  ; 7.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 8.181  ; 8.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 7.882  ; 7.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 8.401  ; 8.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 8.497  ; 8.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 7.873  ; 7.873  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; 1.408  ; 1.408  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 4.594  ; 4.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 11.796 ; 11.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 6.179  ; 6.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 4.717  ; 4.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 5.052  ; 5.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 4.905  ; 4.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 4.937  ; 4.937  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 4.875  ; 4.875  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 5.052  ; 5.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 4.655  ; 4.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 4.465  ; 4.465  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 4.535  ; 4.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 4.990  ; 4.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 6.062  ; 6.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 5.431  ; 5.431  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 5.673  ; 5.673  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 6.296  ; 6.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 5.213  ; 5.213  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; 6.898  ; 6.898  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; 3.815  ; 3.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; 6.701  ; 6.701  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 10.633 ; 10.633 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; 3.921  ; 3.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; 4.889  ; 4.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; 4.636  ; 4.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; 4.494  ; 4.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; 4.526  ; 4.526  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; 4.636  ; 4.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; 4.632  ; 4.632  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; 4.857  ; 4.857  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; 5.464  ; 5.464  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 5.110  ; 5.110  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 10.879 ; 10.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; 4.315  ; 4.315  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 4.323  ; 4.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 10.705 ; 10.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 3.667  ; 3.667  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 3.719  ; 3.719  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 3.957  ; 3.957  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; 3.868  ; 3.868  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 7.153  ; 7.153  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 6.995  ; 6.995  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 6.956  ; 6.956  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 11.926 ; 11.926 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 7.884  ; 7.884  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 7.437  ; 7.437  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 11.926 ; 11.926 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 8.424  ; 8.424  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 5.053  ; 5.053  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 4.592  ; 4.592  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 7.616  ; 7.616  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 7.136  ; 7.136  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 6.752  ; 6.752  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 7.616  ; 7.616  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 6.469  ; 6.469  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 6.644  ; 6.644  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 7.113  ; 7.113  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 7.206  ; 7.206  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 7.097  ; 7.097  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 7.187  ; 7.187  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 6.515  ; 6.515  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 6.842  ; 6.842  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 7.002  ; 7.002  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 6.372  ; 6.372  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 6.712  ; 6.712  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 4.818  ; 4.818  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 5.441  ; 5.441  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 5.186  ; 5.186  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; 1.786  ; 1.786  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; 1.917  ; 1.917  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; 1.458  ; 1.458  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 11.153 ; 11.153 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 11.153 ; 11.153 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 10.939 ; 10.939 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 10.923 ; 10.923 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; 4.499  ; 4.499  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 3.776  ; 3.776  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 8.797  ; 8.797  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; 4.650  ; 4.650  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 8.732  ; 8.732  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 10.954 ; 10.954 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 7.805  ; 7.805  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 7.372  ; 7.372  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 7.372  ; 7.372  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 6.999  ; 6.999  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.552  ; 6.552  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 6.689  ; 6.689  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 6.889  ; 6.889  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 6.858  ; 6.858  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 7.061  ; 7.061  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 7.228  ; 7.228  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 7.982  ; 7.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 7.903  ; 7.903  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 7.621  ; 7.621  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 7.675  ; 7.675  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 7.681  ; 7.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 6.911  ; 6.911  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 7.261  ; 7.261  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 7.022  ; 7.022  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 7.201  ; 7.201  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 7.982  ; 7.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 6.937  ; 6.937  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 7.141  ; 7.141  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 7.298  ; 7.298  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 6.939  ; 6.939  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 7.519  ; 7.519  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 7.490  ; 7.490  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 6.899  ; 6.899  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 11.040 ; 11.040 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 10.116 ; 10.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 4.485  ; 4.485  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; 4.463  ; 4.463  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 10.353 ; 10.353 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; 11.355 ; 11.355 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 3.559  ; 3.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 5.272  ; 5.272  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 4.005  ; 4.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 5.728  ; 5.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 4.821  ; 4.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 5.168  ; 5.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 4.846  ; 4.846  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 5.130  ; 5.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 5.540  ; 5.540  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 5.475  ; 5.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 5.728  ; 5.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 5.545  ; 5.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 7.381  ; 7.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 7.387  ; 7.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 7.661  ; 7.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; 5.618  ; 5.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 15.296 ; 15.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 8.534  ; 8.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 8.087  ; 8.087  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[3]     ; CRT_PIN4_CLK1 ; 15.296 ; 15.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 12.686 ; 12.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 9.079  ; 9.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 5.703  ; 5.703  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 5.242  ; 5.242  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.935  ; 7.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 7.524  ; 7.524  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 7.144  ; 7.144  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 7.844  ; 7.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 6.977  ; 6.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 7.226  ; 7.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 7.896  ; 7.896  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 7.911  ; 7.911  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.747  ; 7.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 7.935  ; 7.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 7.380  ; 7.380  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 7.552  ; 7.552  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 7.885  ; 7.885  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 7.315  ; 7.315  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 7.594  ; 7.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.825  ; 5.825  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 6.415  ; 6.415  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 4.541  ; 4.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 6.467  ; 6.467  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 12.137 ; 12.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 12.137 ; 12.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 11.839 ; 11.839 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 11.676 ; 11.676 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; 6.384  ; 6.384  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; 2.904  ; 2.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; 5.327  ; 5.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; 7.262  ; 7.262  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; 4.449  ; 4.449  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 4.764  ; 4.764  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 9.580  ; 9.580  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 5.748  ; 5.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 9.515  ; 9.515  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; 4.002  ; 4.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 11.752 ; 11.752 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 8.193  ; 8.193  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 8.120  ; 8.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 7.864  ; 7.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 7.262  ; 7.262  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 7.572  ; 7.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 7.832  ; 7.832  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 7.740  ; 7.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 8.068  ; 8.068  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; 3.324  ; 3.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; 2.052  ; 2.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; 2.335  ; 2.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; 2.637  ; 2.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; 2.677  ; 2.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; 2.125  ; 2.125  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 8.730  ; 8.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 8.291  ; 8.291  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 8.013  ; 8.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 7.903  ; 7.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 8.189  ; 8.189  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 7.493  ; 7.493  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 8.044  ; 8.044  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 7.727  ; 7.727  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 7.851  ; 7.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 8.730  ; 8.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 7.802  ; 7.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 7.851  ; 7.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 8.181  ; 8.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 7.882  ; 7.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 8.401  ; 8.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 8.497  ; 8.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 7.873  ; 7.873  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; 1.408  ; 1.408  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 4.594  ; 4.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 11.796 ; 11.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 6.179  ; 6.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 4.717  ; 4.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 5.052  ; 5.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 4.905  ; 4.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 4.937  ; 4.937  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 4.875  ; 4.875  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 5.052  ; 5.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 4.655  ; 4.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 4.465  ; 4.465  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 4.535  ; 4.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 4.990  ; 4.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 6.062  ; 6.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 5.431  ; 5.431  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 5.673  ; 5.673  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 6.296  ; 6.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 5.213  ; 5.213  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; 6.898  ; 6.898  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; 3.815  ; 3.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; 6.701  ; 6.701  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 10.633 ; 10.633 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; 3.921  ; 3.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; 4.889  ; 4.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; 4.636  ; 4.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; 4.494  ; 4.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; 4.526  ; 4.526  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; 4.636  ; 4.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; 4.632  ; 4.632  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; 4.857  ; 4.857  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; 5.464  ; 5.464  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 5.110  ; 5.110  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 10.879 ; 10.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; 4.315  ; 4.315  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 4.323  ; 4.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 10.705 ; 10.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 3.667  ; 3.667  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 3.719  ; 3.719  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 3.957  ; 3.957  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; 3.868  ; 3.868  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 7.153  ; 7.153  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 6.995  ; 6.995  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 6.956  ; 6.956  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 11.926 ; 11.926 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 7.884  ; 7.884  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 7.437  ; 7.437  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 11.926 ; 11.926 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 8.424  ; 8.424  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 5.053  ; 5.053  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 4.592  ; 4.592  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.616  ; 7.616  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 7.136  ; 7.136  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 6.752  ; 6.752  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 7.616  ; 7.616  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 6.469  ; 6.469  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 6.644  ; 6.644  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 7.113  ; 7.113  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 7.206  ; 7.206  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.097  ; 7.097  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 7.187  ; 7.187  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 6.515  ; 6.515  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 6.842  ; 6.842  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 7.002  ; 7.002  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 6.372  ; 6.372  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.712  ; 6.712  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 4.818  ; 4.818  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.441  ; 5.441  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 5.186  ; 5.186  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; 1.786  ; 1.786  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; 1.917  ; 1.917  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; 1.458  ; 1.458  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 11.153 ; 11.153 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 11.153 ; 11.153 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 10.939 ; 10.939 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 10.923 ; 10.923 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; 4.499  ; 4.499  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 3.776  ; 3.776  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 8.797  ; 8.797  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; 4.650  ; 4.650  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 8.732  ; 8.732  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 10.954 ; 10.954 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 7.805  ; 7.805  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 7.372  ; 7.372  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 7.372  ; 7.372  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 6.999  ; 6.999  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.552  ; 6.552  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 6.689  ; 6.689  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 6.889  ; 6.889  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 6.858  ; 6.858  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 7.061  ; 7.061  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 7.228  ; 7.228  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 7.982  ; 7.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 7.903  ; 7.903  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 7.621  ; 7.621  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 7.675  ; 7.675  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 7.681  ; 7.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 6.911  ; 6.911  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 7.261  ; 7.261  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 7.022  ; 7.022  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 7.201  ; 7.201  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 7.982  ; 7.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 6.937  ; 6.937  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 7.141  ; 7.141  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 7.298  ; 7.298  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 6.939  ; 6.939  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 7.519  ; 7.519  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 7.490  ; 7.490  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 6.899  ; 6.899  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 11.040 ; 11.040 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 10.116 ; 10.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 4.485  ; 4.485  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; 4.463  ; 4.463  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 10.353 ; 10.353 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; 10.567 ; 10.567 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; 6.813  ; 6.813  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; 6.926  ; 6.926  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; 6.864  ; 6.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 11.977 ; 11.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; 7.784  ; 7.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; 7.337  ; 7.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; 5.536  ; 5.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; 11.977 ; 11.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; 8.322  ; 8.322  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; 4.953  ; 4.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 4.492  ; 4.492  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 7.276  ; 7.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 7.063  ; 7.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 6.683  ; 6.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 7.276  ; 7.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 6.355  ; 6.355  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 6.519  ; 6.519  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 7.085  ; 7.085  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 7.114  ; 7.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 6.997  ; 6.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 7.238  ; 7.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; 5.679  ; 5.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 11.163 ; 11.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 11.163 ; 11.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 10.990 ; 10.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 10.974 ; 10.974 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; 8.769  ; 8.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; 8.704  ; 8.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 10.926 ; 10.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; 7.732  ; 7.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; 7.423  ; 7.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; 7.423  ; 7.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 8.033  ; 8.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 7.830  ; 7.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 7.552  ; 7.552  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 7.335  ; 7.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 7.567  ; 7.567  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 6.786  ; 6.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 7.233  ; 7.233  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 6.930  ; 6.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 7.101  ; 7.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 8.033  ; 8.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 5.682  ; 5.682  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 5.583  ; 5.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 5.829  ; 5.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 6.139  ; 6.139  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 6.414  ; 6.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 6.442  ; 6.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 6.602  ; 6.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 11.091 ; 11.091 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 10.043 ; 10.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 10.215 ; 10.215 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 6.372  ; 6.372  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 8.061  ; 8.061  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; 8.061  ; 8.061  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 6.439  ; 6.439  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 6.439  ; 6.439  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 6.276  ; 6.276  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 6.256  ; 6.256  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 6.134  ; 6.134  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 6.656  ; 6.656  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; 10.567 ; 10.567 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 6.813  ; 6.813  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 6.926  ; 6.926  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 6.864  ; 6.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 11.977 ; 11.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 7.784  ; 7.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 7.337  ; 7.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; 5.536  ; 5.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 11.977 ; 11.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 8.322  ; 8.322  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 4.953  ; 4.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 4.492  ; 4.492  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.276  ; 7.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 7.063  ; 7.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 6.683  ; 6.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 7.276  ; 7.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 6.355  ; 6.355  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 6.519  ; 6.519  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 7.085  ; 7.085  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 7.114  ; 7.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.997  ; 6.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 7.238  ; 7.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 5.679  ; 5.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 11.163 ; 11.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 11.163 ; 11.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 10.990 ; 10.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 10.974 ; 10.974 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 8.769  ; 8.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 8.704  ; 8.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 10.926 ; 10.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 7.732  ; 7.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 7.423  ; 7.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 7.423  ; 7.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 8.033  ; 8.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 7.830  ; 7.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 7.552  ; 7.552  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 7.335  ; 7.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 7.567  ; 7.567  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 6.786  ; 6.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 7.233  ; 7.233  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 6.930  ; 6.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 7.101  ; 7.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 8.033  ; 8.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 5.682  ; 5.682  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 5.583  ; 5.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 5.829  ; 5.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 6.139  ; 6.139  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 6.414  ; 6.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 6.442  ; 6.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 6.602  ; 6.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 11.091 ; 11.091 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 10.043 ; 10.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 10.215 ; 10.215 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 6.372  ; 6.372  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 8.061  ; 8.061  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 8.061  ; 8.061  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 6.439  ; 6.439  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 6.439  ; 6.439  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 6.276  ; 6.276  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 6.256  ; 6.256  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 6.134  ; 6.134  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 6.656  ; 6.656  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; 10.397 ; 10.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; 6.186  ; 6.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; 6.168  ; 6.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; 6.225  ; 6.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; 11.825 ; 11.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; 7.152  ; 7.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; 6.705  ; 6.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[5]     ; CLK_PLL1      ; 11.825 ; 11.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; 8.456  ; 8.456  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; 4.321  ; 4.321  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 3.860  ; 3.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; 7.277  ; 7.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 6.295  ; 6.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 5.925  ; 5.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 6.649  ; 6.649  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 5.742  ; 5.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 5.895  ; 5.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 6.476  ; 6.476  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 6.475  ; 6.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 6.365  ; 6.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 7.086  ; 7.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 6.135  ; 6.135  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 6.937  ; 6.937  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 7.277  ; 7.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 6.561  ; 6.561  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 6.864  ; 6.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 4.365  ; 4.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 4.849  ; 4.849  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; 11.011 ; 11.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; 11.011 ; 11.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; 10.838 ; 10.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; 10.822 ; 10.822 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; 8.160  ; 8.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; 8.095  ; 8.095  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; 10.709 ; 10.709 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; 6.964  ; 6.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 8.052  ; 8.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; 7.271  ; 7.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; 6.619  ; 6.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.647  ; 6.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 8.041  ; 8.041  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 7.693  ; 7.693  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 8.052  ; 8.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 7.717  ; 7.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; 7.194  ; 7.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 7.881  ; 7.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 7.062  ; 7.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 6.794  ; 6.794  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 6.708  ; 6.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 6.954  ; 6.954  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 6.162  ; 6.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 6.624  ; 6.624  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 6.291  ; 6.291  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 6.469  ; 6.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 7.881  ; 7.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 6.557  ; 6.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 7.236  ; 7.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 7.573  ; 7.573  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 7.128  ; 7.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 7.671  ; 7.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 7.306  ; 7.306  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 6.865  ; 6.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; 10.939 ; 10.939 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; 9.483  ; 9.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; 9.857  ; 9.857  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; 10.397 ; 10.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 6.186  ; 6.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 6.168  ; 6.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 6.225  ; 6.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 11.825 ; 11.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 7.152  ; 7.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 6.705  ; 6.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 11.825 ; 11.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 8.456  ; 8.456  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 4.321  ; 4.321  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 3.860  ; 3.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.277  ; 7.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 6.295  ; 6.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 5.925  ; 5.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 6.649  ; 6.649  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 5.742  ; 5.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 5.895  ; 5.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.476  ; 6.476  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.475  ; 6.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.365  ; 6.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 7.086  ; 7.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 6.135  ; 6.135  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 6.937  ; 6.937  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 7.277  ; 7.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 6.561  ; 6.561  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.864  ; 6.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 4.365  ; 4.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 4.849  ; 4.849  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 11.011 ; 11.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 11.011 ; 11.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 10.838 ; 10.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 10.822 ; 10.822 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 8.160  ; 8.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 8.095  ; 8.095  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 10.709 ; 10.709 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 6.964  ; 6.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 8.052  ; 8.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 7.271  ; 7.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 6.619  ; 6.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.647  ; 6.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 8.041  ; 8.041  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 7.693  ; 7.693  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 8.052  ; 8.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 7.717  ; 7.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 7.194  ; 7.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 7.881  ; 7.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 7.062  ; 7.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 6.794  ; 6.794  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 6.708  ; 6.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 6.954  ; 6.954  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 6.162  ; 6.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 6.624  ; 6.624  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 6.291  ; 6.291  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 6.469  ; 6.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 7.881  ; 7.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 6.557  ; 6.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 7.236  ; 7.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 7.573  ; 7.573  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 7.128  ; 7.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 7.671  ; 7.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 7.306  ; 7.306  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 6.865  ; 6.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 10.939 ; 10.939 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 9.483  ; 9.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 9.857  ; 9.857  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 0.078  ; 0.078  ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; -5.044 ; -5.044 ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; 0.367  ; 0.367  ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; -5.366 ; -5.366 ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; -3.324 ; -3.324 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -3.439 ; -3.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -3.686 ; -3.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -3.885 ; -3.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; -3.618 ; -3.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; -3.618 ; -3.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; -3.652 ; -3.652 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; -3.891 ; -3.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; -3.659 ; -3.659 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; -3.762 ; -3.762 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; -3.801 ; -3.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; -3.870 ; -3.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; -3.760 ; -3.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -3.535 ; -3.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -3.406 ; -3.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -3.968 ; -3.968 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; -4.295 ; -4.295 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.183 ; -4.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -5.406 ; -5.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -5.036 ; -5.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[3]     ; CLK_PLL1      ; -4.183 ; -4.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -6.128 ; -6.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -5.249 ; -5.249 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -2.652 ; -2.652 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -2.191 ; -2.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -3.590 ; -3.590 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -3.937 ; -3.937 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -3.920 ; -3.920 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -3.747 ; -3.747 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -3.904 ; -3.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -3.911 ; -3.911 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -3.838 ; -3.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -3.877 ; -3.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -4.174 ; -4.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -3.590 ; -3.590 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -4.209 ; -4.209 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -4.019 ; -4.019 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -4.630 ; -4.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.829 ; -4.829 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -4.454 ; -4.454 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -3.837 ; -3.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -4.300 ; -4.300 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; -4.421 ; -4.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -3.861 ; -3.861 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -4.992 ; -4.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -4.992 ; -4.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -4.997 ; -4.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -4.992 ; -4.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; -4.604 ; -4.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; -1.634 ; -1.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; -4.258 ; -4.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; -4.782 ; -4.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; -3.727 ; -3.727 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -3.913 ; -3.913 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -5.361 ; -5.361 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; -3.991 ; -3.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -5.296 ; -5.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; -3.882 ; -3.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -3.809 ; -3.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -4.488 ; -4.488 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -5.917 ; -5.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.943 ; -6.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.685 ; -6.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -5.917 ; -5.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.156 ; -6.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -6.290 ; -6.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -6.476 ; -6.476 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -6.573 ; -6.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.916 ; -6.916 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; -3.204 ; -3.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; -1.528 ; -1.528 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; -1.811 ; -1.811 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; -2.113 ; -2.113 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; -2.207 ; -2.207 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; -1.801 ; -1.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.901 ; -3.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -4.027 ; -4.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.969 ; -3.969 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -4.386 ; -4.386 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -4.401 ; -4.401 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -4.244 ; -4.244 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -4.630 ; -4.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -4.746 ; -4.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -4.088 ; -4.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -4.285 ; -4.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -4.143 ; -4.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -4.002 ; -4.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -4.127 ; -4.127 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -4.055 ; -4.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -3.901 ; -3.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -3.915 ; -3.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; -1.288 ; -1.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; -4.474 ; -4.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -3.521 ; -3.521 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; -4.499 ; -4.499 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; -3.908 ; -3.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; -3.683 ; -3.683 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; -3.696 ; -3.696 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; -3.885 ; -3.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; -3.665 ; -3.665 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; -3.797 ; -3.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; -3.666 ; -3.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; -3.444 ; -3.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; -3.928 ; -3.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; -3.518 ; -3.518 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; -4.038 ; -4.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; -3.946 ; -3.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; -3.904 ; -3.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; -4.107 ; -4.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; -3.575 ; -3.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; -4.541 ; -4.541 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -4.527 ; -4.527 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; -3.795 ; -3.795 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; -4.761 ; -4.761 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; -3.774 ; -3.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; -3.774 ; -3.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; -3.776 ; -3.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; -4.050 ; -4.050 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; -4.392 ; -4.392 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; -4.731 ; -4.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; -5.336 ; -5.336 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -4.891 ; -4.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -4.661 ; -4.661 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; -4.192 ; -4.192 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; -3.780 ; -3.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; -4.886 ; -4.886 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -3.547 ; -3.547 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -3.599 ; -3.599 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -3.837 ; -3.837 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; -3.748 ; -3.748 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -6.641 ; -6.641 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -6.518 ; -6.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -6.585 ; -6.585 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.927 ; -4.927 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.584 ; -7.584 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -7.137 ; -7.137 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -5.957 ; -5.957 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -4.927 ; -4.927 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -4.753 ; -4.753 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -4.292 ; -4.292 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -4.269 ; -4.269 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -4.372 ; -4.372 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -4.628 ; -4.628 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -4.344 ; -4.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -4.269 ; -4.269 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -4.560 ; -4.560 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -4.760 ; -4.760 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -4.999 ; -4.999 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -5.371 ; -5.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -4.546 ; -4.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -4.291 ; -4.291 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -4.297 ; -4.297 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -4.828 ; -4.828 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.945 ; -4.945 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -4.606 ; -4.606 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -4.350 ; -4.350 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -4.990 ; -4.990 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -4.936 ; -4.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; -1.528 ; -1.528 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; -1.474 ; -1.474 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; -1.268 ; -1.268 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -4.770 ; -4.770 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -4.953 ; -4.953 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -4.790 ; -4.790 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -4.770 ; -4.770 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; -4.379 ; -4.379 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -3.656 ; -3.656 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -8.486 ; -8.486 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; -4.530 ; -4.530 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -8.421 ; -8.421 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -4.559 ; -4.559 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -7.459 ; -7.459 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -6.195 ; -6.195 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.908 ; -6.908 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.767 ; -6.767 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.195 ; -6.195 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.354 ; -6.354 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -6.406 ; -6.406 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -6.628 ; -6.628 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -6.593 ; -6.593 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.777 ; -6.777 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -6.448 ; -6.448 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -7.557 ; -7.557 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -7.144 ; -7.144 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -7.163 ; -7.163 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -7.291 ; -7.291 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -6.655 ; -6.655 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -6.950 ; -6.950 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -6.651 ; -6.651 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -6.901 ; -6.901 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -7.518 ; -7.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -6.705 ; -6.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -6.784 ; -6.784 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -6.963 ; -6.963 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -6.456 ; -6.456 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -7.289 ; -7.289 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -7.022 ; -7.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -6.448 ; -6.448 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -4.668 ; -4.668 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -5.696 ; -5.696 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -4.365 ; -4.365 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; -4.343 ; -4.343 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -5.587 ; -5.587 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; -3.324 ; -3.324 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -3.439 ; -3.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -3.686 ; -3.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -3.885 ; -3.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -3.618 ; -3.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -3.618 ; -3.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -3.652 ; -3.652 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -3.891 ; -3.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -3.659 ; -3.659 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -3.762 ; -3.762 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -3.801 ; -3.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -3.870 ; -3.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -3.760 ; -3.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -3.535 ; -3.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -3.406 ; -3.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -3.968 ; -3.968 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; -4.295 ; -4.295 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.183 ; -4.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -5.406 ; -5.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -5.036 ; -5.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[3]     ; CRT_PIN4_CLK1 ; -4.183 ; -4.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -6.128 ; -6.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -5.249 ; -5.249 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -2.652 ; -2.652 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -2.191 ; -2.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -3.590 ; -3.590 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -3.937 ; -3.937 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -3.920 ; -3.920 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -3.747 ; -3.747 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -3.904 ; -3.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -3.911 ; -3.911 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -3.838 ; -3.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -3.877 ; -3.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.174 ; -4.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -3.590 ; -3.590 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -4.209 ; -4.209 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.019 ; -4.019 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.630 ; -4.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.829 ; -4.829 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.454 ; -4.454 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -3.837 ; -3.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.300 ; -4.300 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; -4.421 ; -4.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -3.861 ; -3.861 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -4.992 ; -4.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -4.992 ; -4.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -4.997 ; -4.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -4.992 ; -4.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; -4.604 ; -4.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; -1.634 ; -1.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; -4.258 ; -4.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; -4.782 ; -4.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; -3.727 ; -3.727 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -3.913 ; -3.913 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -5.361 ; -5.361 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; -3.991 ; -3.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -5.296 ; -5.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; -3.882 ; -3.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -3.809 ; -3.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -4.488 ; -4.488 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -5.917 ; -5.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.943 ; -6.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.685 ; -6.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -5.917 ; -5.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.156 ; -6.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -6.290 ; -6.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -6.476 ; -6.476 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -6.573 ; -6.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.916 ; -6.916 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; -3.204 ; -3.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; -1.528 ; -1.528 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; -1.811 ; -1.811 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; -2.113 ; -2.113 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; -2.207 ; -2.207 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; -1.801 ; -1.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.901 ; -3.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -4.027 ; -4.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.969 ; -3.969 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -4.386 ; -4.386 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -4.401 ; -4.401 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -4.244 ; -4.244 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -4.630 ; -4.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -4.746 ; -4.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -4.088 ; -4.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -4.285 ; -4.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -4.143 ; -4.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -4.002 ; -4.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -4.127 ; -4.127 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -4.055 ; -4.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -3.901 ; -3.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -3.915 ; -3.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; -1.288 ; -1.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; -4.474 ; -4.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -3.521 ; -3.521 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; -4.499 ; -4.499 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; -3.908 ; -3.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; -3.683 ; -3.683 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; -3.696 ; -3.696 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; -3.885 ; -3.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; -3.665 ; -3.665 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; -3.797 ; -3.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; -3.666 ; -3.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; -3.444 ; -3.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; -3.928 ; -3.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; -3.518 ; -3.518 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; -4.038 ; -4.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; -3.946 ; -3.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; -3.904 ; -3.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; -4.107 ; -4.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; -3.575 ; -3.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; -4.541 ; -4.541 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -4.527 ; -4.527 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; -3.795 ; -3.795 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; -4.761 ; -4.761 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; -3.774 ; -3.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; -3.774 ; -3.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; -3.776 ; -3.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; -4.050 ; -4.050 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; -4.392 ; -4.392 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; -4.731 ; -4.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; -5.336 ; -5.336 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -4.891 ; -4.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -4.661 ; -4.661 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; -4.192 ; -4.192 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; -3.780 ; -3.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -4.886 ; -4.886 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -3.547 ; -3.547 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -3.599 ; -3.599 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -3.837 ; -3.837 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; -3.748 ; -3.748 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -6.641 ; -6.641 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -6.518 ; -6.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.585 ; -6.585 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.927 ; -4.927 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.584 ; -7.584 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -7.137 ; -7.137 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -5.957 ; -5.957 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -4.927 ; -4.927 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -4.753 ; -4.753 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -4.292 ; -4.292 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.269 ; -4.269 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.372 ; -4.372 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.628 ; -4.628 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.344 ; -4.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.269 ; -4.269 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.560 ; -4.560 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.760 ; -4.760 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.999 ; -4.999 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -5.371 ; -5.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.546 ; -4.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -4.291 ; -4.291 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.297 ; -4.297 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.828 ; -4.828 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.945 ; -4.945 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.606 ; -4.606 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.350 ; -4.350 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.990 ; -4.990 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -4.936 ; -4.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; -1.528 ; -1.528 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; -1.474 ; -1.474 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; -1.268 ; -1.268 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -4.770 ; -4.770 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -4.953 ; -4.953 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -4.790 ; -4.790 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -4.770 ; -4.770 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; -4.379 ; -4.379 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -3.656 ; -3.656 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -8.486 ; -8.486 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; -4.530 ; -4.530 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -8.421 ; -8.421 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.559 ; -4.559 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.459 ; -7.459 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -6.195 ; -6.195 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.908 ; -6.908 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.767 ; -6.767 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.195 ; -6.195 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.354 ; -6.354 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -6.406 ; -6.406 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -6.628 ; -6.628 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -6.593 ; -6.593 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.777 ; -6.777 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -6.448 ; -6.448 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -7.557 ; -7.557 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -7.144 ; -7.144 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -7.163 ; -7.163 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -7.291 ; -7.291 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -6.655 ; -6.655 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -6.950 ; -6.950 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -6.651 ; -6.651 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -6.901 ; -6.901 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -7.518 ; -7.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -6.705 ; -6.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -6.784 ; -6.784 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -6.963 ; -6.963 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -6.456 ; -6.456 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -7.289 ; -7.289 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -7.022 ; -7.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -6.448 ; -6.448 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.668 ; -4.668 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.696 ; -5.696 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -4.365 ; -4.365 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; -4.343 ; -4.343 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.587 ; -5.587 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; -4.426 ; -4.426 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; -6.457 ; -6.457 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; -6.484 ; -6.484 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; -6.485 ; -6.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.574 ; -4.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; -4.574 ; -4.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; -4.775 ; -4.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; -5.016 ; -5.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; -5.218 ; -5.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; -5.330 ; -5.330 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; -2.055 ; -2.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -2.133 ; -2.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; -4.594 ; -4.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; -4.160 ; -4.160 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; -4.167 ; -4.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; -4.200 ; -4.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; -4.528 ; -4.528 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; -4.899 ; -4.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; -5.144 ; -5.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; -4.941 ; -4.941 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; -5.339 ; -5.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -5.046 ; -5.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -5.174 ; -5.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -5.046 ; -5.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -5.437 ; -5.437 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; -8.254 ; -8.254 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; -8.189 ; -8.189 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -4.389 ; -4.389 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; -7.096 ; -7.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; -7.303 ; -7.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; -7.303 ; -7.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.537 ; -3.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -3.732 ; -3.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.708 ; -3.708 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -3.781 ; -3.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -3.690 ; -3.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -3.614 ; -3.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -3.846 ; -3.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -3.537 ; -3.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -3.859 ; -3.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -3.845 ; -3.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -3.758 ; -3.758 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -3.775 ; -3.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -3.751 ; -3.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -3.808 ; -3.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -3.859 ; -3.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -3.682 ; -3.682 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -3.841 ; -3.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; -3.382 ; -3.382 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -5.475 ; -5.475 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; -4.927 ; -4.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; -5.408 ; -5.408 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -6.562 ; -6.562 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; -6.562 ; -6.562 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -5.966 ; -5.966 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -6.149 ; -6.149 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -5.986 ; -5.986 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -5.966 ; -5.966 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -5.805 ; -5.805 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -5.858 ; -5.858 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; -4.426 ; -4.426 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -6.457 ; -6.457 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -6.484 ; -6.484 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.485 ; -6.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.574 ; -4.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -4.574 ; -4.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -4.775 ; -4.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; -5.016 ; -5.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -5.218 ; -5.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -5.330 ; -5.330 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -2.055 ; -2.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -2.133 ; -2.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.594 ; -4.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.160 ; -4.160 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.167 ; -4.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.200 ; -4.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.528 ; -4.528 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.899 ; -4.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -5.144 ; -5.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.941 ; -4.941 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -5.339 ; -5.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.046 ; -5.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.174 ; -5.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.046 ; -5.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.437 ; -5.437 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -8.254 ; -8.254 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -8.189 ; -8.189 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.389 ; -4.389 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.096 ; -7.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -7.303 ; -7.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -7.303 ; -7.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.537 ; -3.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -3.732 ; -3.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.708 ; -3.708 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -3.781 ; -3.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -3.690 ; -3.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -3.614 ; -3.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -3.846 ; -3.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -3.537 ; -3.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -3.859 ; -3.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -3.845 ; -3.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -3.758 ; -3.758 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -3.775 ; -3.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -3.751 ; -3.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -3.808 ; -3.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -3.859 ; -3.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -3.682 ; -3.682 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -3.841 ; -3.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -3.382 ; -3.382 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.475 ; -5.475 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -4.927 ; -4.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -5.408 ; -5.408 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -6.562 ; -6.562 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -6.562 ; -6.562 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.966 ; -5.966 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -6.149 ; -6.149 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.986 ; -5.986 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.966 ; -5.966 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -5.805 ; -5.805 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.858 ; -5.858 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; -4.116 ; -4.116 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; -6.066 ; -6.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; -6.048 ; -6.048 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; -6.105 ; -6.105 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; -6.111 ; -6.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.032 ; -7.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; -6.585 ; -6.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[5]     ; CLK_PLL1      ; -6.111 ; -6.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; -6.407 ; -6.407 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; -4.201 ; -4.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -3.740 ; -3.740 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; -4.158 ; -4.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; -3.769 ; -3.769 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; -3.812 ; -3.812 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; -3.947 ; -3.947 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; -4.314 ; -4.314 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; -4.519 ; -4.519 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; -4.819 ; -4.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; -4.316 ; -4.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; -3.806 ; -3.806 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; -3.768 ; -3.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; -4.378 ; -4.378 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; -4.575 ; -4.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; -4.061 ; -4.061 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; -4.184 ; -4.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; -4.376 ; -4.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; -4.738 ; -4.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; -4.738 ; -4.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; -4.743 ; -4.743 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; -6.295 ; -6.295 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; -8.040 ; -8.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; -7.975 ; -7.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; -5.815 ; -5.815 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; -6.844 ; -6.844 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; -3.794 ; -3.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.678 ; -6.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.282 ; -6.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; -5.666 ; -5.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; -4.013 ; -4.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; -3.914 ; -3.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; -3.794 ; -3.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; -3.865 ; -3.865 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.516 ; -6.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -6.042 ; -6.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -6.942 ; -6.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -6.674 ; -6.674 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -6.588 ; -6.588 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -6.834 ; -6.834 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -6.042 ; -6.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -6.504 ; -6.504 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -6.171 ; -6.171 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -6.349 ; -6.349 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -7.288 ; -7.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -6.220 ; -6.220 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -6.255 ; -6.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -6.513 ; -6.513 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -6.086 ; -6.086 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -6.744 ; -6.744 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -6.856 ; -6.856 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -6.187 ; -6.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; -4.549 ; -4.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; -6.547 ; -6.547 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; -5.137 ; -5.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; -4.116 ; -4.116 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -6.066 ; -6.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -6.048 ; -6.048 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.105 ; -6.105 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -6.111 ; -6.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.032 ; -7.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -6.585 ; -6.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -6.111 ; -6.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -6.407 ; -6.407 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -4.201 ; -4.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -3.740 ; -3.740 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.158 ; -4.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -3.769 ; -3.769 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -3.812 ; -3.812 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -3.947 ; -3.947 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.314 ; -4.314 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.519 ; -4.519 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.819 ; -4.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.316 ; -4.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -3.806 ; -3.806 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -3.768 ; -3.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.378 ; -4.378 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.575 ; -4.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.061 ; -4.061 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.184 ; -4.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.376 ; -4.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -4.738 ; -4.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -4.738 ; -4.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -4.743 ; -4.743 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -6.295 ; -6.295 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -8.040 ; -8.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -7.975 ; -7.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -5.815 ; -5.815 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -6.844 ; -6.844 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -3.794 ; -3.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.678 ; -6.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.282 ; -6.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -5.666 ; -5.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -4.013 ; -4.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -3.914 ; -3.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -3.794 ; -3.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -3.865 ; -3.865 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.516 ; -6.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -6.042 ; -6.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -6.942 ; -6.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -6.674 ; -6.674 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -6.588 ; -6.588 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -6.834 ; -6.834 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -6.042 ; -6.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -6.504 ; -6.504 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -6.171 ; -6.171 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -6.349 ; -6.349 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -7.288 ; -7.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -6.220 ; -6.220 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -6.255 ; -6.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -6.513 ; -6.513 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -6.086 ; -6.086 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -6.744 ; -6.744 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -6.856 ; -6.856 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -6.187 ; -6.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.549 ; -4.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -6.547 ; -6.547 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.137 ; -5.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                      ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 9.107  ; 9.107  ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 9.196  ; 9.196  ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 8.848  ; 8.848  ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 13.110 ; 13.110 ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 12.989 ; 12.989 ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 12.947 ; 12.947 ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 11.563 ; 11.563 ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 13.110 ; 13.110 ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 13.006 ; 13.006 ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 12.774 ; 12.774 ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 12.987 ; 12.987 ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 11.729 ; 11.729 ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 11.950 ; 11.950 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 11.327 ; 11.327 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 11.491 ; 11.491 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 11.237 ; 11.237 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 11.950 ; 11.950 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 11.445 ; 11.445 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 11.308 ; 11.308 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 10.731 ; 10.731 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 11.181 ; 11.181 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 10.998 ; 10.998 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 10.500 ; 10.500 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 9.899  ; 9.899  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 10.226 ; 10.226 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 10.238 ; 10.238 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 10.421 ; 10.421 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 10.905 ; 10.905 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 11.087 ; 11.087 ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 4.529  ; 4.529  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 12.407 ; 12.407 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 12.079 ; 12.079 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 11.757 ; 11.757 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 11.443 ; 11.443 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 11.941 ; 11.941 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 11.250 ; 11.250 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 12.407 ; 12.407 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 11.793 ; 11.793 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 12.243 ; 12.243 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 11.876 ; 11.876 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 10.663 ; 10.663 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 10.098 ; 10.098 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 10.715 ; 10.715 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 10.757 ; 10.757 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 10.614 ; 10.614 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 11.884 ; 11.884 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 11.320 ; 11.320 ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 6.448  ; 6.448  ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 3.730  ; 3.730  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 3.409  ; 3.409  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 8.319  ; 8.319  ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 8.319  ; 8.319  ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 9.381  ; 9.381  ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 9.381  ; 9.381  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 9.165  ; 9.165  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 8.181  ; 8.181  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 8.643  ; 8.643  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 8.009  ; 8.009  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 9.165  ; 9.165  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 8.500  ; 8.500  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 7.805  ; 7.805  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 7.971  ; 7.971  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 8.243  ; 8.243  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 8.746  ; 8.746  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 8.332  ; 8.332  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 7.781  ; 7.781  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 8.183  ; 8.183  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 8.216  ; 8.216  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 8.484  ; 8.484  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 9.042  ; 9.042  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 8.992  ; 8.992  ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 10.021 ; 10.021 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 8.933  ; 8.933  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 8.909  ; 8.909  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 8.215  ; 8.215  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 9.156  ; 9.156  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 8.305  ; 8.305  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 8.904  ; 8.904  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 9.033  ; 9.033  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 9.305  ; 9.305  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 9.624  ; 9.624  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 8.495  ; 8.495  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 7.980  ; 7.980  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 8.672  ; 8.672  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 8.735  ; 8.735  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 8.677  ; 8.677  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 10.021 ; 10.021 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 9.225  ; 9.225  ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.333  ; 7.333  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.333  ; 7.333  ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 4.357  ; 4.357  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 8.395  ; 8.395  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.395  ; 8.395  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.241  ; 5.241  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.398  ; 5.398  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.450  ; 5.450  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.914  ; 4.914  ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 4.229  ; 4.229  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.333  ; 7.333  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.333  ; 7.333  ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 4.357  ; 4.357  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 8.395  ; 8.395  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.395  ; 8.395  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.241  ; 5.241  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.398  ; 5.398  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.450  ; 5.450  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.914  ; 4.914  ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 4.229  ; 4.229  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 12.301 ; 12.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 12.390 ; 12.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 9.090  ; 9.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 7.806  ; 7.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 7.908  ; 7.908  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 7.815  ; 7.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 7.765  ; 7.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 7.846  ; 7.846  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 8.062  ; 8.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 7.583  ; 7.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 8.029  ; 8.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 7.930  ; 7.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 7.857  ; 7.857  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 7.845  ; 7.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 8.591  ; 8.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 8.691  ; 8.691  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 8.284  ; 8.284  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 9.027  ; 9.027  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 9.090  ; 9.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 8.601  ; 8.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 9.029  ; 9.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 8.670  ; 8.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 8.644  ; 8.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 8.771  ; 8.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 8.476  ; 8.476  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 8.359  ; 8.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 4.189  ; 4.189  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 1.848  ; 1.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 3.451  ; 3.451  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 3.090  ; 3.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 3.357  ; 3.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 11.327 ; 11.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 12.042 ; 12.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 16.304 ; 16.304 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 16.183 ; 16.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 16.141 ; 16.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 14.757 ; 14.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 16.304 ; 16.304 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 16.200 ; 16.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 15.968 ; 15.968 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 16.181 ; 16.181 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 14.923 ; 14.923 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 2.866  ; 2.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 2.660  ; 2.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 3.215  ; 3.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 3.114  ; 3.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 2.821  ; 2.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 2.597  ; 2.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 3.407  ; 3.407  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 15.838 ; 15.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 14.948 ; 14.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 15.225 ; 15.225 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 14.836 ; 14.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 15.838 ; 15.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 15.262 ; 15.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 15.522 ; 15.522 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 14.838 ; 14.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 15.089 ; 15.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 15.558 ; 15.558 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 15.076 ; 15.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 14.538 ; 14.538 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 14.739 ; 14.739 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 14.565 ; 14.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 15.006 ; 15.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 14.976 ; 14.976 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 15.109 ; 15.109 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 4.319  ; 4.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 3.072  ; 3.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 4.387  ; 4.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 2.553  ; 2.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 2.574  ; 2.574  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 8.071  ; 8.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 8.071  ; 8.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 7.697  ; 7.697  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 7.749  ; 7.749  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 2.828  ; 2.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 2.958  ; 2.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 3.400  ; 3.400  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 3.655  ; 3.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 3.598  ; 3.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 3.508  ; 3.508  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 3.090  ; 3.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 3.615  ; 3.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 8.560  ; 8.560  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 8.476  ; 8.476  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 12.133 ; 12.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 12.146 ; 12.146 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 2.899  ; 2.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 2.296  ; 2.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 3.037  ; 3.037  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 4.459  ; 4.459  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 3.984  ; 3.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 3.497  ; 3.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 10.388 ; 10.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 10.714 ; 10.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 10.469 ; 10.469 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 10.521 ; 10.521 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 10.544 ; 10.544 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 11.024 ; 11.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 11.266 ; 11.266 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 12.319 ; 12.319 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 12.170 ; 12.170 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 10.698 ; 10.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 3.364  ; 3.364  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 4.341  ; 4.341  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 3.961  ; 3.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 3.921  ; 3.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 4.341  ; 4.341  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 4.178  ; 4.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 9.656  ; 9.656  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 3.092  ; 3.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 2.569  ; 2.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 2.993  ; 2.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 2.788  ; 2.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.787  ; 3.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 3.946  ; 3.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 3.940  ; 3.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 2.686  ; 2.686  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 2.806  ; 2.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 4.142  ; 4.142  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 4.654  ; 4.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 12.301 ; 12.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 10.448 ; 10.448 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 9.629  ; 9.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 9.657  ; 9.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 10.054 ; 10.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 9.595  ; 9.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 10.724 ; 10.724 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 9.991  ; 9.991  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 10.161 ; 10.161 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 12.301 ; 12.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 10.213 ; 10.213 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 8.501  ; 8.501  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 9.005  ; 9.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 8.631  ; 8.631  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 11.723 ; 11.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 11.723 ; 11.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 10.959 ; 10.959 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 11.807 ; 11.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 11.839 ; 11.839 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 16.621 ; 16.621 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 15.700 ; 15.700 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 15.491 ; 15.491 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 15.042 ; 15.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 15.829 ; 15.829 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 15.067 ; 15.067 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 16.621 ; 16.621 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 15.900 ; 15.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 16.151 ; 16.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 16.436 ; 16.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 15.239 ; 15.239 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 14.737 ; 14.737 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 15.228 ; 15.228 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 15.084 ; 15.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 15.199 ; 15.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 15.955 ; 15.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 15.342 ; 15.342 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 12.321 ; 12.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 11.907 ; 11.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 11.583 ; 11.583 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 11.917 ; 11.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 12.073 ; 12.073 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 11.883 ; 11.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 4.930  ; 4.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 10.619 ; 10.619 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 10.364 ; 10.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 10.779 ; 10.779 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 10.597 ; 10.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 11.045 ; 11.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 10.480 ; 10.480 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 10.523 ; 10.523 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 5.108  ; 5.108  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 4.148  ; 4.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 3.341  ; 3.341  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 3.152  ; 3.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 5.276  ; 5.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 3.377  ; 3.377  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 3.291  ; 3.291  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 3.377  ; 3.377  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 3.175  ; 3.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 3.247  ; 3.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 3.007  ; 3.007  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 3.048  ; 3.048  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 3.010  ; 3.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 2.973  ; 2.973  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 2.743  ; 2.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 3.716  ; 3.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 2.335  ; 2.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 2.620  ; 2.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 4.117  ; 4.117  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 3.780  ; 3.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 3.436  ; 3.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 3.736  ; 3.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 4.550  ; 4.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 4.580  ; 4.580  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 2.972  ; 2.972  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 4.697  ; 4.697  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 3.458  ; 3.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 3.883  ; 3.883  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 3.879  ; 3.879  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 3.856  ; 3.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 3.879  ; 3.879  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 3.868  ; 3.868  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 3.860  ; 3.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 9.806  ; 9.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 3.276  ; 3.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 2.452  ; 2.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 3.512  ; 3.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 5.099  ; 5.099  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 5.685  ; 5.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 5.343  ; 5.343  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 7.113  ; 7.113  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 7.202  ; 7.202  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 3.321  ; 3.321  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 6.139  ; 5.906  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 6.854  ; 6.621  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 11.116 ; 11.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 10.995 ; 10.995 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 10.953 ; 10.953 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 9.569  ; 9.569  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 11.116 ; 11.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 11.012 ; 11.012 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 10.780 ; 10.780 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 10.993 ; 10.993 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 9.735  ; 9.735  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 10.650 ; 10.417 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 9.760  ; 9.699  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 10.037 ; 9.813  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 9.581  ; 9.648  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 10.650 ; 10.417 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 10.074 ; 10.017 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 10.334 ; 10.267 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 9.650  ; 9.565  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 9.901  ; 9.668  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 10.318 ; 10.370 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 9.732  ; 9.888  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 9.350  ; 9.204  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 9.551  ; 9.551  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 9.377  ; 9.302  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 9.818  ; 9.743  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 9.788  ; 9.788  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 9.921  ; 9.921  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 3.358  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 3.473  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 6.945  ; 6.890  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 6.958  ; 6.903  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 5.200  ; 5.174  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 5.526  ; 5.500  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 5.281  ; 5.255  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 5.333  ; 5.307  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 5.356  ; 5.330  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 5.836  ; 5.810  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 6.078  ; 5.845  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 7.131  ; 6.898  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 6.749  ; 6.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 5.277  ; 5.510  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 4.017  ; 4.017  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 6.737  ; 6.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 5.566  ; 5.566  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 5.190  ; 5.190  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 5.039  ; 5.039  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 4.979  ; 4.979  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 4.893  ; 4.893  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 6.183  ; 6.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 4.934  ; 4.934  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 5.181  ; 5.181  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 6.737  ; 5.360  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 5.559  ; 5.559  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 3.695  ; 3.695  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 4.013  ; 4.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 3.789  ; 3.789  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 6.159  ; 4.782  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 6.159  ; 4.782  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 5.395  ; 4.018  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 6.243  ; 4.866  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 4.898  ; 6.275  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 11.433 ; 11.366 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 10.512 ; 10.451 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 10.303 ; 10.079 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 9.787  ; 9.854  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 10.641 ; 10.408 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 9.879  ; 9.822  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 11.433 ; 11.366 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 10.712 ; 10.627 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 10.963 ; 10.730 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 11.196 ; 11.248 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 9.895  ; 10.051 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 9.549  ; 9.403  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 10.040 ; 10.040 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 9.896  ; 9.821  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 10.011 ; 9.936  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 10.767 ; 10.767 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 10.154 ; 10.154 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 6.757  ; 5.380  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 6.343  ; 4.966  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 4.642  ; 6.019  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 4.976  ; 6.353  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 6.509  ; 5.132  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 4.942  ; 6.319  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 5.160  ; 4.299  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 5.089  ; 4.180  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 5.591  ; 5.536  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 5.409  ; 3.259  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 5.816  ; 5.574  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 5.292  ; 4.822  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 5.299  ; 3.151  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 4.168  ; 4.168  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 12.301 ; 12.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 12.390 ; 12.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 9.090  ; 9.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 7.806  ; 7.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 7.908  ; 7.908  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 7.815  ; 7.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 7.765  ; 7.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 7.846  ; 7.846  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 8.062  ; 8.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 7.583  ; 7.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 8.029  ; 8.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 7.930  ; 7.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 7.857  ; 7.857  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 7.845  ; 7.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 8.591  ; 8.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 8.691  ; 8.691  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 8.284  ; 8.284  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 9.027  ; 9.027  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 9.090  ; 9.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 8.601  ; 8.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 9.029  ; 9.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 8.670  ; 8.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 8.644  ; 8.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 8.771  ; 8.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 8.476  ; 8.476  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 8.359  ; 8.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 4.189  ; 4.189  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 1.848  ; 1.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 3.451  ; 3.451  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 3.090  ; 3.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 3.357  ; 3.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 11.327 ; 11.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 12.042 ; 12.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 16.304 ; 16.304 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 16.183 ; 16.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 16.141 ; 16.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 14.757 ; 14.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 16.304 ; 16.304 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 16.200 ; 16.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 15.968 ; 15.968 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 16.181 ; 16.181 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 14.923 ; 14.923 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 2.866  ; 2.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 2.660  ; 2.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 3.215  ; 3.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 3.114  ; 3.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 2.821  ; 2.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 2.597  ; 2.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 3.407  ; 3.407  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 15.838 ; 15.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 14.948 ; 14.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 15.225 ; 15.225 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 14.836 ; 14.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 15.838 ; 15.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 15.262 ; 15.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 15.522 ; 15.522 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 14.838 ; 14.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 15.089 ; 15.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 15.558 ; 15.558 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 15.076 ; 15.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 14.538 ; 14.538 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 14.739 ; 14.739 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 14.565 ; 14.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 15.006 ; 15.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 14.976 ; 14.976 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 15.109 ; 15.109 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 4.319  ; 4.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 3.072  ; 3.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 4.387  ; 4.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 2.553  ; 2.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 2.574  ; 2.574  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 8.071  ; 8.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 8.071  ; 8.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 7.697  ; 7.697  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 7.749  ; 7.749  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 2.828  ; 2.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 2.958  ; 2.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 3.400  ; 3.400  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 3.655  ; 3.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 3.598  ; 3.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 3.508  ; 3.508  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 3.090  ; 3.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 3.615  ; 3.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 8.560  ; 8.560  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 8.476  ; 8.476  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 12.133 ; 12.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 12.146 ; 12.146 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 2.899  ; 2.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 2.296  ; 2.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 3.037  ; 3.037  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 4.459  ; 4.459  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 3.984  ; 3.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.497  ; 3.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 10.388 ; 10.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 10.714 ; 10.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 10.469 ; 10.469 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 10.521 ; 10.521 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 10.544 ; 10.544 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 11.024 ; 11.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 11.266 ; 11.266 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 12.319 ; 12.319 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 12.170 ; 12.170 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 10.698 ; 10.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 3.364  ; 3.364  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 4.341  ; 4.341  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 3.961  ; 3.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 3.921  ; 3.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 4.341  ; 4.341  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 4.178  ; 4.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 9.656  ; 9.656  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 3.092  ; 3.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 2.569  ; 2.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 2.993  ; 2.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 2.788  ; 2.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.787  ; 3.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 3.946  ; 3.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 3.940  ; 3.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 2.686  ; 2.686  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 2.806  ; 2.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 4.142  ; 4.142  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 4.654  ; 4.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 12.301 ; 12.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 10.448 ; 10.448 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 9.629  ; 9.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 9.657  ; 9.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 10.054 ; 10.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 9.595  ; 9.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 10.724 ; 10.724 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 9.991  ; 9.991  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 10.161 ; 10.161 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 12.301 ; 12.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 10.213 ; 10.213 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 8.501  ; 8.501  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 9.005  ; 9.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 8.631  ; 8.631  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 11.723 ; 11.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 11.723 ; 11.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 10.959 ; 10.959 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 11.807 ; 11.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 11.839 ; 11.839 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 16.621 ; 16.621 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 15.700 ; 15.700 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 15.491 ; 15.491 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 15.042 ; 15.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 15.829 ; 15.829 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 15.067 ; 15.067 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 16.621 ; 16.621 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 15.900 ; 15.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 16.151 ; 16.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 16.436 ; 16.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 15.239 ; 15.239 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 14.737 ; 14.737 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 15.228 ; 15.228 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 15.084 ; 15.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 15.199 ; 15.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 15.955 ; 15.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 15.342 ; 15.342 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 12.321 ; 12.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 11.907 ; 11.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 11.583 ; 11.583 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 11.917 ; 11.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 12.073 ; 12.073 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 11.883 ; 11.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 4.930  ; 4.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 10.619 ; 10.619 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 10.364 ; 10.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 10.779 ; 10.779 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 10.597 ; 10.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 11.045 ; 11.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 10.480 ; 10.480 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 10.523 ; 10.523 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 5.108  ; 5.108  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 4.148  ; 4.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 3.341  ; 3.341  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 3.152  ; 3.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 5.276  ; 5.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 3.377  ; 3.377  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 3.291  ; 3.291  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 3.377  ; 3.377  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 3.175  ; 3.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 3.247  ; 3.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 3.007  ; 3.007  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 3.048  ; 3.048  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 3.010  ; 3.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 2.973  ; 2.973  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 2.743  ; 2.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 3.716  ; 3.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 2.335  ; 2.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 2.620  ; 2.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 4.117  ; 4.117  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 3.780  ; 3.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 3.436  ; 3.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 3.736  ; 3.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 4.550  ; 4.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 4.580  ; 4.580  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 2.972  ; 2.972  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 4.697  ; 4.697  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 3.458  ; 3.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 3.883  ; 3.883  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 3.879  ; 3.879  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 3.856  ; 3.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 3.879  ; 3.879  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 3.868  ; 3.868  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 3.860  ; 3.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 9.806  ; 9.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 3.276  ; 3.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 2.452  ; 2.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.512  ; 3.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 5.099  ; 5.099  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 5.685  ; 5.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 5.343  ; 5.343  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 7.113  ; 7.113  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 7.202  ; 7.202  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.321  ; 3.321  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 6.139  ; 5.906  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 6.854  ; 6.621  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 11.116 ; 11.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 10.995 ; 10.995 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 10.953 ; 10.953 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 9.569  ; 9.569  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 11.116 ; 11.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 11.012 ; 11.012 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 10.780 ; 10.780 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 10.993 ; 10.993 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 9.735  ; 9.735  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 10.650 ; 10.417 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 9.760  ; 9.699  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 10.037 ; 9.813  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 9.581  ; 9.648  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 10.650 ; 10.417 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 10.074 ; 10.017 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 10.334 ; 10.267 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 9.650  ; 9.565  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 9.901  ; 9.668  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 10.318 ; 10.370 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 9.732  ; 9.888  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 9.350  ; 9.204  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 9.551  ; 9.551  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 9.377  ; 9.302  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 9.818  ; 9.743  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 9.788  ; 9.788  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 9.921  ; 9.921  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 3.358  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 3.473  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 6.945  ; 6.890  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 6.958  ; 6.903  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 5.200  ; 5.174  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 5.526  ; 5.500  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 5.281  ; 5.255  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 5.333  ; 5.307  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 5.356  ; 5.330  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 5.836  ; 5.810  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 6.078  ; 5.845  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 7.131  ; 6.898  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 6.749  ; 6.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 5.277  ; 5.510  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 4.017  ; 4.017  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 6.737  ; 6.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 5.566  ; 5.566  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 5.190  ; 5.190  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 5.039  ; 5.039  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 4.979  ; 4.979  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 4.893  ; 4.893  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 6.183  ; 6.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 4.934  ; 4.934  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 5.181  ; 5.181  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 6.737  ; 5.360  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 5.559  ; 5.559  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 3.695  ; 3.695  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 4.013  ; 4.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 3.789  ; 3.789  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 6.159  ; 4.782  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 6.159  ; 4.782  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 5.395  ; 4.018  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 6.243  ; 4.866  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 4.898  ; 6.275  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 11.433 ; 11.366 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 10.512 ; 10.451 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 10.303 ; 10.079 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 9.787  ; 9.854  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 10.641 ; 10.408 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 9.879  ; 9.822  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 11.433 ; 11.366 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 10.712 ; 10.627 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 10.963 ; 10.730 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 11.196 ; 11.248 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 9.895  ; 10.051 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 9.549  ; 9.403  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 10.040 ; 10.040 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 9.896  ; 9.821  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 10.011 ; 9.936  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 10.767 ; 10.767 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 10.154 ; 10.154 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 6.757  ; 5.380  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 6.343  ; 4.966  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 4.642  ; 6.019  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 4.976  ; 6.353  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 6.509  ; 5.132  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 4.942  ; 6.319  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 5.160  ; 4.299  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 5.089  ; 4.180  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 5.591  ; 5.536  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 5.409  ; 3.259  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 5.816  ; 5.574  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 5.292  ; 4.822  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 5.299  ; 3.151  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 4.168  ; 4.168  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 6.508  ; 6.508  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 6.597  ; 6.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 3.324  ; 3.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 2.793  ; 2.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 2.851  ; 2.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 6.249  ; 6.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 10.511 ; 10.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 10.390 ; 10.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 10.348 ; 10.348 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 8.964  ; 8.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 10.511 ; 10.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 10.407 ; 10.407 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 10.175 ; 10.175 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 10.388 ; 10.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 9.130  ; 9.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 3.767  ; 3.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 3.767  ; 3.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 3.078  ; 3.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 3.218  ; 3.218  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 2.998  ; 2.998  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 3.812  ; 3.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 3.812  ; 3.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 2.969  ; 2.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 3.275  ; 3.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 2.988  ; 2.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 6.133  ; 6.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 3.358  ; 3.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 3.358  ; 3.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 3.079  ; 3.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 2.760  ; 2.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 2.823  ; 2.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 9.351  ; 9.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 8.728  ; 8.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 8.892  ; 8.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 8.638  ; 8.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 9.351  ; 9.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 8.846  ; 8.846  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 8.709  ; 8.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 8.132  ; 8.132  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 8.582  ; 8.582  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 8.399  ; 8.399  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 7.901  ; 7.901  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 7.300  ; 7.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 7.627  ; 7.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 7.639  ; 7.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 7.822  ; 7.822  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 8.306  ; 8.306  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 8.488  ; 8.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 4.137  ; 4.137  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 3.445  ; 3.445  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 2.807  ; 2.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 2.847  ; 2.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 3.514  ; 3.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 6.661  ; 6.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 5.444  ; 5.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 5.419  ; 5.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 5.419  ; 5.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 5.371  ; 5.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 5.446  ; 5.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 6.661  ; 6.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 5.160  ; 5.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 5.283  ; 5.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 5.294  ; 5.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 5.886  ; 5.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 4.347  ; 4.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 4.731  ; 4.731  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 4.404  ; 4.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 4.500  ; 4.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 4.500  ; 4.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 3.049  ; 3.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 4.840  ; 4.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 4.866  ; 4.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 9.808  ; 9.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 9.480  ; 9.480  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 9.158  ; 9.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 8.844  ; 8.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 9.342  ; 9.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 8.651  ; 8.651  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 9.808  ; 9.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 9.194  ; 9.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 9.644  ; 9.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 9.753  ; 9.753  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 9.163  ; 9.163  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 8.840  ; 8.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 8.167  ; 8.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 8.947  ; 8.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 8.445  ; 8.445  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 9.285  ; 9.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 8.721  ; 8.721  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 5.352  ; 5.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 4.943  ; 4.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 4.614  ; 4.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 4.948  ; 4.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 5.102  ; 5.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 4.929  ; 4.929  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 4.479  ; 4.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 4.405  ; 4.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 3.798  ; 3.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 3.514  ; 3.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 3.550  ; 3.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 4.203  ; 4.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 3.786  ; 3.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 3.840  ; 3.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 4.636  ; 4.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 3.846  ; 3.846  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 3.177  ; 3.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 3.033  ; 3.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 3.177  ; 3.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 2.930  ; 2.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 3.013  ; 3.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 3.069  ; 3.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 6.508  ; 6.508  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 6.597  ; 6.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.324  ; 3.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 2.793  ; 2.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 2.851  ; 2.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 6.249  ; 6.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 10.511 ; 10.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 10.390 ; 10.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 10.348 ; 10.348 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 8.964  ; 8.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 10.511 ; 10.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 10.407 ; 10.407 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 10.175 ; 10.175 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 10.388 ; 10.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 9.130  ; 9.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 3.767  ; 3.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 3.767  ; 3.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 3.078  ; 3.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 3.218  ; 3.218  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 2.998  ; 2.998  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 3.812  ; 3.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 3.812  ; 3.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 2.969  ; 2.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 3.275  ; 3.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 2.988  ; 2.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 6.133  ; 6.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 3.358  ; 3.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 3.358  ; 3.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 3.079  ; 3.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 2.760  ; 2.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 2.823  ; 2.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 9.351  ; 9.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 8.728  ; 8.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 8.892  ; 8.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 8.638  ; 8.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 9.351  ; 9.351  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 8.846  ; 8.846  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 8.709  ; 8.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 8.132  ; 8.132  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 8.582  ; 8.582  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 8.399  ; 8.399  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 7.901  ; 7.901  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 7.300  ; 7.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 7.627  ; 7.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 7.639  ; 7.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 7.822  ; 7.822  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 8.306  ; 8.306  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 8.488  ; 8.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 4.137  ; 4.137  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.445  ; 3.445  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 2.807  ; 2.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 2.847  ; 2.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 3.514  ; 3.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 6.661  ; 6.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 5.444  ; 5.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 5.419  ; 5.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 5.419  ; 5.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 5.371  ; 5.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 5.446  ; 5.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 6.661  ; 6.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 5.160  ; 5.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 5.283  ; 5.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 5.294  ; 5.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 5.886  ; 5.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 4.347  ; 4.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 4.731  ; 4.731  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 4.404  ; 4.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 4.500  ; 4.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 4.500  ; 4.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 3.049  ; 3.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 4.840  ; 4.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 4.866  ; 4.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 9.808  ; 9.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 9.480  ; 9.480  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 9.158  ; 9.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 8.844  ; 8.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 9.342  ; 9.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 8.651  ; 8.651  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 9.808  ; 9.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 9.194  ; 9.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 9.644  ; 9.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 9.753  ; 9.753  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 9.163  ; 9.163  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 8.840  ; 8.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 8.167  ; 8.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 8.947  ; 8.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 8.445  ; 8.445  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 9.285  ; 9.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 8.721  ; 8.721  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 5.352  ; 5.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 4.943  ; 4.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 4.614  ; 4.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 4.948  ; 4.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 5.102  ; 5.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 4.929  ; 4.929  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 4.479  ; 4.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 4.405  ; 4.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.798  ; 3.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 3.514  ; 3.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 3.550  ; 3.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 4.203  ; 4.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 3.786  ; 3.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 3.840  ; 3.840  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 4.636  ; 4.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.846  ; 3.846  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 3.177  ; 3.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 3.033  ; 3.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 3.177  ; 3.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 2.930  ; 2.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 3.013  ; 3.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 3.069  ; 3.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 12.366 ; 12.366 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 11.793 ; 11.793 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 12.062 ; 12.062 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 11.730 ; 11.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 12.366 ; 12.366 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 12.270 ; 12.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 11.830 ; 11.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 11.313 ; 11.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 11.860 ; 11.860 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 11.940 ; 11.940 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 11.362 ; 11.362 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 11.060 ; 11.060 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 11.031 ; 11.031 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 10.835 ; 10.835 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 11.536 ; 11.536 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 10.621 ; 10.621 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 10.917 ; 10.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 5.658  ; 5.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 5.416  ; 5.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 5.440  ; 5.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 5.658  ; 5.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 5.646  ; 5.646  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 12.929 ; 12.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 12.545 ; 12.545 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 12.328 ; 12.328 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 11.936 ; 11.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 12.357 ; 12.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 12.075 ; 12.075 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 12.929 ; 12.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 12.375 ; 12.375 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 12.922 ; 12.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 12.818 ; 12.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 11.525 ; 11.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 11.259 ; 11.259 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 11.520 ; 11.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 11.354 ; 11.354 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 11.729 ; 11.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 11.600 ; 11.600 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 11.150 ; 11.150 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 12.366 ; 12.366 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 11.793 ; 11.793 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 12.062 ; 12.062 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 11.730 ; 11.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 12.366 ; 12.366 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 12.270 ; 12.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 11.830 ; 11.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 11.313 ; 11.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 11.860 ; 11.860 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 11.940 ; 11.940 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 11.362 ; 11.362 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 11.060 ; 11.060 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 11.031 ; 11.031 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 10.835 ; 10.835 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 11.536 ; 11.536 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 10.621 ; 10.621 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 10.917 ; 10.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 5.658  ; 5.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 5.416  ; 5.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 5.440  ; 5.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 5.658  ; 5.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 5.646  ; 5.646  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 12.929 ; 12.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 12.545 ; 12.545 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 12.328 ; 12.328 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 11.936 ; 11.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 12.357 ; 12.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 12.075 ; 12.075 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 12.929 ; 12.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 12.375 ; 12.375 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 12.922 ; 12.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 12.818 ; 12.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 11.525 ; 11.525 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 11.259 ; 11.259 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 11.520 ; 11.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 11.354 ; 11.354 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 11.729 ; 11.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 11.600 ; 11.600 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 11.150 ; 11.150 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.141  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.141  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 8.763  ; 8.763  ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 8.844  ; 8.844  ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 8.848  ; 8.848  ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 8.951  ; 8.951  ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 9.565  ; 9.565  ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 9.644  ; 9.644  ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 8.951  ; 8.951  ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 9.807  ; 9.807  ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 9.346  ; 9.346  ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 8.953  ; 8.953  ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 9.067  ; 9.067  ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 9.465  ; 9.465  ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 8.951  ; 8.951  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 9.717  ; 9.717  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 10.044 ; 10.044 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 9.506  ; 9.506  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 10.482 ; 10.482 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 10.199 ; 10.199 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 9.925  ; 9.925  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 9.236  ; 9.236  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 9.549  ; 9.549  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 10.504 ; 10.504 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 10.063 ; 10.063 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 9.572  ; 9.572  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 10.010 ; 10.010 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 9.958  ; 9.958  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 10.041 ; 10.041 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 8.951  ; 8.951  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 9.314  ; 9.314  ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 4.529  ; 4.529  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 9.547  ; 9.547  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 10.469 ; 10.469 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 10.310 ; 10.310 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 9.712  ; 9.712  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 10.473 ; 10.473 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 10.004 ; 10.004 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 11.024 ; 11.024 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 10.298 ; 10.298 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 10.611 ; 10.611 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 11.382 ; 11.382 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 10.226 ; 10.226 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 9.771  ; 9.771  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 10.499 ; 10.499 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 10.477 ; 10.477 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 10.234 ; 10.234 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 9.930  ; 9.930  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 9.547  ; 9.547  ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 6.448  ; 6.448  ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 3.730  ; 3.730  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 3.409  ; 3.409  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 8.319  ; 8.319  ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 8.319  ; 8.319  ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 9.381  ; 9.381  ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 9.381  ; 9.381  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 6.774  ; 6.774  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 7.335  ; 7.335  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 7.664  ; 7.664  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 7.125  ; 7.125  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 8.263  ; 8.263  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 7.613  ; 7.613  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 7.170  ; 7.170  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 6.866  ; 6.866  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 7.287  ; 7.287  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 7.979  ; 7.979  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 7.418  ; 7.418  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 6.774  ; 6.774  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 7.146  ; 7.146  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 7.023  ; 7.023  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 7.421  ; 7.421  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 7.914  ; 7.914  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 7.927  ; 7.927  ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 6.973  ; 6.973  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 8.087  ; 8.087  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 7.930  ; 7.930  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 7.331  ; 7.331  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 8.254  ; 8.254  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 7.418  ; 7.418  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 8.269  ; 8.269  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 7.928  ; 7.928  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 8.349  ; 8.349  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 8.857  ; 8.857  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 7.581  ; 7.581  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 6.973  ; 6.973  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 7.635  ; 7.635  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 7.542  ; 7.542  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 7.614  ; 7.614  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 8.893  ; 8.893  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 8.160  ; 8.160  ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.333  ; 7.333  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.333  ; 7.333  ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 4.357  ; 4.357  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.914  ; 4.914  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.395  ; 8.395  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.241  ; 5.241  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.398  ; 5.398  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.450  ; 5.450  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.914  ; 4.914  ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 4.229  ; 4.229  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.333  ; 7.333  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.333  ; 7.333  ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 4.357  ; 4.357  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.914  ; 4.914  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.395  ; 8.395  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.241  ; 5.241  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.398  ; 5.398  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.450  ; 5.450  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.914  ; 4.914  ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 4.229  ; 4.229  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 3.525  ; 3.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 3.608  ; 3.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 2.666  ; 2.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 4.055  ; 4.055  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 4.135  ; 4.135  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 4.010  ; 4.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 3.925  ; 3.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 3.761  ; 3.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 4.207  ; 4.207  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 3.821  ; 3.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 3.940  ; 3.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 4.014  ; 4.014  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 3.767  ; 3.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 3.832  ; 3.832  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 2.666  ; 2.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 3.198  ; 3.198  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 3.320  ; 3.320  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 3.383  ; 3.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 3.309  ; 3.309  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 3.266  ; 3.266  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 3.257  ; 3.257  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 3.278  ; 3.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 4.069  ; 4.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 3.663  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 3.479  ; 3.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 3.056  ; 2.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 1.848  ; 1.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 2.994  ; 2.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 2.955  ; 2.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 3.357  ; 3.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 4.925  ; 4.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 3.616  ; 3.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 2.999  ; 2.999  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 2.999  ; 2.999  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 3.065  ; 3.065  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 3.386  ; 3.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 3.165  ; 3.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 3.781  ; 3.781  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 3.388  ; 3.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 3.502  ; 3.502  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 2.866  ; 2.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 2.660  ; 2.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 2.049  ; 2.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 3.114  ; 3.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 2.821  ; 2.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 2.597  ; 2.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 3.354  ; 3.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 2.696  ; 2.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 3.012  ; 3.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 3.151  ; 3.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 2.992  ; 2.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 3.009  ; 3.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 3.194  ; 3.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 3.027  ; 3.027  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 2.789  ; 2.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 3.054  ; 3.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 2.749  ; 2.749  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 2.727  ; 2.727  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 2.897  ; 2.897  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 2.728  ; 2.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 2.881  ; 2.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 3.453  ; 3.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 2.696  ; 2.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 2.929  ; 2.929  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 4.197  ; 4.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 3.072  ; 3.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 3.444  ; 3.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 2.553  ; 2.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 2.574  ; 2.574  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 2.647  ; 2.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 3.231  ; 3.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 2.766  ; 2.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 2.647  ; 2.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 2.828  ; 2.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 2.958  ; 2.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 3.400  ; 3.400  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 3.655  ; 3.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 3.598  ; 3.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 3.508  ; 3.508  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 3.090  ; 3.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 3.615  ; 3.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 3.273  ; 3.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 3.325  ; 3.325  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 3.157  ; 3.157  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 3.170  ; 3.170  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 2.752  ; 2.752  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 2.296  ; 2.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 3.037  ; 3.037  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 3.206  ; 3.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 2.724  ; 2.724  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 3.497  ; 3.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 4.110  ; 4.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 4.762  ; 4.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 4.517  ; 4.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 4.569  ; 4.707  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 4.592  ; 4.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 5.072  ; 5.210  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 5.170  ; 4.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 6.223  ; 5.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 5.806  ; 6.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 3.992  ; 3.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 2.976  ; 2.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 2.899  ; 2.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 2.943  ; 2.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 2.899  ; 2.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 3.552  ; 3.552  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 3.237  ; 3.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 2.710  ; 2.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 3.092  ; 3.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 2.569  ; 2.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 2.569  ; 2.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 2.993  ; 2.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 2.788  ; 2.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.657  ; 3.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 3.705  ; 3.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 3.848  ; 3.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 3.423  ; 3.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 2.686  ; 2.686  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 2.806  ; 2.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 3.602  ; 3.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 4.230  ; 4.230  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.695  ; 3.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 4.964  ; 4.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 4.786  ; 4.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 4.654  ; 4.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 4.689  ; 4.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 4.393  ; 4.393  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 5.197  ; 5.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 4.370  ; 4.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 4.451  ; 4.451  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 4.797  ; 5.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 5.559  ; 5.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 3.695  ; 3.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 4.013  ; 4.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 3.789  ; 3.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 3.758  ; 3.872  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 4.126  ; 4.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 3.758  ; 3.872  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 4.581  ; 4.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 4.855  ; 4.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 4.242  ; 4.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 5.008  ; 5.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 4.715  ; 4.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 4.892  ; 4.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 4.444  ; 4.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 4.640  ; 4.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 5.335  ; 5.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 5.063  ; 5.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 5.237  ; 5.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 5.124  ; 5.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 5.034  ; 5.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 4.335  ; 4.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 4.497  ; 4.707  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 4.454  ; 4.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 4.481  ; 4.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 4.670  ; 4.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 4.242  ; 4.415  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 5.095  ; 5.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 4.681  ; 4.923  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 4.599  ; 4.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 4.933  ; 4.691  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 4.847  ; 5.089  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 4.899  ; 4.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 4.292  ; 4.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 4.038  ; 3.883  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 3.653  ; 4.050  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 4.097  ; 4.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 3.259  ; 3.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 3.739  ; 3.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 3.687  ; 3.474  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 3.151  ; 3.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 3.458  ; 3.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 2.829  ; 2.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 3.341  ; 3.341  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 2.889  ; 2.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 2.808  ; 2.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 2.228  ; 2.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 2.491  ; 2.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 2.414  ; 2.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 2.387  ; 2.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 2.388  ; 2.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 2.336  ; 2.336  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 2.411  ; 2.411  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 2.294  ; 2.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 2.228  ; 2.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 2.743  ; 2.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 2.921  ; 2.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 2.335  ; 2.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 2.620  ; 2.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 3.419  ; 3.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 3.185  ; 3.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 3.237  ; 3.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 3.857  ; 3.857  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 3.643  ; 3.643  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 2.972  ; 2.972  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 3.759  ; 3.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 3.458  ; 3.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 3.645  ; 3.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 3.049  ; 3.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 3.036  ; 3.036  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 2.982  ; 2.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 3.276  ; 3.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 2.452  ; 2.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 3.512  ; 3.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 2.464  ; 2.464  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 2.791  ; 2.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 2.818  ; 2.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 5.342  ; 5.342  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 5.423  ; 5.423  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 2.677  ; 2.966  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 4.795  ; 4.925  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 5.623  ; 5.427  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 5.530  ; 5.532  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 6.144  ; 6.340  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 6.223  ; 6.419  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 5.530  ; 5.726  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 6.386  ; 6.582  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 5.925  ; 5.925  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 5.532  ; 5.532  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 5.646  ; 5.646  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 6.044  ; 6.044  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 5.357  ; 5.357  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 5.845  ; 5.562  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 5.943  ; 5.802  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 5.873  ; 6.046  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 6.649  ; 6.531  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 6.137  ; 6.213  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 5.755  ; 5.857  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 5.720  ; 5.570  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 6.089  ; 6.115  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 6.190  ; 6.288  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 5.884  ; 5.884  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 5.665  ; 5.665  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 5.404  ; 5.404  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 5.829  ; 6.014  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 6.583  ; 6.527  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 5.372  ; 5.372  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 5.357  ; 5.357  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 3.358  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 3.473  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 5.433  ; 5.451  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 5.446  ; 5.464  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 4.574  ; 4.110  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 4.458  ; 4.762  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 4.655  ; 4.517  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 4.707  ; 4.569  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 4.730  ; 4.592  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 5.210  ; 5.072  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 4.902  ; 5.170  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 5.955  ; 6.223  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 6.074  ; 5.806  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 3.903  ; 3.992  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 2.968  ; 3.563  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.695  ; 3.695  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 4.964  ; 4.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 4.786  ; 4.786  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 4.654  ; 4.654  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 4.689  ; 4.689  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 4.393  ; 4.393  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 5.197  ; 5.197  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 4.370  ; 4.370  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 4.451  ; 4.451  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 6.185  ; 4.797  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 5.559  ; 5.559  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 3.695  ; 3.695  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 4.013  ; 4.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 3.789  ; 3.789  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 4.843  ; 3.758  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 5.607  ; 4.126  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 4.843  ; 3.758  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 5.691  ; 4.581  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 4.613  ; 5.723  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 4.415  ; 4.242  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 5.008  ; 5.008  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 4.715  ; 4.715  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 4.952  ; 4.952  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 4.444  ; 4.444  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 4.640  ; 4.640  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 5.335  ; 5.335  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 5.063  ; 5.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 5.237  ; 5.237  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 5.334  ; 5.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 5.307  ; 5.127  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 4.819  ; 4.609  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 4.707  ; 4.497  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 4.627  ; 4.454  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 4.654  ; 4.481  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 4.843  ; 4.670  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 4.415  ; 4.242  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 6.205  ; 5.095  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 5.791  ; 4.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 4.357  ; 5.467  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 4.691  ; 5.801  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 5.957  ; 4.847  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 4.657  ; 5.767  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 3.883  ; 4.038  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 4.356  ; 3.653  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 4.079  ; 4.097  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 3.572  ; 3.259  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 3.668  ; 3.739  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 3.474  ; 3.687  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 3.267  ; 3.151  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 3.369  ; 3.714  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 3.525  ; 3.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 3.608  ; 3.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 2.666  ; 2.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 4.055  ; 4.055  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 4.135  ; 4.135  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 4.010  ; 4.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 3.925  ; 3.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 3.761  ; 3.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 4.207  ; 4.207  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 3.821  ; 3.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 3.940  ; 3.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 4.014  ; 4.014  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 3.767  ; 3.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 3.832  ; 3.832  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 2.666  ; 2.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 3.198  ; 3.198  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 3.320  ; 3.320  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 3.383  ; 3.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 3.309  ; 3.309  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 3.266  ; 3.266  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 3.257  ; 3.257  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 3.278  ; 3.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 4.069  ; 4.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 3.663  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 3.479  ; 3.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.056  ; 2.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 1.848  ; 1.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 2.994  ; 2.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 2.955  ; 2.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 3.357  ; 3.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.925  ; 4.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 3.616  ; 3.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 2.999  ; 2.999  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 2.999  ; 2.999  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 3.065  ; 3.065  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 3.386  ; 3.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 3.165  ; 3.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 3.781  ; 3.781  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 3.388  ; 3.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 3.502  ; 3.502  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 2.866  ; 2.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 2.660  ; 2.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 2.049  ; 2.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 3.114  ; 3.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 2.821  ; 2.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 2.597  ; 2.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 3.354  ; 3.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 2.696  ; 2.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 3.012  ; 3.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 3.151  ; 3.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 2.992  ; 2.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 3.009  ; 3.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 3.194  ; 3.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 3.027  ; 3.027  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 2.789  ; 2.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 3.054  ; 3.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 2.749  ; 2.749  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 2.727  ; 2.727  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 2.897  ; 2.897  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 2.728  ; 2.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 2.881  ; 2.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 3.453  ; 3.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 2.696  ; 2.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 2.929  ; 2.929  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 4.197  ; 4.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 3.072  ; 3.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 3.444  ; 3.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 2.553  ; 2.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 2.574  ; 2.574  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 2.647  ; 2.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 3.231  ; 3.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 2.766  ; 2.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 2.647  ; 2.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 2.828  ; 2.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 2.958  ; 2.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 3.400  ; 3.400  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 3.655  ; 3.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 3.598  ; 3.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 3.508  ; 3.508  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 3.090  ; 3.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 3.615  ; 3.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 3.273  ; 3.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 3.325  ; 3.325  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 3.157  ; 3.157  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 3.170  ; 3.170  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 2.752  ; 2.752  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 2.296  ; 2.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 3.037  ; 3.037  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 3.206  ; 3.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 2.724  ; 2.724  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.497  ; 3.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 4.110  ; 4.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 4.762  ; 4.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 4.517  ; 4.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 4.569  ; 4.707  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 4.592  ; 4.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 5.072  ; 5.210  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 5.170  ; 4.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 6.223  ; 5.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 5.806  ; 6.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 3.992  ; 3.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 2.976  ; 2.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 2.899  ; 2.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 2.943  ; 2.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 2.899  ; 2.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 3.552  ; 3.552  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 3.237  ; 3.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 2.710  ; 2.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 3.092  ; 3.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 2.569  ; 2.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 2.569  ; 2.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 2.993  ; 2.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 2.788  ; 2.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.657  ; 3.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 3.705  ; 3.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 3.848  ; 3.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 3.423  ; 3.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 2.686  ; 2.686  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 2.806  ; 2.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 3.602  ; 3.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 4.230  ; 4.230  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.695  ; 3.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 4.964  ; 4.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 4.786  ; 4.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 4.654  ; 4.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 4.689  ; 4.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 4.393  ; 4.393  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 5.197  ; 5.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 4.370  ; 4.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 4.451  ; 4.451  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 4.797  ; 5.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 5.559  ; 5.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 3.695  ; 3.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 4.013  ; 4.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 3.789  ; 3.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 3.758  ; 3.872  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 4.126  ; 4.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 3.758  ; 3.872  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 4.581  ; 4.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 4.855  ; 4.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.242  ; 4.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 5.008  ; 5.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 4.715  ; 4.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 4.892  ; 4.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 4.444  ; 4.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 4.640  ; 4.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 5.335  ; 5.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 5.063  ; 5.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 5.237  ; 5.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 5.124  ; 5.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 5.034  ; 5.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 4.335  ; 4.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 4.497  ; 4.707  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 4.454  ; 4.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 4.481  ; 4.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.670  ; 4.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.242  ; 4.415  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 5.095  ; 5.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 4.681  ; 4.923  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 4.599  ; 4.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 4.933  ; 4.691  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 4.847  ; 5.089  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 4.899  ; 4.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 4.292  ; 4.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 4.038  ; 3.883  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 3.653  ; 4.050  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 4.097  ; 4.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 3.259  ; 3.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 3.739  ; 3.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 3.687  ; 3.474  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 3.151  ; 3.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.458  ; 3.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 2.829  ; 2.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 3.341  ; 3.341  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 2.889  ; 2.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 2.808  ; 2.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 2.228  ; 2.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 2.491  ; 2.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 2.414  ; 2.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 2.387  ; 2.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 2.388  ; 2.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 2.336  ; 2.336  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 2.411  ; 2.411  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 2.294  ; 2.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 2.228  ; 2.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 2.743  ; 2.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 2.921  ; 2.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 2.335  ; 2.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 2.620  ; 2.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 3.419  ; 3.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 3.185  ; 3.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 3.237  ; 3.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 3.857  ; 3.857  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 3.643  ; 3.643  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 2.972  ; 2.972  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 3.759  ; 3.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 3.458  ; 3.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 3.645  ; 3.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 3.049  ; 3.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 3.036  ; 3.036  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 2.982  ; 2.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 3.276  ; 3.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 2.452  ; 2.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.512  ; 3.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 2.464  ; 2.464  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 2.791  ; 2.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 2.818  ; 2.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 5.342  ; 5.342  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 5.423  ; 5.423  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 2.677  ; 2.966  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.795  ; 4.925  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 5.623  ; 5.427  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 5.530  ; 5.532  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 6.144  ; 6.340  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 6.223  ; 6.419  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 5.530  ; 5.726  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 6.386  ; 6.582  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 5.925  ; 5.925  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 5.532  ; 5.532  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 5.646  ; 5.646  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 6.044  ; 6.044  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 5.357  ; 5.357  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 5.845  ; 5.562  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 5.943  ; 5.802  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 5.873  ; 6.046  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 6.649  ; 6.531  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 6.137  ; 6.213  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 5.755  ; 5.857  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 5.720  ; 5.570  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.089  ; 6.115  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.190  ; 6.288  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 5.884  ; 5.884  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.665  ; 5.665  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 5.404  ; 5.404  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.829  ; 6.014  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.583  ; 6.527  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.372  ; 5.372  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.357  ; 5.357  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 3.358  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 3.473  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 5.433  ; 5.451  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 5.446  ; 5.464  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 4.574  ; 4.110  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 4.458  ; 4.762  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 4.655  ; 4.517  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 4.707  ; 4.569  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 4.730  ; 4.592  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 5.210  ; 5.072  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 4.902  ; 5.170  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 5.955  ; 6.223  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 6.074  ; 5.806  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 3.903  ; 3.992  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 2.968  ; 3.563  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.695  ; 3.695  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 4.964  ; 4.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 4.786  ; 4.786  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 4.654  ; 4.654  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 4.689  ; 4.689  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 4.393  ; 4.393  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 5.197  ; 5.197  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 4.370  ; 4.370  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 4.451  ; 4.451  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 6.185  ; 4.797  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 5.559  ; 5.559  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 3.695  ; 3.695  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 4.013  ; 4.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 3.789  ; 3.789  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 4.843  ; 3.758  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 5.607  ; 4.126  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 4.843  ; 3.758  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 5.691  ; 4.581  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 4.613  ; 5.723  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.415  ; 4.242  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 5.008  ; 5.008  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 4.715  ; 4.715  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 4.952  ; 4.952  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 4.444  ; 4.444  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 4.640  ; 4.640  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 5.335  ; 5.335  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 5.063  ; 5.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 5.237  ; 5.237  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 5.334  ; 5.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 5.307  ; 5.127  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 4.819  ; 4.609  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 4.707  ; 4.497  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 4.627  ; 4.454  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 4.654  ; 4.481  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.843  ; 4.670  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.415  ; 4.242  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 6.205  ; 5.095  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 5.791  ; 4.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 4.357  ; 5.467  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 4.691  ; 5.801  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 5.957  ; 4.847  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 4.657  ; 5.767  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 3.883  ; 4.038  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 4.356  ; 3.653  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 4.079  ; 4.097  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 3.572  ; 3.259  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 3.668  ; 3.739  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 3.474  ; 3.687  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 3.267  ; 3.151  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.369  ; 3.714  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 5.449  ; 5.449  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 5.530  ; 5.530  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 3.173  ; 3.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 2.793  ; 2.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 2.851  ; 2.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 5.534  ; 5.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 4.009  ; 4.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 5.231  ; 5.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 4.247  ; 4.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 6.032  ; 6.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 5.639  ; 5.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 5.753  ; 5.753  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 5.397  ; 5.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 2.916  ; 2.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 3.683  ; 3.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 3.071  ; 3.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 3.178  ; 3.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 2.916  ; 2.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 3.660  ; 3.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 3.046  ; 3.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 2.981  ; 2.981  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 3.158  ; 3.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 2.721  ; 2.721  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 3.274  ; 3.274  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 3.005  ; 3.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 2.721  ; 2.721  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 2.745  ; 2.745  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 4.062  ; 4.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 4.544  ; 4.544  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 4.833  ; 4.833  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 4.618  ; 4.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 5.969  ; 5.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 4.855  ; 4.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 4.783  ; 4.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 4.062  ; 4.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 4.378  ; 4.378  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 6.812  ; 6.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 6.300  ; 6.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 5.713  ; 5.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 6.040  ; 6.040  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 5.771  ; 5.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 6.235  ; 6.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 5.637  ; 5.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 6.000  ; 6.000  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 3.361  ; 3.361  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 3.213  ; 3.213  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 2.807  ; 2.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 2.847  ; 2.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 3.106  ; 3.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.053  ; 3.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 3.461  ; 3.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 3.491  ; 3.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 3.316  ; 3.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 3.471  ; 3.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 3.610  ; 3.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 3.663  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 3.281  ; 3.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 3.286  ; 3.286  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 3.570  ; 3.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 3.708  ; 3.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 3.053  ; 3.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 3.450  ; 3.450  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 3.201  ; 3.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 3.049  ; 3.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 3.267  ; 3.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 3.049  ; 3.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 3.742  ; 3.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 3.767  ; 3.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 2.957  ; 2.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 4.187  ; 4.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 3.779  ; 3.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 3.534  ; 3.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 3.648  ; 3.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 3.948  ; 3.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 3.676  ; 3.676  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 3.855  ; 3.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 3.947  ; 3.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 3.612  ; 3.612  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 3.365  ; 3.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 3.400  ; 3.400  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 3.539  ; 3.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 3.439  ; 3.439  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 3.577  ; 3.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 2.957  ; 2.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 4.269  ; 4.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 3.860  ; 3.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 3.531  ; 3.531  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 3.844  ; 3.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 3.673  ; 3.673  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 3.322  ; 3.322  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 3.582  ; 3.582  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 3.798  ; 3.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 3.436  ; 3.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 3.505  ; 3.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 4.124  ; 4.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 3.655  ; 3.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 3.762  ; 3.762  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 4.557  ; 4.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 1.262  ; 2.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 3.033  ; 3.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 3.177  ; 3.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 2.930  ; 2.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 3.013  ; 3.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 3.069  ; 3.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 5.449  ; 5.449  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 5.530  ; 5.530  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.173  ; 3.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 2.793  ; 2.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 2.851  ; 2.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 5.534  ; 5.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 4.009  ; 4.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 5.231  ; 5.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 4.247  ; 4.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 6.032  ; 6.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 5.639  ; 5.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 5.753  ; 5.753  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 5.397  ; 5.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 2.916  ; 2.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 3.683  ; 3.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 3.071  ; 3.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 3.178  ; 3.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 2.916  ; 2.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 3.660  ; 3.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 3.046  ; 3.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 2.981  ; 2.981  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 3.158  ; 3.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 2.721  ; 2.721  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 3.274  ; 3.274  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 3.005  ; 3.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 2.721  ; 2.721  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 2.745  ; 2.745  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 4.062  ; 4.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 4.544  ; 4.544  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 4.833  ; 4.833  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 4.618  ; 4.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 5.969  ; 5.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 4.855  ; 4.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 4.783  ; 4.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 4.062  ; 4.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 4.378  ; 4.378  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.812  ; 6.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 6.300  ; 6.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.713  ; 5.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.040  ; 6.040  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.771  ; 5.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.235  ; 6.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.637  ; 5.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 6.000  ; 6.000  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 3.361  ; 3.361  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.213  ; 3.213  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 2.807  ; 2.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 2.847  ; 2.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 3.106  ; 3.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.053  ; 3.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 3.461  ; 3.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 3.491  ; 3.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 3.316  ; 3.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 3.471  ; 3.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 3.610  ; 3.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 3.663  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 3.281  ; 3.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 3.286  ; 3.286  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 3.570  ; 3.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 3.708  ; 3.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 3.053  ; 3.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 3.450  ; 3.450  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 3.201  ; 3.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 3.049  ; 3.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 3.267  ; 3.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 3.049  ; 3.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 3.742  ; 3.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 3.767  ; 3.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 2.957  ; 2.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 4.187  ; 4.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 3.779  ; 3.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 3.534  ; 3.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 3.648  ; 3.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 3.948  ; 3.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 3.676  ; 3.676  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 3.855  ; 3.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 3.947  ; 3.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 3.612  ; 3.612  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 3.365  ; 3.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 3.400  ; 3.400  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 3.539  ; 3.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 3.439  ; 3.439  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 3.577  ; 3.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 2.957  ; 2.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 4.269  ; 4.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 3.860  ; 3.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 3.531  ; 3.531  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 3.844  ; 3.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 3.673  ; 3.673  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 3.322  ; 3.322  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 3.582  ; 3.582  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.798  ; 3.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 3.436  ; 3.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 3.505  ; 3.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 4.124  ; 4.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 3.655  ; 3.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 3.762  ; 3.762  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 4.557  ; 4.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 1.262  ; 2.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 3.033  ; 3.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 3.177  ; 3.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 2.930  ; 2.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 3.013  ; 3.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 3.069  ; 3.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 5.383  ; 5.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 6.452  ; 6.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 6.618  ; 6.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 6.389  ; 6.389  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 7.273  ; 7.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 6.398  ; 6.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 6.614  ; 6.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 6.008  ; 6.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 6.191  ; 6.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 6.376  ; 6.376  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 6.373  ; 6.373  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 5.912  ; 5.912  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 6.158  ; 6.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 5.851  ; 5.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 6.462  ; 6.462  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 5.383  ; 5.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 5.746  ; 5.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 3.021  ; 3.021  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.105  ; 3.105  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 3.021  ; 3.021  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 3.264  ; 3.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 3.246  ; 3.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 5.979  ; 5.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 7.204  ; 7.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 6.884  ; 6.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 6.595  ; 6.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 7.264  ; 7.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 6.203  ; 6.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 7.713  ; 7.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 7.070  ; 7.070  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 7.253  ; 7.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 7.254  ; 7.254  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 6.536  ; 6.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 6.111  ; 6.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 6.647  ; 6.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 6.370  ; 6.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 6.655  ; 6.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 6.362  ; 6.362  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 5.979  ; 5.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 5.383  ; 5.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 6.452  ; 6.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 6.618  ; 6.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 6.389  ; 6.389  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 7.273  ; 7.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 6.398  ; 6.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.614  ; 6.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.008  ; 6.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.191  ; 6.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.376  ; 6.376  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 6.373  ; 6.373  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.912  ; 5.912  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.158  ; 6.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.851  ; 5.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.462  ; 6.462  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.383  ; 5.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.746  ; 5.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 3.021  ; 3.021  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.105  ; 3.105  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 3.021  ; 3.021  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 3.264  ; 3.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 3.246  ; 3.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 5.979  ; 5.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 7.204  ; 7.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 6.884  ; 6.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 6.595  ; 6.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 7.264  ; 7.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 6.203  ; 6.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 7.713  ; 7.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 7.070  ; 7.070  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 7.253  ; 7.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 7.254  ; 7.254  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 6.536  ; 6.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 6.111  ; 6.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 6.647  ; 6.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 6.370  ; 6.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 6.655  ; 6.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 6.362  ; 6.362  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 5.979  ; 5.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.141  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.141  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------+
; Propagation Delay                                                ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 8.512  ; 8.512  ; 8.512  ; 8.512  ;
; ASn          ; ACSI_WRn      ; 8.601  ; 8.601  ; 8.601  ; 8.601  ;
; ASn          ; BUTTONn       ; 9.636  ;        ;        ; 9.636  ;
; ASn          ; CA1_OUT       ; 8.253  ;        ;        ; 8.253  ;
; ASn          ; CD[0]         ; 12.394 ; 12.394 ; 12.394 ; 12.394 ;
; ASn          ; CD[1]         ; 12.352 ; 12.352 ; 12.352 ; 12.352 ;
; ASn          ; CD[2]         ; 10.968 ; 10.968 ; 10.968 ; 10.968 ;
; ASn          ; CD[3]         ; 12.515 ; 12.515 ; 12.515 ; 12.515 ;
; ASn          ; CD[4]         ; 12.411 ; 12.411 ; 12.411 ; 12.411 ;
; ASn          ; CD[5]         ; 12.179 ; 12.179 ; 12.179 ; 12.179 ;
; ASn          ; CD[6]         ; 12.392 ; 12.392 ; 12.392 ; 12.392 ;
; ASn          ; CD[7]         ; 11.134 ; 11.134 ; 11.134 ; 11.134 ;
; ASn          ; DATA[0]       ; 13.019 ; 12.899 ; 12.899 ; 13.019 ;
; ASn          ; DATA[1]       ; 13.350 ; 13.141 ; 13.141 ; 13.350 ;
; ASn          ; DATA[2]       ; 13.174 ; 12.847 ; 12.847 ; 13.174 ;
; ASn          ; DATA[3]       ; 13.763 ; 13.382 ; 13.382 ; 13.763 ;
; ASn          ; DATA[4]       ; 13.371 ; 13.367 ; 13.367 ; 13.371 ;
; ASn          ; DATA[5]       ; 13.208 ; 13.533 ; 13.533 ; 13.208 ;
; ASn          ; DATA[6]       ; 12.907 ; 12.661 ; 12.661 ; 12.907 ;
; ASn          ; DATA[7]       ; 13.038 ; 12.648 ; 12.648 ; 13.038 ;
; ASn          ; DATA[8]       ; 13.045 ; 13.097 ; 13.097 ; 13.045 ;
; ASn          ; DATA[9]       ; 12.648 ; 12.728 ; 12.728 ; 12.648 ;
; ASn          ; DATA[10]      ; 12.298 ; 12.047 ; 12.047 ; 12.298 ;
; ASn          ; DATA[11]      ; 12.663 ; 12.663 ; 12.663 ; 12.663 ;
; ASn          ; DATA[12]      ; 12.419 ; 12.199 ; 12.199 ; 12.419 ;
; ASn          ; DATA[13]      ; 12.791 ; 12.791 ; 12.791 ; 12.791 ;
; ASn          ; DATA[14]      ; 12.914 ; 12.914 ; 12.914 ; 12.914 ;
; ASn          ; DATA[15]      ; 13.096 ; 13.096 ; 13.096 ; 13.096 ;
; ASn          ; DTACKn        ; 9.675  ; 9.675  ; 9.675  ; 9.675  ;
; ASn          ; FLASH_CEn     ; 8.731  ;        ;        ; 8.731  ;
; ASn          ; FLASH_OEn     ; 8.744  ;        ;        ; 8.744  ;
; ASn          ; IDE_CS0n      ; 6.702  ;        ;        ; 6.702  ;
; ASn          ; IDE_CS1n      ; 7.028  ;        ;        ; 7.028  ;
; ASn          ; IDE_D_EN_INn  ; 6.997  ;        ;        ; 6.997  ;
; ASn          ; IDE_D_EN_OUTn ; 6.835  ;        ;        ; 6.835  ;
; ASn          ; IDE_IORDn     ; 6.772  ;        ;        ; 6.772  ;
; ASn          ; IDE_IOWRn     ; 7.265  ;        ;        ; 7.265  ;
; ASn          ; JOY_RHn       ; 7.885  ;        ;        ; 7.885  ;
; ASn          ; JOY_RLn       ; 8.938  ;        ;        ; 8.938  ;
; ASn          ; JOY_WEn       ;        ; 8.789  ; 8.789  ;        ;
; ASn          ; JOY_WL        ;        ; 6.600  ; 6.600  ;        ;
; ASn          ; RAM_ADR[8]    ;        ; 8.453  ; 8.453  ;        ;
; ASn          ; RAM_BA[0]     ;        ; 7.875  ; 7.875  ;        ;
; ASn          ; RAM_BA[1]     ;        ; 7.111  ; 7.111  ;        ;
; ASn          ; RAM_CAS0n     ;        ; 7.959  ; 7.959  ;        ;
; ASn          ; RAM_CAS1n     ; 7.991  ;        ;        ; 7.991  ;
; ASn          ; RAM_DATA[0]   ; 13.771 ; 13.651 ; 13.651 ; 13.771 ;
; ASn          ; RAM_DATA[1]   ; 13.616 ; 13.407 ; 13.407 ; 13.616 ;
; ASn          ; RAM_DATA[2]   ; 13.380 ; 13.053 ; 13.053 ; 13.380 ;
; ASn          ; RAM_DATA[3]   ; 13.754 ; 13.373 ; 13.373 ; 13.754 ;
; ASn          ; RAM_DATA[4]   ; 13.176 ; 13.172 ; 13.172 ; 13.176 ;
; ASn          ; RAM_DATA[5]   ; 14.307 ; 14.632 ; 14.632 ; 14.307 ;
; ASn          ; RAM_DATA[6]   ; 13.969 ; 13.723 ; 13.723 ; 13.969 ;
; ASn          ; RAM_DATA[7]   ; 14.100 ; 13.710 ; 13.710 ; 14.100 ;
; ASn          ; RAM_DATA[8]   ; 13.923 ; 13.975 ; 13.975 ; 13.923 ;
; ASn          ; RAM_DATA[9]   ; 12.811 ; 12.891 ; 12.891 ; 12.811 ;
; ASn          ; RAM_DATA[10]  ; 12.497 ; 12.246 ; 12.246 ; 12.497 ;
; ASn          ; RAM_DATA[11]  ; 13.152 ; 13.152 ; 13.152 ; 13.152 ;
; ASn          ; RAM_DATA[12]  ; 12.938 ; 12.718 ; 12.718 ; 12.938 ;
; ASn          ; RAM_DATA[13]  ; 12.984 ; 12.984 ; 12.984 ; 12.984 ;
; ASn          ; RAM_DATA[14]  ; 13.893 ; 13.893 ; 13.893 ; 13.893 ;
; ASn          ; RAM_DATA[15]  ; 13.329 ; 13.329 ; 13.329 ; 13.329 ;
; ASn          ; RAM_DQM0H     ;        ; 8.473  ; 8.473  ;        ;
; ASn          ; RAM_DQM0L     ;        ; 8.059  ; 8.059  ;        ;
; ASn          ; RAM_DQM1H     ; 7.735  ;        ;        ; 7.735  ;
; ASn          ; RAM_DQM1L     ; 8.069  ;        ;        ; 8.069  ;
; ASn          ; RAM_RAS0n     ;        ; 8.225  ; 8.225  ;        ;
; ASn          ; RAM_RAS1n     ; 8.035  ;        ;        ; 8.035  ;
; ASn          ; ROM0n         ; 8.310  ;        ;        ; 8.310  ;
; ASn          ; ROM1n         ; 8.055  ;        ;        ; 8.055  ;
; ASn          ; ROM2n         ; 7.377  ;        ;        ; 7.377  ;
; ASn          ; ROM3n         ; 8.195  ;        ;        ; 8.195  ;
; ASn          ; ROM4n         ; 8.736  ;        ;        ; 8.736  ;
; ASn          ; ROM5n         ; 6.876  ;        ;        ; 6.876  ;
; ASn          ; ROM6n         ; 8.214  ;        ;        ; 8.214  ;
; COM_CTS      ; DATA[2]       ;        ; 9.622  ; 9.622  ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 9.828  ; 9.828  ;        ;
; COM_DCD      ; DATA[1]       ;        ; 9.709  ; 9.709  ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 9.975  ; 9.975  ;        ;
; COM_RI       ; DATA[6]       ;        ; 9.337  ; 9.337  ;        ;
; COM_RI       ; RAM_DATA[6]   ;        ; 10.399 ; 10.399 ;        ;
; CONFIG[1]    ; DATA[7]       ; 10.625 ; 10.625 ; 10.625 ; 10.625 ;
; CONFIG[1]    ; HSYNC         ; 7.064  ; 7.064  ; 7.064  ; 7.064  ;
; CONFIG[1]    ; RAM_DATA[7]   ; 11.687 ; 11.687 ; 11.687 ; 11.687 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 7.819  ; 7.819  ; 7.819  ; 7.819  ;
; CONFIG[1]    ; RAM_DATA[13]  ; 7.976  ; 7.976  ; 7.976  ; 7.976  ;
; CONFIG[1]    ; RAM_DATA[14]  ; 8.028  ; 8.028  ; 8.028  ; 8.028  ;
; CONFIG[1]    ; RAM_DATA[15]  ; 7.492  ; 7.492  ; 7.492  ; 7.492  ;
; CONFIG[1]    ; VSYNC         ; 6.943  ; 6.943  ; 6.943  ; 6.943  ;
; CONFIG[2]    ; DATA[7]       ; 10.178 ; 10.178 ; 10.178 ; 10.178 ;
; CONFIG[2]    ; HSYNC         ; 7.054  ; 7.054  ; 7.054  ; 7.054  ;
; CONFIG[2]    ; RAM_DATA[7]   ; 11.240 ; 11.240 ; 11.240 ; 11.240 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 7.914  ; 7.914  ; 7.914  ; 7.914  ;
; CONFIG[2]    ; RAM_DATA[13]  ; 8.071  ; 8.071  ; 8.071  ; 8.071  ;
; CONFIG[2]    ; RAM_DATA[14]  ; 8.123  ; 8.123  ; 8.123  ; 8.123  ;
; CONFIG[2]    ; RAM_DATA[15]  ; 7.587  ; 7.587  ; 7.587  ; 7.587  ;
; CONFIG[2]    ; VSYNC         ; 6.927  ; 6.927  ; 6.927  ; 6.927  ;
; CONFIG[3]    ; LDSn          ; 10.464 ; 10.543 ; 10.543 ; 10.464 ;
; CONFIG[3]    ; UDSn          ; 10.614 ; 10.693 ; 10.693 ; 10.614 ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 7.654  ; 7.654  ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 6.940  ; 6.940  ;        ;
; CONFIG[5]    ; ACSI_RDn      ; 11.570 ; 11.570 ; 11.570 ; 11.570 ;
; CONFIG[5]    ; ACSI_WRn      ; 11.659 ; 11.659 ; 11.659 ; 11.659 ;
; CONFIG[5]    ; BUTTONn       ; 10.596 ; 9.788  ; 9.788  ; 10.596 ;
; CONFIG[5]    ; CA1_OUT       ; 11.311 ; 10.503 ; 10.503 ; 11.311 ;
; CONFIG[5]    ; CD[0]         ; 15.452 ; 15.452 ; 15.452 ; 15.452 ;
; CONFIG[5]    ; CD[1]         ; 15.410 ; 15.410 ; 15.410 ; 15.410 ;
; CONFIG[5]    ; CD[2]         ; 14.026 ; 14.026 ; 14.026 ; 14.026 ;
; CONFIG[5]    ; CD[3]         ; 15.573 ; 15.573 ; 15.573 ; 15.573 ;
; CONFIG[5]    ; CD[4]         ; 15.469 ; 15.469 ; 15.469 ; 15.469 ;
; CONFIG[5]    ; CD[5]         ; 15.237 ; 15.237 ; 15.237 ; 15.237 ;
; CONFIG[5]    ; CD[6]         ; 15.450 ; 15.450 ; 15.450 ; 15.450 ;
; CONFIG[5]    ; CD[7]         ; 14.192 ; 14.192 ; 14.192 ; 14.192 ;
; CONFIG[5]    ; DATA[0]       ; 14.217 ; 14.156 ; 14.156 ; 14.217 ;
; CONFIG[5]    ; DATA[1]       ; 14.494 ; 14.270 ; 14.270 ; 14.494 ;
; CONFIG[5]    ; DATA[2]       ; 14.038 ; 14.105 ; 14.105 ; 14.038 ;
; CONFIG[5]    ; DATA[3]       ; 15.107 ; 14.820 ; 14.820 ; 15.107 ;
; CONFIG[5]    ; DATA[4]       ; 14.531 ; 14.474 ; 14.474 ; 14.531 ;
; CONFIG[5]    ; DATA[5]       ; 14.791 ; 14.724 ; 14.724 ; 14.791 ;
; CONFIG[5]    ; DATA[6]       ; 14.107 ; 14.022 ; 14.022 ; 14.107 ;
; CONFIG[5]    ; DATA[7]       ; 14.358 ; 14.100 ; 14.100 ; 14.358 ;
; CONFIG[5]    ; DATA[8]       ; 14.775 ; 14.827 ; 14.827 ; 14.775 ;
; CONFIG[5]    ; DATA[9]       ; 14.189 ; 14.345 ; 14.345 ; 14.189 ;
; CONFIG[5]    ; DATA[10]      ; 13.807 ; 13.661 ; 13.661 ; 13.807 ;
; CONFIG[5]    ; DATA[11]      ; 14.008 ; 14.008 ; 14.008 ; 14.008 ;
; CONFIG[5]    ; DATA[12]      ; 13.834 ; 13.759 ; 13.759 ; 13.834 ;
; CONFIG[5]    ; DATA[13]      ; 14.275 ; 14.200 ; 14.200 ; 14.275 ;
; CONFIG[5]    ; DATA[14]      ; 14.245 ; 14.245 ; 14.245 ; 14.245 ;
; CONFIG[5]    ; DATA[15]      ; 14.378 ; 14.378 ; 14.378 ; 14.378 ;
; CONFIG[5]    ; DTACKn        ; 12.006 ; 12.006 ; 12.006 ; 12.006 ;
; CONFIG[5]    ; FLASH_CEn     ; 11.402 ; 11.347 ; 11.347 ; 11.402 ;
; CONFIG[5]    ; FLASH_OEn     ; 11.415 ; 11.360 ; 11.360 ; 11.415 ;
; CONFIG[5]    ; IDE_CS0n      ; 9.657  ; 8.849  ; 8.849  ; 9.657  ;
; CONFIG[5]    ; IDE_CS1n      ; 9.983  ; 9.175  ; 9.175  ; 9.983  ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 9.738  ; 8.930  ; 8.930  ; 9.738  ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 9.790  ; 8.982  ; 8.982  ; 9.790  ;
; CONFIG[5]    ; IDE_IORDn     ; 9.813  ; 9.005  ; 9.005  ; 9.813  ;
; CONFIG[5]    ; IDE_IOWRn     ; 10.293 ; 9.485  ; 9.485  ; 10.293 ;
; CONFIG[5]    ; JOY_RHn       ; 10.535 ; 9.727  ; 9.727  ; 10.535 ;
; CONFIG[5]    ; JOY_RLn       ; 11.588 ; 10.780 ; 10.780 ; 11.588 ;
; CONFIG[5]    ; JOY_WEn       ; 10.631 ; 11.439 ; 11.439 ; 10.631 ;
; CONFIG[5]    ; JOY_WL        ; 9.159  ; 9.967  ; 9.967  ; 9.159  ;
; CONFIG[5]    ; RAM_ADR[8]    ; 11.340 ; 10.762 ; 10.762 ; 11.340 ;
; CONFIG[5]    ; RAM_BA[0]     ; 10.762 ; 10.184 ; 10.184 ; 10.762 ;
; CONFIG[5]    ; RAM_BA[1]     ; 9.998  ; 9.420  ; 9.420  ; 9.998  ;
; CONFIG[5]    ; RAM_CAS0n     ; 10.846 ; 10.268 ; 10.268 ; 10.846 ;
; CONFIG[5]    ; RAM_CAS1n     ; 10.300 ; 10.878 ; 10.878 ; 10.300 ;
; CONFIG[5]    ; RAM_DATA[0]   ; 14.969 ; 14.908 ; 14.908 ; 14.969 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 14.760 ; 14.536 ; 14.536 ; 14.760 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 14.244 ; 14.311 ; 14.311 ; 14.244 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 15.098 ; 14.811 ; 14.811 ; 15.098 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 14.336 ; 14.279 ; 14.279 ; 14.336 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 15.890 ; 15.823 ; 15.823 ; 15.890 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 15.169 ; 15.084 ; 15.084 ; 15.169 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 15.420 ; 15.162 ; 15.162 ; 15.420 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 15.653 ; 15.705 ; 15.705 ; 15.653 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 14.352 ; 14.508 ; 14.508 ; 14.352 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 14.006 ; 13.860 ; 13.860 ; 14.006 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 14.497 ; 14.497 ; 14.497 ; 14.497 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 14.353 ; 14.278 ; 14.278 ; 14.353 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 14.468 ; 14.393 ; 14.393 ; 14.468 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 15.224 ; 15.224 ; 15.224 ; 15.224 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 14.611 ; 14.611 ; 14.611 ; 14.611 ;
; CONFIG[5]    ; RAM_DQM0H     ; 11.360 ; 10.782 ; 10.782 ; 11.360 ;
; CONFIG[5]    ; RAM_DQM0L     ; 10.946 ; 10.368 ; 10.368 ; 10.946 ;
; CONFIG[5]    ; RAM_DQM1H     ; 10.044 ; 10.622 ; 10.622 ; 10.044 ;
; CONFIG[5]    ; RAM_DQM1L     ; 10.378 ; 10.956 ; 10.956 ; 10.378 ;
; CONFIG[5]    ; RAM_RAS0n     ; 11.112 ; 10.534 ; 10.534 ; 11.112 ;
; CONFIG[5]    ; RAM_RAS1n     ; 10.344 ; 10.922 ; 10.922 ; 10.344 ;
; CONFIG[5]    ; ROM0n         ; 9.614  ; 9.080  ; 9.080  ; 9.614  ;
; CONFIG[5]    ; ROM1n         ; 9.546  ; 8.825  ; 8.825  ; 9.546  ;
; CONFIG[5]    ; ROM2n         ; 10.048 ; 9.993  ; 9.993  ; 10.048 ;
; CONFIG[5]    ; ROM3n         ; 9.866  ; 9.058  ; 9.058  ; 9.866  ;
; CONFIG[5]    ; ROM4n         ; 10.273 ; 10.031 ; 10.031 ; 10.273 ;
; CONFIG[5]    ; ROM5n         ; 9.749  ; 9.279  ; 9.279  ; 9.749  ;
; CONFIG[5]    ; ROM6n         ; 9.756  ; 8.984  ; 8.984  ; 9.756  ;
; CONFIG[6]    ; DATA[0]       ; 10.893 ; 10.893 ; 10.893 ; 10.893 ;
; CONFIG[6]    ; DATA[1]       ; 10.384 ; 10.384 ; 10.384 ; 10.384 ;
; CONFIG[6]    ; DATA[2]       ; 10.893 ; 10.893 ; 10.893 ; 10.893 ;
; CONFIG[6]    ; DATA[3]       ; 10.739 ; 10.739 ; 10.739 ; 10.739 ;
; CONFIG[6]    ; DATA[4]       ; 10.770 ; 10.770 ; 10.770 ; 10.770 ;
; CONFIG[6]    ; DATA[5]       ; 11.272 ; 11.272 ; 11.272 ; 11.272 ;
; CONFIG[6]    ; DATA[6]       ; 10.678 ; 10.678 ; 10.678 ; 10.678 ;
; CONFIG[6]    ; DATA[7]       ; 10.000 ; 10.000 ; 10.000 ; 10.000 ;
; CONFIG[6]    ; DATA[8]       ; 10.939 ; 10.939 ; 10.939 ; 10.939 ;
; CONFIG[6]    ; DATA[9]       ; 10.850 ; 10.850 ; 10.850 ; 10.850 ;
; CONFIG[6]    ; DATA[10]      ; 10.525 ; 10.525 ; 10.525 ; 10.525 ;
; CONFIG[6]    ; DATA[11]      ; 10.722 ; 10.722 ; 10.722 ; 10.722 ;
; CONFIG[6]    ; DATA[12]      ; 10.322 ; 10.322 ; 10.322 ; 10.322 ;
; CONFIG[6]    ; DATA[13]      ; 10.665 ; 10.665 ; 10.665 ; 10.665 ;
; CONFIG[6]    ; DATA[14]      ; 9.744  ; 9.744  ; 9.744  ; 9.744  ;
; CONFIG[6]    ; DATA[15]      ; 10.107 ; 10.107 ; 10.107 ; 10.107 ;
; CONFIG[6]    ; DTACKn        ; 8.630  ; 8.630  ; 8.630  ; 8.630  ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 7.379  ; 7.379  ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 7.219  ; 7.219  ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 8.534  ; 8.534  ; 8.534  ; 8.534  ;
; CONFIG[6]    ; FLASH_OEn     ; 8.547  ; 8.547  ; 8.547  ; 8.547  ;
; CONFIG[6]    ; RAM_DATA[0]   ; 11.645 ; 11.645 ; 11.645 ; 11.645 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 10.650 ; 10.650 ; 10.650 ; 10.650 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 11.099 ; 11.099 ; 11.099 ; 11.099 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 10.730 ; 10.730 ; 10.730 ; 10.730 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 10.575 ; 10.575 ; 10.575 ; 10.575 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 12.371 ; 12.371 ; 12.371 ; 12.371 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 11.740 ; 11.740 ; 11.740 ; 11.740 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 11.062 ; 11.062 ; 11.062 ; 11.062 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 11.817 ; 11.817 ; 11.817 ; 11.817 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 11.013 ; 11.013 ; 11.013 ; 11.013 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 10.724 ; 10.724 ; 10.724 ; 10.724 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 11.211 ; 11.211 ; 11.211 ; 11.211 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 10.841 ; 10.841 ; 10.841 ; 10.841 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 10.858 ; 10.858 ; 10.858 ; 10.858 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 10.723 ; 10.723 ; 10.723 ; 10.723 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 10.340 ; 10.340 ; 10.340 ; 10.340 ;
; CONFIG[6]    ; ROM2n         ; 7.180  ; 7.180  ; 7.180  ; 7.180  ;
; CRT_PIN3     ; DATA[7]       ; 7.794  ; 7.794  ; 7.794  ; 7.794  ;
; CRT_PIN3     ; RAM_DATA[7]   ; 8.856  ; 8.856  ; 8.856  ; 8.856  ;
; CRT_PIN3     ; RAM_DATA[12]  ; 5.169  ; 5.169  ; 5.169  ; 5.169  ;
; CRT_PIN3     ; RAM_DATA[13]  ; 5.326  ; 5.326  ; 5.326  ; 5.326  ;
; CRT_PIN3     ; RAM_DATA[14]  ; 5.378  ; 5.378  ; 5.378  ; 5.378  ;
; CRT_PIN3     ; RAM_DATA[15]  ; 4.842  ; 4.842  ; 4.842  ; 4.842  ;
; DATA[0]      ; DATA[0]       ; 9.634  ;        ;        ; 9.634  ;
; DATA[0]      ; RAM_DATA[0]   ; 10.386 ;        ;        ; 10.386 ;
; DATA[1]      ; DATA[1]       ; 9.466  ;        ;        ; 9.466  ;
; DATA[1]      ; RAM_DATA[1]   ; 9.732  ;        ;        ; 9.732  ;
; DATA[2]      ; DATA[2]       ; 10.085 ;        ;        ; 10.085 ;
; DATA[2]      ; RAM_DATA[2]   ; 10.291 ;        ;        ; 10.291 ;
; DATA[3]      ; DATA[3]       ; 9.786  ;        ;        ; 9.786  ;
; DATA[3]      ; RAM_DATA[3]   ; 9.777  ;        ;        ; 9.777  ;
; DATA[4]      ; DATA[4]       ; 9.702  ;        ;        ; 9.702  ;
; DATA[4]      ; RAM_DATA[4]   ; 9.507  ;        ;        ; 9.507  ;
; DATA[5]      ; DATA[5]       ; 10.089 ;        ;        ; 10.089 ;
; DATA[5]      ; RAM_DATA[5]   ; 11.188 ;        ;        ; 11.188 ;
; DATA[6]      ; DATA[6]       ; 9.587  ;        ;        ; 9.587  ;
; DATA[6]      ; RAM_DATA[6]   ; 10.649 ;        ;        ; 10.649 ;
; DATA[7]      ; DATA[7]       ; 9.838  ;        ;        ; 9.838  ;
; DATA[7]      ; RAM_DATA[7]   ; 10.900 ;        ;        ; 10.900 ;
; DATA[8]      ; DATA[8]       ; 10.088 ;        ;        ; 10.088 ;
; DATA[8]      ; RAM_DATA[8]   ; 10.966 ;        ;        ; 10.966 ;
; DATA[9]      ; DATA[9]       ; 9.487  ;        ;        ; 9.487  ;
; DATA[9]      ; RAM_DATA[9]   ; 9.650  ;        ;        ; 9.650  ;
; DATA[10]     ; DATA[10]      ; 9.176  ;        ;        ; 9.176  ;
; DATA[10]     ; RAM_DATA[10]  ; 9.375  ;        ;        ; 9.375  ;
; DATA[11]     ; DATA[11]      ; 9.543  ;        ;        ; 9.543  ;
; DATA[11]     ; RAM_DATA[11]  ; 10.032 ;        ;        ; 10.032 ;
; DATA[12]     ; DATA[12]      ; 8.847  ;        ;        ; 8.847  ;
; DATA[12]     ; RAM_DATA[12]  ; 9.366  ;        ;        ; 9.366  ;
; DATA[13]     ; DATA[13]      ; 9.786  ;        ;        ; 9.786  ;
; DATA[13]     ; RAM_DATA[13]  ; 9.979  ;        ;        ; 9.979  ;
; DATA[14]     ; DATA[14]      ; 7.384  ;        ;        ; 7.384  ;
; DATA[14]     ; RAM_DATA[14]  ; 8.363  ;        ;        ; 8.363  ;
; DATA[15]     ; DATA[15]      ; 8.298  ;        ;        ; 8.298  ;
; DATA[15]     ; RAM_DATA[15]  ; 8.531  ;        ;        ; 8.531  ;
; FC[0]        ; ACSI_RDn      ; 9.832  ; 9.832  ; 9.832  ; 9.832  ;
; FC[0]        ; ACSI_WRn      ; 9.921  ; 9.921  ; 9.921  ; 9.921  ;
; FC[0]        ; BUTTONn       ; 8.705  ; 8.705  ; 8.705  ; 8.705  ;
; FC[0]        ; CA1_OUT       ; 9.573  ; 9.573  ; 9.573  ; 9.573  ;
; FC[0]        ; CD[0]         ; 13.714 ; 13.714 ; 13.714 ; 13.714 ;
; FC[0]        ; CD[1]         ; 13.672 ; 13.672 ; 13.672 ; 13.672 ;
; FC[0]        ; CD[2]         ; 12.288 ; 12.288 ; 12.288 ; 12.288 ;
; FC[0]        ; CD[3]         ; 13.835 ; 13.835 ; 13.835 ; 13.835 ;
; FC[0]        ; CD[4]         ; 13.731 ; 13.731 ; 13.731 ; 13.731 ;
; FC[0]        ; CD[5]         ; 13.499 ; 13.499 ; 13.499 ; 13.499 ;
; FC[0]        ; CD[6]         ; 13.712 ; 13.712 ; 13.712 ; 13.712 ;
; FC[0]        ; CD[7]         ; 12.454 ; 12.454 ; 12.454 ; 12.454 ;
; FC[0]        ; DATA[0]       ; 13.651 ; 13.651 ; 13.651 ; 13.651 ;
; FC[0]        ; DATA[1]       ; 13.792 ; 13.792 ; 13.792 ; 13.792 ;
; FC[0]        ; DATA[2]       ; 13.380 ; 13.380 ; 13.380 ; 13.380 ;
; FC[0]        ; DATA[3]       ; 14.444 ; 14.444 ; 14.444 ; 14.444 ;
; FC[0]        ; DATA[4]       ; 13.790 ; 13.790 ; 13.790 ; 13.790 ;
; FC[0]        ; DATA[5]       ; 13.661 ; 13.661 ; 13.661 ; 13.661 ;
; FC[0]        ; DATA[6]       ; 13.237 ; 13.237 ; 13.237 ; 13.237 ;
; FC[0]        ; DATA[7]       ; 13.652 ; 13.652 ; 13.652 ; 13.652 ;
; FC[0]        ; DATA[8]       ; 14.013 ; 14.013 ; 14.013 ; 14.013 ;
; FC[0]        ; DATA[9]       ; 13.581 ; 13.581 ; 13.581 ; 13.581 ;
; FC[0]        ; DATA[10]      ; 12.954 ; 12.954 ; 12.954 ; 12.954 ;
; FC[0]        ; DATA[11]      ; 13.249 ; 13.249 ; 13.249 ; 13.249 ;
; FC[0]        ; DATA[12]      ; 13.069 ; 13.069 ; 13.069 ; 13.069 ;
; FC[0]        ; DATA[13]      ; 13.461 ; 13.461 ; 13.461 ; 13.461 ;
; FC[0]        ; DATA[14]      ; 13.696 ; 13.696 ; 13.696 ; 13.696 ;
; FC[0]        ; DATA[15]      ; 13.775 ; 13.775 ; 13.775 ; 13.775 ;
; FC[0]        ; DTACKn        ; 10.750 ; 10.750 ; 10.750 ; 10.750 ;
; FC[0]        ; FLASH_CEn     ; 8.676  ; 8.676  ; 8.676  ; 8.676  ;
; FC[0]        ; FLASH_OEn     ; 8.689  ; 8.689  ; 8.689  ; 8.689  ;
; FC[0]        ; JOY_RHn       ; 9.710  ; 9.710  ; 9.710  ; 9.710  ;
; FC[0]        ; JOY_RLn       ; 10.763 ; 10.763 ; 10.763 ; 10.763 ;
; FC[0]        ; JOY_WEn       ; 10.614 ; 10.614 ; 10.614 ; 10.614 ;
; FC[0]        ; JOY_WL        ; 8.425  ; 8.425  ; 8.425  ; 8.425  ;
; FC[0]        ; RAM_ADR[8]    ; 8.399  ; 8.399  ; 8.399  ; 8.399  ;
; FC[0]        ; RAM_BA[0]     ; 7.821  ; 7.821  ; 7.821  ; 7.821  ;
; FC[0]        ; RAM_BA[1]     ; 7.057  ; 7.057  ; 7.057  ; 7.057  ;
; FC[0]        ; RAM_CAS0n     ; 7.905  ; 7.905  ; 7.905  ; 7.905  ;
; FC[0]        ; RAM_CAS1n     ; 7.937  ; 7.937  ; 7.937  ; 7.937  ;
; FC[0]        ; RAM_DATA[0]   ; 14.403 ; 14.403 ; 14.403 ; 14.403 ;
; FC[0]        ; RAM_DATA[1]   ; 14.058 ; 14.058 ; 14.058 ; 14.058 ;
; FC[0]        ; RAM_DATA[2]   ; 13.586 ; 13.586 ; 13.586 ; 13.586 ;
; FC[0]        ; RAM_DATA[3]   ; 14.435 ; 14.435 ; 14.435 ; 14.435 ;
; FC[0]        ; RAM_DATA[4]   ; 13.595 ; 13.595 ; 13.595 ; 13.595 ;
; FC[0]        ; RAM_DATA[5]   ; 14.760 ; 14.760 ; 14.760 ; 14.760 ;
; FC[0]        ; RAM_DATA[6]   ; 14.299 ; 14.299 ; 14.299 ; 14.299 ;
; FC[0]        ; RAM_DATA[7]   ; 14.714 ; 14.714 ; 14.714 ; 14.714 ;
; FC[0]        ; RAM_DATA[8]   ; 14.891 ; 14.891 ; 14.891 ; 14.891 ;
; FC[0]        ; RAM_DATA[9]   ; 13.744 ; 13.744 ; 13.744 ; 13.744 ;
; FC[0]        ; RAM_DATA[10]  ; 13.153 ; 13.153 ; 13.153 ; 13.153 ;
; FC[0]        ; RAM_DATA[11]  ; 13.738 ; 13.738 ; 13.738 ; 13.738 ;
; FC[0]        ; RAM_DATA[12]  ; 13.588 ; 13.588 ; 13.588 ; 13.588 ;
; FC[0]        ; RAM_DATA[13]  ; 13.654 ; 13.654 ; 13.654 ; 13.654 ;
; FC[0]        ; RAM_DATA[14]  ; 14.675 ; 14.675 ; 14.675 ; 14.675 ;
; FC[0]        ; RAM_DATA[15]  ; 14.008 ; 14.008 ; 14.008 ; 14.008 ;
; FC[0]        ; RAM_DQM0H     ; 8.419  ; 8.419  ; 8.419  ; 8.419  ;
; FC[0]        ; RAM_DQM0L     ; 8.005  ; 8.005  ; 8.005  ; 8.005  ;
; FC[0]        ; RAM_DQM1H     ; 7.681  ; 7.681  ; 7.681  ; 7.681  ;
; FC[0]        ; RAM_DQM1L     ; 8.015  ; 8.015  ; 8.015  ; 8.015  ;
; FC[0]        ; RAM_RAS0n     ; 8.171  ; 8.171  ; 8.171  ; 8.171  ;
; FC[0]        ; RAM_RAS1n     ; 7.981  ; 7.981  ; 7.981  ; 7.981  ;
; FC[0]        ; ROM0n         ; 8.255  ; 8.255  ; 8.255  ; 8.255  ;
; FC[0]        ; ROM1n         ; 8.000  ; 8.000  ; 8.000  ; 8.000  ;
; FC[0]        ; ROM2n         ; 7.322  ; 7.322  ; 7.322  ; 7.322  ;
; FC[0]        ; ROM3n         ; 8.140  ; 8.140  ; 8.140  ; 8.140  ;
; FC[0]        ; ROM4n         ; 8.681  ; 8.681  ; 8.681  ; 8.681  ;
; FC[0]        ; ROM5n         ; 6.821  ; 6.821  ; 6.821  ; 6.821  ;
; FC[0]        ; ROM6n         ; 8.159  ; 8.159  ; 8.159  ; 8.159  ;
; FC[1]        ; ACSI_RDn      ; 9.664  ; 9.664  ; 9.664  ; 9.664  ;
; FC[1]        ; ACSI_WRn      ; 9.753  ; 9.753  ; 9.753  ; 9.753  ;
; FC[1]        ; BUTTONn       ; 8.535  ; 8.535  ; 8.535  ; 8.535  ;
; FC[1]        ; CA1_OUT       ; 9.405  ; 9.405  ; 9.405  ; 9.405  ;
; FC[1]        ; CD[0]         ; 13.546 ; 13.546 ; 13.546 ; 13.546 ;
; FC[1]        ; CD[1]         ; 13.504 ; 13.504 ; 13.504 ; 13.504 ;
; FC[1]        ; CD[2]         ; 12.120 ; 12.120 ; 12.120 ; 12.120 ;
; FC[1]        ; CD[3]         ; 13.667 ; 13.667 ; 13.667 ; 13.667 ;
; FC[1]        ; CD[4]         ; 13.563 ; 13.563 ; 13.563 ; 13.563 ;
; FC[1]        ; CD[5]         ; 13.331 ; 13.331 ; 13.331 ; 13.331 ;
; FC[1]        ; CD[6]         ; 13.544 ; 13.544 ; 13.544 ; 13.544 ;
; FC[1]        ; CD[7]         ; 12.286 ; 12.286 ; 12.286 ; 12.286 ;
; FC[1]        ; DATA[0]       ; 13.353 ; 13.353 ; 13.353 ; 13.353 ;
; FC[1]        ; DATA[1]       ; 13.501 ; 13.501 ; 13.501 ; 13.501 ;
; FC[1]        ; DATA[2]       ; 13.082 ; 13.082 ; 13.082 ; 13.082 ;
; FC[1]        ; DATA[3]       ; 14.146 ; 14.146 ; 14.146 ; 14.146 ;
; FC[1]        ; DATA[4]       ; 13.492 ; 13.492 ; 13.492 ; 13.492 ;
; FC[1]        ; DATA[5]       ; 13.493 ; 13.493 ; 13.493 ; 13.493 ;
; FC[1]        ; DATA[6]       ; 12.939 ; 12.939 ; 12.939 ; 12.939 ;
; FC[1]        ; DATA[7]       ; 13.354 ; 13.354 ; 13.354 ; 13.354 ;
; FC[1]        ; DATA[8]       ; 13.840 ; 13.840 ; 13.840 ; 13.840 ;
; FC[1]        ; DATA[9]       ; 13.358 ; 13.358 ; 13.358 ; 13.358 ;
; FC[1]        ; DATA[10]      ; 12.674 ; 12.674 ; 12.674 ; 12.674 ;
; FC[1]        ; DATA[11]      ; 13.021 ; 13.021 ; 13.021 ; 13.021 ;
; FC[1]        ; DATA[12]      ; 12.844 ; 12.844 ; 12.844 ; 12.844 ;
; FC[1]        ; DATA[13]      ; 13.288 ; 13.288 ; 13.288 ; 13.288 ;
; FC[1]        ; DATA[14]      ; 13.398 ; 13.398 ; 13.398 ; 13.398 ;
; FC[1]        ; DATA[15]      ; 13.477 ; 13.477 ; 13.477 ; 13.477 ;
; FC[1]        ; DTACKn        ; 10.452 ; 10.452 ; 10.452 ; 10.452 ;
; FC[1]        ; FLASH_CEn     ; 8.498  ; 8.498  ; 8.498  ; 8.498  ;
; FC[1]        ; FLASH_OEn     ; 8.511  ; 8.511  ; 8.511  ; 8.511  ;
; FC[1]        ; JOY_RHn       ; 9.542  ; 9.542  ; 9.542  ; 9.542  ;
; FC[1]        ; JOY_RLn       ; 10.595 ; 10.595 ; 10.595 ; 10.595 ;
; FC[1]        ; JOY_WEn       ; 10.446 ; 10.446 ; 10.446 ; 10.446 ;
; FC[1]        ; JOY_WL        ; 8.257  ; 8.257  ; 8.257  ; 8.257  ;
; FC[1]        ; RAM_ADR[8]    ; 8.232  ; 8.232  ; 8.232  ; 8.232  ;
; FC[1]        ; RAM_BA[0]     ; 7.654  ; 7.654  ; 7.654  ; 7.654  ;
; FC[1]        ; RAM_BA[1]     ; 6.890  ; 6.890  ; 6.890  ; 6.890  ;
; FC[1]        ; RAM_CAS0n     ; 7.738  ; 7.738  ; 7.738  ; 7.738  ;
; FC[1]        ; RAM_CAS1n     ; 7.770  ; 7.770  ; 7.770  ; 7.770  ;
; FC[1]        ; RAM_DATA[0]   ; 14.105 ; 14.105 ; 14.105 ; 14.105 ;
; FC[1]        ; RAM_DATA[1]   ; 13.767 ; 13.767 ; 13.767 ; 13.767 ;
; FC[1]        ; RAM_DATA[2]   ; 13.288 ; 13.288 ; 13.288 ; 13.288 ;
; FC[1]        ; RAM_DATA[3]   ; 14.137 ; 14.137 ; 14.137 ; 14.137 ;
; FC[1]        ; RAM_DATA[4]   ; 13.297 ; 13.297 ; 13.297 ; 13.297 ;
; FC[1]        ; RAM_DATA[5]   ; 14.592 ; 14.592 ; 14.592 ; 14.592 ;
; FC[1]        ; RAM_DATA[6]   ; 14.001 ; 14.001 ; 14.001 ; 14.001 ;
; FC[1]        ; RAM_DATA[7]   ; 14.416 ; 14.416 ; 14.416 ; 14.416 ;
; FC[1]        ; RAM_DATA[8]   ; 14.718 ; 14.718 ; 14.718 ; 14.718 ;
; FC[1]        ; RAM_DATA[9]   ; 13.521 ; 13.521 ; 13.521 ; 13.521 ;
; FC[1]        ; RAM_DATA[10]  ; 12.873 ; 12.873 ; 12.873 ; 12.873 ;
; FC[1]        ; RAM_DATA[11]  ; 13.510 ; 13.510 ; 13.510 ; 13.510 ;
; FC[1]        ; RAM_DATA[12]  ; 13.363 ; 13.363 ; 13.363 ; 13.363 ;
; FC[1]        ; RAM_DATA[13]  ; 13.481 ; 13.481 ; 13.481 ; 13.481 ;
; FC[1]        ; RAM_DATA[14]  ; 14.377 ; 14.377 ; 14.377 ; 14.377 ;
; FC[1]        ; RAM_DATA[15]  ; 13.710 ; 13.710 ; 13.710 ; 13.710 ;
; FC[1]        ; RAM_DQM0H     ; 8.252  ; 8.252  ; 8.252  ; 8.252  ;
; FC[1]        ; RAM_DQM0L     ; 7.838  ; 7.838  ; 7.838  ; 7.838  ;
; FC[1]        ; RAM_DQM1H     ; 7.514  ; 7.514  ; 7.514  ; 7.514  ;
; FC[1]        ; RAM_DQM1L     ; 7.848  ; 7.848  ; 7.848  ; 7.848  ;
; FC[1]        ; RAM_RAS0n     ; 8.004  ; 8.004  ; 8.004  ; 8.004  ;
; FC[1]        ; RAM_RAS1n     ; 7.814  ; 7.814  ; 7.814  ; 7.814  ;
; FC[1]        ; ROM0n         ; 8.077  ; 8.077  ; 8.077  ; 8.077  ;
; FC[1]        ; ROM1n         ; 7.822  ; 7.822  ; 7.822  ; 7.822  ;
; FC[1]        ; ROM2n         ; 7.144  ; 7.144  ; 7.144  ; 7.144  ;
; FC[1]        ; ROM3n         ; 7.962  ; 7.962  ; 7.962  ; 7.962  ;
; FC[1]        ; ROM4n         ; 8.503  ; 8.503  ; 8.503  ; 8.503  ;
; FC[1]        ; ROM5n         ; 6.643  ; 6.643  ; 6.643  ; 6.643  ;
; FC[1]        ; ROM6n         ; 7.981  ; 7.981  ; 7.981  ; 7.981  ;
; FC[2]        ; ACSI_RDn      ; 9.647  ; 9.647  ; 9.647  ; 9.647  ;
; FC[2]        ; ACSI_WRn      ; 9.736  ; 9.736  ; 9.736  ; 9.736  ;
; FC[2]        ; CA1_OUT       ;        ; 9.388  ; 9.388  ;        ;
; FC[2]        ; CD[0]         ; 13.529 ; 13.529 ; 13.529 ; 13.529 ;
; FC[2]        ; CD[1]         ; 13.487 ; 13.487 ; 13.487 ; 13.487 ;
; FC[2]        ; CD[2]         ; 12.103 ; 12.103 ; 12.103 ; 12.103 ;
; FC[2]        ; CD[3]         ; 13.650 ; 13.650 ; 13.650 ; 13.650 ;
; FC[2]        ; CD[4]         ; 13.546 ; 13.546 ; 13.546 ; 13.546 ;
; FC[2]        ; CD[5]         ; 13.314 ; 13.314 ; 13.314 ; 13.314 ;
; FC[2]        ; CD[6]         ; 13.527 ; 13.527 ; 13.527 ; 13.527 ;
; FC[2]        ; CD[7]         ; 12.269 ; 12.269 ; 12.269 ; 12.269 ;
; FC[2]        ; DATA[0]       ; 12.813 ; 13.207 ; 13.207 ; 12.813 ;
; FC[2]        ; DATA[1]       ; 13.260 ; 13.484 ; 13.484 ; 13.260 ;
; FC[2]        ; DATA[2]       ; 12.790 ; 12.793 ; 12.793 ; 12.790 ;
; FC[2]        ; DATA[3]       ; 13.777 ; 14.097 ; 14.097 ; 13.777 ;
; FC[2]        ; DATA[4]       ; 13.310 ; 13.314 ; 13.314 ; 13.310 ;
; FC[2]        ; DATA[5]       ; 13.476 ; 13.284 ; 13.284 ; 13.476 ;
; FC[2]        ; DATA[6]       ; 12.604 ; 12.656 ; 12.656 ; 12.604 ;
; FC[2]        ; DATA[7]       ; 12.666 ; 12.868 ; 12.868 ; 12.666 ;
; FC[2]        ; DATA[8]       ; 13.824 ; 13.772 ; 13.772 ; 13.824 ;
; FC[2]        ; DATA[9]       ; 13.342 ; 13.186 ; 13.186 ; 13.342 ;
; FC[2]        ; DATA[10]      ; 12.658 ; 12.658 ; 12.658 ; 12.658 ;
; FC[2]        ; DATA[11]      ; 13.005 ; 13.005 ; 13.005 ; 13.005 ;
; FC[2]        ; DATA[12]      ; 12.756 ; 12.828 ; 12.828 ; 12.756 ;
; FC[2]        ; DATA[13]      ; 13.197 ; 13.272 ; 13.272 ; 13.197 ;
; FC[2]        ; DATA[14]      ; 13.235 ; 13.235 ; 13.235 ; 13.235 ;
; FC[2]        ; DATA[15]      ; 13.375 ; 13.375 ; 13.375 ; 13.375 ;
; FC[2]        ; DTACKn        ; 10.263 ; 10.263 ; 10.263 ; 10.263 ;
; FC[2]        ; JOY_RHn       ;        ; 9.525  ; 9.525  ;        ;
; FC[2]        ; JOY_RLn       ;        ; 10.578 ; 10.578 ;        ;
; FC[2]        ; JOY_WEn       ; 10.429 ;        ;        ; 10.429 ;
; FC[2]        ; JOY_WL        ; 8.240  ;        ;        ; 8.240  ;
; FC[2]        ; RAM_DATA[0]   ; 13.565 ; 13.959 ; 13.959 ; 13.565 ;
; FC[2]        ; RAM_DATA[1]   ; 13.526 ; 13.750 ; 13.750 ; 13.526 ;
; FC[2]        ; RAM_DATA[2]   ; 12.996 ; 12.999 ; 12.999 ; 12.996 ;
; FC[2]        ; RAM_DATA[3]   ; 13.768 ; 14.088 ; 14.088 ; 13.768 ;
; FC[2]        ; RAM_DATA[4]   ; 13.115 ; 13.119 ; 13.119 ; 13.115 ;
; FC[2]        ; RAM_DATA[5]   ; 14.575 ; 14.383 ; 14.383 ; 14.575 ;
; FC[2]        ; RAM_DATA[6]   ; 13.666 ; 13.718 ; 13.718 ; 13.666 ;
; FC[2]        ; RAM_DATA[7]   ; 13.728 ; 13.930 ; 13.930 ; 13.728 ;
; FC[2]        ; RAM_DATA[8]   ; 14.702 ; 14.650 ; 14.650 ; 14.702 ;
; FC[2]        ; RAM_DATA[9]   ; 13.505 ; 13.349 ; 13.349 ; 13.505 ;
; FC[2]        ; RAM_DATA[10]  ; 12.857 ; 12.857 ; 12.857 ; 12.857 ;
; FC[2]        ; RAM_DATA[11]  ; 13.494 ; 13.494 ; 13.494 ; 13.494 ;
; FC[2]        ; RAM_DATA[12]  ; 13.275 ; 13.347 ; 13.347 ; 13.275 ;
; FC[2]        ; RAM_DATA[13]  ; 13.390 ; 13.465 ; 13.465 ; 13.390 ;
; FC[2]        ; RAM_DATA[14]  ; 14.214 ; 14.214 ; 14.214 ; 14.214 ;
; FC[2]        ; RAM_DATA[15]  ; 13.608 ; 13.608 ; 13.608 ; 13.608 ;
; HDINTn       ; DATA[5]       ; 11.773 ;        ;        ; 11.773 ;
; HDINTn       ; RAM_DATA[5]   ; 12.872 ;        ;        ; 12.872 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 11.708 ; 11.708 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 12.807 ; 12.807 ;        ;
; IDE_IORDY    ; DTACKn        ; 7.994  ; 7.994  ; 7.994  ; 7.994  ;
; LDSn         ; ACSI_RDn      ; 8.956  ; 8.956  ; 8.956  ; 8.956  ;
; LDSn         ; ACSI_WRn      ; 9.045  ; 9.045  ; 9.045  ; 9.045  ;
; LDSn         ; BUTTONn       ; 9.948  ;        ;        ; 9.948  ;
; LDSn         ; CA1_OUT       ; 8.697  ;        ;        ; 8.697  ;
; LDSn         ; CD[0]         ; 12.838 ; 12.838 ; 12.838 ; 12.838 ;
; LDSn         ; CD[1]         ; 12.796 ; 12.796 ; 12.796 ; 12.796 ;
; LDSn         ; CD[2]         ; 11.412 ; 11.412 ; 11.412 ; 11.412 ;
; LDSn         ; CD[3]         ; 12.959 ; 12.959 ; 12.959 ; 12.959 ;
; LDSn         ; CD[4]         ; 12.855 ; 12.855 ; 12.855 ; 12.855 ;
; LDSn         ; CD[5]         ; 12.623 ; 12.623 ; 12.623 ; 12.623 ;
; LDSn         ; CD[6]         ; 12.836 ; 12.836 ; 12.836 ; 12.836 ;
; LDSn         ; CD[7]         ; 11.578 ; 11.578 ; 11.578 ; 11.578 ;
; LDSn         ; DATA[0]       ; 12.942 ; 13.239 ; 13.239 ; 12.942 ;
; LDSn         ; DATA[1]       ; 13.215 ; 13.538 ; 13.538 ; 13.215 ;
; LDSn         ; DATA[2]       ; 13.119 ; 13.244 ; 13.244 ; 13.119 ;
; LDSn         ; DATA[3]       ; 13.945 ; 13.779 ; 13.779 ; 13.945 ;
; LDSn         ; DATA[4]       ; 13.768 ; 13.764 ; 13.764 ; 13.768 ;
; LDSn         ; DATA[5]       ; 13.605 ; 13.930 ; 13.930 ; 13.605 ;
; LDSn         ; DATA[6]       ; 13.006 ; 13.058 ; 13.058 ; 13.006 ;
; LDSn         ; DATA[7]       ; 13.299 ; 13.034 ; 13.034 ; 13.299 ;
; LDSn         ; DATA[8]       ; 13.275 ; 13.275 ; 13.275 ; 13.275 ;
; LDSn         ; DATA[9]       ; 12.960 ; 12.960 ; 12.960 ; 12.960 ;
; LDSn         ; DATA[10]      ; 12.625 ; 12.318 ; 12.318 ; 12.625 ;
; LDSn         ; DATA[11]      ; 12.975 ; 12.975 ; 12.975 ; 12.975 ;
; LDSn         ; DATA[12]      ; 12.746 ; 12.526 ; 12.526 ; 12.746 ;
; LDSn         ; DATA[13]      ; 13.103 ; 13.103 ; 13.103 ; 13.103 ;
; LDSn         ; DATA[14]      ; 13.311 ; 13.311 ; 13.311 ; 13.311 ;
; LDSn         ; DATA[15]      ; 13.493 ; 13.493 ; 13.493 ; 13.493 ;
; LDSn         ; DTACKn        ; 9.987  ; 9.987  ; 9.987  ; 9.987  ;
; LDSn         ; IDE_IORDn     ; 6.550  ;        ;        ; 6.550  ;
; LDSn         ; IDE_IOWRn     ; 7.033  ;        ;        ; 7.033  ;
; LDSn         ; JOY_RLn       ; 8.347  ;        ;        ; 8.347  ;
; LDSn         ; JOY_WEn       ;        ; 8.198  ; 8.198  ;        ;
; LDSn         ; JOY_WL        ;        ; 7.193  ; 7.193  ;        ;
; LDSn         ; RAM_CAS0n     ; 7.109  ;        ;        ; 7.109  ;
; LDSn         ; RAM_CAS1n     ; 7.129  ;        ;        ; 7.129  ;
; LDSn         ; RAM_DATA[0]   ; 13.694 ; 13.991 ; 13.991 ; 13.694 ;
; LDSn         ; RAM_DATA[1]   ; 13.481 ; 13.804 ; 13.804 ; 13.481 ;
; LDSn         ; RAM_DATA[2]   ; 13.325 ; 13.450 ; 13.450 ; 13.325 ;
; LDSn         ; RAM_DATA[3]   ; 13.936 ; 13.770 ; 13.770 ; 13.936 ;
; LDSn         ; RAM_DATA[4]   ; 13.573 ; 13.569 ; 13.569 ; 13.573 ;
; LDSn         ; RAM_DATA[5]   ; 14.704 ; 15.029 ; 15.029 ; 14.704 ;
; LDSn         ; RAM_DATA[6]   ; 14.068 ; 14.120 ; 14.120 ; 14.068 ;
; LDSn         ; RAM_DATA[7]   ; 14.361 ; 14.096 ; 14.096 ; 14.361 ;
; LDSn         ; RAM_DATA[8]   ; 14.153 ; 14.153 ; 14.153 ; 14.153 ;
; LDSn         ; RAM_DATA[9]   ; 13.123 ; 13.123 ; 13.123 ; 13.123 ;
; LDSn         ; RAM_DATA[10]  ; 12.824 ; 12.517 ; 12.517 ; 12.824 ;
; LDSn         ; RAM_DATA[11]  ; 13.464 ; 13.464 ; 13.464 ; 13.464 ;
; LDSn         ; RAM_DATA[12]  ; 13.265 ; 13.045 ; 13.045 ; 13.265 ;
; LDSn         ; RAM_DATA[13]  ; 13.296 ; 13.296 ; 13.296 ; 13.296 ;
; LDSn         ; RAM_DATA[14]  ; 14.290 ; 14.290 ; 14.290 ; 14.290 ;
; LDSn         ; RAM_DATA[15]  ; 13.726 ; 13.726 ; 13.726 ; 13.726 ;
; LDSn         ; RAM_DQM0L     ; 7.576  ;        ;        ; 7.576  ;
; LDSn         ; RAM_DQM1L     ; 7.582  ;        ;        ; 7.582  ;
; LPT_BSY      ; DATA[0]       ; 10.303 ;        ;        ; 10.303 ;
; LPT_BSY      ; RAM_DATA[0]   ; 11.055 ;        ;        ; 11.055 ;
; LPT_D[0]     ; DATA[8]       ; 10.273 ;        ;        ; 10.273 ;
; LPT_D[0]     ; RAM_DATA[8]   ; 11.151 ;        ;        ; 11.151 ;
; LPT_D[1]     ; DATA[9]       ; 9.971  ;        ;        ; 9.971  ;
; LPT_D[1]     ; RAM_DATA[9]   ; 10.134 ;        ;        ; 10.134 ;
; LPT_D[2]     ; DATA[10]      ; 8.886  ;        ;        ; 8.886  ;
; LPT_D[2]     ; RAM_DATA[10]  ; 9.085  ;        ;        ; 9.085  ;
; LPT_D[3]     ; DATA[11]      ; 9.230  ;        ;        ; 9.230  ;
; LPT_D[3]     ; RAM_DATA[11]  ; 9.719  ;        ;        ; 9.719  ;
; LPT_D[4]     ; DATA[12]      ; 9.364  ;        ;        ; 9.364  ;
; LPT_D[4]     ; RAM_DATA[12]  ; 9.883  ;        ;        ; 9.883  ;
; LPT_D[5]     ; DATA[13]      ; 9.932  ;        ;        ; 9.932  ;
; LPT_D[5]     ; RAM_DATA[13]  ; 10.125 ;        ;        ; 10.125 ;
; LPT_D[6]     ; DATA[14]      ; 9.627  ; 9.627  ; 9.627  ; 9.627  ;
; LPT_D[6]     ; RAM_DATA[14]  ; 10.606 ; 10.606 ; 10.606 ; 10.606 ;
; LPT_D[7]     ; DATA[15]      ; 10.085 ; 10.085 ; 10.085 ; 10.085 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 10.318 ; 10.318 ; 10.318 ; 10.318 ;
; MIDI_IN      ; MIDI_TLR      ; 4.717  ;        ;        ; 4.717  ;
; RAM_DATA[0]  ; DATA[0]       ; 10.401 ;        ;        ; 10.401 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 11.153 ;        ;        ; 11.153 ;
; RAM_DATA[1]  ; DATA[1]       ; 10.335 ;        ;        ; 10.335 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 10.601 ;        ;        ; 10.601 ;
; RAM_DATA[2]  ; DATA[2]       ; 10.144 ;        ;        ; 10.144 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 10.350 ;        ;        ; 10.350 ;
; RAM_DATA[3]  ; DATA[3]       ; 10.998 ;        ;        ; 10.998 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 10.989 ;        ;        ; 10.989 ;
; RAM_DATA[4]  ; DATA[4]       ; 9.969  ;        ;        ; 9.969  ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 9.774  ;        ;        ; 9.774  ;
; RAM_DATA[5]  ; DATA[5]       ; 10.237 ;        ;        ; 10.237 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 11.336 ;        ;        ; 11.336 ;
; RAM_DATA[6]  ; DATA[6]       ; 9.403  ;        ;        ; 9.403  ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 10.465 ;        ;        ; 10.465 ;
; RAM_DATA[7]  ; DATA[7]       ; 9.942  ;        ;        ; 9.942  ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 11.004 ;        ;        ; 11.004 ;
; RAM_DATA[8]  ; DATA[8]       ; 10.883 ;        ;        ; 10.883 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 11.761 ;        ;        ; 11.761 ;
; RAM_DATA[9]  ; DATA[9]       ; 9.909  ;        ;        ; 9.909  ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 10.072 ;        ;        ; 10.072 ;
; RAM_DATA[10] ; DATA[10]      ; 9.475  ;        ;        ; 9.475  ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 9.674  ;        ;        ; 9.674  ;
; RAM_DATA[11] ; DATA[11]      ; 9.839  ;        ;        ; 9.839  ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 10.328 ;        ;        ; 10.328 ;
; RAM_DATA[12] ; DATA[12]      ; 9.414  ;        ;        ; 9.414  ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 9.933  ;        ;        ; 9.933  ;
; RAM_DATA[13] ; DATA[13]      ; 10.593 ;        ;        ; 10.593 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 10.786 ;        ;        ; 10.786 ;
; RAM_DATA[14] ; DATA[14]      ; 10.056 ; 10.056 ; 10.056 ; 10.056 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 11.035 ; 11.035 ; 11.035 ; 11.035 ;
; RAM_DATA[15] ; DATA[15]      ; 9.756  ; 9.756  ; 9.756  ; 9.756  ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 9.989  ; 9.989  ; 9.989  ; 9.989  ;
; RWn          ; ACSI_RDn      ; 9.767  ; 9.767  ; 9.767  ; 9.767  ;
; RWn          ; ACSI_WRn      ; 9.856  ; 9.856  ; 9.856  ; 9.856  ;
; RWn          ; BUTTONn       ;        ; 9.776  ; 9.776  ;        ;
; RWn          ; CA1_OUT       ;        ; 9.508  ; 9.508  ;        ;
; RWn          ; CD[0]         ; 13.649 ; 13.649 ; 13.649 ; 13.649 ;
; RWn          ; CD[1]         ; 13.607 ; 13.607 ; 13.607 ; 13.607 ;
; RWn          ; CD[2]         ; 12.223 ; 12.223 ; 12.223 ; 12.223 ;
; RWn          ; CD[3]         ; 13.770 ; 13.770 ; 13.770 ; 13.770 ;
; RWn          ; CD[4]         ; 13.666 ; 13.666 ; 13.666 ; 13.666 ;
; RWn          ; CD[5]         ; 13.434 ; 13.434 ; 13.434 ; 13.434 ;
; RWn          ; CD[6]         ; 13.647 ; 13.647 ; 13.647 ; 13.647 ;
; RWn          ; CD[7]         ; 12.389 ; 12.389 ; 12.389 ; 12.389 ;
; RWn          ; DATA[0]       ; 13.039 ; 13.327 ; 13.327 ; 13.039 ;
; RWn          ; DATA[1]       ; 13.380 ; 13.604 ; 13.604 ; 13.380 ;
; RWn          ; DATA[2]       ; 12.910 ; 13.316 ; 13.316 ; 12.910 ;
; RWn          ; DATA[3]       ; 13.897 ; 14.217 ; 14.217 ; 13.897 ;
; RWn          ; DATA[4]       ; 13.430 ; 13.434 ; 13.434 ; 13.430 ;
; RWn          ; DATA[5]       ; 13.596 ; 13.404 ; 13.404 ; 13.596 ;
; RWn          ; DATA[6]       ; 12.759 ; 13.049 ; 13.049 ; 12.759 ;
; RWn          ; DATA[7]       ; 12.788 ; 13.180 ; 13.180 ; 12.788 ;
; RWn          ; DATA[8]       ; 13.889 ; 13.941 ; 13.941 ; 13.889 ;
; RWn          ; DATA[9]       ; 13.303 ; 13.459 ; 13.459 ; 13.303 ;
; RWn          ; DATA[10]      ; 12.775 ; 12.775 ; 12.775 ; 12.775 ;
; RWn          ; DATA[11]      ; 13.122 ; 13.122 ; 13.122 ; 13.122 ;
; RWn          ; DATA[12]      ; 12.945 ; 12.873 ; 12.873 ; 12.945 ;
; RWn          ; DATA[13]      ; 13.389 ; 13.314 ; 13.314 ; 13.389 ;
; RWn          ; DATA[14]      ; 13.355 ; 13.355 ; 13.355 ; 13.355 ;
; RWn          ; DATA[15]      ; 13.492 ; 13.492 ; 13.492 ; 13.492 ;
; RWn          ; DTACKn        ; 10.380 ; 10.380 ; 10.380 ; 10.380 ;
; RWn          ; FLASH_CEn     ;        ; 8.609  ; 8.609  ;        ;
; RWn          ; FLASH_OEn     ;        ; 8.622  ; 8.622  ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 6.876  ; 6.876  ;        ;
; RWn          ; IDE_D_EN_OUTn ; 6.826  ;        ;        ; 6.826  ;
; RWn          ; IDE_IORDn     ;        ; 6.869  ; 6.869  ;        ;
; RWn          ; IDE_IOWRn     ; 7.329  ;        ;        ; 7.329  ;
; RWn          ; JOY_RHn       ;        ; 9.645  ; 9.645  ;        ;
; RWn          ; JOY_RLn       ;        ; 10.698 ; 10.698 ;        ;
; RWn          ; JOY_WEn       ; 10.549 ;        ;        ; 10.549 ;
; RWn          ; JOY_WL        ; 8.360  ; 7.143  ; 7.143  ; 8.360  ;
; RWn          ; RAM_DATA[0]   ; 13.791 ; 14.079 ; 14.079 ; 13.791 ;
; RWn          ; RAM_DATA[1]   ; 13.646 ; 13.870 ; 13.870 ; 13.646 ;
; RWn          ; RAM_DATA[2]   ; 13.116 ; 13.522 ; 13.522 ; 13.116 ;
; RWn          ; RAM_DATA[3]   ; 13.888 ; 14.208 ; 14.208 ; 13.888 ;
; RWn          ; RAM_DATA[4]   ; 13.235 ; 13.239 ; 13.239 ; 13.235 ;
; RWn          ; RAM_DATA[5]   ; 14.695 ; 14.503 ; 14.503 ; 14.695 ;
; RWn          ; RAM_DATA[6]   ; 13.821 ; 14.111 ; 14.111 ; 13.821 ;
; RWn          ; RAM_DATA[7]   ; 13.850 ; 14.242 ; 14.242 ; 13.850 ;
; RWn          ; RAM_DATA[8]   ; 14.767 ; 14.819 ; 14.819 ; 14.767 ;
; RWn          ; RAM_DATA[9]   ; 13.466 ; 13.622 ; 13.622 ; 13.466 ;
; RWn          ; RAM_DATA[10]  ; 12.974 ; 12.974 ; 12.974 ; 12.974 ;
; RWn          ; RAM_DATA[11]  ; 13.611 ; 13.611 ; 13.611 ; 13.611 ;
; RWn          ; RAM_DATA[12]  ; 13.464 ; 13.392 ; 13.392 ; 13.464 ;
; RWn          ; RAM_DATA[13]  ; 13.582 ; 13.507 ; 13.507 ; 13.582 ;
; RWn          ; RAM_DATA[14]  ; 14.334 ; 14.334 ; 14.334 ; 14.334 ;
; RWn          ; RAM_DATA[15]  ; 13.725 ; 13.725 ; 13.725 ; 13.725 ;
; RWn          ; RAM_WEn       ; 6.778  ;        ;        ; 6.778  ;
; RWn          ; ROM0n         ;        ; 8.188  ; 8.188  ;        ;
; RWn          ; ROM1n         ;        ; 7.933  ; 7.933  ;        ;
; RWn          ; ROM2n         ;        ; 7.255  ; 7.255  ;        ;
; RWn          ; ROM3n         ;        ; 8.073  ; 8.073  ;        ;
; RWn          ; ROM4n         ;        ; 8.614  ; 8.614  ;        ;
; RWn          ; ROM5n         ;        ; 6.754  ; 6.754  ;        ;
; RWn          ; ROM6n         ;        ; 8.092  ; 8.092  ;        ;
; SCSI_ACKn    ; CD[0]         ; 7.846  ; 7.846  ; 7.846  ; 7.846  ;
; SCSI_ATNn    ; CD[1]         ; 8.363  ; 8.363  ; 8.363  ; 8.363  ;
; SCSI_BSYn    ; CD[6]         ; 9.673  ; 9.673  ; 9.673  ; 9.673  ;
; SCSI_D[0]    ; CD[0]         ; 7.986  ; 7.986  ; 7.986  ; 7.986  ;
; SCSI_D[1]    ; CD[1]         ; 8.119  ; 8.119  ; 8.119  ; 8.119  ;
; SCSI_D[2]    ; CD[2]         ;        ; 8.333  ; 8.333  ;        ;
; SCSI_D[3]    ; CD[3]         ; 8.336  ; 8.336  ; 8.336  ; 8.336  ;
; SCSI_D[4]    ; CD[4]         ; 9.159  ; 9.159  ; 9.159  ; 9.159  ;
; SCSI_D[5]    ; CD[5]         ; 9.101  ; 9.101  ; 9.101  ; 9.101  ;
; SCSI_D[6]    ; CD[6]         ; 9.426  ; 9.426  ; 9.426  ; 9.426  ;
; SCSI_D[7]    ; CD[7]         ; 8.245  ; 8.245  ; 8.245  ; 8.245  ;
; SCSI_DCn     ; CD[3]         ; 9.422  ; 9.422  ; 9.422  ; 9.422  ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 8.586  ; 8.586  ; 8.586  ; 8.586  ;
; SCSI_DCn     ; SCSI_D[0]     ; 8.360  ; 8.360  ; 8.360  ; 8.360  ;
; SCSI_DCn     ; SCSI_D[1]     ; 8.360  ; 8.360  ; 8.360  ; 8.360  ;
; SCSI_DCn     ; SCSI_D[2]     ; 8.061  ; 8.061  ; 8.061  ; 8.061  ;
; SCSI_DCn     ; SCSI_D[3]     ; 8.061  ; 8.061  ; 8.061  ; 8.061  ;
; SCSI_DCn     ; SCSI_D[4]     ; 7.932  ; 7.932  ; 7.932  ; 7.932  ;
; SCSI_DCn     ; SCSI_D[5]     ; 7.932  ; 7.932  ; 7.932  ; 7.932  ;
; SCSI_DCn     ; SCSI_D[6]     ; 7.927  ; 7.927  ; 7.927  ; 7.927  ;
; SCSI_DCn     ; SCSI_D[7]     ; 7.927  ; 7.927  ; 7.927  ; 7.927  ;
; SCSI_DCn     ; SCSI_DP       ; 8.370  ; 8.370  ; 8.370  ; 8.370  ;
; SCSI_DP      ; CD[0]         ; 7.837  ; 7.837  ; 7.837  ; 7.837  ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 6.498  ; 6.498  ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 6.473  ;        ;        ; 6.473  ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 6.358  ; 6.358  ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 6.377  ;        ;        ; 6.377  ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 6.380  ; 6.380  ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 6.291  ;        ;        ; 6.291  ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 6.345  ; 6.345  ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 6.339  ;        ;        ; 6.339  ;
; SCSI_IDn[1]  ; SCSI_DP       ; 6.967  ; 6.967  ; 6.967  ; 6.967  ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 6.307  ; 6.307  ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 6.296  ; 6.296  ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 6.165  ;        ;        ; 6.165  ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 6.208  ;        ;        ; 6.208  ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 6.183  ; 6.183  ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 6.114  ; 6.114  ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 6.138  ;        ;        ; 6.138  ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 6.164  ;        ;        ; 6.164  ;
; SCSI_IDn[2]  ; SCSI_DP       ; 6.792  ; 6.792  ; 6.792  ; 6.792  ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 6.581  ; 6.581  ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 6.568  ; 6.568  ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 6.440  ; 6.440  ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 6.482  ; 6.482  ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 6.451  ;        ;        ; 6.451  ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 6.375  ;        ;        ; 6.375  ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 6.410  ;        ;        ; 6.410  ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 6.436  ;        ;        ; 6.436  ;
; SCSI_IDn[3]  ; SCSI_DP       ; 7.064  ; 7.064  ; 7.064  ; 7.064  ;
; SCSI_IOn     ; CD[2]         ;        ; 8.136  ; 8.136  ;        ;
; SCSI_IOn     ; CD[3]         ; 8.791  ; 8.791  ; 8.791  ; 8.791  ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 7.955  ; 7.955  ; 7.955  ; 7.955  ;
; SCSI_IOn     ; SCSI_D[0]     ; 7.729  ; 7.729  ; 7.729  ; 7.729  ;
; SCSI_IOn     ; SCSI_D[1]     ; 7.729  ; 7.729  ; 7.729  ; 7.729  ;
; SCSI_IOn     ; SCSI_D[2]     ; 7.430  ; 7.430  ; 7.430  ; 7.430  ;
; SCSI_IOn     ; SCSI_D[3]     ; 7.430  ; 7.430  ; 7.430  ; 7.430  ;
; SCSI_IOn     ; SCSI_D[4]     ; 7.301  ; 7.301  ; 7.301  ; 7.301  ;
; SCSI_IOn     ; SCSI_D[5]     ; 7.301  ; 7.301  ; 7.301  ; 7.301  ;
; SCSI_IOn     ; SCSI_D[6]     ; 7.296  ; 7.296  ; 7.296  ; 7.296  ;
; SCSI_IOn     ; SCSI_D[7]     ; 7.296  ; 7.296  ; 7.296  ; 7.296  ;
; SCSI_IOn     ; SCSI_DP       ; 7.739  ; 7.739  ; 7.739  ; 7.739  ;
; SCSI_IOn     ; SCSI_RDn      ; 6.315  ;        ;        ; 6.315  ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 6.741  ; 6.741  ;        ;
; SCSI_MSGn    ; CD[3]         ; 9.033  ; 9.033  ; 9.033  ; 9.033  ;
; SCSI_MSGn    ; CD[4]         ; 9.510  ; 9.510  ; 9.510  ; 9.510  ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 8.197  ; 8.197  ; 8.197  ; 8.197  ;
; SCSI_MSGn    ; SCSI_D[0]     ; 7.971  ; 7.971  ; 7.971  ; 7.971  ;
; SCSI_MSGn    ; SCSI_D[1]     ; 7.971  ; 7.971  ; 7.971  ; 7.971  ;
; SCSI_MSGn    ; SCSI_D[2]     ; 7.672  ; 7.672  ; 7.672  ; 7.672  ;
; SCSI_MSGn    ; SCSI_D[3]     ; 7.672  ; 7.672  ; 7.672  ; 7.672  ;
; SCSI_MSGn    ; SCSI_D[4]     ; 7.543  ; 7.543  ; 7.543  ; 7.543  ;
; SCSI_MSGn    ; SCSI_D[5]     ; 7.543  ; 7.543  ; 7.543  ; 7.543  ;
; SCSI_MSGn    ; SCSI_D[6]     ; 7.538  ; 7.538  ; 7.538  ; 7.538  ;
; SCSI_MSGn    ; SCSI_D[7]     ; 7.538  ; 7.538  ; 7.538  ; 7.538  ;
; SCSI_MSGn    ; SCSI_DP       ; 7.981  ; 7.981  ; 7.981  ; 7.981  ;
; SCSI_REQn    ; CD[3]         ; 9.043  ; 9.043  ; 9.043  ; 9.043  ;
; SCSI_REQn    ; CD[5]         ; 9.406  ; 9.406  ; 9.406  ; 9.406  ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 8.207  ;        ;        ; 8.207  ;
; SCSI_REQn    ; SCSI_D[0]     ; 7.981  ; 7.981  ; 7.981  ; 7.981  ;
; SCSI_REQn    ; SCSI_D[1]     ; 7.981  ; 7.981  ; 7.981  ; 7.981  ;
; SCSI_REQn    ; SCSI_D[2]     ; 7.682  ; 7.682  ; 7.682  ; 7.682  ;
; SCSI_REQn    ; SCSI_D[3]     ; 7.682  ; 7.682  ; 7.682  ; 7.682  ;
; SCSI_REQn    ; SCSI_D[4]     ; 7.553  ; 7.553  ; 7.553  ; 7.553  ;
; SCSI_REQn    ; SCSI_D[5]     ; 7.553  ; 7.553  ; 7.553  ; 7.553  ;
; SCSI_REQn    ; SCSI_D[6]     ; 7.548  ; 7.548  ; 7.548  ; 7.548  ;
; SCSI_REQn    ; SCSI_D[7]     ; 7.548  ; 7.548  ; 7.548  ; 7.548  ;
; SCSI_REQn    ; SCSI_DP       ; 7.991  ; 7.991  ; 7.991  ; 7.991  ;
; SCSI_RSTn    ; CD[7]         ;        ; 8.697  ; 8.697  ;        ;
; SCSI_SELn    ; CD[1]         ; 7.734  ; 7.734  ; 7.734  ; 7.734  ;
; SD_AVR_ENn   ; RESETn        ;        ; 7.858  ; 7.858  ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 6.964  ; 6.964  ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 6.014  ; 6.014  ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 7.086  ;        ;        ; 7.086  ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 6.502  ;        ;        ; 6.502  ;
; SD_RESETn    ; ACSI_RDn      ; 10.394 ; 10.394 ; 10.394 ; 10.394 ;
; SD_RESETn    ; ACSI_WRn      ; 10.483 ; 10.483 ; 10.483 ; 10.483 ;
; SD_RESETn    ; CA1_OUT       ; 10.135 ;        ;        ; 10.135 ;
; SD_RESETn    ; CD[0]         ; 14.276 ; 14.276 ; 14.276 ; 14.276 ;
; SD_RESETn    ; CD[1]         ; 14.234 ; 14.234 ; 14.234 ; 14.234 ;
; SD_RESETn    ; CD[2]         ; 12.850 ; 12.850 ; 12.850 ; 12.850 ;
; SD_RESETn    ; CD[3]         ; 14.397 ; 14.397 ; 14.397 ; 14.397 ;
; SD_RESETn    ; CD[4]         ; 14.293 ; 14.293 ; 14.293 ; 14.293 ;
; SD_RESETn    ; CD[5]         ; 14.061 ; 14.061 ; 14.061 ; 14.061 ;
; SD_RESETn    ; CD[6]         ; 14.274 ; 14.274 ; 14.274 ; 14.274 ;
; SD_RESETn    ; CD[7]         ; 13.016 ; 13.016 ; 13.016 ; 13.016 ;
; SD_RESETn    ; COM_TxD       ; 7.967  ; 7.967  ; 7.967  ; 7.967  ;
; SD_RESETn    ; DATA[0]       ; 12.614 ; 12.614 ; 12.614 ; 12.614 ;
; SD_RESETn    ; DATA[1]       ; 12.778 ; 12.778 ; 12.778 ; 12.778 ;
; SD_RESETn    ; DATA[2]       ; 12.524 ; 12.524 ; 12.524 ; 12.524 ;
; SD_RESETn    ; DATA[3]       ; 13.237 ; 13.228 ; 13.228 ; 13.237 ;
; SD_RESETn    ; DATA[4]       ; 12.696 ; 12.732 ; 12.732 ; 12.696 ;
; SD_RESETn    ; DATA[5]       ; 12.595 ; 12.595 ; 12.595 ; 12.595 ;
; SD_RESETn    ; DATA[6]       ; 12.018 ; 12.018 ; 12.018 ; 12.018 ;
; SD_RESETn    ; DATA[7]       ; 12.468 ; 12.468 ; 12.468 ; 12.468 ;
; SD_RESETn    ; DATA[8]       ; 11.791 ; 12.285 ; 12.285 ; 11.791 ;
; SD_RESETn    ; DATA[9]       ; 11.350 ; 11.787 ; 11.787 ; 11.350 ;
; SD_RESETn    ; DATA[10]      ; 10.859 ; 11.186 ; 11.186 ; 10.859 ;
; SD_RESETn    ; DATA[11]      ; 11.297 ; 11.513 ; 11.513 ; 11.297 ;
; SD_RESETn    ; DATA[12]      ; 11.245 ; 11.525 ; 11.525 ; 11.245 ;
; SD_RESETn    ; DATA[13]      ; 11.328 ; 11.708 ; 11.708 ; 11.328 ;
; SD_RESETn    ; DATA[14]      ; 12.192 ; 12.192 ; 12.192 ; 12.192 ;
; SD_RESETn    ; DATA[15]      ; 12.374 ; 12.374 ; 12.374 ; 12.374 ;
; SD_RESETn    ; DTACKn        ; 9.713  ; 9.713  ; 9.713  ; 9.713  ;
; SD_RESETn    ; RAM_DATA[0]   ; 13.366 ; 13.366 ; 13.366 ; 13.366 ;
; SD_RESETn    ; RAM_DATA[1]   ; 13.044 ; 13.044 ; 13.044 ; 13.044 ;
; SD_RESETn    ; RAM_DATA[2]   ; 12.730 ; 12.730 ; 12.730 ; 12.730 ;
; SD_RESETn    ; RAM_DATA[3]   ; 13.228 ; 13.219 ; 13.219 ; 13.228 ;
; SD_RESETn    ; RAM_DATA[4]   ; 12.501 ; 12.537 ; 12.537 ; 12.501 ;
; SD_RESETn    ; RAM_DATA[5]   ; 13.694 ; 13.694 ; 13.694 ; 13.694 ;
; SD_RESETn    ; RAM_DATA[6]   ; 13.080 ; 13.080 ; 13.080 ; 13.080 ;
; SD_RESETn    ; RAM_DATA[7]   ; 13.530 ; 13.530 ; 13.530 ; 13.530 ;
; SD_RESETn    ; RAM_DATA[8]   ; 12.669 ; 13.163 ; 13.163 ; 12.669 ;
; SD_RESETn    ; RAM_DATA[9]   ; 11.513 ; 11.950 ; 11.950 ; 11.513 ;
; SD_RESETn    ; RAM_DATA[10]  ; 11.058 ; 11.385 ; 11.385 ; 11.058 ;
; SD_RESETn    ; RAM_DATA[11]  ; 11.786 ; 12.002 ; 12.002 ; 11.786 ;
; SD_RESETn    ; RAM_DATA[12]  ; 11.764 ; 12.044 ; 12.044 ; 11.764 ;
; SD_RESETn    ; RAM_DATA[13]  ; 11.521 ; 11.901 ; 11.901 ; 11.521 ;
; SD_RESETn    ; RAM_DATA[14]  ; 13.171 ; 13.171 ; 13.171 ; 13.171 ;
; SD_RESETn    ; RAM_DATA[15]  ; 12.607 ; 12.607 ; 12.607 ; 12.607 ;
; UDSn         ; ACSI_RDn      ; 8.703  ; 8.703  ; 8.703  ; 8.703  ;
; UDSn         ; ACSI_WRn      ; 8.792  ; 8.792  ; 8.792  ; 8.792  ;
; UDSn         ; CA1_OUT       ; 8.444  ;        ;        ; 8.444  ;
; UDSn         ; CD[0]         ; 12.585 ; 12.585 ; 12.585 ; 12.585 ;
; UDSn         ; CD[1]         ; 12.543 ; 12.543 ; 12.543 ; 12.543 ;
; UDSn         ; CD[2]         ; 11.159 ; 11.159 ; 11.159 ; 11.159 ;
; UDSn         ; CD[3]         ; 12.706 ; 12.706 ; 12.706 ; 12.706 ;
; UDSn         ; CD[4]         ; 12.602 ; 12.602 ; 12.602 ; 12.602 ;
; UDSn         ; CD[5]         ; 12.370 ; 12.370 ; 12.370 ; 12.370 ;
; UDSn         ; CD[6]         ; 12.583 ; 12.583 ; 12.583 ; 12.583 ;
; UDSn         ; CD[7]         ; 11.325 ; 11.325 ; 11.325 ; 11.325 ;
; UDSn         ; DATA[0]       ; 12.667 ; 12.254 ; 12.254 ; 12.667 ;
; UDSn         ; DATA[1]       ; 12.998 ; 12.366 ; 12.366 ; 12.998 ;
; UDSn         ; DATA[2]       ; 12.822 ; 12.112 ; 12.112 ; 12.822 ;
; UDSn         ; DATA[3]       ; 13.411 ; 13.018 ; 13.018 ; 13.411 ;
; UDSn         ; DATA[4]       ; 12.504 ; 12.504 ; 12.504 ; 12.504 ;
; UDSn         ; DATA[5]       ; 12.684 ; 12.684 ; 12.684 ; 12.684 ;
; UDSn         ; DATA[6]       ; 12.555 ; 12.256 ; 12.256 ; 12.555 ;
; UDSn         ; DATA[7]       ; 12.686 ; 12.226 ; 12.226 ; 12.686 ;
; UDSn         ; DATA[8]       ; 12.695 ; 12.747 ; 12.747 ; 12.695 ;
; UDSn         ; DATA[9]       ; 12.262 ; 12.376 ; 12.376 ; 12.262 ;
; UDSn         ; DATA[10]      ; 11.947 ; 11.695 ; 11.695 ; 11.947 ;
; UDSn         ; DATA[11]      ; 11.928 ; 12.123 ; 12.123 ; 11.928 ;
; UDSn         ; DATA[12]      ; 12.068 ; 11.848 ; 11.848 ; 12.068 ;
; UDSn         ; DATA[13]      ; 12.286 ; 12.256 ; 12.256 ; 12.286 ;
; UDSn         ; DATA[14]      ; 12.270 ; 12.270 ; 12.270 ; 12.270 ;
; UDSn         ; DATA[15]      ; 12.349 ; 12.349 ; 12.349 ; 12.349 ;
; UDSn         ; DTACKn        ; 9.324  ; 9.324  ; 9.324  ; 9.324  ;
; UDSn         ; JOY_RHn       ; 7.060  ;        ;        ; 7.060  ;
; UDSn         ; RAM_CAS0n     ; 6.967  ;        ;        ; 6.967  ;
; UDSn         ; RAM_CAS1n     ; 6.987  ;        ;        ; 6.987  ;
; UDSn         ; RAM_DATA[0]   ; 13.419 ; 13.006 ; 13.006 ; 13.419 ;
; UDSn         ; RAM_DATA[1]   ; 13.264 ; 12.632 ; 12.632 ; 13.264 ;
; UDSn         ; RAM_DATA[2]   ; 13.028 ; 12.318 ; 12.318 ; 13.028 ;
; UDSn         ; RAM_DATA[3]   ; 13.402 ; 13.009 ; 13.009 ; 13.402 ;
; UDSn         ; RAM_DATA[4]   ; 12.309 ; 12.309 ; 12.309 ; 12.309 ;
; UDSn         ; RAM_DATA[5]   ; 13.783 ; 13.783 ; 13.783 ; 13.783 ;
; UDSn         ; RAM_DATA[6]   ; 13.617 ; 13.318 ; 13.318 ; 13.617 ;
; UDSn         ; RAM_DATA[7]   ; 13.748 ; 13.288 ; 13.288 ; 13.748 ;
; UDSn         ; RAM_DATA[8]   ; 13.573 ; 13.625 ; 13.625 ; 13.573 ;
; UDSn         ; RAM_DATA[9]   ; 12.425 ; 12.539 ; 12.539 ; 12.425 ;
; UDSn         ; RAM_DATA[10]  ; 12.146 ; 11.894 ; 11.894 ; 12.146 ;
; UDSn         ; RAM_DATA[11]  ; 12.417 ; 12.612 ; 12.612 ; 12.417 ;
; UDSn         ; RAM_DATA[12]  ; 12.587 ; 12.367 ; 12.367 ; 12.587 ;
; UDSn         ; RAM_DATA[13]  ; 12.479 ; 12.449 ; 12.449 ; 12.479 ;
; UDSn         ; RAM_DATA[14]  ; 13.249 ; 13.249 ; 13.249 ; 13.249 ;
; UDSn         ; RAM_DATA[15]  ; 12.582 ; 12.582 ; 12.582 ; 12.582 ;
; UDSn         ; RAM_DQM0H     ; 7.461  ;        ;        ; 7.461  ;
; UDSn         ; RAM_DQM1H     ; 6.725  ;        ;        ; 6.725  ;
+--------------+---------------+--------+--------+--------+--------+


+------------------------------------------------------------------+
; Minimum Propagation Delay                                        ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 8.168  ; 8.168  ; 8.168  ; 8.168  ;
; ASn          ; ACSI_WRn      ; 8.249  ; 8.249  ; 8.249  ; 8.249  ;
; ASn          ; BUTTONn       ; 9.636  ;        ;        ; 9.636  ;
; ASn          ; CA1_OUT       ; 8.253  ;        ;        ; 8.253  ;
; ASn          ; CD[0]         ; 9.254  ; 8.970  ; 8.970  ; 9.254  ;
; ASn          ; CD[1]         ; 9.331  ; 9.049  ; 9.049  ; 9.331  ;
; ASn          ; CD[2]         ; 8.631  ; 8.356  ; 8.356  ; 8.631  ;
; ASn          ; CD[3]         ; 9.355  ; 9.212  ; 9.212  ; 9.355  ;
; ASn          ; CD[4]         ; 8.751  ; 8.751  ; 8.751  ; 8.751  ;
; ASn          ; CD[5]         ; 8.358  ; 8.358  ; 8.358  ; 8.358  ;
; ASn          ; CD[6]         ; 8.472  ; 8.472  ; 8.472  ; 8.472  ;
; ASn          ; CD[7]         ; 8.870  ; 8.870  ; 8.870  ; 8.870  ;
; ASn          ; DATA[0]       ; 8.762  ; 8.762  ; 8.762  ; 8.762  ;
; ASn          ; DATA[1]       ; 8.762  ; 8.762  ; 8.762  ; 8.762  ;
; ASn          ; DATA[2]       ; 8.749  ; 8.749  ; 8.749  ; 8.749  ;
; ASn          ; DATA[3]       ; 8.749  ; 8.749  ; 8.749  ; 8.749  ;
; ASn          ; DATA[4]       ; 8.736  ; 8.736  ; 8.736  ; 8.736  ;
; ASn          ; DATA[5]       ; 8.736  ; 8.736  ; 8.736  ; 8.736  ;
; ASn          ; DATA[6]       ; 8.707  ; 8.707  ; 8.707  ; 8.707  ;
; ASn          ; DATA[7]       ; 8.697  ; 8.697  ; 8.697  ; 8.697  ;
; ASn          ; DATA[8]       ; 8.745  ; 8.745  ; 8.745  ; 8.745  ;
; ASn          ; DATA[9]       ; 8.745  ; 8.745  ; 8.745  ; 8.745  ;
; ASn          ; DATA[10]      ; 8.876  ; 8.898  ; 8.898  ; 8.876  ;
; ASn          ; DATA[11]      ; 8.898  ; 8.814  ; 8.814  ; 8.898  ;
; ASn          ; DATA[12]      ; 8.765  ; 8.877  ; 8.877  ; 8.765  ;
; ASn          ; DATA[13]      ; 8.877  ; 8.877  ; 8.877  ; 8.877  ;
; ASn          ; DATA[14]      ; 8.872  ; 8.872  ; 8.872  ; 8.872  ;
; ASn          ; DATA[15]      ; 9.026  ; 9.026  ; 9.026  ; 9.026  ;
; ASn          ; DTACKn        ; 6.952  ; 6.952  ; 6.952  ; 6.952  ;
; ASn          ; FLASH_CEn     ; 8.731  ;        ;        ; 8.731  ;
; ASn          ; FLASH_OEn     ; 8.744  ;        ;        ; 8.744  ;
; ASn          ; IDE_CS0n      ; 6.702  ;        ;        ; 6.702  ;
; ASn          ; IDE_CS1n      ; 7.028  ;        ;        ; 7.028  ;
; ASn          ; IDE_D_EN_INn  ; 6.997  ;        ;        ; 6.997  ;
; ASn          ; IDE_D_EN_OUTn ; 6.835  ;        ;        ; 6.835  ;
; ASn          ; IDE_IORDn     ; 6.772  ;        ;        ; 6.772  ;
; ASn          ; IDE_IOWRn     ; 7.265  ;        ;        ; 7.265  ;
; ASn          ; JOY_RHn       ; 7.885  ;        ;        ; 7.885  ;
; ASn          ; JOY_RLn       ; 8.938  ;        ;        ; 8.938  ;
; ASn          ; JOY_WEn       ;        ; 8.789  ; 8.789  ;        ;
; ASn          ; JOY_WL        ;        ; 6.600  ; 6.600  ;        ;
; ASn          ; RAM_ADR[8]    ;        ; 8.453  ; 8.453  ;        ;
; ASn          ; RAM_BA[0]     ;        ; 7.875  ; 7.875  ;        ;
; ASn          ; RAM_BA[1]     ;        ; 7.111  ; 7.111  ;        ;
; ASn          ; RAM_CAS0n     ;        ; 7.959  ; 7.959  ;        ;
; ASn          ; RAM_CAS1n     ; 7.991  ;        ;        ; 7.991  ;
; ASn          ; RAM_DATA[0]   ; 10.112 ; 10.112 ; 10.112 ; 10.112 ;
; ASn          ; RAM_DATA[1]   ; 9.665  ; 9.665  ; 9.665  ; 9.665  ;
; ASn          ; RAM_DATA[2]   ; 9.543  ; 9.985  ; 9.985  ; 9.543  ;
; ASn          ; RAM_DATA[3]   ; 9.769  ; 10.204 ; 10.204 ; 9.769  ;
; ASn          ; RAM_DATA[4]   ; 9.352  ; 9.771  ; 9.771  ; 9.352  ;
; ASn          ; RAM_DATA[5]   ; 10.918 ; 10.918 ; 10.918 ; 10.918 ;
; ASn          ; RAM_DATA[6]   ; 9.989  ; 10.159 ; 10.159 ; 9.989  ;
; ASn          ; RAM_DATA[7]   ; 10.211 ; 10.494 ; 10.494 ; 10.211 ;
; ASn          ; RAM_DATA[8]   ; 10.661 ; 10.801 ; 10.801 ; 10.661 ;
; ASn          ; RAM_DATA[9]   ; 9.290  ; 9.723  ; 9.723  ; 9.290  ;
; ASn          ; RAM_DATA[10]  ; 9.075  ; 9.521  ; 9.521  ; 9.075  ;
; ASn          ; RAM_DATA[11]  ; 9.794  ; 9.303  ; 9.303  ; 9.794  ;
; ASn          ; RAM_DATA[12]  ; 9.284  ; 9.777  ; 9.777  ; 9.284  ;
; ASn          ; RAM_DATA[13]  ; 9.658  ; 9.694  ; 9.694  ; 9.658  ;
; ASn          ; RAM_DATA[14]  ; 9.851  ; 9.851  ; 9.851  ; 9.851  ;
; ASn          ; RAM_DATA[15]  ; 9.468  ; 9.468  ; 9.468  ; 9.468  ;
; ASn          ; RAM_DQM0H     ;        ; 8.473  ; 8.473  ;        ;
; ASn          ; RAM_DQM0L     ;        ; 8.059  ; 8.059  ;        ;
; ASn          ; RAM_DQM1H     ; 7.735  ;        ;        ; 7.735  ;
; ASn          ; RAM_DQM1L     ; 8.069  ;        ;        ; 8.069  ;
; ASn          ; RAM_RAS0n     ;        ; 8.225  ; 8.225  ;        ;
; ASn          ; RAM_RAS1n     ; 8.035  ;        ;        ; 8.035  ;
; ASn          ; ROM0n         ; 8.310  ;        ;        ; 8.310  ;
; ASn          ; ROM1n         ; 8.055  ;        ;        ; 8.055  ;
; ASn          ; ROM2n         ; 7.377  ;        ;        ; 7.377  ;
; ASn          ; ROM3n         ; 8.195  ;        ;        ; 8.195  ;
; ASn          ; ROM4n         ; 8.736  ;        ;        ; 8.736  ;
; ASn          ; ROM5n         ; 6.876  ;        ;        ; 6.876  ;
; ASn          ; ROM6n         ; 8.214  ;        ;        ; 8.214  ;
; COM_CTS      ; DATA[2]       ;        ; 9.622  ; 9.622  ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 9.828  ; 9.828  ;        ;
; COM_DCD      ; DATA[1]       ;        ; 9.709  ; 9.709  ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 9.975  ; 9.975  ;        ;
; COM_RI       ; DATA[6]       ;        ; 9.337  ; 9.337  ;        ;
; COM_RI       ; RAM_DATA[6]   ;        ; 10.399 ; 10.399 ;        ;
; CONFIG[1]    ; DATA[7]       ; 10.625 ; 10.625 ; 10.625 ; 10.625 ;
; CONFIG[1]    ; HSYNC         ; 7.064  ; 7.064  ; 7.064  ; 7.064  ;
; CONFIG[1]    ; RAM_DATA[7]   ; 11.687 ; 11.687 ; 11.687 ; 11.687 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 7.819  ; 7.819  ; 7.819  ; 7.819  ;
; CONFIG[1]    ; RAM_DATA[13]  ; 7.976  ; 7.976  ; 7.976  ; 7.976  ;
; CONFIG[1]    ; RAM_DATA[14]  ; 8.028  ; 8.028  ; 8.028  ; 8.028  ;
; CONFIG[1]    ; RAM_DATA[15]  ; 7.492  ; 7.492  ; 7.492  ; 7.492  ;
; CONFIG[1]    ; VSYNC         ; 6.943  ; 6.943  ; 6.943  ; 6.943  ;
; CONFIG[2]    ; DATA[7]       ; 10.178 ; 10.178 ; 10.178 ; 10.178 ;
; CONFIG[2]    ; HSYNC         ; 7.054  ; 7.054  ; 7.054  ; 7.054  ;
; CONFIG[2]    ; RAM_DATA[7]   ; 11.240 ; 11.240 ; 11.240 ; 11.240 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 7.914  ; 7.914  ; 7.914  ; 7.914  ;
; CONFIG[2]    ; RAM_DATA[13]  ; 8.071  ; 8.071  ; 8.071  ; 8.071  ;
; CONFIG[2]    ; RAM_DATA[14]  ; 8.123  ; 8.123  ; 8.123  ; 8.123  ;
; CONFIG[2]    ; RAM_DATA[15]  ; 7.587  ; 7.587  ; 7.587  ; 7.587  ;
; CONFIG[2]    ; VSYNC         ; 6.927  ; 6.927  ; 6.927  ; 6.927  ;
; CONFIG[3]    ; LDSn          ; 10.464 ; 10.504 ; 10.504 ; 10.464 ;
; CONFIG[3]    ; UDSn          ; 10.614 ; 10.654 ; 10.654 ; 10.614 ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 7.654  ; 7.654  ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 6.940  ; 6.940  ;        ;
; CONFIG[5]    ; ACSI_RDn      ; 10.237 ; 10.237 ; 10.237 ; 10.237 ;
; CONFIG[5]    ; ACSI_WRn      ; 10.318 ; 10.318 ; 10.318 ; 10.318 ;
; CONFIG[5]    ; BUTTONn       ; 9.607  ; 9.607  ; 9.607  ; 9.607  ;
; CONFIG[5]    ; CA1_OUT       ; 10.322 ; 10.322 ; 10.322 ; 10.322 ;
; CONFIG[5]    ; CD[0]         ; 11.039 ; 11.039 ; 11.039 ; 11.039 ;
; CONFIG[5]    ; CD[1]         ; 11.118 ; 11.118 ; 11.118 ; 11.118 ;
; CONFIG[5]    ; CD[2]         ; 10.425 ; 10.425 ; 10.425 ; 10.425 ;
; CONFIG[5]    ; CD[3]         ; 11.281 ; 11.281 ; 11.281 ; 11.281 ;
; CONFIG[5]    ; CD[4]         ; 10.820 ; 10.820 ; 10.820 ; 10.820 ;
; CONFIG[5]    ; CD[5]         ; 10.427 ; 10.427 ; 10.427 ; 10.427 ;
; CONFIG[5]    ; CD[6]         ; 10.541 ; 10.541 ; 10.541 ; 10.541 ;
; CONFIG[5]    ; CD[7]         ; 10.939 ; 10.939 ; 10.939 ; 10.939 ;
; CONFIG[5]    ; DATA[0]       ; 8.732  ; 8.732  ; 8.732  ; 8.732  ;
; CONFIG[5]    ; DATA[1]       ; 8.732  ; 8.732  ; 8.732  ; 8.732  ;
; CONFIG[5]    ; DATA[2]       ; 8.719  ; 8.719  ; 8.719  ; 8.719  ;
; CONFIG[5]    ; DATA[3]       ; 8.719  ; 8.719  ; 8.719  ; 8.719  ;
; CONFIG[5]    ; DATA[4]       ; 8.706  ; 8.706  ; 8.706  ; 8.706  ;
; CONFIG[5]    ; DATA[5]       ; 8.706  ; 8.706  ; 8.706  ; 8.706  ;
; CONFIG[5]    ; DATA[6]       ; 8.677  ; 8.677  ; 8.677  ; 8.677  ;
; CONFIG[5]    ; DATA[7]       ; 8.667  ; 8.667  ; 8.667  ; 8.667  ;
; CONFIG[5]    ; DATA[8]       ; 8.715  ; 8.715  ; 8.715  ; 8.715  ;
; CONFIG[5]    ; DATA[9]       ; 8.715  ; 8.715  ; 8.715  ; 8.715  ;
; CONFIG[5]    ; DATA[10]      ; 8.868  ; 8.868  ; 8.868  ; 8.868  ;
; CONFIG[5]    ; DATA[11]      ; 8.868  ; 8.868  ; 8.868  ; 8.868  ;
; CONFIG[5]    ; DATA[12]      ; 8.847  ; 8.847  ; 8.847  ; 8.847  ;
; CONFIG[5]    ; DATA[13]      ; 8.847  ; 8.847  ; 8.847  ; 8.847  ;
; CONFIG[5]    ; DATA[14]      ; 9.006  ; 9.006  ; 9.006  ; 9.006  ;
; CONFIG[5]    ; DATA[15]      ; 8.996  ; 8.996  ; 8.996  ; 8.996  ;
; CONFIG[5]    ; DTACKn        ; 9.021  ; 9.021  ; 9.021  ; 9.021  ;
; CONFIG[5]    ; FLASH_CEn     ; 9.587  ; 9.587  ; 9.587  ; 9.587  ;
; CONFIG[5]    ; FLASH_OEn     ; 9.600  ; 9.600  ; 9.600  ; 9.600  ;
; CONFIG[5]    ; IDE_CS0n      ; 8.646  ; 8.646  ; 8.646  ; 8.646  ;
; CONFIG[5]    ; IDE_CS1n      ; 8.972  ; 8.972  ; 8.972  ; 8.972  ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 8.727  ; 8.727  ; 8.727  ; 8.727  ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 8.779  ; 8.779  ; 8.779  ; 8.779  ;
; CONFIG[5]    ; IDE_IORDn     ; 8.802  ; 8.802  ; 8.802  ; 8.802  ;
; CONFIG[5]    ; IDE_IOWRn     ; 9.282  ; 9.282  ; 9.282  ; 9.282  ;
; CONFIG[5]    ; JOY_RHn       ; 9.546  ; 9.546  ; 9.546  ; 9.546  ;
; CONFIG[5]    ; JOY_RLn       ; 10.599 ; 10.599 ; 10.599 ; 10.599 ;
; CONFIG[5]    ; JOY_WEn       ; 10.450 ; 10.450 ; 10.450 ; 10.450 ;
; CONFIG[5]    ; JOY_WL        ; 8.978  ; 8.978  ; 8.978  ; 8.978  ;
; CONFIG[5]    ; RAM_ADR[8]    ; 9.221  ; 8.404  ; 8.404  ; 9.221  ;
; CONFIG[5]    ; RAM_BA[0]     ; 8.643  ; 7.826  ; 7.826  ; 8.643  ;
; CONFIG[5]    ; RAM_BA[1]     ; 7.776  ; 7.062  ; 7.062  ; 7.776  ;
; CONFIG[5]    ; RAM_CAS0n     ; 8.578  ; 7.910  ; 7.910  ; 8.578  ;
; CONFIG[5]    ; RAM_CAS1n     ; 7.942  ; 8.610  ; 8.610  ; 7.942  ;
; CONFIG[5]    ; RAM_DATA[0]   ; 10.998 ; 10.998 ; 10.998 ; 10.998 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 10.812 ; 10.812 ; 10.812 ; 10.812 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 10.763 ; 10.763 ; 10.763 ; 10.763 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 11.347 ; 11.347 ; 11.347 ; 11.347 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 10.626 ; 10.626 ; 10.626 ; 10.626 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 11.538 ; 11.538 ; 11.538 ; 11.538 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 11.316 ; 11.316 ; 11.316 ; 11.316 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 11.861 ; 11.861 ; 11.861 ; 11.861 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 11.752 ; 11.752 ; 11.752 ; 11.752 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 11.077 ; 11.077 ; 11.077 ; 11.077 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 10.680 ; 10.680 ; 10.680 ; 10.680 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 10.921 ; 10.921 ; 10.921 ; 10.921 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 11.032 ; 11.032 ; 11.032 ; 11.032 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 11.404 ; 11.404 ; 11.404 ; 11.404 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 11.716 ; 11.716 ; 11.716 ; 11.716 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 11.101 ; 11.101 ; 11.101 ; 11.101 ;
; CONFIG[5]    ; RAM_DQM0H     ; 9.092  ; 8.424  ; 8.424  ; 9.092  ;
; CONFIG[5]    ; RAM_DQM0L     ; 8.678  ; 8.010  ; 8.010  ; 8.678  ;
; CONFIG[5]    ; RAM_DQM1H     ; 7.686  ; 8.354  ; 8.354  ; 7.686  ;
; CONFIG[5]    ; RAM_DQM1L     ; 8.020  ; 8.688  ; 8.688  ; 8.020  ;
; CONFIG[5]    ; RAM_RAS0n     ; 8.844  ; 8.176  ; 8.176  ; 8.844  ;
; CONFIG[5]    ; RAM_RAS1n     ; 7.986  ; 8.654  ; 8.654  ; 7.986  ;
; CONFIG[5]    ; ROM0n         ; 8.506  ; 8.506  ; 8.506  ; 8.506  ;
; CONFIG[5]    ; ROM1n         ; 8.259  ; 8.137  ; 8.137  ; 8.259  ;
; CONFIG[5]    ; ROM2n         ; 8.233  ; 8.233  ; 8.233  ; 8.233  ;
; CONFIG[5]    ; ROM3n         ; 8.936  ; 8.914  ; 8.914  ; 8.936  ;
; CONFIG[5]    ; ROM4n         ; 9.079  ; 9.101  ; 9.101  ; 9.079  ;
; CONFIG[5]    ; ROM5n         ; 8.349  ; 8.349  ; 8.349  ; 8.349  ;
; CONFIG[5]    ; ROM6n         ; 8.826  ; 8.804  ; 8.804  ; 8.826  ;
; CONFIG[6]    ; DATA[0]       ; 10.893 ; 10.893 ; 10.893 ; 10.893 ;
; CONFIG[6]    ; DATA[1]       ; 10.384 ; 10.384 ; 10.384 ; 10.384 ;
; CONFIG[6]    ; DATA[2]       ; 10.893 ; 10.893 ; 10.893 ; 10.893 ;
; CONFIG[6]    ; DATA[3]       ; 10.739 ; 10.739 ; 10.739 ; 10.739 ;
; CONFIG[6]    ; DATA[4]       ; 10.770 ; 10.770 ; 10.770 ; 10.770 ;
; CONFIG[6]    ; DATA[5]       ; 11.272 ; 11.272 ; 11.272 ; 11.272 ;
; CONFIG[6]    ; DATA[6]       ; 10.678 ; 10.678 ; 10.678 ; 10.678 ;
; CONFIG[6]    ; DATA[7]       ; 10.000 ; 10.000 ; 10.000 ; 10.000 ;
; CONFIG[6]    ; DATA[8]       ; 10.939 ; 10.939 ; 10.939 ; 10.939 ;
; CONFIG[6]    ; DATA[9]       ; 10.850 ; 10.850 ; 10.850 ; 10.850 ;
; CONFIG[6]    ; DATA[10]      ; 10.387 ; 10.387 ; 10.387 ; 10.387 ;
; CONFIG[6]    ; DATA[11]      ; 10.722 ; 10.722 ; 10.722 ; 10.722 ;
; CONFIG[6]    ; DATA[12]      ; 10.222 ; 10.222 ; 10.222 ; 10.222 ;
; CONFIG[6]    ; DATA[13]      ; 10.665 ; 10.665 ; 10.665 ; 10.665 ;
; CONFIG[6]    ; DATA[14]      ; 9.744  ; 9.744  ; 9.744  ; 9.744  ;
; CONFIG[6]    ; DATA[15]      ; 10.107 ; 10.107 ; 10.107 ; 10.107 ;
; CONFIG[6]    ; DTACKn        ; 8.630  ; 8.630  ; 8.630  ; 8.630  ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 7.379  ; 7.379  ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 7.219  ; 7.219  ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 8.534  ; 8.534  ; 8.534  ; 8.534  ;
; CONFIG[6]    ; FLASH_OEn     ; 8.547  ; 8.547  ; 8.547  ; 8.547  ;
; CONFIG[6]    ; RAM_DATA[0]   ; 11.645 ; 11.645 ; 11.645 ; 11.645 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 10.650 ; 10.650 ; 10.650 ; 10.650 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 11.099 ; 11.099 ; 11.099 ; 11.099 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 10.730 ; 10.730 ; 10.730 ; 10.730 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 10.575 ; 10.575 ; 10.575 ; 10.575 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 12.371 ; 12.371 ; 12.371 ; 12.371 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 11.740 ; 11.740 ; 11.740 ; 11.740 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 11.062 ; 11.062 ; 11.062 ; 11.062 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 11.817 ; 11.817 ; 11.817 ; 11.817 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 11.013 ; 11.013 ; 11.013 ; 11.013 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 10.586 ; 10.586 ; 10.586 ; 10.586 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 11.211 ; 11.211 ; 11.211 ; 11.211 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 10.741 ; 10.741 ; 10.741 ; 10.741 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 10.858 ; 10.858 ; 10.858 ; 10.858 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 10.723 ; 10.723 ; 10.723 ; 10.723 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 10.340 ; 10.340 ; 10.340 ; 10.340 ;
; CONFIG[6]    ; ROM2n         ; 7.180  ; 7.180  ; 7.180  ; 7.180  ;
; CRT_PIN3     ; DATA[7]       ; 7.794  ; 7.794  ; 7.794  ; 7.794  ;
; CRT_PIN3     ; RAM_DATA[7]   ; 8.856  ; 8.856  ; 8.856  ; 8.856  ;
; CRT_PIN3     ; RAM_DATA[12]  ; 5.169  ; 5.169  ; 5.169  ; 5.169  ;
; CRT_PIN3     ; RAM_DATA[13]  ; 5.326  ; 5.326  ; 5.326  ; 5.326  ;
; CRT_PIN3     ; RAM_DATA[14]  ; 5.378  ; 5.378  ; 5.378  ; 5.378  ;
; CRT_PIN3     ; RAM_DATA[15]  ; 4.842  ; 4.842  ; 4.842  ; 4.842  ;
; DATA[0]      ; DATA[0]       ; 7.216  ;        ;        ; 7.216  ;
; DATA[0]      ; RAM_DATA[0]   ; 7.968  ;        ;        ; 7.968  ;
; DATA[1]      ; DATA[1]       ; 7.819  ;        ;        ; 7.819  ;
; DATA[1]      ; RAM_DATA[1]   ; 8.085  ;        ;        ; 8.085  ;
; DATA[2]      ; DATA[2]       ; 7.325  ;        ;        ; 7.325  ;
; DATA[2]      ; RAM_DATA[2]   ; 7.531  ;        ;        ; 7.531  ;
; DATA[3]      ; DATA[3]       ; 7.976  ;        ;        ; 7.976  ;
; DATA[3]      ; RAM_DATA[3]   ; 7.967  ;        ;        ; 7.967  ;
; DATA[4]      ; DATA[4]       ; 7.874  ;        ;        ; 7.874  ;
; DATA[4]      ; RAM_DATA[4]   ; 7.679  ;        ;        ; 7.679  ;
; DATA[5]      ; DATA[5]       ; 8.047  ;        ;        ; 8.047  ;
; DATA[5]      ; RAM_DATA[5]   ; 9.146  ;        ;        ; 9.146  ;
; DATA[6]      ; DATA[6]       ; 7.751  ;        ;        ; 7.751  ;
; DATA[6]      ; RAM_DATA[6]   ; 8.813  ;        ;        ; 8.813  ;
; DATA[7]      ; DATA[7]       ; 8.412  ;        ;        ; 8.412  ;
; DATA[7]      ; RAM_DATA[7]   ; 9.474  ;        ;        ; 9.474  ;
; DATA[8]      ; DATA[8]       ; 7.911  ;        ;        ; 7.911  ;
; DATA[8]      ; RAM_DATA[8]   ; 8.789  ;        ;        ; 8.789  ;
; DATA[9]      ; DATA[9]       ; 7.495  ;        ;        ; 7.495  ;
; DATA[9]      ; RAM_DATA[9]   ; 7.658  ;        ;        ; 7.658  ;
; DATA[10]     ; DATA[10]      ; 6.988  ;        ;        ; 6.988  ;
; DATA[10]     ; RAM_DATA[10]  ; 7.187  ;        ;        ; 7.187  ;
; DATA[11]     ; DATA[11]      ; 7.704  ;        ;        ; 7.704  ;
; DATA[11]     ; RAM_DATA[11]  ; 8.193  ;        ;        ; 8.193  ;
; DATA[12]     ; DATA[12]      ; 7.903  ;        ;        ; 7.903  ;
; DATA[12]     ; RAM_DATA[12]  ; 8.422  ;        ;        ; 8.422  ;
; DATA[13]     ; DATA[13]      ; 7.910  ;        ;        ; 7.910  ;
; DATA[13]     ; RAM_DATA[13]  ; 8.103  ;        ;        ; 8.103  ;
; DATA[14]     ; DATA[14]      ; 7.384  ;        ;        ; 7.384  ;
; DATA[14]     ; RAM_DATA[14]  ; 8.363  ;        ;        ; 8.363  ;
; DATA[15]     ; DATA[15]      ; 8.298  ;        ;        ; 8.298  ;
; DATA[15]     ; RAM_DATA[15]  ; 8.531  ;        ;        ; 8.531  ;
; FC[0]        ; ACSI_RDn      ; 9.488  ; 9.488  ; 9.488  ; 9.488  ;
; FC[0]        ; ACSI_WRn      ; 9.569  ; 9.569  ; 9.569  ; 9.569  ;
; FC[0]        ; BUTTONn       ; 8.705  ; 8.705  ; 8.705  ; 8.705  ;
; FC[0]        ; CA1_OUT       ; 9.573  ; 9.573  ; 9.573  ; 9.573  ;
; FC[0]        ; CD[0]         ; 10.290 ; 10.290 ; 10.290 ; 10.290 ;
; FC[0]        ; CD[1]         ; 10.369 ; 10.369 ; 10.369 ; 10.369 ;
; FC[0]        ; CD[2]         ; 9.676  ; 9.676  ; 9.676  ; 9.676  ;
; FC[0]        ; CD[3]         ; 10.532 ; 10.532 ; 10.532 ; 10.532 ;
; FC[0]        ; CD[4]         ; 10.071 ; 10.071 ; 10.071 ; 10.071 ;
; FC[0]        ; CD[5]         ; 9.678  ; 9.678  ; 9.678  ; 9.678  ;
; FC[0]        ; CD[6]         ; 9.792  ; 9.792  ; 9.792  ; 9.792  ;
; FC[0]        ; CD[7]         ; 10.190 ; 10.190 ; 10.190 ; 10.190 ;
; FC[0]        ; DATA[0]       ; 9.026  ; 9.026  ; 9.026  ; 9.026  ;
; FC[0]        ; DATA[1]       ; 8.757  ; 8.757  ; 8.757  ; 8.757  ;
; FC[0]        ; DATA[2]       ; 8.638  ; 8.638  ; 8.638  ; 8.638  ;
; FC[0]        ; DATA[3]       ; 9.079  ; 9.079  ; 9.079  ; 9.079  ;
; FC[0]        ; DATA[4]       ; 8.848  ; 8.848  ; 8.848  ; 8.848  ;
; FC[0]        ; DATA[5]       ; 10.167 ; 10.167 ; 10.167 ; 10.167 ;
; FC[0]        ; DATA[6]       ; 8.228  ; 8.228  ; 8.228  ; 8.228  ;
; FC[0]        ; DATA[7]       ; 8.450  ; 8.450  ; 8.450  ; 8.450  ;
; FC[0]        ; DATA[8]       ; 9.159  ; 9.159  ; 9.159  ; 9.159  ;
; FC[0]        ; DATA[9]       ; 8.428  ; 8.428  ; 8.428  ; 8.428  ;
; FC[0]        ; DATA[10]      ; 8.177  ; 8.177  ; 8.177  ; 8.177  ;
; FC[0]        ; DATA[11]      ; 8.606  ; 8.606  ; 8.606  ; 8.606  ;
; FC[0]        ; DATA[12]      ; 8.066  ; 8.066  ; 8.066  ; 8.066  ;
; FC[0]        ; DATA[13]      ; 8.766  ; 8.766  ; 8.766  ; 8.766  ;
; FC[0]        ; DATA[14]      ; 8.528  ; 8.528  ; 8.528  ; 8.528  ;
; FC[0]        ; DATA[15]      ; 8.490  ; 8.490  ; 8.490  ; 8.490  ;
; FC[0]        ; DTACKn        ; 7.281  ; 7.281  ; 7.281  ; 7.281  ;
; FC[0]        ; FLASH_CEn     ; 8.676  ; 8.676  ; 8.676  ; 8.676  ;
; FC[0]        ; FLASH_OEn     ; 8.689  ; 8.689  ; 8.689  ; 8.689  ;
; FC[0]        ; JOY_RHn       ; 9.710  ; 9.710  ; 9.710  ; 9.710  ;
; FC[0]        ; JOY_RLn       ; 10.763 ; 10.763 ; 10.763 ; 10.763 ;
; FC[0]        ; JOY_WEn       ; 10.614 ; 10.614 ; 10.614 ; 10.614 ;
; FC[0]        ; JOY_WL        ; 8.425  ; 8.425  ; 8.425  ; 8.425  ;
; FC[0]        ; RAM_ADR[8]    ; 8.399  ; 8.399  ; 8.399  ; 8.399  ;
; FC[0]        ; RAM_BA[0]     ; 7.821  ; 7.821  ; 7.821  ; 7.821  ;
; FC[0]        ; RAM_BA[1]     ; 7.057  ; 7.057  ; 7.057  ; 7.057  ;
; FC[0]        ; RAM_CAS0n     ; 7.905  ; 7.905  ; 7.905  ; 7.905  ;
; FC[0]        ; RAM_CAS1n     ; 7.937  ; 7.937  ; 7.937  ; 7.937  ;
; FC[0]        ; RAM_DATA[0]   ; 9.778  ; 9.778  ; 9.778  ; 9.778  ;
; FC[0]        ; RAM_DATA[1]   ; 9.023  ; 9.023  ; 9.023  ; 9.023  ;
; FC[0]        ; RAM_DATA[2]   ; 8.844  ; 8.844  ; 8.844  ; 8.844  ;
; FC[0]        ; RAM_DATA[3]   ; 9.070  ; 9.070  ; 9.070  ; 9.070  ;
; FC[0]        ; RAM_DATA[4]   ; 8.653  ; 8.653  ; 8.653  ; 8.653  ;
; FC[0]        ; RAM_DATA[5]   ; 11.266 ; 11.266 ; 11.266 ; 11.266 ;
; FC[0]        ; RAM_DATA[6]   ; 9.290  ; 9.290  ; 9.290  ; 9.290  ;
; FC[0]        ; RAM_DATA[7]   ; 9.512  ; 9.512  ; 9.512  ; 9.512  ;
; FC[0]        ; RAM_DATA[8]   ; 10.037 ; 10.037 ; 10.037 ; 10.037 ;
; FC[0]        ; RAM_DATA[9]   ; 8.591  ; 8.591  ; 8.591  ; 8.591  ;
; FC[0]        ; RAM_DATA[10]  ; 8.376  ; 8.376  ; 8.376  ; 8.376  ;
; FC[0]        ; RAM_DATA[11]  ; 9.095  ; 9.095  ; 9.095  ; 9.095  ;
; FC[0]        ; RAM_DATA[12]  ; 8.585  ; 8.585  ; 8.585  ; 8.585  ;
; FC[0]        ; RAM_DATA[13]  ; 8.959  ; 8.959  ; 8.959  ; 8.959  ;
; FC[0]        ; RAM_DATA[14]  ; 9.507  ; 9.507  ; 9.507  ; 9.507  ;
; FC[0]        ; RAM_DATA[15]  ; 8.723  ; 8.723  ; 8.723  ; 8.723  ;
; FC[0]        ; RAM_DQM0H     ; 8.419  ; 8.419  ; 8.419  ; 8.419  ;
; FC[0]        ; RAM_DQM0L     ; 8.005  ; 8.005  ; 8.005  ; 8.005  ;
; FC[0]        ; RAM_DQM1H     ; 7.681  ; 7.681  ; 7.681  ; 7.681  ;
; FC[0]        ; RAM_DQM1L     ; 8.015  ; 8.015  ; 8.015  ; 8.015  ;
; FC[0]        ; RAM_RAS0n     ; 8.171  ; 8.171  ; 8.171  ; 8.171  ;
; FC[0]        ; RAM_RAS1n     ; 7.981  ; 7.981  ; 7.981  ; 7.981  ;
; FC[0]        ; ROM0n         ; 8.255  ; 8.255  ; 8.255  ; 8.255  ;
; FC[0]        ; ROM1n         ; 8.000  ; 8.000  ; 8.000  ; 8.000  ;
; FC[0]        ; ROM2n         ; 7.322  ; 7.322  ; 7.322  ; 7.322  ;
; FC[0]        ; ROM3n         ; 8.140  ; 8.140  ; 8.140  ; 8.140  ;
; FC[0]        ; ROM4n         ; 8.681  ; 8.681  ; 8.681  ; 8.681  ;
; FC[0]        ; ROM5n         ; 6.821  ; 6.821  ; 6.821  ; 6.821  ;
; FC[0]        ; ROM6n         ; 8.159  ; 8.159  ; 8.159  ; 8.159  ;
; FC[1]        ; ACSI_RDn      ; 9.320  ; 9.320  ; 9.320  ; 9.320  ;
; FC[1]        ; ACSI_WRn      ; 9.401  ; 9.401  ; 9.401  ; 9.401  ;
; FC[1]        ; BUTTONn       ; 8.535  ; 8.535  ; 8.535  ; 8.535  ;
; FC[1]        ; CA1_OUT       ; 9.405  ; 9.405  ; 9.405  ; 9.405  ;
; FC[1]        ; CD[0]         ; 10.122 ; 10.122 ; 10.122 ; 10.122 ;
; FC[1]        ; CD[1]         ; 10.201 ; 10.201 ; 10.201 ; 10.201 ;
; FC[1]        ; CD[2]         ; 9.508  ; 9.508  ; 9.508  ; 9.508  ;
; FC[1]        ; CD[3]         ; 10.364 ; 10.364 ; 10.364 ; 10.364 ;
; FC[1]        ; CD[4]         ; 9.903  ; 9.903  ; 9.903  ; 9.903  ;
; FC[1]        ; CD[5]         ; 9.510  ; 9.510  ; 9.510  ; 9.510  ;
; FC[1]        ; CD[6]         ; 9.624  ; 9.624  ; 9.624  ; 9.624  ;
; FC[1]        ; CD[7]         ; 10.022 ; 10.022 ; 10.022 ; 10.022 ;
; FC[1]        ; DATA[0]       ; 9.031  ; 9.031  ; 9.031  ; 9.031  ;
; FC[1]        ; DATA[1]       ; 8.762  ; 8.762  ; 8.762  ; 8.762  ;
; FC[1]        ; DATA[2]       ; 8.643  ; 8.643  ; 8.643  ; 8.643  ;
; FC[1]        ; DATA[3]       ; 9.084  ; 9.084  ; 9.084  ; 9.084  ;
; FC[1]        ; DATA[4]       ; 8.853  ; 8.853  ; 8.853  ; 8.853  ;
; FC[1]        ; DATA[5]       ; 9.997  ; 9.997  ; 9.997  ; 9.997  ;
; FC[1]        ; DATA[6]       ; 8.233  ; 8.233  ; 8.233  ; 8.233  ;
; FC[1]        ; DATA[7]       ; 8.455  ; 8.455  ; 8.455  ; 8.455  ;
; FC[1]        ; DATA[8]       ; 9.164  ; 9.164  ; 9.164  ; 9.164  ;
; FC[1]        ; DATA[9]       ; 8.433  ; 8.433  ; 8.433  ; 8.433  ;
; FC[1]        ; DATA[10]      ; 8.182  ; 8.182  ; 8.182  ; 8.182  ;
; FC[1]        ; DATA[11]      ; 8.611  ; 8.611  ; 8.611  ; 8.611  ;
; FC[1]        ; DATA[12]      ; 8.071  ; 8.071  ; 8.071  ; 8.071  ;
; FC[1]        ; DATA[13]      ; 8.771  ; 8.771  ; 8.771  ; 8.771  ;
; FC[1]        ; DATA[14]      ; 8.533  ; 8.533  ; 8.533  ; 8.533  ;
; FC[1]        ; DATA[15]      ; 8.495  ; 8.495  ; 8.495  ; 8.495  ;
; FC[1]        ; DTACKn        ; 7.111  ; 7.111  ; 7.111  ; 7.111  ;
; FC[1]        ; FLASH_CEn     ; 8.498  ; 8.498  ; 8.498  ; 8.498  ;
; FC[1]        ; FLASH_OEn     ; 8.511  ; 8.511  ; 8.511  ; 8.511  ;
; FC[1]        ; JOY_RHn       ; 9.542  ; 9.542  ; 9.542  ; 9.542  ;
; FC[1]        ; JOY_RLn       ; 10.595 ; 10.595 ; 10.595 ; 10.595 ;
; FC[1]        ; JOY_WEn       ; 10.446 ; 10.446 ; 10.446 ; 10.446 ;
; FC[1]        ; JOY_WL        ; 8.257  ; 8.257  ; 8.257  ; 8.257  ;
; FC[1]        ; RAM_ADR[8]    ; 8.232  ; 8.232  ; 8.232  ; 8.232  ;
; FC[1]        ; RAM_BA[0]     ; 7.654  ; 7.654  ; 7.654  ; 7.654  ;
; FC[1]        ; RAM_BA[1]     ; 6.890  ; 6.890  ; 6.890  ; 6.890  ;
; FC[1]        ; RAM_CAS0n     ; 7.738  ; 7.738  ; 7.738  ; 7.738  ;
; FC[1]        ; RAM_CAS1n     ; 7.770  ; 7.770  ; 7.770  ; 7.770  ;
; FC[1]        ; RAM_DATA[0]   ; 9.783  ; 9.783  ; 9.783  ; 9.783  ;
; FC[1]        ; RAM_DATA[1]   ; 9.028  ; 9.028  ; 9.028  ; 9.028  ;
; FC[1]        ; RAM_DATA[2]   ; 8.849  ; 8.849  ; 8.849  ; 8.849  ;
; FC[1]        ; RAM_DATA[3]   ; 9.075  ; 9.075  ; 9.075  ; 9.075  ;
; FC[1]        ; RAM_DATA[4]   ; 8.658  ; 8.658  ; 8.658  ; 8.658  ;
; FC[1]        ; RAM_DATA[5]   ; 11.096 ; 11.096 ; 11.096 ; 11.096 ;
; FC[1]        ; RAM_DATA[6]   ; 9.295  ; 9.295  ; 9.295  ; 9.295  ;
; FC[1]        ; RAM_DATA[7]   ; 9.517  ; 9.517  ; 9.517  ; 9.517  ;
; FC[1]        ; RAM_DATA[8]   ; 10.042 ; 10.042 ; 10.042 ; 10.042 ;
; FC[1]        ; RAM_DATA[9]   ; 8.596  ; 8.596  ; 8.596  ; 8.596  ;
; FC[1]        ; RAM_DATA[10]  ; 8.381  ; 8.381  ; 8.381  ; 8.381  ;
; FC[1]        ; RAM_DATA[11]  ; 9.100  ; 9.100  ; 9.100  ; 9.100  ;
; FC[1]        ; RAM_DATA[12]  ; 8.590  ; 8.590  ; 8.590  ; 8.590  ;
; FC[1]        ; RAM_DATA[13]  ; 8.964  ; 8.964  ; 8.964  ; 8.964  ;
; FC[1]        ; RAM_DATA[14]  ; 9.512  ; 9.512  ; 9.512  ; 9.512  ;
; FC[1]        ; RAM_DATA[15]  ; 8.728  ; 8.728  ; 8.728  ; 8.728  ;
; FC[1]        ; RAM_DQM0H     ; 8.252  ; 8.252  ; 8.252  ; 8.252  ;
; FC[1]        ; RAM_DQM0L     ; 7.838  ; 7.838  ; 7.838  ; 7.838  ;
; FC[1]        ; RAM_DQM1H     ; 7.514  ; 7.514  ; 7.514  ; 7.514  ;
; FC[1]        ; RAM_DQM1L     ; 7.848  ; 7.848  ; 7.848  ; 7.848  ;
; FC[1]        ; RAM_RAS0n     ; 8.004  ; 8.004  ; 8.004  ; 8.004  ;
; FC[1]        ; RAM_RAS1n     ; 7.814  ; 7.814  ; 7.814  ; 7.814  ;
; FC[1]        ; ROM0n         ; 8.077  ; 8.077  ; 8.077  ; 8.077  ;
; FC[1]        ; ROM1n         ; 7.822  ; 7.822  ; 7.822  ; 7.822  ;
; FC[1]        ; ROM2n         ; 7.144  ; 7.144  ; 7.144  ; 7.144  ;
; FC[1]        ; ROM3n         ; 7.962  ; 7.962  ; 7.962  ; 7.962  ;
; FC[1]        ; ROM4n         ; 8.503  ; 8.503  ; 8.503  ; 8.503  ;
; FC[1]        ; ROM5n         ; 6.643  ; 6.643  ; 6.643  ; 6.643  ;
; FC[1]        ; ROM6n         ; 7.981  ; 7.981  ; 7.981  ; 7.981  ;
; FC[2]        ; ACSI_RDn      ; 9.303  ; 9.303  ; 9.303  ; 9.303  ;
; FC[2]        ; ACSI_WRn      ; 9.384  ; 9.384  ; 9.384  ; 9.384  ;
; FC[2]        ; CA1_OUT       ;        ; 9.388  ; 9.388  ;        ;
; FC[2]        ; CD[0]         ; 10.105 ; 10.389 ; 10.389 ; 10.105 ;
; FC[2]        ; CD[1]         ; 10.184 ; 10.466 ; 10.466 ; 10.184 ;
; FC[2]        ; CD[2]         ; 9.491  ; 9.766  ; 9.766  ; 9.491  ;
; FC[2]        ; CD[3]         ; 10.347 ; 10.490 ; 10.490 ; 10.347 ;
; FC[2]        ; CD[4]         ; 9.886  ; 9.886  ; 9.886  ; 9.886  ;
; FC[2]        ; CD[5]         ; 9.493  ; 9.493  ; 9.493  ; 9.493  ;
; FC[2]        ; CD[6]         ; 9.607  ; 9.607  ; 9.607  ; 9.607  ;
; FC[2]        ; CD[7]         ; 10.005 ; 10.005 ; 10.005 ; 10.005 ;
; FC[2]        ; DATA[0]       ; 9.967  ; 9.967  ; 9.967  ; 9.967  ;
; FC[2]        ; DATA[1]       ; 10.006 ; 10.006 ; 10.006 ; 10.006 ;
; FC[2]        ; DATA[2]       ; 10.728 ; 10.195 ; 10.195 ; 10.728 ;
; FC[2]        ; DATA[3]       ; 11.369 ; 10.636 ; 10.636 ; 11.369 ;
; FC[2]        ; DATA[4]       ; 11.086 ; 10.405 ; 10.405 ; 11.086 ;
; FC[2]        ; DATA[5]       ; 10.880 ; 10.535 ; 10.535 ; 10.880 ;
; FC[2]        ; DATA[6]       ; 10.158 ; 9.635  ; 9.635  ; 10.158 ;
; FC[2]        ; DATA[7]       ; 10.463 ; 10.007 ; 10.007 ; 10.463 ;
; FC[2]        ; DATA[8]       ; 11.514 ; 10.557 ; 10.557 ; 11.514 ;
; FC[2]        ; DATA[9]       ; 11.151 ; 9.985  ; 9.985  ; 11.151 ;
; FC[2]        ; DATA[10]      ; 10.622 ; 9.734  ; 9.734  ; 10.622 ;
; FC[2]        ; DATA[11]      ; 10.935 ; 10.081 ; 10.081 ; 10.935 ;
; FC[2]        ; DATA[12]      ; 10.849 ; 9.623  ; 9.623  ; 10.849 ;
; FC[2]        ; DATA[13]      ; 11.092 ; 10.323 ; 10.323 ; 11.092 ;
; FC[2]        ; DATA[14]      ; 9.766  ; 9.766  ; 9.766  ; 9.766  ;
; FC[2]        ; DATA[15]      ; 10.022 ; 10.022 ; 10.022 ; 10.022 ;
; FC[2]        ; DTACKn        ; 8.014  ; 8.014  ; 8.014  ; 8.014  ;
; FC[2]        ; JOY_RHn       ;        ; 9.525  ; 9.525  ;        ;
; FC[2]        ; JOY_RLn       ;        ; 10.578 ; 10.578 ;        ;
; FC[2]        ; JOY_WEn       ; 10.429 ;        ;        ; 10.429 ;
; FC[2]        ; JOY_WL        ; 8.240  ;        ;        ; 8.240  ;
; FC[2]        ; RAM_DATA[0]   ; 10.719 ; 10.719 ; 10.719 ; 10.719 ;
; FC[2]        ; RAM_DATA[1]   ; 10.272 ; 10.272 ; 10.272 ; 10.272 ;
; FC[2]        ; RAM_DATA[2]   ; 10.934 ; 10.401 ; 10.401 ; 10.934 ;
; FC[2]        ; RAM_DATA[3]   ; 11.360 ; 10.627 ; 10.627 ; 11.360 ;
; FC[2]        ; RAM_DATA[4]   ; 10.891 ; 10.210 ; 10.210 ; 10.891 ;
; FC[2]        ; RAM_DATA[5]   ; 11.979 ; 11.634 ; 11.634 ; 11.979 ;
; FC[2]        ; RAM_DATA[6]   ; 11.220 ; 10.697 ; 10.697 ; 11.220 ;
; FC[2]        ; RAM_DATA[7]   ; 11.525 ; 11.069 ; 11.069 ; 11.525 ;
; FC[2]        ; RAM_DATA[8]   ; 12.392 ; 11.435 ; 11.435 ; 12.392 ;
; FC[2]        ; RAM_DATA[9]   ; 11.314 ; 10.148 ; 10.148 ; 11.314 ;
; FC[2]        ; RAM_DATA[10]  ; 10.821 ; 9.933  ; 9.933  ; 10.821 ;
; FC[2]        ; RAM_DATA[11]  ; 11.424 ; 10.570 ; 10.570 ; 11.424 ;
; FC[2]        ; RAM_DATA[12]  ; 11.368 ; 10.142 ; 10.142 ; 11.368 ;
; FC[2]        ; RAM_DATA[13]  ; 11.285 ; 10.516 ; 10.516 ; 11.285 ;
; FC[2]        ; RAM_DATA[14]  ; 10.745 ; 10.745 ; 10.745 ; 10.745 ;
; FC[2]        ; RAM_DATA[15]  ; 10.255 ; 10.255 ; 10.255 ; 10.255 ;
; HDINTn       ; DATA[5]       ; 11.773 ;        ;        ; 11.773 ;
; HDINTn       ; RAM_DATA[5]   ; 12.872 ;        ;        ; 12.872 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 11.708 ; 11.708 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 12.807 ; 12.807 ;        ;
; IDE_IORDY    ; DTACKn        ; 7.994  ; 7.994  ; 7.994  ; 7.994  ;
; LDSn         ; ACSI_RDn      ; 8.612  ; 8.612  ; 8.612  ; 8.612  ;
; LDSn         ; ACSI_WRn      ; 8.693  ; 8.693  ; 8.693  ; 8.693  ;
; LDSn         ; BUTTONn       ; 9.948  ;        ;        ; 9.948  ;
; LDSn         ; CA1_OUT       ; 8.697  ;        ;        ; 8.697  ;
; LDSn         ; CD[0]         ; 9.698  ; 9.414  ; 9.414  ; 9.698  ;
; LDSn         ; CD[1]         ; 9.775  ; 9.493  ; 9.493  ; 9.775  ;
; LDSn         ; CD[2]         ; 9.075  ; 8.800  ; 8.800  ; 9.075  ;
; LDSn         ; CD[3]         ; 9.799  ; 9.656  ; 9.656  ; 9.799  ;
; LDSn         ; CD[4]         ; 9.195  ; 9.195  ; 9.195  ; 9.195  ;
; LDSn         ; CD[5]         ; 8.802  ; 8.802  ; 8.802  ; 8.802  ;
; LDSn         ; CD[6]         ; 8.916  ; 8.916  ; 8.916  ; 8.916  ;
; LDSn         ; CD[7]         ; 9.314  ; 9.314  ; 9.314  ; 9.314  ;
; LDSn         ; DATA[0]       ; 9.089  ; 9.089  ; 9.089  ; 9.089  ;
; LDSn         ; DATA[1]       ; 9.089  ; 9.089  ; 9.089  ; 9.089  ;
; LDSn         ; DATA[2]       ; 9.076  ; 9.076  ; 9.076  ; 9.076  ;
; LDSn         ; DATA[3]       ; 9.076  ; 9.076  ; 9.076  ; 9.076  ;
; LDSn         ; DATA[4]       ; 9.063  ; 9.063  ; 9.063  ; 9.063  ;
; LDSn         ; DATA[5]       ; 9.063  ; 9.063  ; 9.063  ; 9.063  ;
; LDSn         ; DATA[6]       ; 9.034  ; 9.034  ; 9.034  ; 9.034  ;
; LDSn         ; DATA[7]       ; 9.024  ; 9.024  ; 9.024  ; 9.024  ;
; LDSn         ; DATA[8]       ; 9.072  ; 9.072  ; 9.072  ; 9.072  ;
; LDSn         ; DATA[9]       ; 9.072  ; 9.072  ; 9.072  ; 9.072  ;
; LDSn         ; DATA[10]      ; 9.225  ; 9.225  ; 9.225  ; 9.225  ;
; LDSn         ; DATA[11]      ; 9.225  ; 9.141  ; 9.141  ; 9.225  ;
; LDSn         ; DATA[12]      ; 9.204  ; 9.204  ; 9.204  ; 9.204  ;
; LDSn         ; DATA[13]      ; 9.204  ; 9.204  ; 9.204  ; 9.204  ;
; LDSn         ; DATA[14]      ; 9.363  ; 9.363  ; 9.363  ; 9.363  ;
; LDSn         ; DATA[15]      ; 9.353  ; 9.353  ; 9.353  ; 9.353  ;
; LDSn         ; DTACKn        ; 7.396  ; 7.396  ; 7.396  ; 7.396  ;
; LDSn         ; IDE_IORDn     ; 6.550  ;        ;        ; 6.550  ;
; LDSn         ; IDE_IOWRn     ; 7.033  ;        ;        ; 7.033  ;
; LDSn         ; JOY_RLn       ; 8.347  ;        ;        ; 8.347  ;
; LDSn         ; JOY_WEn       ;        ; 8.198  ; 8.198  ;        ;
; LDSn         ; JOY_WL        ;        ; 7.193  ; 7.193  ;        ;
; LDSn         ; RAM_CAS0n     ; 7.109  ;        ;        ; 7.109  ;
; LDSn         ; RAM_CAS1n     ; 7.129  ;        ;        ; 7.129  ;
; LDSn         ; RAM_DATA[0]   ; 10.291 ; 10.579 ; 10.579 ; 10.291 ;
; LDSn         ; RAM_DATA[1]   ; 10.019 ; 10.314 ; 10.314 ; 10.019 ;
; LDSn         ; RAM_DATA[2]   ; 10.209 ; 10.312 ; 10.312 ; 10.209 ;
; LDSn         ; RAM_DATA[3]   ; 10.473 ; 10.531 ; 10.531 ; 10.473 ;
; LDSn         ; RAM_DATA[4]   ; 10.098 ; 10.098 ; 10.098 ; 10.098 ;
; LDSn         ; RAM_DATA[5]   ; 11.315 ; 11.315 ; 11.315 ; 11.315 ;
; LDSn         ; RAM_DATA[6]   ; 10.556 ; 10.556 ; 10.556 ; 10.556 ;
; LDSn         ; RAM_DATA[7]   ; 10.891 ; 10.891 ; 10.891 ; 10.891 ;
; LDSn         ; RAM_DATA[8]   ; 10.988 ; 11.183 ; 11.183 ; 10.988 ;
; LDSn         ; RAM_DATA[9]   ; 10.276 ; 10.232 ; 10.232 ; 10.276 ;
; LDSn         ; RAM_DATA[10]  ; 9.670  ; 9.670  ; 9.670  ; 9.670  ;
; LDSn         ; RAM_DATA[11]  ; 10.195 ; 9.630  ; 9.630  ; 10.195 ;
; LDSn         ; RAM_DATA[12]  ; 10.036 ; 10.049 ; 10.049 ; 10.036 ;
; LDSn         ; RAM_DATA[13]  ; 10.449 ; 10.449 ; 10.449 ; 10.449 ;
; LDSn         ; RAM_DATA[14]  ; 10.535 ; 10.535 ; 10.535 ; 10.535 ;
; LDSn         ; RAM_DATA[15]  ; 10.152 ; 10.152 ; 10.152 ; 10.152 ;
; LDSn         ; RAM_DQM0L     ; 7.576  ;        ;        ; 7.576  ;
; LDSn         ; RAM_DQM1L     ; 7.582  ;        ;        ; 7.582  ;
; LPT_BSY      ; DATA[0]       ; 10.303 ;        ;        ; 10.303 ;
; LPT_BSY      ; RAM_DATA[0]   ; 11.055 ;        ;        ; 11.055 ;
; LPT_D[0]     ; DATA[8]       ; 10.273 ;        ;        ; 10.273 ;
; LPT_D[0]     ; RAM_DATA[8]   ; 11.151 ;        ;        ; 11.151 ;
; LPT_D[1]     ; DATA[9]       ; 9.971  ;        ;        ; 9.971  ;
; LPT_D[1]     ; RAM_DATA[9]   ; 10.134 ;        ;        ; 10.134 ;
; LPT_D[2]     ; DATA[10]      ; 8.886  ;        ;        ; 8.886  ;
; LPT_D[2]     ; RAM_DATA[10]  ; 9.085  ;        ;        ; 9.085  ;
; LPT_D[3]     ; DATA[11]      ; 9.230  ;        ;        ; 9.230  ;
; LPT_D[3]     ; RAM_DATA[11]  ; 9.719  ;        ;        ; 9.719  ;
; LPT_D[4]     ; DATA[12]      ; 9.364  ;        ;        ; 9.364  ;
; LPT_D[4]     ; RAM_DATA[12]  ; 9.883  ;        ;        ; 9.883  ;
; LPT_D[5]     ; DATA[13]      ; 9.932  ;        ;        ; 9.932  ;
; LPT_D[5]     ; RAM_DATA[13]  ; 10.125 ;        ;        ; 10.125 ;
; LPT_D[6]     ; DATA[14]      ; 9.627  ; 9.627  ; 9.627  ; 9.627  ;
; LPT_D[6]     ; RAM_DATA[14]  ; 10.606 ; 10.606 ; 10.606 ; 10.606 ;
; LPT_D[7]     ; DATA[15]      ; 10.085 ; 10.085 ; 10.085 ; 10.085 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 10.318 ; 10.318 ; 10.318 ; 10.318 ;
; MIDI_IN      ; MIDI_TLR      ; 4.717  ;        ;        ; 4.717  ;
; RAM_DATA[0]  ; DATA[0]       ; 10.401 ;        ;        ; 10.401 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 11.153 ;        ;        ; 11.153 ;
; RAM_DATA[1]  ; DATA[1]       ; 10.335 ;        ;        ; 10.335 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 10.601 ;        ;        ; 10.601 ;
; RAM_DATA[2]  ; DATA[2]       ; 10.144 ;        ;        ; 10.144 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 10.350 ;        ;        ; 10.350 ;
; RAM_DATA[3]  ; DATA[3]       ; 10.998 ;        ;        ; 10.998 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 10.989 ;        ;        ; 10.989 ;
; RAM_DATA[4]  ; DATA[4]       ; 9.969  ;        ;        ; 9.969  ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 9.774  ;        ;        ; 9.774  ;
; RAM_DATA[5]  ; DATA[5]       ; 10.237 ;        ;        ; 10.237 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 11.336 ;        ;        ; 11.336 ;
; RAM_DATA[6]  ; DATA[6]       ; 9.403  ;        ;        ; 9.403  ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 10.465 ;        ;        ; 10.465 ;
; RAM_DATA[7]  ; DATA[7]       ; 9.942  ;        ;        ; 9.942  ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 11.004 ;        ;        ; 11.004 ;
; RAM_DATA[8]  ; DATA[8]       ; 10.883 ;        ;        ; 10.883 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 11.761 ;        ;        ; 11.761 ;
; RAM_DATA[9]  ; DATA[9]       ; 9.909  ;        ;        ; 9.909  ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 10.072 ;        ;        ; 10.072 ;
; RAM_DATA[10] ; DATA[10]      ; 9.475  ;        ;        ; 9.475  ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 9.674  ;        ;        ; 9.674  ;
; RAM_DATA[11] ; DATA[11]      ; 9.839  ;        ;        ; 9.839  ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 10.328 ;        ;        ; 10.328 ;
; RAM_DATA[12] ; DATA[12]      ; 9.414  ;        ;        ; 9.414  ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 9.933  ;        ;        ; 9.933  ;
; RAM_DATA[13] ; DATA[13]      ; 10.593 ;        ;        ; 10.593 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 10.786 ;        ;        ; 10.786 ;
; RAM_DATA[14] ; DATA[14]      ; 10.056 ; 10.056 ; 10.056 ; 10.056 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 11.035 ; 11.035 ; 11.035 ; 11.035 ;
; RAM_DATA[15] ; DATA[15]      ; 9.756  ; 9.756  ; 9.756  ; 9.756  ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 9.989  ; 9.989  ; 9.989  ; 9.989  ;
; RWn          ; ACSI_RDn      ; 9.423  ; 6.722  ; 6.722  ; 9.423  ;
; RWn          ; ACSI_WRn      ; 6.797  ; 9.504  ; 9.504  ; 6.797  ;
; RWn          ; BUTTONn       ;        ; 9.776  ; 9.776  ;        ;
; RWn          ; CA1_OUT       ;        ; 9.508  ; 9.508  ;        ;
; RWn          ; CD[0]         ; 7.808  ; 7.524  ; 7.524  ; 7.808  ;
; RWn          ; CD[1]         ; 7.885  ; 7.603  ; 7.603  ; 7.885  ;
; RWn          ; CD[2]         ; 7.185  ; 6.910  ; 6.910  ; 7.185  ;
; RWn          ; CD[3]         ; 7.909  ; 7.766  ; 7.766  ; 7.909  ;
; RWn          ; CD[4]         ; 7.305  ; 7.305  ; 7.305  ; 7.305  ;
; RWn          ; CD[5]         ; 6.912  ; 6.912  ; 6.912  ; 6.912  ;
; RWn          ; CD[6]         ; 7.026  ; 7.026  ; 7.026  ; 7.026  ;
; RWn          ; CD[7]         ; 7.424  ; 7.424  ; 7.424  ; 7.424  ;
; RWn          ; DATA[0]       ; 8.644  ; 8.537  ; 8.537  ; 8.644  ;
; RWn          ; DATA[1]       ; 8.914  ; 8.896  ; 8.896  ; 8.914  ;
; RWn          ; DATA[2]       ; 8.619  ; 8.105  ; 8.105  ; 8.619  ;
; RWn          ; DATA[3]       ; 8.901  ; 8.901  ; 8.901  ; 8.901  ;
; RWn          ; DATA[4]       ; 8.888  ; 8.888  ; 8.888  ; 8.888  ;
; RWn          ; DATA[5]       ; 8.529  ; 8.529  ; 8.529  ; 8.529  ;
; RWn          ; DATA[6]       ; 7.835  ; 7.835  ; 7.835  ; 7.835  ;
; RWn          ; DATA[7]       ; 8.148  ; 8.148  ; 8.148  ; 8.148  ;
; RWn          ; DATA[8]       ; 8.897  ; 8.897  ; 8.897  ; 8.897  ;
; RWn          ; DATA[9]       ; 8.882  ; 8.395  ; 8.395  ; 8.882  ;
; RWn          ; DATA[10]      ; 8.447  ; 8.171  ; 8.171  ; 8.447  ;
; RWn          ; DATA[11]      ; 8.731  ; 8.609  ; 8.609  ; 8.731  ;
; RWn          ; DATA[12]      ; 8.656  ; 8.557  ; 8.557  ; 8.656  ;
; RWn          ; DATA[13]      ; 9.029  ; 8.640  ; 8.640  ; 9.029  ;
; RWn          ; DATA[14]      ; 7.945  ; 7.945  ; 7.945  ; 7.945  ;
; RWn          ; DATA[15]      ; 8.308  ; 8.308  ; 8.308  ; 8.308  ;
; RWn          ; DTACKn        ; 8.134  ; 8.134  ; 8.134  ; 8.134  ;
; RWn          ; FLASH_CEn     ;        ; 8.609  ; 8.609  ;        ;
; RWn          ; FLASH_OEn     ;        ; 8.622  ; 8.622  ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 6.876  ; 6.876  ;        ;
; RWn          ; IDE_D_EN_OUTn ; 6.826  ;        ;        ; 6.826  ;
; RWn          ; IDE_IORDn     ;        ; 6.869  ; 6.869  ;        ;
; RWn          ; IDE_IOWRn     ; 7.329  ;        ;        ; 7.329  ;
; RWn          ; JOY_RHn       ;        ; 7.465  ; 7.465  ;        ;
; RWn          ; JOY_RLn       ;        ; 8.518  ; 8.518  ;        ;
; RWn          ; JOY_WEn       ; 8.369  ;        ;        ; 8.369  ;
; RWn          ; JOY_WL        ; 8.360  ; 7.143  ; 7.143  ; 8.360  ;
; RWn          ; RAM_DATA[0]   ; 7.740  ; 7.740  ; 7.740  ; 7.740  ;
; RWn          ; RAM_DATA[1]   ; 7.445  ; 7.445  ; 7.445  ; 7.445  ;
; RWn          ; RAM_DATA[2]   ; 7.087  ; 7.087  ; 7.087  ; 7.087  ;
; RWn          ; RAM_DATA[3]   ; 7.201  ; 7.201  ; 7.201  ; 7.201  ;
; RWn          ; RAM_DATA[4]   ; 7.147  ; 7.147  ; 7.147  ; 7.147  ;
; RWn          ; RAM_DATA[5]   ; 7.763  ; 7.763  ; 7.763  ; 7.763  ;
; RWn          ; RAM_DATA[6]   ; 7.719  ; 7.719  ; 7.719  ; 7.719  ;
; RWn          ; RAM_DATA[7]   ; 7.763  ; 7.763  ; 7.763  ; 7.763  ;
; RWn          ; RAM_DATA[8]   ; 7.500  ; 7.500  ; 7.500  ; 7.500  ;
; RWn          ; RAM_DATA[9]   ; 7.165  ; 7.165  ; 7.165  ; 7.165  ;
; RWn          ; RAM_DATA[10]  ; 6.918  ; 6.918  ; 6.918  ; 6.918  ;
; RWn          ; RAM_DATA[11]  ; 7.022  ; 7.022  ; 7.022  ; 7.022  ;
; RWn          ; RAM_DATA[12]  ; 7.092  ; 7.092  ; 7.092  ; 7.092  ;
; RWn          ; RAM_DATA[13]  ; 6.992  ; 6.992  ; 6.992  ; 6.992  ;
; RWn          ; RAM_DATA[14]  ; 7.308  ; 7.308  ; 7.308  ; 7.308  ;
; RWn          ; RAM_DATA[15]  ; 6.881  ; 6.881  ; 6.881  ; 6.881  ;
; RWn          ; RAM_WEn       ; 6.778  ;        ;        ; 6.778  ;
; RWn          ; ROM0n         ;        ; 8.188  ; 8.188  ;        ;
; RWn          ; ROM1n         ;        ; 7.933  ; 7.933  ;        ;
; RWn          ; ROM2n         ;        ; 7.255  ; 7.255  ;        ;
; RWn          ; ROM3n         ;        ; 8.073  ; 8.073  ;        ;
; RWn          ; ROM4n         ;        ; 8.614  ; 8.614  ;        ;
; RWn          ; ROM5n         ;        ; 6.754  ; 6.754  ;        ;
; RWn          ; ROM6n         ;        ; 8.092  ; 8.092  ;        ;
; SCSI_ACKn    ; CD[0]         ; 7.846  ; 7.846  ; 7.846  ; 7.846  ;
; SCSI_ATNn    ; CD[1]         ; 8.363  ; 8.363  ; 8.363  ; 8.363  ;
; SCSI_BSYn    ; CD[6]         ; 9.673  ; 9.673  ; 9.673  ; 9.673  ;
; SCSI_D[0]    ; CD[0]         ; 7.986  ; 7.986  ; 7.986  ; 7.986  ;
; SCSI_D[1]    ; CD[1]         ; 8.119  ; 8.119  ; 8.119  ; 8.119  ;
; SCSI_D[2]    ; CD[2]         ;        ; 8.333  ; 8.333  ;        ;
; SCSI_D[3]    ; CD[3]         ; 8.336  ; 8.336  ; 8.336  ; 8.336  ;
; SCSI_D[4]    ; CD[4]         ; 9.159  ; 9.159  ; 9.159  ; 9.159  ;
; SCSI_D[5]    ; CD[5]         ; 9.101  ; 9.101  ; 9.101  ; 9.101  ;
; SCSI_D[6]    ; CD[6]         ; 9.426  ; 9.426  ; 9.426  ; 9.426  ;
; SCSI_D[7]    ; CD[7]         ; 8.245  ; 8.245  ; 8.245  ; 8.245  ;
; SCSI_DCn     ; CD[3]         ; 8.147  ; 8.147  ; 8.147  ; 8.147  ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 8.586  ; 8.586  ; 8.586  ; 8.586  ;
; SCSI_DCn     ; SCSI_D[0]     ; 8.360  ; 8.360  ; 8.360  ; 8.360  ;
; SCSI_DCn     ; SCSI_D[1]     ; 8.360  ; 8.360  ; 8.360  ; 8.360  ;
; SCSI_DCn     ; SCSI_D[2]     ; 8.061  ; 8.061  ; 8.061  ; 8.061  ;
; SCSI_DCn     ; SCSI_D[3]     ; 8.061  ; 8.061  ; 8.061  ; 8.061  ;
; SCSI_DCn     ; SCSI_D[4]     ; 7.932  ; 7.932  ; 7.932  ; 7.932  ;
; SCSI_DCn     ; SCSI_D[5]     ; 7.932  ; 7.932  ; 7.932  ; 7.932  ;
; SCSI_DCn     ; SCSI_D[6]     ; 7.927  ; 7.927  ; 7.927  ; 7.927  ;
; SCSI_DCn     ; SCSI_D[7]     ; 7.927  ; 7.927  ; 7.927  ; 7.927  ;
; SCSI_DCn     ; SCSI_DP       ; 8.370  ; 8.370  ; 8.370  ; 8.370  ;
; SCSI_DP      ; CD[0]         ; 7.837  ; 7.837  ; 7.837  ; 7.837  ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 6.498  ; 6.498  ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 6.473  ;        ;        ; 6.473  ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 6.358  ; 6.358  ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 6.377  ;        ;        ; 6.377  ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 6.380  ; 6.380  ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 6.291  ;        ;        ; 6.291  ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 6.345  ; 6.345  ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 6.339  ;        ;        ; 6.339  ;
; SCSI_IDn[1]  ; SCSI_DP       ; 6.712  ; 6.712  ; 6.712  ; 6.712  ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 6.307  ; 6.307  ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 6.296  ; 6.296  ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 6.165  ;        ;        ; 6.165  ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 6.208  ;        ;        ; 6.208  ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 6.183  ; 6.183  ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 6.114  ; 6.114  ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 6.138  ;        ;        ; 6.138  ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 6.164  ;        ;        ; 6.164  ;
; SCSI_IDn[2]  ; SCSI_DP       ; 6.535  ; 6.535  ; 6.535  ; 6.535  ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 6.581  ; 6.581  ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 6.568  ; 6.568  ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 6.440  ; 6.440  ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 6.482  ; 6.482  ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 6.451  ;        ;        ; 6.451  ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 6.375  ;        ;        ; 6.375  ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 6.410  ;        ;        ; 6.410  ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 6.436  ;        ;        ; 6.436  ;
; SCSI_IDn[3]  ; SCSI_DP       ; 6.807  ; 6.807  ; 6.807  ; 6.807  ;
; SCSI_IOn     ; CD[2]         ;        ; 8.136  ; 8.136  ;        ;
; SCSI_IOn     ; CD[3]         ; 8.791  ; 8.791  ; 8.791  ; 8.791  ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 6.881  ; 7.955  ; 7.955  ; 6.881  ;
; SCSI_IOn     ; SCSI_D[0]     ; 6.655  ; 6.655  ; 6.655  ; 6.655  ;
; SCSI_IOn     ; SCSI_D[1]     ; 6.655  ; 6.655  ; 6.655  ; 6.655  ;
; SCSI_IOn     ; SCSI_D[2]     ; 6.356  ; 6.356  ; 6.356  ; 6.356  ;
; SCSI_IOn     ; SCSI_D[3]     ; 6.356  ; 6.356  ; 6.356  ; 6.356  ;
; SCSI_IOn     ; SCSI_D[4]     ; 6.227  ; 6.227  ; 6.227  ; 6.227  ;
; SCSI_IOn     ; SCSI_D[5]     ; 6.227  ; 6.227  ; 6.227  ; 6.227  ;
; SCSI_IOn     ; SCSI_D[6]     ; 6.222  ; 6.222  ; 6.222  ; 6.222  ;
; SCSI_IOn     ; SCSI_D[7]     ; 6.222  ; 6.222  ; 6.222  ; 6.222  ;
; SCSI_IOn     ; SCSI_DP       ; 6.665  ; 6.665  ; 6.665  ; 6.665  ;
; SCSI_IOn     ; SCSI_RDn      ; 6.315  ;        ;        ; 6.315  ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 6.741  ; 6.741  ;        ;
; SCSI_MSGn    ; CD[3]         ; 9.033  ; 9.033  ; 9.033  ; 9.033  ;
; SCSI_MSGn    ; CD[4]         ; 9.510  ; 9.510  ; 9.510  ; 9.510  ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 8.197  ; 8.197  ; 8.197  ; 8.197  ;
; SCSI_MSGn    ; SCSI_D[0]     ; 7.971  ; 7.971  ; 7.971  ; 7.971  ;
; SCSI_MSGn    ; SCSI_D[1]     ; 7.971  ; 7.971  ; 7.971  ; 7.971  ;
; SCSI_MSGn    ; SCSI_D[2]     ; 7.672  ; 7.672  ; 7.672  ; 7.672  ;
; SCSI_MSGn    ; SCSI_D[3]     ; 7.672  ; 7.672  ; 7.672  ; 7.672  ;
; SCSI_MSGn    ; SCSI_D[4]     ; 7.543  ; 7.543  ; 7.543  ; 7.543  ;
; SCSI_MSGn    ; SCSI_D[5]     ; 7.543  ; 7.543  ; 7.543  ; 7.543  ;
; SCSI_MSGn    ; SCSI_D[6]     ; 7.538  ; 7.538  ; 7.538  ; 7.538  ;
; SCSI_MSGn    ; SCSI_D[7]     ; 7.538  ; 7.538  ; 7.538  ; 7.538  ;
; SCSI_MSGn    ; SCSI_DP       ; 7.981  ; 7.981  ; 7.981  ; 7.981  ;
; SCSI_REQn    ; CD[3]         ; 9.043  ; 9.043  ; 9.043  ; 9.043  ;
; SCSI_REQn    ; CD[5]         ; 9.406  ; 9.406  ; 9.406  ; 9.406  ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 8.207  ;        ;        ; 8.207  ;
; SCSI_REQn    ; SCSI_D[0]     ; 7.981  ; 7.981  ; 7.981  ; 7.981  ;
; SCSI_REQn    ; SCSI_D[1]     ; 7.981  ; 7.981  ; 7.981  ; 7.981  ;
; SCSI_REQn    ; SCSI_D[2]     ; 7.682  ; 7.682  ; 7.682  ; 7.682  ;
; SCSI_REQn    ; SCSI_D[3]     ; 7.682  ; 7.682  ; 7.682  ; 7.682  ;
; SCSI_REQn    ; SCSI_D[4]     ; 7.553  ; 7.553  ; 7.553  ; 7.553  ;
; SCSI_REQn    ; SCSI_D[5]     ; 7.553  ; 7.553  ; 7.553  ; 7.553  ;
; SCSI_REQn    ; SCSI_D[6]     ; 7.548  ; 7.548  ; 7.548  ; 7.548  ;
; SCSI_REQn    ; SCSI_D[7]     ; 7.548  ; 7.548  ; 7.548  ; 7.548  ;
; SCSI_REQn    ; SCSI_DP       ; 7.991  ; 7.991  ; 7.991  ; 7.991  ;
; SCSI_RSTn    ; CD[7]         ;        ; 8.697  ; 8.697  ;        ;
; SCSI_SELn    ; CD[1]         ; 7.734  ; 7.734  ; 7.734  ; 7.734  ;
; SD_AVR_ENn   ; RESETn        ;        ; 7.858  ; 7.858  ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 6.964  ; 6.964  ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 6.014  ; 6.014  ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 7.086  ;        ;        ; 7.086  ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 6.502  ;        ;        ; 6.502  ;
; SD_RESETn    ; ACSI_RDn      ; 10.050 ; 10.050 ; 10.050 ; 10.050 ;
; SD_RESETn    ; ACSI_WRn      ; 10.131 ; 10.131 ; 10.131 ; 10.131 ;
; SD_RESETn    ; CA1_OUT       ; 10.135 ;        ;        ; 10.135 ;
; SD_RESETn    ; CD[0]         ; 11.136 ; 10.852 ; 10.852 ; 11.136 ;
; SD_RESETn    ; CD[1]         ; 11.213 ; 10.931 ; 10.931 ; 11.213 ;
; SD_RESETn    ; CD[2]         ; 10.513 ; 10.238 ; 10.238 ; 10.513 ;
; SD_RESETn    ; CD[3]         ; 11.237 ; 11.094 ; 11.094 ; 11.237 ;
; SD_RESETn    ; CD[4]         ; 10.633 ; 10.633 ; 10.633 ; 10.633 ;
; SD_RESETn    ; CD[5]         ; 10.240 ; 10.240 ; 10.240 ; 10.240 ;
; SD_RESETn    ; CD[6]         ; 10.354 ; 10.354 ; 10.354 ; 10.354 ;
; SD_RESETn    ; CD[7]         ; 10.752 ; 10.752 ; 10.752 ; 10.752 ;
; SD_RESETn    ; COM_TxD       ; 7.967  ; 7.967  ; 7.967  ; 7.967  ;
; SD_RESETn    ; DATA[0]       ; 11.004 ; 11.004 ; 11.004 ; 11.004 ;
; SD_RESETn    ; DATA[1]       ; 11.331 ; 11.463 ; 11.463 ; 11.331 ;
; SD_RESETn    ; DATA[2]       ; 10.793 ; 11.179 ; 11.179 ; 10.793 ;
; SD_RESETn    ; DATA[3]       ; 11.769 ; 11.769 ; 11.769 ; 11.769 ;
; SD_RESETn    ; DATA[4]       ; 11.486 ; 11.486 ; 11.486 ; 11.486 ;
; SD_RESETn    ; DATA[5]       ; 11.212 ; 11.217 ; 11.217 ; 11.212 ;
; SD_RESETn    ; DATA[6]       ; 10.523 ; 10.523 ; 10.523 ; 10.523 ;
; SD_RESETn    ; DATA[7]       ; 10.836 ; 10.836 ; 10.836 ; 10.836 ;
; SD_RESETn    ; DATA[8]       ; 11.791 ; 12.172 ; 12.172 ; 11.791 ;
; SD_RESETn    ; DATA[9]       ; 11.350 ; 11.674 ; 11.674 ; 11.350 ;
; SD_RESETn    ; DATA[10]      ; 10.859 ; 11.073 ; 11.073 ; 10.859 ;
; SD_RESETn    ; DATA[11]      ; 11.297 ; 11.400 ; 11.400 ; 11.297 ;
; SD_RESETn    ; DATA[12]      ; 11.245 ; 11.412 ; 11.412 ; 11.245 ;
; SD_RESETn    ; DATA[13]      ; 11.328 ; 11.595 ; 11.595 ; 11.328 ;
; SD_RESETn    ; DATA[14]      ; 10.238 ; 10.238 ; 10.238 ; 10.238 ;
; SD_RESETn    ; DATA[15]      ; 10.601 ; 10.601 ; 10.601 ; 10.601 ;
; SD_RESETn    ; DTACKn        ; 8.078  ; 8.078  ; 8.078  ; 8.078  ;
; SD_RESETn    ; RAM_DATA[0]   ; 11.756 ; 11.756 ; 11.756 ; 11.756 ;
; SD_RESETn    ; RAM_DATA[1]   ; 11.597 ; 11.729 ; 11.729 ; 11.597 ;
; SD_RESETn    ; RAM_DATA[2]   ; 10.999 ; 11.385 ; 11.385 ; 10.999 ;
; SD_RESETn    ; RAM_DATA[3]   ; 11.760 ; 11.760 ; 11.760 ; 11.760 ;
; SD_RESETn    ; RAM_DATA[4]   ; 11.291 ; 11.291 ; 11.291 ; 11.291 ;
; SD_RESETn    ; RAM_DATA[5]   ; 12.311 ; 12.316 ; 12.316 ; 12.311 ;
; SD_RESETn    ; RAM_DATA[6]   ; 11.585 ; 11.585 ; 11.585 ; 11.585 ;
; SD_RESETn    ; RAM_DATA[7]   ; 11.898 ; 11.898 ; 11.898 ; 11.898 ;
; SD_RESETn    ; RAM_DATA[8]   ; 12.669 ; 13.050 ; 13.050 ; 12.669 ;
; SD_RESETn    ; RAM_DATA[9]   ; 11.513 ; 11.837 ; 11.837 ; 11.513 ;
; SD_RESETn    ; RAM_DATA[10]  ; 11.058 ; 11.272 ; 11.272 ; 11.058 ;
; SD_RESETn    ; RAM_DATA[11]  ; 11.786 ; 11.889 ; 11.889 ; 11.786 ;
; SD_RESETn    ; RAM_DATA[12]  ; 11.764 ; 11.931 ; 11.931 ; 11.764 ;
; SD_RESETn    ; RAM_DATA[13]  ; 11.521 ; 11.788 ; 11.788 ; 11.521 ;
; SD_RESETn    ; RAM_DATA[14]  ; 11.217 ; 11.217 ; 11.217 ; 11.217 ;
; SD_RESETn    ; RAM_DATA[15]  ; 10.834 ; 10.834 ; 10.834 ; 10.834 ;
; UDSn         ; ACSI_RDn      ; 8.359  ; 8.359  ; 8.359  ; 8.359  ;
; UDSn         ; ACSI_WRn      ; 8.440  ; 8.440  ; 8.440  ; 8.440  ;
; UDSn         ; CA1_OUT       ; 8.444  ;        ;        ; 8.444  ;
; UDSn         ; CD[0]         ; 9.445  ; 9.161  ; 9.161  ; 9.445  ;
; UDSn         ; CD[1]         ; 9.522  ; 9.240  ; 9.240  ; 9.522  ;
; UDSn         ; CD[2]         ; 8.822  ; 8.547  ; 8.547  ; 8.822  ;
; UDSn         ; CD[3]         ; 9.546  ; 9.403  ; 9.403  ; 9.546  ;
; UDSn         ; CD[4]         ; 8.942  ; 8.942  ; 8.942  ; 8.942  ;
; UDSn         ; CD[5]         ; 8.549  ; 8.549  ; 8.549  ; 8.549  ;
; UDSn         ; CD[6]         ; 8.663  ; 8.663  ; 8.663  ; 8.663  ;
; UDSn         ; CD[7]         ; 9.061  ; 9.061  ; 9.061  ; 9.061  ;
; UDSn         ; DATA[0]       ; 8.411  ; 8.411  ; 8.411  ; 8.411  ;
; UDSn         ; DATA[1]       ; 8.411  ; 8.411  ; 8.411  ; 8.411  ;
; UDSn         ; DATA[2]       ; 8.398  ; 8.398  ; 8.398  ; 8.398  ;
; UDSn         ; DATA[3]       ; 8.398  ; 8.398  ; 8.398  ; 8.398  ;
; UDSn         ; DATA[4]       ; 8.385  ; 8.385  ; 8.385  ; 8.385  ;
; UDSn         ; DATA[5]       ; 8.385  ; 8.385  ; 8.385  ; 8.385  ;
; UDSn         ; DATA[6]       ; 8.356  ; 8.356  ; 8.356  ; 8.356  ;
; UDSn         ; DATA[7]       ; 8.346  ; 8.346  ; 8.346  ; 8.346  ;
; UDSn         ; DATA[8]       ; 8.394  ; 8.394  ; 8.394  ; 8.394  ;
; UDSn         ; DATA[9]       ; 8.394  ; 8.394  ; 8.394  ; 8.394  ;
; UDSn         ; DATA[10]      ; 8.547  ; 8.547  ; 8.547  ; 8.547  ;
; UDSn         ; DATA[11]      ; 8.547  ; 8.463  ; 8.463  ; 8.547  ;
; UDSn         ; DATA[12]      ; 8.526  ; 8.526  ; 8.526  ; 8.526  ;
; UDSn         ; DATA[13]      ; 8.526  ; 8.526  ; 8.526  ; 8.526  ;
; UDSn         ; DATA[14]      ; 8.685  ; 8.685  ; 8.685  ; 8.685  ;
; UDSn         ; DATA[15]      ; 8.675  ; 8.675  ; 8.675  ; 8.675  ;
; UDSn         ; DTACKn        ; 7.143  ; 7.143  ; 7.143  ; 7.143  ;
; UDSn         ; JOY_RHn       ; 7.060  ;        ;        ; 7.060  ;
; UDSn         ; RAM_CAS0n     ; 6.967  ;        ;        ; 6.967  ;
; UDSn         ; RAM_CAS1n     ; 6.987  ;        ;        ; 6.987  ;
; UDSn         ; RAM_DATA[0]   ; 9.901  ; 9.901  ; 9.901  ; 9.901  ;
; UDSn         ; RAM_DATA[1]   ; 9.341  ; 9.636  ; 9.636  ; 9.341  ;
; UDSn         ; RAM_DATA[2]   ; 9.531  ; 9.634  ; 9.634  ; 9.531  ;
; UDSn         ; RAM_DATA[3]   ; 9.795  ; 9.853  ; 9.853  ; 9.795  ;
; UDSn         ; RAM_DATA[4]   ; 9.420  ; 9.420  ; 9.420  ; 9.420  ;
; UDSn         ; RAM_DATA[5]   ; 10.754 ; 10.780 ; 10.780 ; 10.754 ;
; UDSn         ; RAM_DATA[6]   ; 9.878  ; 10.109 ; 10.109 ; 9.878  ;
; UDSn         ; RAM_DATA[7]   ; 10.302 ; 10.430 ; 10.430 ; 10.302 ;
; UDSn         ; RAM_DATA[8]   ; 10.310 ; 10.505 ; 10.505 ; 10.310 ;
; UDSn         ; RAM_DATA[9]   ; 9.664  ; 9.554  ; 9.554  ; 9.664  ;
; UDSn         ; RAM_DATA[10]  ; 9.170  ; 9.170  ; 9.170  ; 9.170  ;
; UDSn         ; RAM_DATA[11]  ; 9.517  ; 8.952  ; 8.952  ; 9.517  ;
; UDSn         ; RAM_DATA[12]  ; 9.658  ; 9.669  ; 9.669  ; 9.658  ;
; UDSn         ; RAM_DATA[13]  ; 9.894  ; 9.894  ; 9.894  ; 9.894  ;
; UDSn         ; RAM_DATA[14]  ; 9.889  ; 9.889  ; 9.889  ; 9.889  ;
; UDSn         ; RAM_DATA[15]  ; 9.506  ; 9.506  ; 9.506  ; 9.506  ;
; UDSn         ; RAM_DQM0H     ; 7.461  ;        ;        ; 7.461  ;
; UDSn         ; RAM_DQM1H     ; 6.725  ;        ;        ; 6.725  ;
+--------------+---------------+--------+--------+--------+--------+


+-------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                     ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise   ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 11.006 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 11.093 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 11.084 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 11.088 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 11.084 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 11.006 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 11.006 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 11.087 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 11.087 ;      ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 6.680  ;      ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 8.426  ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 4.708  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 5.248  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 5.248  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 5.224  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 5.224  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 5.238  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 5.228  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 4.906  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 4.906  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 4.708  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 4.708  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 4.808  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 4.798  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 4.962  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 4.952  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 5.156  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 5.156  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 4.791  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 5.003  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 5.003  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 5.342  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 5.204  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 5.214  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 5.342  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 3.710  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 14.200 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 14.287 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 14.278 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 14.282 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 14.278 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 14.200 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 14.200 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 14.281 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 14.281 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 4.874  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 11.173 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 11.238 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 11.238 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 11.225 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 11.225 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 11.212 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 11.212 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 11.183 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 11.173 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 11.221 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 11.221 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 11.374 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 11.374 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 11.353 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 11.353 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 11.512 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 11.502 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 3.994  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 12.737 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.568  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 3.578  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.568  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.568  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 3.486  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 3.731  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 3.165  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 3.251  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 3.165  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 3.165  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.678  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.678  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 3.702  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 3.702  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 3.599  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 10.953 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 11.282 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 11.158 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 10.953 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.262 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.262 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 11.289 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 11.283 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 11.289 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 11.113 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 11.113 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 11.113 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 11.103 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 10.963 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 10.963 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 11.277 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 11.177 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 3.858  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.383  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 3.912  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.283  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 4.617  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 5.050  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 5.050  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 4.751  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 4.751  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 4.622  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 4.622  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 4.617  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 4.617  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.616  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 5.060  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.846  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.606  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.616  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.634  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.714  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 3.731  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 3.719  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 3.501  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 3.276  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.816  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.816  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.792  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.792  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.806  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.796  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.474  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.474  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.276  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.276  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.376  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.366  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.530  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.520  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.724  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.724  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.359  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.571  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.571  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.910  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.772  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.782  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.910  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 9.012  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 9.099  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 9.090  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 9.094  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 9.090  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 9.012  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 9.012  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 9.093  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 9.093  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 6.072  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 6.137  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 6.137  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 6.124  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 6.124  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 6.111  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 6.111  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 6.082  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 6.072  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 6.120  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 6.120  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 6.273  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 6.273  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 6.252  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 6.252  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 6.411  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 6.401  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 7.549  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 6.662  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 6.991  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 6.867  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 6.662  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 6.971  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 6.971  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 6.998  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 6.992  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 6.998  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 6.822  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 6.822  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 6.822  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 6.812  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 6.672  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 6.672  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 6.986  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 6.886  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 4.708  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 5.248  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 5.248  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 5.224  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 5.224  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 5.238  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 5.228  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 4.906  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 4.906  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 4.708  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 4.708  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 4.808  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 4.798  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 4.962  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 4.952  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 5.156  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 5.156  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 4.791  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 5.003  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 5.003  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 5.342  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 5.204  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 5.214  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 5.342  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 3.710  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 14.200 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 14.287 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 14.278 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 14.282 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 14.278 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 14.200 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 14.200 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 14.281 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 14.281 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 4.874  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 11.173 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 11.238 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 11.238 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 11.225 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 11.225 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 11.212 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 11.212 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 11.183 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 11.173 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 11.221 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 11.221 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 11.374 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 11.374 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 11.353 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 11.353 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 11.512 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 11.502 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 3.994  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 12.737 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.568  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.578  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.568  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.568  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 3.486  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.731  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 3.165  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 3.251  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 3.165  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 3.165  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.678  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.678  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 3.702  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 3.702  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 3.599  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 10.953 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 11.282 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 11.158 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 10.953 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.262 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.262 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 11.289 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 11.283 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 11.289 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 11.113 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 11.113 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 11.113 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 11.103 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 10.963 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 10.963 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 11.277 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 11.177 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.858  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.383  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 3.912  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.283  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 4.617  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 5.050  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 5.050  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 4.751  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 4.751  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 4.622  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 4.622  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 4.617  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 4.617  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.616  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 5.060  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.846  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.606  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.616  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.634  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.714  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.731  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 3.719  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.501  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.276  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.816  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.816  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.792  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.792  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.806  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.796  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.474  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.474  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.276  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.276  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.376  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.366  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.530  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.520  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.724  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.724  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.359  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.571  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.571  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.910  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.772  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.782  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.910  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 9.012  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 9.099  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 9.090  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 9.094  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 9.090  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 9.012  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 9.012  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 9.093  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 9.093  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 6.072  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 6.137  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 6.137  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 6.124  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 6.124  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 6.111  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 6.111  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 6.082  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 6.072  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 6.120  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 6.120  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 6.273  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 6.273  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 6.252  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 6.252  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 6.411  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 6.401  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 7.549  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 6.662  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 6.991  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 6.867  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 6.662  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 6.971  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 6.971  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 6.998  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 6.992  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 6.998  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 6.822  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 6.822  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 6.822  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 6.812  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 6.672  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 6.672  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 6.986  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 6.886  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 2.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 8.407  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 8.494  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 8.485  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 8.489  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 8.485  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 8.407  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 8.407  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 8.488  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 8.488  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 4.081  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 5.827  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 3.278  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 3.288  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 3.278  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 3.278  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 3.441  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 5.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 5.909  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 5.785  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 5.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 5.889  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 5.889  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 5.916  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 5.910  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 5.916  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 5.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 5.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 5.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 5.730  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 5.590  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 5.590  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 5.904  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 5.804  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 3.568  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.521  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 4.016  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.387  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.212  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.645  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.645  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.346  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.346  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.217  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.217  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 3.212  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 3.212  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.702  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 3.655  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.932  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.692  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.702  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.965  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.852  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 3.441  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 5.058  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 2.640  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 8.407  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 8.494  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 8.485  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 8.489  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 8.485  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 8.407  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 8.407  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 8.488  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 8.488  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 4.081  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 5.827  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.278  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.288  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.278  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.278  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.441  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 5.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 5.909  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 5.785  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 5.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 5.889  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 5.889  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 5.916  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 5.910  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 5.916  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 5.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 5.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 5.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 5.730  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 5.590  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 5.590  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 5.904  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 5.804  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.568  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.521  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 4.016  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.387  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.212  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.645  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.645  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.346  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.346  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.217  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.217  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 3.212  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 3.212  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.702  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.655  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.932  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.692  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.702  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.965  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.852  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.441  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 5.058  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 5.481  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 5.481  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 5.481  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 5.565  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 5.565  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 5.481  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 5.481  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 5.481  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 5.565  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 5.565  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                            ;
+---------------+---------------+-------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise  ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-------+------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 9.872 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 9.959 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 9.950 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 9.954 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 9.950 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 9.872 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 9.872 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 9.953 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 9.953 ;      ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 6.680 ;      ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 6.791 ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 3.228 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.768 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.768 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.744 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.744 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.758 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.748 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.426 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.426 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.228 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.228 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.328 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.318 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.482 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.472 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.676 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.676 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.311 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.523 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.523 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.862 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.724 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.734 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.862 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 2.777 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 3.323 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 3.410 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 3.401 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 3.405 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 3.401 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 3.323 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 3.323 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 3.404 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 3.404 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 2.167 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 3.772 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 3.837 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 3.837 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 3.824 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 3.824 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 3.811 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 3.811 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 3.782 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 3.772 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 3.820 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 3.820 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 3.973 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 3.973 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 3.952 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 3.952 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 4.111 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 4.101 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 3.845 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 3.781 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.342 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 3.352 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.342 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.342 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 3.486 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 3.505 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 3.165 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 3.251 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 3.165 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 3.165 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 3.702 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 3.702 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 3.599 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 4.508 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.837 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.713 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.508 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.817 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.817 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 4.844 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.838 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 4.844 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.668 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.668 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.668 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.658 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.518 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.518 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.832 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.732 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 3.632 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 2.843 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 3.912 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.283 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 2.588 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 2.722 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 2.722 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 2.593 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 2.593 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 2.588 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 2.588 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.616 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 3.031 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.846 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.606 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.616 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.204 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.174 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 3.505 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 3.644 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 3.501 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 3.276 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.816 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.816 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.792 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.792 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.806 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.796 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.474 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.474 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.276 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.276 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.376 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.366 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.530 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.520 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.724 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.724 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.359 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.571 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.571 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.910 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.772 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.782 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.910 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 6.451 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 6.538 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 6.529 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 6.533 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 6.529 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 6.451 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 6.451 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 6.532 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 6.532 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 3.983 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 4.048 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 4.048 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 4.035 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 4.035 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 4.022 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 4.022 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 3.993 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 3.983 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 4.031 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 4.031 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 4.184 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 4.184 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 4.163 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 4.163 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 4.322 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 4.312 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 4.126 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 4.508 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.837 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.713 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.508 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.817 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.817 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 4.844 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 4.844 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.668 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.668 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.668 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.658 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.518 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.518 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.832 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.732 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.228 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.768 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.768 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.744 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.744 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.758 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.748 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.426 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.426 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.228 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.228 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.328 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.318 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.482 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.472 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.676 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.676 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.311 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.523 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.523 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.862 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.724 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.734 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.862 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 2.777 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 3.323 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 3.410 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 3.401 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 3.405 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 3.401 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 3.323 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 3.323 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 3.404 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 3.404 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 2.167 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 3.772 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 3.837 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 3.837 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 3.824 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 3.824 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 3.811 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 3.811 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 3.782 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 3.772 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 3.820 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 3.820 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 3.973 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 3.973 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 3.952 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 3.952 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 4.111 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 4.101 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 3.845 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 3.781 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.342 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.352 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.342 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.342 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 3.486 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.505 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 3.165 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 3.251 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 3.165 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 3.165 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 3.702 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 3.702 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 3.599 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 4.508 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.837 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.713 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.508 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.817 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.817 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 4.844 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.838 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 4.844 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.668 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.668 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.668 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.658 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.518 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.518 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.832 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.732 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.632 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 2.843 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 3.912 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.283 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 2.588 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 2.722 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 2.722 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 2.593 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 2.593 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 2.588 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 2.588 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.616 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.031 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.846 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.606 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.616 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.204 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.174 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.505 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 3.644 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.501 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.276 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.816 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.816 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.792 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.792 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.806 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.796 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.474 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.474 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.276 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.276 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.376 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.366 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.530 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.520 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.724 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.724 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.359 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.571 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.571 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.910 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.772 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.782 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.910 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 6.451 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 6.538 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 6.529 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 6.533 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 6.529 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 6.451 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 6.451 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 6.532 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 6.532 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 3.983 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 4.048 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 4.048 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 4.035 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 4.035 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 4.022 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 4.022 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 3.993 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 3.983 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 4.031 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 4.031 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 4.184 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 4.184 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 4.163 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 4.163 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 4.322 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 4.312 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 4.126 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 4.508 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.837 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.713 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.508 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.817 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.817 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 4.844 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 4.844 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.668 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.668 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.668 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.658 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.518 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.518 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.832 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.732 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 2.640 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 4.004 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 4.091 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 4.082 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 4.086 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 4.082 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 4.004 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 4.004 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 4.085 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 4.085 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 3.366 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 3.477 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 3.278 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 3.288 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 3.278 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 3.278 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 3.441 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 3.874 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.203 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.079 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 3.874 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.183 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.183 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 4.210 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.204 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 4.210 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.034 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.034 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.034 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.024 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 3.884 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 3.884 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.198 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.098 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 3.568 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.409 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 3.938 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.309 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.131 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.564 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.564 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.265 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.265 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.136 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.136 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 3.131 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 3.131 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.623 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 3.574 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.853 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.613 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.623 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.823 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.740 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 3.441 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 5.058 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 2.640 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 4.004 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 4.091 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 4.082 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 4.086 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 4.082 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 4.004 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 4.004 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 4.085 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 4.085 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 3.366 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 3.477 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.278 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.288 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.278 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.278 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.441 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 3.874 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.203 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.079 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 3.874 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.183 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.183 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 4.210 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.204 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 4.210 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.034 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.034 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.034 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.024 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 3.884 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 3.884 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.198 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.098 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.568 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.409 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 3.938 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.309 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.131 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.564 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.564 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.265 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.265 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.136 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.136 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 3.131 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 3.131 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.623 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.574 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.853 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.613 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.623 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.823 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.740 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.441 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 5.058 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 3.170 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.170 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.170 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 3.171 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 3.171 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 3.170 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.170 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.170 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 3.171 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 3.171 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+-------+------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 11.006    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 11.093    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 11.084    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 11.088    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 11.084    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 11.006    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 11.006    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 11.087    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 11.087    ;           ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 6.680     ;           ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 8.426     ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 4.708     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 5.248     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 5.248     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 5.224     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 5.224     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 5.238     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 5.228     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 4.906     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 4.906     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 4.708     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 4.708     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 4.808     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 4.798     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 4.962     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 4.952     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 5.156     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 5.156     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 4.791     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 5.003     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 5.003     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 5.342     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 5.204     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 5.214     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 5.342     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 3.710     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 14.200    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 14.287    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 14.278    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 14.282    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 14.278    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 14.200    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 14.200    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 14.281    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 14.281    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 4.874     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 11.173    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 11.238    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 11.238    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 11.225    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 11.225    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 11.212    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 11.212    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 11.183    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 11.173    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 11.221    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 11.221    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 11.374    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 11.374    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 11.353    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 11.353    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 11.512    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 11.502    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 3.994     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 12.737    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.568     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 3.578     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.568     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.568     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 3.486     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 3.731     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 3.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 3.251     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 3.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 3.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 3.599     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 10.953    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 11.282    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 11.158    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 10.953    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.262    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.262    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 11.289    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 11.283    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 11.289    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 11.113    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 11.113    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 11.113    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 11.103    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 10.963    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 10.963    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 11.277    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 11.177    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 3.858     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.383     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 3.912     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.283     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 4.617     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 5.050     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 5.050     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 4.751     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 4.751     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 4.622     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 4.622     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 4.617     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 4.617     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.616     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 5.060     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.846     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.606     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.616     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.634     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.714     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 3.731     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 3.719     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 3.501     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 3.276     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.816     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.816     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.792     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.792     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.806     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.796     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.474     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.474     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.276     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.276     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.376     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.366     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.530     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.520     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.724     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.724     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.359     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.571     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.571     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.910     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.772     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.782     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.910     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 9.012     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 9.099     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 9.090     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 9.094     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 9.090     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 9.012     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 9.012     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 9.093     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 9.093     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 6.072     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 6.137     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 6.137     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 6.124     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 6.124     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 6.111     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 6.111     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 6.082     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 6.072     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 6.120     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 6.120     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 6.273     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 6.273     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 6.252     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 6.252     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 6.411     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 6.401     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 7.549     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 6.662     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 6.991     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 6.867     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 6.662     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 6.971     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 6.971     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 6.998     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 6.992     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 6.998     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 6.822     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 6.822     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 6.822     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 6.812     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 6.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 6.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 6.986     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 6.886     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 4.708     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 5.248     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 5.248     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 5.224     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 5.224     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 5.238     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 5.228     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 4.906     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 4.906     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 4.708     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 4.708     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 4.808     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 4.798     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 4.962     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 4.952     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 5.156     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 5.156     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 4.791     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 5.003     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 5.003     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 5.342     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 5.204     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 5.214     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 5.342     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 3.710     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 14.200    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 14.287    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 14.278    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 14.282    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 14.278    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 14.200    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 14.200    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 14.281    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 14.281    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 4.874     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 11.173    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 11.238    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 11.238    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 11.225    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 11.225    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 11.212    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 11.212    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 11.183    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 11.173    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 11.221    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 11.221    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 11.374    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 11.374    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 11.353    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 11.353    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 11.512    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 11.502    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 3.994     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 12.737    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.568     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.578     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.568     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.568     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 3.486     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.731     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 3.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 3.251     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 3.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 3.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 3.599     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 10.953    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 11.282    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 11.158    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 10.953    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.262    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.262    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 11.289    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 11.283    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 11.289    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 11.113    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 11.113    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 11.113    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 11.103    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 10.963    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 10.963    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 11.277    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 11.177    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.858     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.383     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 3.912     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.283     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 4.617     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 5.050     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 5.050     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 4.751     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 4.751     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 4.622     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 4.622     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 4.617     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 4.617     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.616     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 5.060     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.846     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.606     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.616     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.634     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.714     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.731     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 3.719     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.501     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.276     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.816     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.816     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.792     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.792     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.806     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.796     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.474     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.474     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.276     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.276     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.376     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.366     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.530     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.520     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.724     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.724     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.359     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.571     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.571     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.910     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.772     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.782     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.910     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 9.012     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 9.099     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 9.090     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 9.094     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 9.090     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 9.012     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 9.012     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 9.093     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 9.093     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 6.072     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 6.137     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 6.137     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 6.124     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 6.124     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 6.111     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 6.111     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 6.082     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 6.072     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 6.120     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 6.120     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 6.273     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 6.273     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 6.252     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 6.252     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 6.411     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 6.401     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 7.549     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 6.662     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 6.991     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 6.867     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 6.662     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 6.971     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 6.971     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 6.998     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 6.992     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 6.998     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 6.822     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 6.822     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 6.822     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 6.812     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 6.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 6.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 6.986     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 6.886     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 2.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 8.407     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 8.494     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 8.485     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 8.489     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 8.485     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 8.407     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 8.407     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 8.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 8.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 4.081     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 5.827     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 3.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 3.288     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 3.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 3.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 3.441     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 5.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 5.909     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 5.785     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 5.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 5.889     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 5.889     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 5.916     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 5.910     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 5.916     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 5.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 5.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 5.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 5.730     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 5.590     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 5.590     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 5.904     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 5.804     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 3.568     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.521     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 4.016     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.387     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.212     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.645     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.645     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.346     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.346     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.217     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.217     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 3.212     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 3.212     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 3.655     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.932     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.692     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.965     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.852     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 3.441     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 5.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 2.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 8.407     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 8.494     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 8.485     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 8.489     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 8.485     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 8.407     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 8.407     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 8.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 8.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 4.081     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 5.827     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.288     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.441     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 5.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 5.909     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 5.785     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 5.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 5.889     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 5.889     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 5.916     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 5.910     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 5.916     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 5.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 5.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 5.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 5.730     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 5.590     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 5.590     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 5.904     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 5.804     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.568     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.521     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 4.016     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.387     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.212     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.645     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.645     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.346     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.346     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.217     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.217     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 3.212     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 3.212     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.655     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.932     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.692     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.965     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.852     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.441     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 5.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 5.481     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 5.481     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 5.481     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 5.565     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 5.565     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 5.481     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 5.481     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 5.481     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 5.565     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 5.565     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                    ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 9.872     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 9.959     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 9.950     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 9.954     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 9.950     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 9.872     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 9.872     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 9.953     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 9.953     ;           ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 6.680     ;           ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 6.791     ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 3.228     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.768     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.768     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.758     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.748     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.426     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.426     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.228     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.228     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.328     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.318     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.482     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.472     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.676     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.676     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.311     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.523     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.523     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.862     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.724     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.734     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.862     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 2.777     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 3.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 3.410     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 3.401     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 3.405     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 3.401     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 3.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 3.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 3.404     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 3.404     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 2.167     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 3.772     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 3.837     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 3.837     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 3.824     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 3.824     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 3.811     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 3.811     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 3.782     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 3.772     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 3.820     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 3.820     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 3.973     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 3.973     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 3.952     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 3.952     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 4.111     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 4.101     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 3.845     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 3.781     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.342     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 3.352     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.342     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.342     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 3.486     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 3.505     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 3.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 3.251     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 3.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 3.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 3.599     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 4.508     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.837     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.713     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.508     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.817     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.817     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 4.844     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.838     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 4.844     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.668     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.668     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.668     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.658     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.518     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.518     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.832     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.732     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 3.632     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 2.843     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 3.912     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.283     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 2.588     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.021     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.021     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 2.722     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 2.722     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 2.593     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 2.593     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 2.588     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 2.588     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.616     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 3.031     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.846     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.606     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.616     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.204     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.174     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 3.505     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 3.644     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 3.501     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 3.276     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.816     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.816     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.792     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.792     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.806     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.796     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.474     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.474     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.276     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.276     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.376     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.366     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.530     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.520     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.724     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.724     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.359     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.571     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.571     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.910     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.772     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.782     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.910     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 6.451     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 6.538     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 6.529     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 6.533     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 6.529     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 6.451     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 6.451     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 6.532     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 6.532     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 3.983     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 4.048     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 4.048     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 4.035     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 4.035     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 4.022     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 4.022     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 3.993     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 3.983     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 4.031     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 4.031     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 4.184     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 4.184     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 4.163     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 4.163     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 4.322     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 4.312     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 4.126     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 4.508     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.837     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.713     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.508     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.817     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.817     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 4.844     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.838     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 4.844     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.668     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.668     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.668     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.658     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.518     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.518     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.832     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.732     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.228     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.768     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.768     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.758     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.748     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.426     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.426     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.228     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.228     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.328     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.318     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.482     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.472     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.676     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.676     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.311     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.523     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.523     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.862     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.724     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.734     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.862     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 2.777     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 3.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 3.410     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 3.401     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 3.405     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 3.401     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 3.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 3.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 3.404     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 3.404     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 2.167     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 3.772     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 3.837     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 3.837     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 3.824     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 3.824     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 3.811     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 3.811     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 3.782     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 3.772     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 3.820     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 3.820     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 3.973     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 3.973     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 3.952     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 3.952     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 4.111     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 4.101     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 3.845     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 3.781     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.342     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.352     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.342     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.342     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 3.486     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.505     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 3.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 3.251     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 3.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 3.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 3.599     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 4.508     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.837     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.713     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.508     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.817     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.817     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 4.844     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.838     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 4.844     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.668     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.668     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.668     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.658     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.518     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.518     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.832     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.732     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.632     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 2.843     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 3.912     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.283     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 2.588     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.021     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.021     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 2.722     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 2.722     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 2.593     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 2.593     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 2.588     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 2.588     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.616     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.031     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.846     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.606     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.616     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.204     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.174     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.505     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 3.644     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.501     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.276     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.816     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.816     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.792     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.792     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.806     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.796     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.474     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.474     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.276     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.276     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.376     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.366     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.530     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.520     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.724     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.724     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.359     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.571     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.571     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.910     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.772     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.782     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.910     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 6.451     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 6.538     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 6.529     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 6.533     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 6.529     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 6.451     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 6.451     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 6.532     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 6.532     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 3.983     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 4.048     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 4.048     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 4.035     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 4.035     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 4.022     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 4.022     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 3.993     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 3.983     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 4.031     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 4.031     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 4.184     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 4.184     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 4.163     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 4.163     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 4.322     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 4.312     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 4.126     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 4.508     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.837     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.713     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.508     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.817     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.817     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 4.844     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.838     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 4.844     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.668     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.668     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.668     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.658     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.518     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.518     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.832     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.732     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 2.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 4.004     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 4.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 4.082     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 4.086     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 4.082     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 4.004     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 4.004     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 4.085     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 4.085     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 3.366     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 3.477     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 3.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 3.288     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 3.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 3.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 3.441     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 3.874     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.203     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.079     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 3.874     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.183     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.183     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 4.210     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.204     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 4.210     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.034     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.034     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.034     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.024     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 3.884     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 3.884     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.198     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.098     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 3.568     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.409     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 3.938     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.309     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.131     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.564     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.564     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.265     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.265     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.136     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.136     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 3.131     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 3.131     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.623     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 3.574     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.853     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.613     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.623     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.823     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 3.441     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 5.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 2.640     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 4.004     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 4.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 4.082     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 4.086     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 4.082     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 4.004     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 4.004     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 4.085     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 4.085     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 3.366     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 3.477     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.288     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.441     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 3.874     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.203     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.079     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 3.874     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.183     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.183     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 4.210     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.204     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 4.210     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.034     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.034     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.034     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.024     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 3.884     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 3.884     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.198     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.098     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.568     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.409     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 3.938     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.309     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.131     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.564     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.564     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.265     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.265     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.136     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.136     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 3.131     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 3.131     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.623     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.574     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.853     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.613     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.623     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.823     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.441     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 5.058     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 3.170     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.170     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.170     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 3.171     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 3.171     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 3.170     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.170     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.170     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 3.171     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 3.171     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                         ;
+-------------------------------------------------------------+------------+-------+----------+---------+---------------------+
; Clock                                                       ; Setup      ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+-------------------------------------------------------------+------------+-------+----------+---------+---------------------+
; Worst-case Slack                                            ; -15.012    ; 0.073 ; 20.664   ; 1.063   ; 7.852               ;
;  CLK_PLL1                                                   ; 59.724     ; 0.239 ; N/A      ; N/A     ; 30.139              ;
;  CLK_PLL2                                                   ; N/A        ; N/A   ; N/A      ; N/A     ; 31.250              ;
;  CODEC_SCLK                                                 ; 30.318     ; 0.073 ; 78.914   ; 1.073   ; 38.136              ;
;  CRT_PIN4_CLK1                                              ; N/A        ; N/A   ; N/A      ; N/A     ; 31.250              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -15.012    ; 0.215 ; 20.664   ; 1.088   ; 28.943              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -15.012    ; 0.215 ; 20.664   ; 1.088   ; 28.943              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; -14.850    ; 0.215 ; 20.664   ; 1.063   ; 13.061              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; -14.850    ; 0.215 ; 20.664   ; 1.063   ; 13.061              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; -12.179    ; 0.215 ; N/A      ; N/A     ; 7.852               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; -12.179    ; 0.215 ; N/A      ; N/A     ; 7.852               ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 38.203     ; 0.215 ; N/A      ; N/A     ; 18.420              ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 22.922     ; 0.215 ; N/A      ; N/A     ; 11.584              ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 60.376     ; 0.215 ; N/A      ; N/A     ; 30.139              ;
; Design-wide TNS                                             ; -15973.756 ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  CLK_PLL1                                                   ; 0.000      ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  CLK_PLL2                                                   ; N/A        ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  CODEC_SCLK                                                 ; 0.000      ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  CRT_PIN4_CLK1                                              ; N/A        ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -5654.283  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -5654.283  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; -1984.888  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; -1984.888  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; -347.707   ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; -347.707   ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 0.000      ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 0.000      ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 0.000      ; 0.000 ; N/A      ; N/A     ; 0.000               ;
+-------------------------------------------------------------+------------+-------+----------+---------+---------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 0.802  ; 0.802  ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; 11.918 ; 11.918 ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; -0.247 ; -0.247 ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; 13.898 ; 13.898 ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; 27.034 ; 27.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 6.398  ; 6.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 10.854 ; 10.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 7.606  ; 7.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 11.786 ; 11.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 9.605  ; 9.605  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 10.493 ; 10.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 9.830  ; 9.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 10.372 ; 10.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 11.272 ; 11.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 11.032 ; 11.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 11.786 ; 11.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 11.199 ; 11.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 16.904 ; 16.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 16.883 ; 16.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 17.496 ; 17.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; 12.218 ; 12.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 37.095 ; 37.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 19.430 ; 19.430 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 18.145 ; 18.145 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[3]     ; CLK_PLL1      ; 37.095 ; 37.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 30.582 ; 30.582 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 20.491 ; 20.491 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 14.278 ; 14.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 13.088 ; 13.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 17.946 ; 17.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 16.731 ; 16.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 15.921 ; 15.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 17.578 ; 17.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 15.422 ; 15.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 16.110 ; 16.110 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 17.620 ; 17.620 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 17.763 ; 17.763 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 17.256 ; 17.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 17.946 ; 17.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 16.433 ; 16.433 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 16.982 ; 16.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 17.855 ; 17.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 16.453 ; 16.453 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 17.184 ; 17.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 11.783 ; 11.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 13.139 ; 13.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 8.581  ; 8.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 14.092 ; 14.092 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 28.790 ; 28.790 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 28.790 ; 28.790 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 28.085 ; 28.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 27.614 ; 27.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; 13.369 ; 13.369 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; 6.446  ; 6.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; 10.895 ; 10.895 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; 15.965 ; 15.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; 8.679  ; 8.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 9.660  ; 9.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 22.206 ; 22.206 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 11.368 ; 11.368 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 22.126 ; 22.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; 7.466  ; 7.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 27.878 ; 27.878 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 18.711 ; 18.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 18.530 ; 18.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 18.530 ; 18.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 17.765 ; 17.765 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 16.256 ; 16.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 17.083 ; 17.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 17.866 ; 17.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 17.599 ; 17.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 18.210 ; 18.210 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 18.483 ; 18.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; 5.903  ; 5.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; 4.587  ; 4.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; 5.158  ; 5.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; 5.723  ; 5.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; 6.122  ; 6.122  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; 4.198  ; 4.198  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 19.851 ; 19.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 19.066 ; 19.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 18.283 ; 18.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 17.962 ; 17.962 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 18.599 ; 18.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 17.095 ; 17.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 18.501 ; 18.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 17.558 ; 17.558 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 17.851 ; 17.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 19.851 ; 19.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 17.824 ; 17.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 18.045 ; 18.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 18.838 ; 18.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 18.055 ; 18.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 19.162 ; 19.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 19.473 ; 19.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 17.836 ; 17.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; 2.890  ; 2.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 8.494  ; 8.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 28.039 ; 28.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 13.388 ; 13.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 9.379  ; 9.379  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 10.597 ; 10.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 10.082 ; 10.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 10.172 ; 10.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 10.226 ; 10.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 10.597 ; 10.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 9.565  ; 9.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 9.082  ; 9.082  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 9.248  ; 9.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 10.327 ; 10.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 13.163 ; 13.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 11.793 ; 11.793 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 11.957 ; 11.957 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 13.717 ; 13.717 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 10.818 ; 10.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; 14.144 ; 14.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; 7.292  ; 7.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; 13.752 ; 13.752 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 24.832 ; 24.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; 7.496  ; 7.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; 9.558  ; 9.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; 8.977  ; 8.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; 8.604  ; 8.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; 8.693  ; 8.693  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; 8.977  ; 8.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; 9.057  ; 9.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; 9.494  ; 9.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; 10.885 ; 10.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 10.177 ; 10.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 25.807 ; 25.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; 8.443  ; 8.443  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 8.307  ; 8.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 25.332 ; 25.332 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 6.785  ; 6.785  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 6.797  ; 6.797  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 7.401  ; 7.401  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; 7.184  ; 7.184  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 16.263 ; 16.263 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 15.872 ; 15.872 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 15.682 ; 15.682 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 28.741 ; 28.741 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 17.629 ; 17.629 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 16.344 ; 16.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 28.741 ; 28.741 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 18.835 ; 18.835 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 12.477 ; 12.477 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 11.287 ; 11.287 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 16.937 ; 16.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 15.706 ; 15.706 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 14.910 ; 14.910 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 16.937 ; 16.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 14.168 ; 14.168 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 14.583 ; 14.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 15.566 ; 15.566 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 15.949 ; 15.949 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 15.455 ; 15.455 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 16.105 ; 16.105 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 14.249 ; 14.249 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 15.140 ; 15.140 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 15.530 ; 15.530 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 13.907 ; 13.907 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 14.938 ; 14.938 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 9.421  ; 9.421  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 10.849 ; 10.849 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 10.454 ; 10.454 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; 3.956  ; 3.956  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; 3.961  ; 3.961  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; 3.002  ; 3.002  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 26.428 ; 26.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 26.428 ; 26.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 25.850 ; 25.850 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 25.773 ; 25.773 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; 8.340  ; 8.340  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 6.906  ; 6.906  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 20.152 ; 20.152 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; 8.760  ; 8.760  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 20.072 ; 20.072 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 25.824 ; 25.824 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 17.686 ; 17.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 16.689 ; 16.689 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 16.689 ; 16.689 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 15.581 ; 15.581 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 14.414 ; 14.414 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 14.758 ; 14.758 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 15.320 ; 15.320 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 15.353 ; 15.353 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 15.848 ; 15.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 16.193 ; 16.193 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 18.041 ; 18.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 18.041 ; 18.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 17.272 ; 17.272 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 17.321 ; 17.321 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 17.345 ; 17.345 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 15.568 ; 15.568 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 16.447 ; 16.447 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 15.744 ; 15.744 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 16.050 ; 16.050 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 18.010 ; 18.010 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 15.640 ; 15.640 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 16.203 ; 16.203 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 16.513 ; 16.513 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 15.509 ; 15.509 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 16.916 ; 16.916 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 17.111 ; 17.111 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 15.546 ; 15.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 26.198 ; 26.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 23.807 ; 23.807 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 8.248  ; 8.248  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; 8.381  ; 8.381  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 24.499 ; 24.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; 27.034 ; 27.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 6.398  ; 6.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 10.854 ; 10.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 7.606  ; 7.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 11.786 ; 11.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 9.605  ; 9.605  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 10.493 ; 10.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 9.830  ; 9.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 10.372 ; 10.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 11.272 ; 11.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 11.032 ; 11.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 11.786 ; 11.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 11.199 ; 11.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 16.904 ; 16.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 16.883 ; 16.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 17.496 ; 17.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; 12.218 ; 12.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 37.095 ; 37.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 19.430 ; 19.430 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 18.145 ; 18.145 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[3]     ; CRT_PIN4_CLK1 ; 37.095 ; 37.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 30.582 ; 30.582 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 20.491 ; 20.491 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 14.278 ; 14.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 13.088 ; 13.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 17.946 ; 17.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 16.731 ; 16.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 15.921 ; 15.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 17.578 ; 17.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 15.422 ; 15.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 16.110 ; 16.110 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 17.620 ; 17.620 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 17.763 ; 17.763 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.256 ; 17.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 17.946 ; 17.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 16.433 ; 16.433 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 16.982 ; 16.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 17.855 ; 17.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 16.453 ; 16.453 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 17.184 ; 17.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 11.783 ; 11.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 13.139 ; 13.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 8.581  ; 8.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 14.092 ; 14.092 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 28.790 ; 28.790 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 28.790 ; 28.790 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 28.085 ; 28.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 27.614 ; 27.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; 13.369 ; 13.369 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; 6.446  ; 6.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; 10.895 ; 10.895 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; 15.965 ; 15.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; 8.679  ; 8.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 9.660  ; 9.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 22.206 ; 22.206 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 11.368 ; 11.368 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 22.126 ; 22.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; 7.466  ; 7.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 27.878 ; 27.878 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 18.711 ; 18.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 18.530 ; 18.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 18.530 ; 18.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 17.765 ; 17.765 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 16.256 ; 16.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 17.083 ; 17.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 17.866 ; 17.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 17.599 ; 17.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 18.210 ; 18.210 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 18.483 ; 18.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; 5.903  ; 5.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; 4.587  ; 4.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; 5.158  ; 5.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; 5.723  ; 5.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; 6.122  ; 6.122  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; 4.198  ; 4.198  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 19.851 ; 19.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 19.066 ; 19.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 18.283 ; 18.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 17.962 ; 17.962 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 18.599 ; 18.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 17.095 ; 17.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 18.501 ; 18.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 17.558 ; 17.558 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 17.851 ; 17.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 19.851 ; 19.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 17.824 ; 17.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 18.045 ; 18.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 18.838 ; 18.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 18.055 ; 18.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 19.162 ; 19.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 19.473 ; 19.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 17.836 ; 17.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; 2.890  ; 2.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 8.494  ; 8.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 28.039 ; 28.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 13.388 ; 13.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 9.379  ; 9.379  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 10.597 ; 10.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 10.082 ; 10.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 10.172 ; 10.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 10.226 ; 10.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 10.597 ; 10.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 9.565  ; 9.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 9.082  ; 9.082  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 9.248  ; 9.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 10.327 ; 10.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 13.163 ; 13.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 11.793 ; 11.793 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 11.957 ; 11.957 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 13.717 ; 13.717 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 10.818 ; 10.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; 14.144 ; 14.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; 7.292  ; 7.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; 13.752 ; 13.752 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 24.832 ; 24.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; 7.496  ; 7.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; 9.558  ; 9.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; 8.977  ; 8.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; 8.604  ; 8.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; 8.693  ; 8.693  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; 8.977  ; 8.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; 9.057  ; 9.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; 9.494  ; 9.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; 10.885 ; 10.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 10.177 ; 10.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 25.807 ; 25.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; 8.443  ; 8.443  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 8.307  ; 8.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 25.332 ; 25.332 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 6.785  ; 6.785  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 6.797  ; 6.797  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 7.401  ; 7.401  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; 7.184  ; 7.184  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 16.263 ; 16.263 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 15.872 ; 15.872 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 15.682 ; 15.682 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 28.741 ; 28.741 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 17.629 ; 17.629 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 16.344 ; 16.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 28.741 ; 28.741 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 18.835 ; 18.835 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 12.477 ; 12.477 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 11.287 ; 11.287 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 16.937 ; 16.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 15.706 ; 15.706 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 14.910 ; 14.910 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 16.937 ; 16.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 14.168 ; 14.168 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 14.583 ; 14.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 15.566 ; 15.566 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 15.949 ; 15.949 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 15.455 ; 15.455 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 16.105 ; 16.105 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 14.249 ; 14.249 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 15.140 ; 15.140 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 15.530 ; 15.530 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 13.907 ; 13.907 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 14.938 ; 14.938 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 9.421  ; 9.421  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 10.849 ; 10.849 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 10.454 ; 10.454 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; 3.956  ; 3.956  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; 3.961  ; 3.961  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; 3.002  ; 3.002  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 26.428 ; 26.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 26.428 ; 26.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 25.850 ; 25.850 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 25.773 ; 25.773 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; 8.340  ; 8.340  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 6.906  ; 6.906  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 20.152 ; 20.152 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; 8.760  ; 8.760  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 20.072 ; 20.072 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 25.824 ; 25.824 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 17.686 ; 17.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 16.689 ; 16.689 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 16.689 ; 16.689 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 15.581 ; 15.581 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 14.414 ; 14.414 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 14.758 ; 14.758 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 15.320 ; 15.320 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 15.353 ; 15.353 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 15.848 ; 15.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 16.193 ; 16.193 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 18.041 ; 18.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 18.041 ; 18.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 17.272 ; 17.272 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 17.321 ; 17.321 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 17.345 ; 17.345 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 15.568 ; 15.568 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 16.447 ; 16.447 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 15.744 ; 15.744 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 16.050 ; 16.050 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 18.010 ; 18.010 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 15.640 ; 15.640 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 16.203 ; 16.203 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 16.513 ; 16.513 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 15.509 ; 15.509 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 16.916 ; 16.916 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 17.111 ; 17.111 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 15.546 ; 15.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 26.198 ; 26.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 23.807 ; 23.807 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 8.248  ; 8.248  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; 8.381  ; 8.381  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 24.499 ; 24.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; 25.030 ; 25.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; 15.388 ; 15.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; 15.710 ; 15.710 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; 15.436 ; 15.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 28.925 ; 28.925 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; 17.485 ; 17.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; 16.200 ; 16.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; 11.543 ; 11.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; 28.925 ; 28.925 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; 18.587 ; 18.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; 12.333 ; 12.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 11.143 ; 11.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 16.289 ; 16.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 15.458 ; 15.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 14.748 ; 14.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 16.062 ; 16.062 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 13.879 ; 13.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 14.294 ; 14.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 15.549 ; 15.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 15.703 ; 15.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 15.311 ; 15.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 16.289 ; 16.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; 11.800 ; 11.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 26.363 ; 26.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 26.363 ; 26.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 26.034 ; 26.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 25.957 ; 25.957 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; 20.135 ; 20.135 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; 20.055 ; 20.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 25.807 ; 25.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; 17.438 ; 17.438 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; 16.873 ; 16.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; 16.873 ; 16.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 18.194 ; 18.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 17.793 ; 17.793 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 17.110 ; 17.110 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 16.446 ; 16.446 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 17.056 ; 17.056 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 15.279 ; 15.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 16.430 ; 16.430 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 15.498 ; 15.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 15.906 ; 15.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 18.194 ; 18.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 12.089 ; 12.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 11.953 ; 11.953 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 12.478 ; 12.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 13.375 ; 13.375 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 14.016 ; 14.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 14.041 ; 14.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 14.415 ; 14.415 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 26.382 ; 26.382 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 23.559 ; 23.559 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 24.197 ; 24.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 13.671 ; 13.671 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 18.261 ; 18.261 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; 18.261 ; 18.261 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 13.729 ; 13.729 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 13.729 ; 13.729 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 13.410 ; 13.410 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 13.327 ; 13.327 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 12.881 ; 12.881 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 14.426 ; 14.426 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; 25.030 ; 25.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 15.388 ; 15.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 15.710 ; 15.710 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 15.436 ; 15.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 28.925 ; 28.925 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 17.485 ; 17.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 16.200 ; 16.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; 11.543 ; 11.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 28.925 ; 28.925 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 18.587 ; 18.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 12.333 ; 12.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 11.143 ; 11.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 16.289 ; 16.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 15.458 ; 15.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 14.748 ; 14.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 16.062 ; 16.062 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 13.879 ; 13.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 14.294 ; 14.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 15.549 ; 15.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 15.703 ; 15.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 15.311 ; 15.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 16.289 ; 16.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 11.800 ; 11.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 26.363 ; 26.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 26.363 ; 26.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 26.034 ; 26.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 25.957 ; 25.957 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 20.135 ; 20.135 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 20.055 ; 20.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 25.807 ; 25.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 17.438 ; 17.438 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 16.873 ; 16.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 16.873 ; 16.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 18.194 ; 18.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 17.793 ; 17.793 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 17.110 ; 17.110 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 16.446 ; 16.446 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 17.056 ; 17.056 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 15.279 ; 15.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 16.430 ; 16.430 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 15.498 ; 15.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 15.906 ; 15.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 18.194 ; 18.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 12.089 ; 12.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 11.953 ; 11.953 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 12.478 ; 12.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 13.375 ; 13.375 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 14.016 ; 14.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 14.041 ; 14.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 14.415 ; 14.415 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 26.382 ; 26.382 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 23.559 ; 23.559 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 24.197 ; 24.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 13.671 ; 13.671 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 18.261 ; 18.261 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 18.261 ; 18.261 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 13.729 ; 13.729 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 13.729 ; 13.729 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 13.410 ; 13.410 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 13.327 ; 13.327 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 12.881 ; 12.881 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 14.426 ; 14.426 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; 24.440 ; 24.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; 13.819 ; 13.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; 13.804 ; 13.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; 13.847 ; 13.847 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; 28.335 ; 28.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; 15.919 ; 15.919 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; 14.634 ; 14.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[5]     ; CLK_PLL1      ; 28.335 ; 28.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; 18.871 ; 18.871 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; 10.767 ; 10.767 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 9.577  ; 9.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; 16.235 ; 16.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 13.581 ; 13.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 12.842 ; 12.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 14.493 ; 14.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 12.334 ; 12.334 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 12.734 ; 12.734 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 14.001 ; 14.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 14.114 ; 14.114 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 13.745 ; 13.745 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 15.699 ; 15.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 13.328 ; 13.328 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 15.331 ; 15.331 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 16.235 ; 16.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 14.364 ; 14.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 15.177 ; 15.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 8.265  ; 8.265  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 9.276  ; 9.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; 25.882 ; 25.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; 25.882 ; 25.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; 25.444 ; 25.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; 25.367 ; 25.367 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; 18.587 ; 18.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; 18.507 ; 18.507 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; 25.131 ; 25.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; 15.561 ; 15.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 18.223 ; 18.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; 16.283 ; 16.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; 14.660 ; 14.660 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; 14.605 ; 14.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 18.223 ; 18.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 17.155 ; 17.155 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 18.057 ; 18.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 17.280 ; 17.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; 16.021 ; 16.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 17.604 ; 17.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 15.916 ; 15.916 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 15.204 ; 15.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 14.877 ; 14.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 15.511 ; 15.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 13.719 ; 13.719 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 14.882 ; 14.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 13.909 ; 13.909 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 14.340 ; 14.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 17.604 ; 17.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 14.719 ; 14.719 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 16.394 ; 16.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 17.218 ; 17.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 15.966 ; 15.966 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 17.155 ; 17.155 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 16.565 ; 16.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 15.374 ; 15.374 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; 25.792 ; 25.792 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; 21.888 ; 21.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; 23.056 ; 23.056 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; 24.440 ; 24.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 13.819 ; 13.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 13.804 ; 13.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 13.847 ; 13.847 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 28.335 ; 28.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 15.919 ; 15.919 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 14.634 ; 14.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 28.335 ; 28.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 18.871 ; 18.871 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 10.767 ; 10.767 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 9.577  ; 9.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 16.235 ; 16.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 13.581 ; 13.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 12.842 ; 12.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 14.493 ; 14.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 12.334 ; 12.334 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 12.734 ; 12.734 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 14.001 ; 14.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 14.114 ; 14.114 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 13.745 ; 13.745 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 15.699 ; 15.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 13.328 ; 13.328 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 15.331 ; 15.331 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 16.235 ; 16.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 14.364 ; 14.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 15.177 ; 15.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 8.265  ; 8.265  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 9.276  ; 9.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 25.882 ; 25.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 25.882 ; 25.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 25.444 ; 25.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 25.367 ; 25.367 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 18.587 ; 18.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 18.507 ; 18.507 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 25.131 ; 25.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 15.561 ; 15.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 18.223 ; 18.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 16.283 ; 16.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 14.660 ; 14.660 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 14.605 ; 14.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 18.223 ; 18.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 17.155 ; 17.155 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 18.057 ; 18.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 17.280 ; 17.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 16.021 ; 16.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 17.604 ; 17.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 15.916 ; 15.916 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 15.204 ; 15.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 14.877 ; 14.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 15.511 ; 15.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 13.719 ; 13.719 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 14.882 ; 14.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 13.909 ; 13.909 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 14.340 ; 14.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 17.604 ; 17.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 14.719 ; 14.719 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 16.394 ; 16.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 17.218 ; 17.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 15.966 ; 15.966 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 17.155 ; 17.155 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 16.565 ; 16.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 15.374 ; 15.374 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 25.792 ; 25.792 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 21.888 ; 21.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 23.056 ; 23.056 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 0.078  ; 0.078  ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; -5.044 ; -5.044 ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; 0.651  ; 0.651  ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; -5.366 ; -5.366 ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; -3.324 ; -3.324 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -3.439 ; -3.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -3.686 ; -3.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -3.885 ; -3.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; -3.618 ; -3.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; -3.618 ; -3.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; -3.652 ; -3.652 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; -3.891 ; -3.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; -3.659 ; -3.659 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; -3.762 ; -3.762 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; -3.801 ; -3.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; -3.870 ; -3.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; -3.760 ; -3.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -3.535 ; -3.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -3.406 ; -3.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -3.968 ; -3.968 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; -4.295 ; -4.295 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.183 ; -4.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -5.406 ; -5.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -5.036 ; -5.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[3]     ; CLK_PLL1      ; -4.183 ; -4.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -6.128 ; -6.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -5.249 ; -5.249 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -2.652 ; -2.652 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -2.191 ; -2.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -3.590 ; -3.590 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -3.937 ; -3.937 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -3.920 ; -3.920 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -3.747 ; -3.747 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -3.904 ; -3.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -3.911 ; -3.911 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -3.838 ; -3.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -3.877 ; -3.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -4.174 ; -4.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -3.590 ; -3.590 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -4.209 ; -4.209 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -4.019 ; -4.019 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -4.630 ; -4.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.829 ; -4.829 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -4.454 ; -4.454 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -3.837 ; -3.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -4.300 ; -4.300 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; -4.421 ; -4.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -3.861 ; -3.861 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -4.992 ; -4.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -4.992 ; -4.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -4.997 ; -4.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -4.992 ; -4.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; -4.604 ; -4.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; -1.634 ; -1.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; -4.258 ; -4.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; -4.782 ; -4.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; -3.727 ; -3.727 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -3.913 ; -3.913 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -5.361 ; -5.361 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; -3.991 ; -3.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -5.296 ; -5.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; -3.882 ; -3.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -3.809 ; -3.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -4.488 ; -4.488 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -5.917 ; -5.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.943 ; -6.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.685 ; -6.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -5.917 ; -5.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.156 ; -6.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -6.290 ; -6.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -6.476 ; -6.476 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -6.573 ; -6.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.916 ; -6.916 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; -3.204 ; -3.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; -1.528 ; -1.528 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; -1.811 ; -1.811 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; -2.113 ; -2.113 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; -2.207 ; -2.207 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; -1.801 ; -1.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.901 ; -3.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -4.027 ; -4.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.969 ; -3.969 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -4.386 ; -4.386 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -4.401 ; -4.401 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -4.244 ; -4.244 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -4.630 ; -4.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -4.746 ; -4.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -4.088 ; -4.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -4.285 ; -4.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -4.143 ; -4.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -4.002 ; -4.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -4.127 ; -4.127 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -4.055 ; -4.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -3.901 ; -3.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -3.915 ; -3.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; -1.288 ; -1.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; -4.474 ; -4.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -3.521 ; -3.521 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; -4.499 ; -4.499 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; -3.908 ; -3.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; -3.683 ; -3.683 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; -3.696 ; -3.696 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; -3.885 ; -3.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; -3.665 ; -3.665 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; -3.797 ; -3.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; -3.666 ; -3.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; -3.444 ; -3.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; -3.928 ; -3.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; -3.518 ; -3.518 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; -4.038 ; -4.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; -3.946 ; -3.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; -3.904 ; -3.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; -4.107 ; -4.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; -3.575 ; -3.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; -4.541 ; -4.541 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -4.527 ; -4.527 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; -3.795 ; -3.795 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; -4.761 ; -4.761 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; -3.774 ; -3.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; -3.774 ; -3.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; -3.776 ; -3.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; -4.050 ; -4.050 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; -4.392 ; -4.392 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; -4.731 ; -4.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; -5.336 ; -5.336 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -4.891 ; -4.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -4.661 ; -4.661 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; -4.192 ; -4.192 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; -3.780 ; -3.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; -4.886 ; -4.886 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -3.547 ; -3.547 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -3.599 ; -3.599 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -3.837 ; -3.837 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; -3.748 ; -3.748 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -6.641 ; -6.641 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -6.518 ; -6.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -6.585 ; -6.585 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.927 ; -4.927 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.584 ; -7.584 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -7.137 ; -7.137 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -5.957 ; -5.957 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -4.927 ; -4.927 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -4.753 ; -4.753 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -4.292 ; -4.292 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -4.269 ; -4.269 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -4.372 ; -4.372 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -4.628 ; -4.628 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -4.344 ; -4.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -4.269 ; -4.269 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -4.560 ; -4.560 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -4.760 ; -4.760 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -4.999 ; -4.999 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -5.371 ; -5.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -4.546 ; -4.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -4.291 ; -4.291 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -4.297 ; -4.297 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -4.828 ; -4.828 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.945 ; -4.945 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -4.606 ; -4.606 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -4.350 ; -4.350 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -4.990 ; -4.990 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -4.936 ; -4.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; -1.528 ; -1.528 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; -1.474 ; -1.474 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; -1.268 ; -1.268 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -4.770 ; -4.770 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -4.953 ; -4.953 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -4.790 ; -4.790 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -4.770 ; -4.770 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; -4.379 ; -4.379 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -3.656 ; -3.656 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -8.486 ; -8.486 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; -4.530 ; -4.530 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -8.421 ; -8.421 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -4.559 ; -4.559 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -7.459 ; -7.459 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -6.195 ; -6.195 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.908 ; -6.908 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.767 ; -6.767 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.195 ; -6.195 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.354 ; -6.354 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -6.406 ; -6.406 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -6.628 ; -6.628 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -6.593 ; -6.593 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.777 ; -6.777 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -6.448 ; -6.448 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -7.557 ; -7.557 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -7.144 ; -7.144 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -7.163 ; -7.163 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -7.291 ; -7.291 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -6.655 ; -6.655 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -6.950 ; -6.950 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -6.651 ; -6.651 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -6.901 ; -6.901 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -7.518 ; -7.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -6.705 ; -6.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -6.784 ; -6.784 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -6.963 ; -6.963 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -6.456 ; -6.456 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -7.289 ; -7.289 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -7.022 ; -7.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -6.448 ; -6.448 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -4.668 ; -4.668 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -5.696 ; -5.696 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -4.365 ; -4.365 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; -4.343 ; -4.343 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -5.587 ; -5.587 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; -3.324 ; -3.324 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -3.439 ; -3.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -3.686 ; -3.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -3.885 ; -3.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -3.618 ; -3.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -3.618 ; -3.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -3.652 ; -3.652 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -3.891 ; -3.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -3.659 ; -3.659 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -3.762 ; -3.762 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -3.801 ; -3.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -3.870 ; -3.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -3.760 ; -3.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -3.535 ; -3.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -3.406 ; -3.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -3.968 ; -3.968 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; -4.295 ; -4.295 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.183 ; -4.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -5.406 ; -5.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -5.036 ; -5.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[3]     ; CRT_PIN4_CLK1 ; -4.183 ; -4.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -6.128 ; -6.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -5.249 ; -5.249 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -2.652 ; -2.652 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -2.191 ; -2.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -3.590 ; -3.590 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -3.937 ; -3.937 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -3.920 ; -3.920 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -3.747 ; -3.747 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -3.904 ; -3.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -3.911 ; -3.911 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -3.838 ; -3.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -3.877 ; -3.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.174 ; -4.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -3.590 ; -3.590 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -4.209 ; -4.209 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.019 ; -4.019 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.630 ; -4.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.829 ; -4.829 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.454 ; -4.454 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -3.837 ; -3.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.300 ; -4.300 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; -4.421 ; -4.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -3.861 ; -3.861 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -4.992 ; -4.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -4.992 ; -4.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -4.997 ; -4.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -4.992 ; -4.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; -4.604 ; -4.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; -1.634 ; -1.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; -4.258 ; -4.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; -4.782 ; -4.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; -3.727 ; -3.727 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -3.913 ; -3.913 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -5.361 ; -5.361 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; -3.991 ; -3.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -5.296 ; -5.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; -3.882 ; -3.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -3.809 ; -3.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -4.488 ; -4.488 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -5.917 ; -5.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.943 ; -6.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.685 ; -6.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -5.917 ; -5.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.156 ; -6.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -6.290 ; -6.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -6.476 ; -6.476 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -6.573 ; -6.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.916 ; -6.916 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; -3.204 ; -3.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; -1.528 ; -1.528 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; -1.811 ; -1.811 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; -2.113 ; -2.113 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; -2.207 ; -2.207 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; -1.801 ; -1.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.901 ; -3.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -4.027 ; -4.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.969 ; -3.969 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -4.386 ; -4.386 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -4.401 ; -4.401 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -4.244 ; -4.244 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -4.630 ; -4.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -4.746 ; -4.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -4.088 ; -4.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -4.285 ; -4.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -4.143 ; -4.143 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -4.002 ; -4.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -4.127 ; -4.127 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -4.055 ; -4.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -3.901 ; -3.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -3.915 ; -3.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; -1.288 ; -1.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; -4.474 ; -4.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -3.521 ; -3.521 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; -4.499 ; -4.499 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; -3.908 ; -3.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; -3.683 ; -3.683 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; -3.696 ; -3.696 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; -3.885 ; -3.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; -3.665 ; -3.665 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; -3.797 ; -3.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; -3.666 ; -3.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; -3.442 ; -3.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; -3.444 ; -3.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; -3.928 ; -3.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; -3.518 ; -3.518 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; -4.038 ; -4.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; -3.946 ; -3.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; -3.904 ; -3.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; -4.107 ; -4.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; -3.575 ; -3.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; -4.541 ; -4.541 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -4.527 ; -4.527 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; -3.795 ; -3.795 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; -4.761 ; -4.761 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; -3.774 ; -3.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; -3.774 ; -3.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; -3.776 ; -3.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; -4.050 ; -4.050 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; -4.392 ; -4.392 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; -4.731 ; -4.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; -5.336 ; -5.336 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -4.891 ; -4.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -4.661 ; -4.661 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; -4.192 ; -4.192 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; -3.780 ; -3.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -4.886 ; -4.886 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -3.547 ; -3.547 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -3.599 ; -3.599 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -3.837 ; -3.837 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; -3.748 ; -3.748 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -6.641 ; -6.641 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -6.518 ; -6.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.585 ; -6.585 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.927 ; -4.927 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.584 ; -7.584 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -7.137 ; -7.137 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -5.957 ; -5.957 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -4.927 ; -4.927 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -4.753 ; -4.753 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -4.292 ; -4.292 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.269 ; -4.269 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.372 ; -4.372 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.628 ; -4.628 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.344 ; -4.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.269 ; -4.269 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.560 ; -4.560 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.760 ; -4.760 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.999 ; -4.999 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -5.371 ; -5.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.546 ; -4.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -4.291 ; -4.291 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.297 ; -4.297 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.828 ; -4.828 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.945 ; -4.945 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.606 ; -4.606 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.350 ; -4.350 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.990 ; -4.990 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -4.936 ; -4.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; -1.528 ; -1.528 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; -1.474 ; -1.474 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; -1.268 ; -1.268 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -4.770 ; -4.770 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -4.953 ; -4.953 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -4.790 ; -4.790 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -4.770 ; -4.770 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; -4.379 ; -4.379 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -3.656 ; -3.656 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -8.486 ; -8.486 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; -4.530 ; -4.530 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -8.421 ; -8.421 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.559 ; -4.559 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.459 ; -7.459 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -6.195 ; -6.195 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.908 ; -6.908 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.767 ; -6.767 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.195 ; -6.195 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.354 ; -6.354 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -6.406 ; -6.406 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -6.628 ; -6.628 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -6.593 ; -6.593 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.777 ; -6.777 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -6.448 ; -6.448 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -7.557 ; -7.557 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -7.144 ; -7.144 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -7.163 ; -7.163 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -7.291 ; -7.291 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -6.655 ; -6.655 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -6.950 ; -6.950 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -6.651 ; -6.651 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -6.901 ; -6.901 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -7.518 ; -7.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -6.705 ; -6.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -6.784 ; -6.784 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -6.963 ; -6.963 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -6.456 ; -6.456 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -7.289 ; -7.289 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -7.022 ; -7.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -6.448 ; -6.448 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.668 ; -4.668 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.696 ; -5.696 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -4.365 ; -4.365 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; -4.343 ; -4.343 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.587 ; -5.587 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; -4.426 ; -4.426 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; -6.457 ; -6.457 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; -6.484 ; -6.484 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; -6.485 ; -6.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.574 ; -4.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; -4.574 ; -4.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; -4.775 ; -4.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; -5.016 ; -5.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; -5.218 ; -5.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; -5.330 ; -5.330 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; -2.055 ; -2.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -2.133 ; -2.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; -4.594 ; -4.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; -4.160 ; -4.160 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; -4.167 ; -4.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; -4.200 ; -4.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; -4.528 ; -4.528 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; -4.899 ; -4.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; -5.144 ; -5.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; -4.941 ; -4.941 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; -5.339 ; -5.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -5.046 ; -5.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -5.174 ; -5.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -5.046 ; -5.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -5.437 ; -5.437 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; -8.254 ; -8.254 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; -8.189 ; -8.189 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -4.389 ; -4.389 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; -7.096 ; -7.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; -7.303 ; -7.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; -7.303 ; -7.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.537 ; -3.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -3.732 ; -3.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.708 ; -3.708 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -3.781 ; -3.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -3.690 ; -3.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -3.614 ; -3.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -3.846 ; -3.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -3.537 ; -3.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -3.859 ; -3.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -3.845 ; -3.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -3.758 ; -3.758 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -3.775 ; -3.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -3.751 ; -3.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -3.808 ; -3.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -3.859 ; -3.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -3.682 ; -3.682 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -3.841 ; -3.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; -3.382 ; -3.382 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -5.475 ; -5.475 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; -4.927 ; -4.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; -5.408 ; -5.408 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -6.562 ; -6.562 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; -6.562 ; -6.562 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -5.966 ; -5.966 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -6.149 ; -6.149 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -5.986 ; -5.986 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -5.966 ; -5.966 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -5.805 ; -5.805 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -5.858 ; -5.858 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; -4.426 ; -4.426 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -6.457 ; -6.457 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -6.484 ; -6.484 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.485 ; -6.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.574 ; -4.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -4.574 ; -4.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -4.775 ; -4.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; -5.016 ; -5.016 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -5.218 ; -5.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -5.330 ; -5.330 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -2.055 ; -2.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -2.133 ; -2.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.594 ; -4.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.160 ; -4.160 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.167 ; -4.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.200 ; -4.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.528 ; -4.528 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.899 ; -4.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -5.144 ; -5.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.941 ; -4.941 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -5.339 ; -5.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.046 ; -5.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.174 ; -5.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.046 ; -5.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.437 ; -5.437 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -8.254 ; -8.254 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -8.189 ; -8.189 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.389 ; -4.389 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.096 ; -7.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -7.303 ; -7.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -7.303 ; -7.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.537 ; -3.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -3.732 ; -3.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.708 ; -3.708 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -3.781 ; -3.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -3.690 ; -3.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -3.614 ; -3.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -3.846 ; -3.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -3.537 ; -3.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -3.859 ; -3.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -3.845 ; -3.845 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -3.758 ; -3.758 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -3.775 ; -3.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -3.751 ; -3.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -3.808 ; -3.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -3.859 ; -3.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -3.682 ; -3.682 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -3.841 ; -3.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -3.382 ; -3.382 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.475 ; -5.475 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -4.927 ; -4.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -5.408 ; -5.408 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -6.562 ; -6.562 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -6.562 ; -6.562 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.966 ; -5.966 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -6.149 ; -6.149 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.986 ; -5.986 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.966 ; -5.966 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -5.805 ; -5.805 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.858 ; -5.858 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; -4.116 ; -4.116 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; -6.066 ; -6.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; -6.048 ; -6.048 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; -6.105 ; -6.105 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; -6.111 ; -6.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.032 ; -7.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; -6.585 ; -6.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[5]     ; CLK_PLL1      ; -6.111 ; -6.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; -6.407 ; -6.407 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; -4.201 ; -4.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -3.740 ; -3.740 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; -4.158 ; -4.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; -3.769 ; -3.769 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; -3.812 ; -3.812 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; -3.947 ; -3.947 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; -4.314 ; -4.314 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; -4.519 ; -4.519 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; -4.819 ; -4.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; -4.316 ; -4.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; -3.806 ; -3.806 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; -3.768 ; -3.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; -4.378 ; -4.378 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; -4.575 ; -4.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; -4.061 ; -4.061 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; -4.184 ; -4.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; -4.376 ; -4.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; -4.738 ; -4.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; -4.738 ; -4.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; -4.743 ; -4.743 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; -6.295 ; -6.295 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; -8.040 ; -8.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; -7.975 ; -7.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; -5.815 ; -5.815 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; -6.844 ; -6.844 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; -3.794 ; -3.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.678 ; -6.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.282 ; -6.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; -5.666 ; -5.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; -4.013 ; -4.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; -3.914 ; -3.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; -3.794 ; -3.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; -3.865 ; -3.865 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.516 ; -6.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -6.042 ; -6.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -6.942 ; -6.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -6.674 ; -6.674 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -6.588 ; -6.588 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -6.834 ; -6.834 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -6.042 ; -6.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -6.504 ; -6.504 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -6.171 ; -6.171 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -6.349 ; -6.349 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -7.288 ; -7.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -6.220 ; -6.220 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -6.255 ; -6.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -6.513 ; -6.513 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -6.086 ; -6.086 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -6.744 ; -6.744 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -6.856 ; -6.856 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -6.187 ; -6.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; -4.549 ; -4.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; -6.547 ; -6.547 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; -5.137 ; -5.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; -4.116 ; -4.116 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -6.066 ; -6.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -6.048 ; -6.048 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.105 ; -6.105 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -6.111 ; -6.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.032 ; -7.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -6.585 ; -6.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -6.111 ; -6.111 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -6.407 ; -6.407 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -4.201 ; -4.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -3.740 ; -3.740 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.158 ; -4.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -3.769 ; -3.769 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -3.812 ; -3.812 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -3.947 ; -3.947 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.314 ; -4.314 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.519 ; -4.519 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.819 ; -4.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.316 ; -4.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -3.806 ; -3.806 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -3.768 ; -3.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.378 ; -4.378 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.575 ; -4.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.061 ; -4.061 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.184 ; -4.184 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.376 ; -4.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -4.738 ; -4.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -4.738 ; -4.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -4.743 ; -4.743 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -6.295 ; -6.295 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -8.040 ; -8.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -7.975 ; -7.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -5.815 ; -5.815 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -6.844 ; -6.844 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -3.794 ; -3.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.678 ; -6.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.282 ; -6.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -5.666 ; -5.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -4.013 ; -4.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -3.914 ; -3.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -3.794 ; -3.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -3.865 ; -3.865 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.516 ; -6.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -6.042 ; -6.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -6.942 ; -6.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -6.674 ; -6.674 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -6.588 ; -6.588 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -6.834 ; -6.834 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -6.042 ; -6.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -6.504 ; -6.504 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -6.171 ; -6.171 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -6.349 ; -6.349 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -7.288 ; -7.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -6.220 ; -6.220 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -6.255 ; -6.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -6.513 ; -6.513 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -6.086 ; -6.086 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -6.744 ; -6.744 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -6.856 ; -6.856 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -6.187 ; -6.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.549 ; -4.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -6.547 ; -6.547 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.137 ; -5.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                      ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 20.458 ; 20.458 ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 20.735 ; 20.735 ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 19.745 ; 19.745 ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 31.124 ; 31.124 ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 30.642 ; 30.642 ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 30.272 ; 30.272 ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 26.934 ; 26.934 ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 31.001 ; 31.001 ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 31.124 ; 31.124 ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 30.064 ; 30.064 ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 30.947 ; 30.947 ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 27.631 ; 27.631 ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 28.558 ; 28.558 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 27.156 ; 27.156 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 27.703 ; 27.703 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 27.270 ; 27.270 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 28.558 ; 28.558 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 27.647 ; 27.647 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 27.542 ; 27.542 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 25.694 ; 25.694 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 27.074 ; 27.074 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 25.997 ; 25.997 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 24.708 ; 24.708 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 23.156 ; 23.156 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 23.944 ; 23.944 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 23.856 ; 23.856 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 24.497 ; 24.497 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 25.807 ; 25.807 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 26.373 ; 26.373 ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 9.159  ; 9.159  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 30.053 ; 30.053 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 28.804 ; 28.804 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 28.235 ; 28.235 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 27.558 ; 27.558 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 28.509 ; 28.509 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 26.849 ; 26.849 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 30.053 ; 30.053 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 28.180 ; 28.180 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 29.495 ; 29.495 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 27.854 ; 27.854 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 24.860 ; 24.860 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 23.424 ; 23.424 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 25.105 ; 25.105 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 24.982 ; 24.982 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 24.733 ; 24.733 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 28.173 ; 28.173 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 26.695 ; 26.695 ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 13.616 ; 13.616 ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 7.985  ; 7.985  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 7.069  ; 7.069  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 20.261 ; 20.261 ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 20.261 ; 20.261 ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 22.682 ; 22.682 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 22.682 ; 22.682 ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 22.134 ; 22.134 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 19.661 ; 19.661 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 20.847 ; 20.847 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 19.335 ; 19.335 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 21.979 ; 21.979 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 20.719 ; 20.719 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 18.806 ; 18.806 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 19.149 ; 19.149 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 19.891 ; 19.891 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 21.237 ; 21.237 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 20.201 ; 20.201 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 18.583 ; 18.583 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 19.685 ; 19.685 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 19.686 ; 19.686 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 20.452 ; 20.452 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 22.134 ; 22.134 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 22.000 ; 22.000 ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 24.500 ; 24.500 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 21.309 ; 21.309 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 21.379 ; 21.379 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 19.623 ; 19.623 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 21.930 ; 21.930 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 19.921 ; 19.921 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 21.317 ; 21.317 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 21.635 ; 21.635 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 22.312 ; 22.312 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 23.094 ; 23.094 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 20.353 ; 20.353 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 18.851 ; 18.851 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 20.846 ; 20.846 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 20.812 ; 20.812 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 20.688 ; 20.688 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 24.500 ; 24.500 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 22.322 ; 22.322 ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 17.905 ; 17.905 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.905 ; 17.905 ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.746  ; 9.746  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 20.326 ; 20.326 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 20.326 ; 20.326 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 12.086 ; 12.086 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.524 ; 12.524 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.661 ; 12.661 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 11.152 ; 11.152 ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 9.442  ; 9.442  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 17.905 ; 17.905 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.905 ; 17.905 ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.746  ; 9.746  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 20.326 ; 20.326 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 20.326 ; 20.326 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 12.086 ; 12.086 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.524 ; 12.524 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.661 ; 12.661 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 11.152 ; 11.152 ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 9.442  ; 9.442  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 30.698 ; 30.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 30.975 ; 30.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 22.933 ; 22.933 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 19.626 ; 19.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 19.898 ; 19.898 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 19.702 ; 19.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 19.456 ; 19.456 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 19.630 ; 19.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 20.219 ; 20.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 18.990 ; 18.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 20.159 ; 20.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 19.749 ; 19.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 19.639 ; 19.639 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 19.672 ; 19.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 21.452 ; 21.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 21.851 ; 21.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 20.778 ; 20.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 22.731 ; 22.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 22.933 ; 22.933 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 21.435 ; 21.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 22.722 ; 22.722 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 21.687 ; 21.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 21.521 ; 21.521 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 21.831 ; 21.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 20.823 ; 20.823 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 20.729 ; 20.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 10.232 ; 10.232 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 4.042  ; 4.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 8.472  ; 8.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 7.095  ; 7.095  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 7.420  ; 7.420  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 28.273 ; 28.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 29.985 ; 29.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 41.364 ; 41.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 40.882 ; 40.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 40.512 ; 40.512 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 37.174 ; 37.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 41.241 ; 41.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 41.364 ; 41.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 40.304 ; 40.304 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 41.187 ; 41.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 37.871 ; 37.871 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 6.763  ; 6.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 6.175  ; 6.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 6.275  ; 6.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 7.903  ; 7.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 7.267  ; 7.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 6.570  ; 6.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 5.905  ; 5.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 8.079  ; 8.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 40.226 ; 40.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 38.634 ; 38.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 39.007 ; 39.007 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 38.679 ; 38.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 40.151 ; 40.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 39.625 ; 39.625 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 40.198 ; 40.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 38.215 ; 38.215 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 39.083 ; 39.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 40.226 ; 40.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 38.894 ; 38.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 37.269 ; 37.269 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 37.789 ; 37.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 37.640 ; 37.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 38.561 ; 38.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 38.589 ; 38.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 38.827 ; 38.827 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 9.481  ; 9.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 6.696  ; 6.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 9.835  ; 9.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 5.678  ; 5.678  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 5.903  ; 5.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 19.807 ; 19.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 19.807 ; 19.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 19.131 ; 19.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 19.487 ; 19.487 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 6.182  ; 6.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 6.505  ; 6.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 7.388  ; 7.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 8.074  ; 8.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 7.943  ; 7.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 7.889  ; 7.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 6.597  ; 6.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 7.967  ; 7.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 21.293 ; 21.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 21.205 ; 21.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 30.534 ; 30.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 30.464 ; 30.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 6.800  ; 6.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 5.246  ; 5.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 7.124  ; 7.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 10.449 ; 10.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 9.469  ; 9.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 8.269  ; 8.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 26.045 ; 26.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 26.986 ; 26.986 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 26.011 ; 26.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 26.357 ; 26.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 26.418 ; 26.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 27.822 ; 27.822 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 28.112 ; 28.112 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 30.703 ; 30.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 30.337 ; 30.337 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 27.012 ; 27.012 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 7.930  ; 7.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 10.376 ; 10.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 9.393  ; 9.393  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 9.331  ; 9.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 10.376 ; 10.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 9.938  ; 9.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 24.229 ; 24.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 7.751  ; 7.751  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 6.795  ; 6.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 9.568  ; 9.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 5.629  ; 5.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 6.850  ; 6.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.238  ; 6.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 8.974  ; 8.974  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 9.568  ; 9.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 9.339  ; 9.339  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 9.325  ; 9.325  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 5.952  ; 5.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 6.145  ; 6.145  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 9.769  ; 9.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 10.874 ; 10.874 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 31.123 ; 31.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 26.245 ; 26.245 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 24.218 ; 24.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 24.250 ; 24.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 25.329 ; 25.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 24.121 ; 24.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 27.176 ; 27.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 25.238 ; 25.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 25.471 ; 25.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 31.123 ; 31.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 25.816 ; 25.816 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 21.474 ; 21.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 22.660 ; 22.660 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 21.790 ; 21.790 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 29.480 ; 29.480 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 29.480 ; 29.480 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 27.458 ; 27.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 29.642 ; 29.642 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 29.638 ; 29.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 42.709 ; 42.709 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 40.282 ; 40.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 39.539 ; 39.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 38.967 ; 38.967 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 40.102 ; 40.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 38.827 ; 38.827 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 42.709 ; 42.709 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 40.701 ; 40.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 41.504 ; 41.504 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 42.083 ; 42.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 39.046 ; 39.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 37.537 ; 37.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 38.950 ; 38.950 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 38.766 ; 38.766 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 38.797 ; 38.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 40.955 ; 40.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 39.149 ; 39.149 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 30.828 ; 30.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 30.024 ; 30.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 29.076 ; 29.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 29.977 ; 29.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 30.543 ; 30.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 29.902 ; 29.902 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 11.501 ; 11.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 26.506 ; 26.506 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 26.125 ; 26.125 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 27.198 ; 27.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 26.777 ; 26.777 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 27.753 ; 27.753 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 26.639 ; 26.639 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 26.670 ; 26.670 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 12.811 ; 12.811 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 10.124 ; 10.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 7.581  ; 7.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 7.177  ; 7.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 13.257 ; 13.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 8.155  ; 8.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 7.804  ; 7.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 8.155  ; 8.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 7.487  ; 7.487  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 7.807  ; 7.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 7.133  ; 7.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 7.211  ; 7.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 7.181  ; 7.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 7.054  ; 7.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 6.130  ; 6.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 9.110  ; 9.110  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 5.120  ; 5.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 5.830  ; 5.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 9.641  ; 9.641  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 8.960  ; 8.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 7.918  ; 7.918  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 8.946  ; 8.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 10.869 ; 10.869 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 11.195 ; 11.195 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 6.829  ; 6.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 11.170 ; 11.170 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 7.951  ; 7.951  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 9.002  ; 9.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 9.071  ; 9.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 8.993  ; 8.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 9.071  ; 9.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 8.939  ; 8.939  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 9.039  ; 9.039  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 24.627 ; 24.627 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 7.107  ; 7.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 5.597  ; 5.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 8.344  ; 8.344  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 13.015 ; 13.015 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 14.385 ; 14.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 13.443 ; 13.443 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 17.872 ; 17.872 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 18.149 ; 18.149 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 8.089  ; 8.089  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 15.447 ; 14.770 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 17.159 ; 16.482 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 28.538 ; 28.538 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 28.056 ; 28.056 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 27.686 ; 27.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 24.348 ; 24.348 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 28.415 ; 28.415 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 28.538 ; 28.538 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 27.478 ; 27.478 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 28.361 ; 28.361 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 25.045 ; 25.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 27.372 ; 27.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 25.808 ; 25.808 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 26.181 ; 26.084 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 25.504 ; 25.853 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 27.325 ; 27.150 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 26.799 ; 26.630 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 27.372 ; 27.193 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 25.389 ; 25.268 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 26.257 ; 25.612 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 27.262 ; 27.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 25.645 ; 26.068 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 24.443 ; 24.057 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 24.963 ; 24.963 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 24.814 ; 24.346 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 25.735 ; 25.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 25.763 ; 25.763 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 26.001 ; 26.001 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 8.173  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 8.621  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 17.708 ; 17.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 17.638 ; 17.493 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 13.219 ; 12.975 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 14.160 ; 13.916 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 13.185 ; 12.941 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 13.531 ; 13.287 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 13.592 ; 13.348 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 14.996 ; 14.752 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 15.286 ; 14.609 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 17.877 ; 17.200 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 16.834 ; 17.511 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 13.509 ; 14.186 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 9.899  ; 9.899  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 17.268 ; 15.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 13.862 ; 13.862 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 13.018 ; 13.018 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 12.771 ; 12.771 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 12.594 ; 12.594 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 12.325 ; 12.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 15.518 ; 15.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 12.579 ; 12.579 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 12.982 ; 12.982 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 17.268 ; 13.639 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 13.967 ; 13.967 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 9.180  ; 9.180  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 9.914  ; 9.914  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 9.493  ; 9.493  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 15.625 ; 11.996 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 15.625 ; 11.996 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 13.603 ; 9.974  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 15.787 ; 12.158 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 12.154 ; 15.783 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 29.883 ; 29.704 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 27.456 ; 27.456 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 26.713 ; 26.616 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 25.792 ; 26.141 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 27.276 ; 27.101 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 26.001 ; 25.832 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 29.883 ; 29.704 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 27.875 ; 27.754 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 28.678 ; 28.033 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 29.119 ; 29.257 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 25.797 ; 26.220 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 24.711 ; 24.410 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 26.124 ; 26.124 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 25.940 ; 25.472 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 25.971 ; 25.810 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 28.129 ; 28.129 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 26.323 ; 26.323 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 16.973 ; 13.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 16.169 ; 12.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 11.592 ; 15.221 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 12.493 ; 16.122 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 16.688 ; 13.059 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 12.418 ; 16.047 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 12.879 ; 10.644 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 13.093 ; 10.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 14.372 ; 14.227 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 13.951 ; 8.140  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 14.927 ; 14.308 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 13.813 ; 12.627 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 13.844 ; 8.034  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 10.298 ; 10.298 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 30.698 ; 30.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 30.975 ; 30.975 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 22.933 ; 22.933 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 19.626 ; 19.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 19.898 ; 19.898 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 19.702 ; 19.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 19.456 ; 19.456 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 19.630 ; 19.630 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 20.219 ; 20.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 18.990 ; 18.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 20.159 ; 20.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 19.749 ; 19.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 19.639 ; 19.639 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 19.672 ; 19.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 21.452 ; 21.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 21.851 ; 21.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 20.778 ; 20.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 22.731 ; 22.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 22.933 ; 22.933 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 21.435 ; 21.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 22.722 ; 22.722 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 21.687 ; 21.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 21.521 ; 21.521 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 21.831 ; 21.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 20.823 ; 20.823 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 20.729 ; 20.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 10.232 ; 10.232 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 4.042  ; 4.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 8.472  ; 8.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 7.095  ; 7.095  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 7.420  ; 7.420  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 28.273 ; 28.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 29.985 ; 29.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 41.364 ; 41.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 40.882 ; 40.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 40.512 ; 40.512 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 37.174 ; 37.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 41.241 ; 41.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 41.364 ; 41.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 40.304 ; 40.304 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 41.187 ; 41.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 37.871 ; 37.871 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 6.763  ; 6.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 6.175  ; 6.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 6.275  ; 6.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 7.903  ; 7.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 7.267  ; 7.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 6.570  ; 6.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 5.905  ; 5.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 8.079  ; 8.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 40.226 ; 40.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 38.634 ; 38.634 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 39.007 ; 39.007 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 38.679 ; 38.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 40.151 ; 40.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 39.625 ; 39.625 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 40.198 ; 40.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 38.215 ; 38.215 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 39.083 ; 39.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 40.226 ; 40.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 38.894 ; 38.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 37.269 ; 37.269 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 37.789 ; 37.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 37.640 ; 37.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 38.561 ; 38.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 38.589 ; 38.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 38.827 ; 38.827 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 9.481  ; 9.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 6.696  ; 6.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 9.835  ; 9.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 5.678  ; 5.678  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 5.903  ; 5.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 19.807 ; 19.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 19.807 ; 19.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 19.131 ; 19.131 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 19.487 ; 19.487 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 6.182  ; 6.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 6.505  ; 6.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 7.388  ; 7.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 8.074  ; 8.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 7.943  ; 7.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 7.889  ; 7.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 6.597  ; 6.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 7.967  ; 7.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 21.293 ; 21.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 21.205 ; 21.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 30.534 ; 30.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 30.464 ; 30.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 6.800  ; 6.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 5.246  ; 5.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 7.124  ; 7.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 10.449 ; 10.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 9.469  ; 9.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 8.269  ; 8.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 26.045 ; 26.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 26.986 ; 26.986 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 26.011 ; 26.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 26.357 ; 26.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 26.418 ; 26.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 27.822 ; 27.822 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 28.112 ; 28.112 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 30.703 ; 30.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 30.337 ; 30.337 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 27.012 ; 27.012 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 7.930  ; 7.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 10.376 ; 10.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 9.393  ; 9.393  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 9.331  ; 9.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 10.376 ; 10.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 9.938  ; 9.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 24.229 ; 24.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 7.751  ; 7.751  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 6.795  ; 6.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 9.568  ; 9.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 5.629  ; 5.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 6.850  ; 6.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.238  ; 6.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 8.974  ; 8.974  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 9.568  ; 9.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 9.339  ; 9.339  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 9.325  ; 9.325  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 5.952  ; 5.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 6.145  ; 6.145  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 9.769  ; 9.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 10.874 ; 10.874 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 31.123 ; 31.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 26.245 ; 26.245 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 24.218 ; 24.218 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 24.250 ; 24.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 25.329 ; 25.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 24.121 ; 24.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 27.176 ; 27.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 25.238 ; 25.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 25.471 ; 25.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 31.123 ; 31.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 25.816 ; 25.816 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 21.474 ; 21.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 22.660 ; 22.660 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 21.790 ; 21.790 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 29.480 ; 29.480 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 29.480 ; 29.480 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 27.458 ; 27.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 29.642 ; 29.642 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 29.638 ; 29.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 42.709 ; 42.709 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 40.282 ; 40.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 39.539 ; 39.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 38.967 ; 38.967 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 40.102 ; 40.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 38.827 ; 38.827 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 42.709 ; 42.709 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 40.701 ; 40.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 41.504 ; 41.504 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 42.083 ; 42.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 39.046 ; 39.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 37.537 ; 37.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 38.950 ; 38.950 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 38.766 ; 38.766 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 38.797 ; 38.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 40.955 ; 40.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 39.149 ; 39.149 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 30.828 ; 30.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 30.024 ; 30.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 29.076 ; 29.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 29.977 ; 29.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 30.543 ; 30.543 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 29.902 ; 29.902 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 11.501 ; 11.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 26.506 ; 26.506 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 26.125 ; 26.125 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 27.198 ; 27.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 26.777 ; 26.777 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 27.753 ; 27.753 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 26.639 ; 26.639 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 26.670 ; 26.670 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 12.811 ; 12.811 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 10.124 ; 10.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 7.581  ; 7.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 7.177  ; 7.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 13.257 ; 13.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 8.155  ; 8.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 7.804  ; 7.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 8.155  ; 8.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 7.487  ; 7.487  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 7.807  ; 7.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 7.133  ; 7.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 7.211  ; 7.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 7.181  ; 7.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 7.054  ; 7.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 6.130  ; 6.130  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 9.110  ; 9.110  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 5.120  ; 5.120  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 5.830  ; 5.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 9.641  ; 9.641  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 8.960  ; 8.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 7.918  ; 7.918  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 8.946  ; 8.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 10.869 ; 10.869 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 11.195 ; 11.195 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 6.829  ; 6.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 11.170 ; 11.170 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 7.951  ; 7.951  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 9.002  ; 9.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 9.071  ; 9.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 8.993  ; 8.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 9.071  ; 9.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 8.939  ; 8.939  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 9.039  ; 9.039  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 24.627 ; 24.627 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 7.107  ; 7.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 5.597  ; 5.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 8.344  ; 8.344  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 13.015 ; 13.015 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 14.385 ; 14.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 13.443 ; 13.443 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 17.872 ; 17.872 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 18.149 ; 18.149 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 8.089  ; 8.089  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 15.447 ; 14.770 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 17.159 ; 16.482 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 28.538 ; 28.538 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 28.056 ; 28.056 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 27.686 ; 27.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 24.348 ; 24.348 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 28.415 ; 28.415 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 28.538 ; 28.538 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 27.478 ; 27.478 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 28.361 ; 28.361 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 25.045 ; 25.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 27.372 ; 27.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 25.808 ; 25.808 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 26.181 ; 26.084 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 25.504 ; 25.853 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 27.325 ; 27.150 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 26.799 ; 26.630 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 27.372 ; 27.193 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 25.389 ; 25.268 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 26.257 ; 25.612 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 27.262 ; 27.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 25.645 ; 26.068 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 24.443 ; 24.057 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 24.963 ; 24.963 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 24.814 ; 24.346 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 25.735 ; 25.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 25.763 ; 25.763 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 26.001 ; 26.001 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 8.173  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 8.621  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 17.708 ; 17.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 17.638 ; 17.493 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 13.219 ; 12.975 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 14.160 ; 13.916 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 13.185 ; 12.941 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 13.531 ; 13.287 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 13.592 ; 13.348 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 14.996 ; 14.752 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 15.286 ; 14.609 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 17.877 ; 17.200 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 16.834 ; 17.511 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 13.509 ; 14.186 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 9.899  ; 9.899  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 17.268 ; 15.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 13.862 ; 13.862 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 13.018 ; 13.018 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 12.771 ; 12.771 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 12.594 ; 12.594 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 12.325 ; 12.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 15.518 ; 15.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 12.579 ; 12.579 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 12.982 ; 12.982 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 17.268 ; 13.639 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 13.967 ; 13.967 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 9.180  ; 9.180  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 9.914  ; 9.914  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 9.493  ; 9.493  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 15.625 ; 11.996 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 15.625 ; 11.996 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 13.603 ; 9.974  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 15.787 ; 12.158 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 12.154 ; 15.783 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 29.883 ; 29.704 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 27.456 ; 27.456 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 26.713 ; 26.616 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 25.792 ; 26.141 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 27.276 ; 27.101 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 26.001 ; 25.832 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 29.883 ; 29.704 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 27.875 ; 27.754 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 28.678 ; 28.033 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 29.119 ; 29.257 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 25.797 ; 26.220 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 24.711 ; 24.410 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 26.124 ; 26.124 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 25.940 ; 25.472 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 25.971 ; 25.810 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 28.129 ; 28.129 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 26.323 ; 26.323 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 16.973 ; 13.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 16.169 ; 12.540 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 11.592 ; 15.221 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 12.493 ; 16.122 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 16.688 ; 13.059 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 12.418 ; 16.047 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 12.879 ; 10.644 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 13.093 ; 10.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 14.372 ; 14.227 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 13.951 ; 8.140  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 14.927 ; 14.308 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 13.813 ; 12.627 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 13.844 ; 8.034  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 10.298 ; 10.298 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 15.678 ; 15.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 15.955 ; 15.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 7.988  ; 7.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 6.667  ; 6.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 6.568  ; 6.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 14.965 ; 14.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 26.344 ; 26.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 25.862 ; 25.862 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 25.492 ; 25.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 22.154 ; 22.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 26.221 ; 26.221 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 26.344 ; 26.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 25.284 ; 25.284 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 26.167 ; 26.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 22.851 ; 22.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 8.525  ; 8.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 8.525  ; 8.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 7.094  ; 7.094  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 7.537  ; 7.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 6.895  ; 6.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 8.636  ; 8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 8.636  ; 8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 6.841  ; 6.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 7.405  ; 7.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 6.920  ; 6.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 15.471 ; 15.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 7.614  ; 7.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 7.614  ; 7.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 7.155  ; 7.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 6.332  ; 6.332  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 6.499  ; 6.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 23.778 ; 23.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 22.376 ; 22.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 22.923 ; 22.923 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 22.490 ; 22.490 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 23.778 ; 23.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 22.867 ; 22.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 22.762 ; 22.762 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 20.914 ; 20.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 22.294 ; 22.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 21.217 ; 21.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 19.928 ; 19.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 18.376 ; 18.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 19.164 ; 19.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 19.076 ; 19.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 19.717 ; 19.717 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 21.027 ; 21.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 21.593 ; 21.593 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 9.813  ; 9.813  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 8.354  ; 8.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 6.257  ; 6.257  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 6.421  ; 6.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 8.176  ; 8.176  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 16.272 ; 16.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 13.256 ; 13.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 13.114 ; 13.114 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 13.214 ; 13.214 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 13.117 ; 13.117 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 13.344 ; 13.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 16.272 ; 16.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 12.586 ; 12.586 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 12.879 ; 12.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 12.966 ; 12.966 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 14.270 ; 14.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 10.599 ; 10.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 11.393 ; 11.393 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 10.632 ; 10.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 10.391 ; 10.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 10.391 ; 10.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 6.869  ; 6.869  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 11.606 ; 11.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 11.594 ; 11.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 25.406 ; 25.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 24.024 ; 24.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 23.455 ; 23.455 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 22.778 ; 22.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 23.729 ; 23.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 22.069 ; 22.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 25.273 ; 25.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 23.408 ; 23.408 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 24.973 ; 24.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 25.406 ; 25.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 23.906 ; 23.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 22.974 ; 22.974 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 21.002 ; 21.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 23.188 ; 23.188 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 21.785 ; 21.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 23.965 ; 23.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 21.915 ; 21.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 12.780 ; 12.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 11.981 ; 11.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 11.027 ; 11.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 11.928 ; 11.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 12.531 ; 12.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 11.898 ; 11.898 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 10.873 ; 10.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 10.390 ; 10.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 9.386  ; 9.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 8.335  ; 8.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 8.429  ; 8.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 9.806  ; 9.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 8.843  ; 8.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 9.185  ; 9.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 11.034 ; 11.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 9.516  ; 9.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 7.088  ; 7.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 7.019  ; 7.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 7.088  ; 7.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 6.740  ; 6.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 6.843  ; 6.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 6.999  ; 6.999  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 15.678 ; 15.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 15.955 ; 15.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 7.988  ; 7.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 6.667  ; 6.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 6.568  ; 6.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 14.965 ; 14.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 26.344 ; 26.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 25.862 ; 25.862 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 25.492 ; 25.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 22.154 ; 22.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 26.221 ; 26.221 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 26.344 ; 26.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 25.284 ; 25.284 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 26.167 ; 26.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 22.851 ; 22.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 8.525  ; 8.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 8.525  ; 8.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 7.094  ; 7.094  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 7.537  ; 7.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 6.895  ; 6.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 8.636  ; 8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 8.636  ; 8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 6.841  ; 6.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 7.405  ; 7.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 6.920  ; 6.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 15.471 ; 15.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 7.614  ; 7.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 7.614  ; 7.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 7.155  ; 7.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 6.332  ; 6.332  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 6.499  ; 6.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 23.778 ; 23.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 22.376 ; 22.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 22.923 ; 22.923 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 22.490 ; 22.490 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 23.778 ; 23.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 22.867 ; 22.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 22.762 ; 22.762 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 20.914 ; 20.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 22.294 ; 22.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 21.217 ; 21.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 19.928 ; 19.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 18.376 ; 18.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 19.164 ; 19.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 19.076 ; 19.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 19.717 ; 19.717 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 21.027 ; 21.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 21.593 ; 21.593 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 9.813  ; 9.813  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 8.354  ; 8.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 6.257  ; 6.257  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 6.421  ; 6.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 8.176  ; 8.176  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 16.272 ; 16.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 13.256 ; 13.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 13.114 ; 13.114 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 13.214 ; 13.214 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 13.117 ; 13.117 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 13.344 ; 13.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 16.272 ; 16.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 12.586 ; 12.586 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 12.879 ; 12.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 12.966 ; 12.966 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 14.270 ; 14.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 10.599 ; 10.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 11.393 ; 11.393 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 10.632 ; 10.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 10.391 ; 10.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 10.391 ; 10.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 6.869  ; 6.869  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 11.606 ; 11.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 11.594 ; 11.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 25.406 ; 25.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 24.024 ; 24.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 23.455 ; 23.455 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 22.778 ; 22.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 23.729 ; 23.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 22.069 ; 22.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 25.273 ; 25.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 23.408 ; 23.408 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 24.973 ; 24.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 25.406 ; 25.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 23.906 ; 23.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 22.974 ; 22.974 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 21.002 ; 21.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 23.188 ; 23.188 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 21.785 ; 21.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 23.965 ; 23.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 21.915 ; 21.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 12.780 ; 12.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 11.981 ; 11.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 11.027 ; 11.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 11.928 ; 11.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 12.531 ; 12.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 11.898 ; 11.898 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 10.873 ; 10.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 10.390 ; 10.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 9.386  ; 9.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 8.335  ; 8.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 8.429  ; 8.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 9.806  ; 9.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 8.843  ; 8.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 9.185  ; 9.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 11.034 ; 11.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 9.516  ; 9.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 7.088  ; 7.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 7.019  ; 7.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 7.088  ; 7.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 6.740  ; 6.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 6.843  ; 6.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 6.999  ; 6.999  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 32.422 ; 32.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 30.802 ; 30.802 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 31.792 ; 31.792 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 31.018 ; 31.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 32.182 ; 32.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 32.422 ; 32.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 31.140 ; 31.140 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 29.656 ; 29.656 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 31.246 ; 31.246 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 31.557 ; 31.557 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 30.024 ; 30.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 29.122 ; 29.122 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 28.997 ; 28.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 28.481 ; 28.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 30.358 ; 30.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 27.666 ; 27.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 28.460 ; 28.460 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 13.657 ; 13.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 13.083 ; 13.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 13.129 ; 13.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 13.657 ; 13.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 13.638 ; 13.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 33.667 ; 33.667 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 32.450 ; 32.450 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 32.324 ; 32.324 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 31.306 ; 31.306 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 32.133 ; 32.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 31.624 ; 31.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 33.651 ; 33.651 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 32.142 ; 32.142 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 33.667 ; 33.667 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 33.414 ; 33.414 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 30.176 ; 30.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 29.390 ; 29.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 30.158 ; 30.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 29.607 ; 29.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 30.594 ; 30.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 30.032 ; 30.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 28.782 ; 28.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 32.422 ; 32.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 30.802 ; 30.802 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 31.792 ; 31.792 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 31.018 ; 31.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 32.182 ; 32.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 32.422 ; 32.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 31.140 ; 31.140 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 29.656 ; 29.656 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 31.246 ; 31.246 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 31.557 ; 31.557 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 30.024 ; 30.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 29.122 ; 29.122 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 28.997 ; 28.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 28.481 ; 28.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 30.358 ; 30.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 27.666 ; 27.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 28.460 ; 28.460 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 13.657 ; 13.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 13.083 ; 13.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 13.129 ; 13.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 13.657 ; 13.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 13.638 ; 13.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 33.667 ; 33.667 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 32.450 ; 32.450 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 32.324 ; 32.324 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 31.306 ; 31.306 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 32.133 ; 32.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 31.624 ; 31.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 33.651 ; 33.651 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 32.142 ; 32.142 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 33.667 ; 33.667 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 33.414 ; 33.414 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 30.176 ; 30.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 29.390 ; 29.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 30.158 ; 30.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 29.607 ; 29.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 30.594 ; 30.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 30.032 ; 30.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 28.782 ; 28.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.821  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.821  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 8.763  ; 8.763  ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 8.844  ; 8.844  ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 8.848  ; 8.848  ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 8.951  ; 8.951  ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 9.565  ; 9.565  ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 9.644  ; 9.644  ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 8.951  ; 8.951  ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 9.807  ; 9.807  ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 9.346  ; 9.346  ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 8.953  ; 8.953  ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 9.067  ; 9.067  ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 9.465  ; 9.465  ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 8.951  ; 8.951  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 9.717  ; 9.717  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 10.044 ; 10.044 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 9.506  ; 9.506  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 10.482 ; 10.482 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 10.199 ; 10.199 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 9.925  ; 9.925  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 9.236  ; 9.236  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 9.549  ; 9.549  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 10.504 ; 10.504 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 10.063 ; 10.063 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 9.572  ; 9.572  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 10.010 ; 10.010 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 9.958  ; 9.958  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 10.041 ; 10.041 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 8.951  ; 8.951  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 9.314  ; 9.314  ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 4.529  ; 4.529  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 9.547  ; 9.547  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 10.469 ; 10.469 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 10.310 ; 10.310 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 9.712  ; 9.712  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 10.473 ; 10.473 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 10.004 ; 10.004 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 11.024 ; 11.024 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 10.298 ; 10.298 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 10.611 ; 10.611 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 11.382 ; 11.382 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 10.226 ; 10.226 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 9.771  ; 9.771  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 10.499 ; 10.499 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 10.477 ; 10.477 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 10.234 ; 10.234 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 9.930  ; 9.930  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 9.547  ; 9.547  ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 6.448  ; 6.448  ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 3.730  ; 3.730  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 3.409  ; 3.409  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 8.319  ; 8.319  ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 8.319  ; 8.319  ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 9.381  ; 9.381  ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 9.381  ; 9.381  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 6.774  ; 6.774  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 7.335  ; 7.335  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 7.664  ; 7.664  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 7.125  ; 7.125  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 8.263  ; 8.263  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 7.613  ; 7.613  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 7.170  ; 7.170  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 6.866  ; 6.866  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 7.287  ; 7.287  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 7.979  ; 7.979  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 7.418  ; 7.418  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 6.774  ; 6.774  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 7.146  ; 7.146  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 7.023  ; 7.023  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 7.421  ; 7.421  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 7.914  ; 7.914  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 7.927  ; 7.927  ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 6.973  ; 6.973  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 8.087  ; 8.087  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 7.930  ; 7.930  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 7.331  ; 7.331  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 8.254  ; 8.254  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 7.418  ; 7.418  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 8.269  ; 8.269  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 7.928  ; 7.928  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 8.349  ; 8.349  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 8.857  ; 8.857  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 7.581  ; 7.581  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 6.973  ; 6.973  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 7.635  ; 7.635  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 7.542  ; 7.542  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 7.614  ; 7.614  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 8.893  ; 8.893  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 8.160  ; 8.160  ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.333  ; 7.333  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.333  ; 7.333  ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 4.357  ; 4.357  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.914  ; 4.914  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.395  ; 8.395  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.241  ; 5.241  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.398  ; 5.398  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.450  ; 5.450  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.914  ; 4.914  ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 4.229  ; 4.229  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.333  ; 7.333  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.333  ; 7.333  ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 4.357  ; 4.357  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.914  ; 4.914  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.395  ; 8.395  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.241  ; 5.241  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.398  ; 5.398  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.450  ; 5.450  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.914  ; 4.914  ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 4.229  ; 4.229  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 3.525  ; 3.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 3.608  ; 3.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 2.666  ; 2.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 4.055  ; 4.055  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 4.135  ; 4.135  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 4.010  ; 4.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 3.925  ; 3.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 3.761  ; 3.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 4.207  ; 4.207  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 3.821  ; 3.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 3.940  ; 3.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 4.014  ; 4.014  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 3.767  ; 3.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 3.832  ; 3.832  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 2.666  ; 2.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 3.198  ; 3.198  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 3.320  ; 3.320  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 3.383  ; 3.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 3.309  ; 3.309  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 3.266  ; 3.266  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 3.257  ; 3.257  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 3.278  ; 3.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 4.069  ; 4.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 3.663  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 3.479  ; 3.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 3.056  ; 2.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 1.848  ; 1.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 2.994  ; 2.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 2.955  ; 2.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 3.357  ; 3.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 4.925  ; 4.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 3.616  ; 3.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 2.999  ; 2.999  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 2.999  ; 2.999  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 3.065  ; 3.065  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 3.386  ; 3.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 3.165  ; 3.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 3.781  ; 3.781  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 3.388  ; 3.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 3.502  ; 3.502  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 2.866  ; 2.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 2.660  ; 2.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 2.049  ; 2.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 3.114  ; 3.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 2.821  ; 2.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 2.597  ; 2.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 3.354  ; 3.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 2.696  ; 2.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 3.012  ; 3.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 3.151  ; 3.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 2.992  ; 2.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 3.009  ; 3.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 3.194  ; 3.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 3.027  ; 3.027  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 2.789  ; 2.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 3.054  ; 3.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 2.749  ; 2.749  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 2.727  ; 2.727  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 2.897  ; 2.897  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 2.728  ; 2.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 2.881  ; 2.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 3.453  ; 3.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 2.696  ; 2.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 2.929  ; 2.929  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 4.197  ; 4.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 3.072  ; 3.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 3.444  ; 3.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 2.553  ; 2.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 2.574  ; 2.574  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 2.647  ; 2.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 3.231  ; 3.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 2.766  ; 2.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 2.647  ; 2.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 2.828  ; 2.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 2.958  ; 2.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 3.400  ; 3.400  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 3.655  ; 3.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 3.598  ; 3.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 3.508  ; 3.508  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 3.090  ; 3.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 3.615  ; 3.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 3.273  ; 3.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 3.325  ; 3.325  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 3.157  ; 3.157  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 3.170  ; 3.170  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 2.752  ; 2.752  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 2.296  ; 2.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 3.037  ; 3.037  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 3.206  ; 3.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 2.724  ; 2.724  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 3.497  ; 3.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 4.110  ; 4.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 4.762  ; 4.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 4.517  ; 4.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 4.569  ; 4.707  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 4.592  ; 4.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 5.072  ; 5.210  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 5.170  ; 4.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 6.223  ; 5.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 5.806  ; 6.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 3.992  ; 3.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 2.976  ; 2.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 2.899  ; 2.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 2.943  ; 2.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 2.899  ; 2.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 3.552  ; 3.552  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 3.237  ; 3.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 2.710  ; 2.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 3.092  ; 3.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 2.569  ; 2.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 2.569  ; 2.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 2.993  ; 2.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 2.788  ; 2.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.657  ; 3.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 3.705  ; 3.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 3.848  ; 3.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 3.423  ; 3.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 2.686  ; 2.686  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 2.806  ; 2.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 3.602  ; 3.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 4.230  ; 4.230  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.695  ; 3.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 4.964  ; 4.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 4.786  ; 4.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 4.654  ; 4.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 4.689  ; 4.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 4.393  ; 4.393  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 5.197  ; 5.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 4.370  ; 4.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 4.451  ; 4.451  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 4.797  ; 5.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 5.559  ; 5.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 3.695  ; 3.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 4.013  ; 4.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 3.789  ; 3.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 3.758  ; 3.872  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 4.126  ; 4.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 3.758  ; 3.872  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 4.581  ; 4.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 4.855  ; 4.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 4.242  ; 4.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 5.008  ; 5.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 4.715  ; 4.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 4.892  ; 4.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 4.444  ; 4.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 4.640  ; 4.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 5.335  ; 5.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 5.063  ; 5.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 5.237  ; 5.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 5.124  ; 5.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 5.034  ; 5.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 4.335  ; 4.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 4.497  ; 4.707  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 4.454  ; 4.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 4.481  ; 4.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 4.670  ; 4.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 4.242  ; 4.415  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 5.095  ; 5.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 4.681  ; 4.923  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 4.599  ; 4.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 4.933  ; 4.691  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 4.847  ; 5.089  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 4.899  ; 4.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 4.292  ; 4.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 4.038  ; 3.883  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 3.653  ; 4.050  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 4.097  ; 4.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 3.259  ; 3.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 3.739  ; 3.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 3.687  ; 3.474  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 3.151  ; 3.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 3.458  ; 3.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 2.829  ; 2.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 3.341  ; 3.341  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 2.889  ; 2.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 2.808  ; 2.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 2.228  ; 2.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 2.491  ; 2.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 2.414  ; 2.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 2.387  ; 2.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 2.388  ; 2.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 2.336  ; 2.336  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 2.411  ; 2.411  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 2.294  ; 2.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 2.228  ; 2.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 2.743  ; 2.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 2.921  ; 2.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 2.335  ; 2.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 2.620  ; 2.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 3.419  ; 3.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 3.185  ; 3.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 3.237  ; 3.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 3.857  ; 3.857  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 3.643  ; 3.643  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 2.972  ; 2.972  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 3.759  ; 3.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 3.458  ; 3.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 3.645  ; 3.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 3.049  ; 3.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 3.036  ; 3.036  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 2.982  ; 2.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 3.276  ; 3.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 2.452  ; 2.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 3.512  ; 3.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 2.464  ; 2.464  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 2.791  ; 2.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 2.818  ; 2.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 5.342  ; 5.342  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 5.423  ; 5.423  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 2.677  ; 2.966  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 4.795  ; 4.925  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 5.623  ; 5.427  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 5.530  ; 5.532  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 6.144  ; 6.340  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 6.223  ; 6.419  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 5.530  ; 5.726  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 6.386  ; 6.582  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 5.925  ; 5.925  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 5.532  ; 5.532  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 5.646  ; 5.646  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 6.044  ; 6.044  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 5.357  ; 5.357  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 5.845  ; 5.562  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 5.943  ; 5.802  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 5.873  ; 6.046  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 6.649  ; 6.531  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 6.137  ; 6.213  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 5.755  ; 5.857  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 5.720  ; 5.570  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 6.089  ; 6.115  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 6.190  ; 6.288  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 5.884  ; 5.884  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 5.665  ; 5.665  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 5.404  ; 5.404  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 5.829  ; 6.014  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 6.583  ; 6.527  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 5.372  ; 5.372  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 5.357  ; 5.357  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 3.358  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 3.473  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 5.433  ; 5.451  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 5.446  ; 5.464  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 4.574  ; 4.110  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 4.458  ; 4.762  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 4.655  ; 4.517  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 4.707  ; 4.569  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 4.730  ; 4.592  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 5.210  ; 5.072  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 4.902  ; 5.170  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 5.955  ; 6.223  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 6.074  ; 5.806  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 3.903  ; 3.992  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 2.968  ; 3.563  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.695  ; 3.695  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 4.964  ; 4.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 4.786  ; 4.786  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 4.654  ; 4.654  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 4.689  ; 4.689  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 4.393  ; 4.393  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 5.197  ; 5.197  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 4.370  ; 4.370  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 4.451  ; 4.451  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 6.185  ; 4.797  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 5.559  ; 5.559  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 3.695  ; 3.695  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 4.013  ; 4.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 3.789  ; 3.789  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 4.843  ; 3.758  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 5.607  ; 4.126  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 4.843  ; 3.758  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 5.691  ; 4.581  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 4.613  ; 5.723  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 4.415  ; 4.242  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 5.008  ; 5.008  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 4.715  ; 4.715  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 4.952  ; 4.952  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 4.444  ; 4.444  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 4.640  ; 4.640  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 5.335  ; 5.335  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 5.063  ; 5.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 5.237  ; 5.237  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 5.334  ; 5.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 5.307  ; 5.127  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 4.819  ; 4.609  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 4.707  ; 4.497  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 4.627  ; 4.454  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 4.654  ; 4.481  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 4.843  ; 4.670  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 4.415  ; 4.242  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 6.205  ; 5.095  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 5.791  ; 4.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 4.357  ; 5.467  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 4.691  ; 5.801  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 5.957  ; 4.847  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 4.657  ; 5.767  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 3.883  ; 4.038  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 4.356  ; 3.653  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 4.079  ; 4.097  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 3.572  ; 3.259  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 3.668  ; 3.739  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 3.474  ; 3.687  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 3.267  ; 3.151  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 3.369  ; 3.714  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 3.525  ; 3.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 3.608  ; 3.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 2.666  ; 2.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 4.055  ; 4.055  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 4.135  ; 4.135  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 4.010  ; 4.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 3.925  ; 3.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 3.761  ; 3.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 4.207  ; 4.207  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 3.821  ; 3.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 3.940  ; 3.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 4.014  ; 4.014  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 3.767  ; 3.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 3.832  ; 3.832  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 2.666  ; 2.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 3.198  ; 3.198  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 3.320  ; 3.320  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 3.383  ; 3.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 3.309  ; 3.309  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 3.266  ; 3.266  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 3.257  ; 3.257  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 3.278  ; 3.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 4.069  ; 4.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 3.663  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 3.479  ; 3.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.056  ; 2.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 1.848  ; 1.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 2.994  ; 2.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 2.955  ; 2.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 3.357  ; 3.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.925  ; 4.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 3.616  ; 3.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 2.999  ; 2.999  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 2.999  ; 2.999  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 3.065  ; 3.065  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 3.386  ; 3.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 3.165  ; 3.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 3.781  ; 3.781  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 3.388  ; 3.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 3.502  ; 3.502  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 2.866  ; 2.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 2.660  ; 2.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 2.049  ; 2.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 3.114  ; 3.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 2.821  ; 2.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 2.597  ; 2.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 3.354  ; 3.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 2.696  ; 2.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 3.012  ; 3.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 3.151  ; 3.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 2.992  ; 2.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 3.009  ; 3.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 3.194  ; 3.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 3.027  ; 3.027  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 2.789  ; 2.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 3.054  ; 3.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 2.749  ; 2.749  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 2.727  ; 2.727  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 2.897  ; 2.897  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 2.728  ; 2.728  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 2.881  ; 2.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 3.453  ; 3.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 2.696  ; 2.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 2.929  ; 2.929  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 4.197  ; 4.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 3.072  ; 3.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 3.444  ; 3.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 2.553  ; 2.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 2.574  ; 2.574  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 2.647  ; 2.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 3.231  ; 3.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 2.766  ; 2.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 2.647  ; 2.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 2.828  ; 2.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 2.958  ; 2.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 3.400  ; 3.400  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 3.655  ; 3.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 3.598  ; 3.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 3.508  ; 3.508  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 3.090  ; 3.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 3.615  ; 3.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 3.273  ; 3.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 3.325  ; 3.325  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 3.157  ; 3.157  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 3.170  ; 3.170  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 2.752  ; 2.752  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 2.296  ; 2.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 3.037  ; 3.037  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 3.206  ; 3.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 2.724  ; 2.724  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.497  ; 3.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 4.110  ; 4.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 4.762  ; 4.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 4.517  ; 4.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 4.569  ; 4.707  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 4.592  ; 4.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 5.072  ; 5.210  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 5.170  ; 4.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 6.223  ; 5.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 5.806  ; 6.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 3.992  ; 3.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 2.976  ; 2.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 2.899  ; 2.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 2.943  ; 2.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 2.899  ; 2.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 3.552  ; 3.552  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 3.237  ; 3.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 2.710  ; 2.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 3.092  ; 3.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 2.569  ; 2.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 2.569  ; 2.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 2.993  ; 2.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 2.788  ; 2.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.657  ; 3.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 3.705  ; 3.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 3.848  ; 3.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 3.423  ; 3.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 2.686  ; 2.686  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 2.806  ; 2.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 3.602  ; 3.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 4.230  ; 4.230  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.695  ; 3.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 4.964  ; 4.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 4.786  ; 4.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 4.654  ; 4.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 4.689  ; 4.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 4.393  ; 4.393  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 5.197  ; 5.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 4.370  ; 4.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 4.451  ; 4.451  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 4.797  ; 5.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 5.559  ; 5.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 3.695  ; 3.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 4.013  ; 4.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 3.789  ; 3.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 3.758  ; 3.872  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 4.126  ; 4.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 3.758  ; 3.872  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 4.581  ; 4.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 4.855  ; 4.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.242  ; 4.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 5.008  ; 5.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 4.715  ; 4.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 4.892  ; 4.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 4.444  ; 4.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 4.640  ; 4.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 5.335  ; 5.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 5.063  ; 5.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 5.237  ; 5.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 5.124  ; 5.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 5.034  ; 5.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 4.335  ; 4.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 4.497  ; 4.707  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 4.454  ; 4.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 4.481  ; 4.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.670  ; 4.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.242  ; 4.415  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 5.095  ; 5.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 4.681  ; 4.923  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 4.599  ; 4.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 4.933  ; 4.691  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 4.847  ; 5.089  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 4.899  ; 4.657  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 4.292  ; 4.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 4.038  ; 3.883  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 3.653  ; 4.050  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 4.097  ; 4.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 3.259  ; 3.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 3.739  ; 3.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 3.687  ; 3.474  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 3.151  ; 3.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.458  ; 3.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 2.829  ; 2.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 3.341  ; 3.341  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 2.889  ; 2.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 2.808  ; 2.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 2.228  ; 2.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 2.491  ; 2.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 2.414  ; 2.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 2.387  ; 2.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 2.388  ; 2.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 2.336  ; 2.336  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 2.411  ; 2.411  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 2.294  ; 2.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 2.228  ; 2.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 2.743  ; 2.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 2.921  ; 2.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 2.335  ; 2.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 2.620  ; 2.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 3.419  ; 3.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 3.185  ; 3.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 3.237  ; 3.237  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 3.857  ; 3.857  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 3.643  ; 3.643  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 2.972  ; 2.972  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 3.759  ; 3.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 3.458  ; 3.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 3.645  ; 3.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 3.049  ; 3.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 3.036  ; 3.036  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 2.982  ; 2.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 3.276  ; 3.276  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 2.452  ; 2.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.512  ; 3.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 2.464  ; 2.464  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 2.791  ; 2.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 2.818  ; 2.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 5.342  ; 5.342  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 5.423  ; 5.423  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 2.677  ; 2.966  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.795  ; 4.925  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 5.623  ; 5.427  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 5.530  ; 5.532  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 6.144  ; 6.340  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 6.223  ; 6.419  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 5.530  ; 5.726  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 6.386  ; 6.582  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 5.925  ; 5.925  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 5.532  ; 5.532  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 5.646  ; 5.646  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 6.044  ; 6.044  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 5.357  ; 5.357  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 5.845  ; 5.562  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 5.943  ; 5.802  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 5.873  ; 6.046  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 6.649  ; 6.531  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 6.137  ; 6.213  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 5.755  ; 5.857  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 5.720  ; 5.570  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.089  ; 6.115  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.190  ; 6.288  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 5.884  ; 5.884  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.665  ; 5.665  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 5.404  ; 5.404  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.829  ; 6.014  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.583  ; 6.527  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.372  ; 5.372  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.357  ; 5.357  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 3.358  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 3.473  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 5.433  ; 5.451  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 5.446  ; 5.464  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 4.574  ; 4.110  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 4.458  ; 4.762  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 4.655  ; 4.517  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 4.707  ; 4.569  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 4.730  ; 4.592  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 5.210  ; 5.072  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 4.902  ; 5.170  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 5.955  ; 6.223  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 6.074  ; 5.806  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 3.903  ; 3.992  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 2.968  ; 3.563  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.695  ; 3.695  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 4.964  ; 4.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 4.786  ; 4.786  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 4.654  ; 4.654  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 4.689  ; 4.689  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 4.393  ; 4.393  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 5.197  ; 5.197  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 4.370  ; 4.370  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 4.451  ; 4.451  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 6.185  ; 4.797  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 5.559  ; 5.559  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 3.695  ; 3.695  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 4.013  ; 4.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 3.789  ; 3.789  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 4.843  ; 3.758  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 5.607  ; 4.126  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 4.843  ; 3.758  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 5.691  ; 4.581  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 4.613  ; 5.723  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.415  ; 4.242  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 5.008  ; 5.008  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 4.715  ; 4.715  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 4.952  ; 4.952  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 4.444  ; 4.444  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 4.640  ; 4.640  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 5.335  ; 5.335  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 5.063  ; 5.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 5.237  ; 5.237  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 5.334  ; 5.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 5.307  ; 5.127  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 4.819  ; 4.609  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 4.707  ; 4.497  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 4.627  ; 4.454  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 4.654  ; 4.481  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.843  ; 4.670  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.415  ; 4.242  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 6.205  ; 5.095  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 5.791  ; 4.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 4.357  ; 5.467  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 4.691  ; 5.801  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 5.957  ; 4.847  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 4.657  ; 5.767  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 3.883  ; 4.038  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 4.356  ; 3.653  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 4.079  ; 4.097  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 3.572  ; 3.259  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 3.668  ; 3.739  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 3.474  ; 3.687  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 3.267  ; 3.151  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.369  ; 3.714  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 5.449  ; 5.449  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 5.530  ; 5.530  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 3.173  ; 3.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 2.793  ; 2.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 2.851  ; 2.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 5.534  ; 5.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 4.009  ; 4.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 5.231  ; 5.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 4.247  ; 4.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 6.032  ; 6.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 5.639  ; 5.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 5.753  ; 5.753  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 5.397  ; 5.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 2.916  ; 2.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 3.683  ; 3.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 3.071  ; 3.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 3.178  ; 3.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 2.916  ; 2.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 3.660  ; 3.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 3.046  ; 3.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 2.981  ; 2.981  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 3.158  ; 3.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 2.721  ; 2.721  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 3.274  ; 3.274  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 3.005  ; 3.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 2.721  ; 2.721  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 2.745  ; 2.745  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 4.062  ; 4.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 4.544  ; 4.544  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 4.833  ; 4.833  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 4.618  ; 4.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 5.969  ; 5.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 4.855  ; 4.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 4.783  ; 4.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 4.062  ; 4.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 4.378  ; 4.378  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 6.812  ; 6.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 6.300  ; 6.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 5.713  ; 5.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 6.040  ; 6.040  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 5.771  ; 5.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 6.235  ; 6.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 5.637  ; 5.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 6.000  ; 6.000  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 3.361  ; 3.361  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 3.213  ; 3.213  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 2.807  ; 2.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 2.847  ; 2.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 3.106  ; 3.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.053  ; 3.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 3.461  ; 3.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 3.491  ; 3.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 3.316  ; 3.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 3.471  ; 3.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 3.610  ; 3.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 3.663  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 3.281  ; 3.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 3.286  ; 3.286  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 3.570  ; 3.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 3.708  ; 3.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 3.053  ; 3.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 3.450  ; 3.450  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 3.201  ; 3.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 3.049  ; 3.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 3.267  ; 3.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 3.049  ; 3.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 3.742  ; 3.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 3.767  ; 3.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 2.957  ; 2.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 4.187  ; 4.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 3.779  ; 3.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 3.534  ; 3.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 3.648  ; 3.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 3.948  ; 3.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 3.676  ; 3.676  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 3.855  ; 3.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 3.947  ; 3.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 3.612  ; 3.612  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 3.365  ; 3.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 3.400  ; 3.400  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 3.539  ; 3.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 3.439  ; 3.439  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 3.577  ; 3.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 2.957  ; 2.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 4.269  ; 4.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 3.860  ; 3.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 3.531  ; 3.531  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 3.844  ; 3.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 3.673  ; 3.673  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 3.322  ; 3.322  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 3.582  ; 3.582  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 3.798  ; 3.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 3.436  ; 3.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 3.505  ; 3.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 4.124  ; 4.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 3.655  ; 3.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 3.762  ; 3.762  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 4.557  ; 4.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 1.262  ; 2.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 3.033  ; 3.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 3.177  ; 3.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 2.930  ; 2.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 3.013  ; 3.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 3.069  ; 3.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 5.449  ; 5.449  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 5.530  ; 5.530  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.173  ; 3.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 2.793  ; 2.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 2.851  ; 2.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 5.534  ; 5.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 4.009  ; 4.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 5.231  ; 5.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 4.247  ; 4.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 6.032  ; 6.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 5.639  ; 5.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 5.753  ; 5.753  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 5.397  ; 5.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 2.916  ; 2.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 3.683  ; 3.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 3.071  ; 3.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 3.178  ; 3.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 2.916  ; 2.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 3.660  ; 3.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 3.046  ; 3.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 2.981  ; 2.981  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 3.158  ; 3.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 2.721  ; 2.721  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 3.274  ; 3.274  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 3.005  ; 3.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 2.721  ; 2.721  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 2.745  ; 2.745  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 4.062  ; 4.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 4.544  ; 4.544  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 4.833  ; 4.833  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 4.618  ; 4.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 5.969  ; 5.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 4.855  ; 4.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 4.783  ; 4.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 4.062  ; 4.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 4.378  ; 4.378  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.812  ; 6.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 6.300  ; 6.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.713  ; 5.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.040  ; 6.040  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.771  ; 5.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.235  ; 6.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.637  ; 5.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 6.000  ; 6.000  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 3.361  ; 3.361  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.213  ; 3.213  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 2.807  ; 2.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 2.847  ; 2.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 3.106  ; 3.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.053  ; 3.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 3.461  ; 3.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 3.491  ; 3.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 3.316  ; 3.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 3.471  ; 3.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 3.610  ; 3.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 3.663  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 3.281  ; 3.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 3.286  ; 3.286  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 3.570  ; 3.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 3.708  ; 3.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 3.053  ; 3.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 3.450  ; 3.450  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 3.201  ; 3.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 3.049  ; 3.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 3.267  ; 3.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 3.049  ; 3.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 3.742  ; 3.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 3.767  ; 3.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 2.957  ; 2.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 4.187  ; 4.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 3.779  ; 3.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 3.534  ; 3.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 3.648  ; 3.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 3.948  ; 3.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 3.676  ; 3.676  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 3.855  ; 3.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 3.947  ; 3.947  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 3.612  ; 3.612  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 3.365  ; 3.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 3.400  ; 3.400  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 3.539  ; 3.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 3.439  ; 3.439  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 3.577  ; 3.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 2.957  ; 2.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 4.269  ; 4.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 3.860  ; 3.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 3.531  ; 3.531  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 3.844  ; 3.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 3.673  ; 3.673  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 3.322  ; 3.322  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 3.582  ; 3.582  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.798  ; 3.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 3.436  ; 3.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 3.505  ; 3.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 4.124  ; 4.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 3.655  ; 3.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 3.762  ; 3.762  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 4.557  ; 4.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 1.262  ; 2.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 3.033  ; 3.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 3.177  ; 3.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 2.930  ; 2.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 3.013  ; 3.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 3.069  ; 3.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 5.383  ; 5.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 6.452  ; 6.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 6.618  ; 6.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 6.389  ; 6.389  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 7.273  ; 7.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 6.398  ; 6.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 6.614  ; 6.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 6.008  ; 6.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 6.191  ; 6.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 6.376  ; 6.376  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 6.373  ; 6.373  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 5.912  ; 5.912  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 6.158  ; 6.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 5.851  ; 5.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 6.462  ; 6.462  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 5.383  ; 5.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 5.746  ; 5.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 3.021  ; 3.021  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.105  ; 3.105  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 3.021  ; 3.021  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 3.264  ; 3.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 3.246  ; 3.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 5.979  ; 5.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 7.204  ; 7.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 6.884  ; 6.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 6.595  ; 6.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 7.264  ; 7.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 6.203  ; 6.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 7.713  ; 7.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 7.070  ; 7.070  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 7.253  ; 7.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 7.254  ; 7.254  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 6.536  ; 6.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 6.111  ; 6.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 6.647  ; 6.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 6.370  ; 6.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 6.655  ; 6.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 6.362  ; 6.362  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 5.979  ; 5.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 5.383  ; 5.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 6.452  ; 6.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 6.618  ; 6.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 6.389  ; 6.389  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 7.273  ; 7.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 6.398  ; 6.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.614  ; 6.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.008  ; 6.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.191  ; 6.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.376  ; 6.376  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 6.373  ; 6.373  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.912  ; 5.912  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.158  ; 6.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.851  ; 5.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.462  ; 6.462  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.383  ; 5.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.746  ; 5.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 3.021  ; 3.021  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.105  ; 3.105  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 3.021  ; 3.021  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 3.264  ; 3.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 3.246  ; 3.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 5.979  ; 5.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 7.204  ; 7.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 6.884  ; 6.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 6.595  ; 6.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 7.264  ; 7.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 6.203  ; 6.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 7.713  ; 7.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 7.070  ; 7.070  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 7.253  ; 7.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 7.254  ; 7.254  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 6.536  ; 6.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 6.111  ; 6.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 6.647  ; 6.647  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 6.370  ; 6.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 6.655  ; 6.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 6.362  ; 6.362  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 5.979  ; 5.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.141  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.141  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------+
; Progagation Delay                                                ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 18.172 ; 18.172 ; 18.172 ; 18.172 ;
; ASn          ; ACSI_WRn      ; 18.449 ; 18.449 ; 18.449 ; 18.449 ;
; ASn          ; BUTTONn       ; 21.015 ;        ;        ; 21.015 ;
; ASn          ; CA1_OUT       ; 17.459 ;        ;        ; 17.459 ;
; ASn          ; CD[0]         ; 28.356 ; 28.356 ; 28.356 ; 28.356 ;
; ASn          ; CD[1]         ; 27.986 ; 27.986 ; 27.986 ; 27.986 ;
; ASn          ; CD[2]         ; 24.648 ; 24.648 ; 24.648 ; 24.648 ;
; ASn          ; CD[3]         ; 28.715 ; 28.715 ; 28.715 ; 28.715 ;
; ASn          ; CD[4]         ; 28.838 ; 28.838 ; 28.838 ; 28.838 ;
; ASn          ; CD[5]         ; 27.778 ; 27.778 ; 27.778 ; 27.778 ;
; ASn          ; CD[6]         ; 28.661 ; 28.661 ; 28.661 ; 28.661 ;
; ASn          ; CD[7]         ; 25.345 ; 25.345 ; 25.345 ; 25.345 ;
; ASn          ; DATA[0]       ; 30.522 ; 30.236 ; 30.236 ; 30.522 ;
; ASn          ; DATA[1]       ; 31.555 ; 31.049 ; 31.049 ; 31.555 ;
; ASn          ; DATA[2]       ; 31.130 ; 30.303 ; 30.303 ; 31.130 ;
; ASn          ; DATA[3]       ; 32.242 ; 31.313 ; 31.313 ; 32.242 ;
; ASn          ; DATA[4]       ; 31.638 ; 31.538 ; 31.538 ; 31.638 ;
; ASn          ; DATA[5]       ; 31.103 ; 32.076 ; 32.076 ; 31.103 ;
; ASn          ; DATA[6]       ; 30.216 ; 29.559 ; 29.559 ; 30.216 ;
; ASn          ; DATA[7]       ; 30.728 ; 29.794 ; 29.794 ; 30.728 ;
; ASn          ; DATA[8]       ; 30.595 ; 30.733 ; 30.733 ; 30.595 ;
; ASn          ; DATA[9]       ; 29.648 ; 30.039 ; 30.039 ; 29.648 ;
; ASn          ; DATA[10]      ; 28.439 ; 27.911 ; 27.911 ; 28.439 ;
; ASn          ; DATA[11]      ; 29.671 ; 29.671 ; 29.671 ; 29.671 ;
; ASn          ; DATA[12]      ; 29.007 ; 28.359 ; 28.359 ; 29.007 ;
; ASn          ; DATA[13]      ; 29.979 ; 29.979 ; 29.979 ; 29.979 ;
; ASn          ; DATA[14]      ; 30.003 ; 30.003 ; 30.003 ; 30.003 ;
; ASn          ; DATA[15]      ; 30.569 ; 30.569 ; 30.569 ; 30.569 ;
; ASn          ; DTACKn        ; 21.786 ; 21.786 ; 21.786 ; 21.786 ;
; ASn          ; FLASH_CEn     ; 18.663 ;        ;        ; 18.663 ;
; ASn          ; FLASH_OEn     ; 18.593 ;        ;        ; 18.593 ;
; ASn          ; IDE_CS0n      ; 13.444 ;        ;        ; 13.444 ;
; ASn          ; IDE_CS1n      ; 14.385 ;        ;        ; 14.385 ;
; ASn          ; IDE_D_EN_INn  ; 13.942 ;        ;        ; 13.942 ;
; ASn          ; IDE_D_EN_OUTn ; 13.756 ;        ;        ; 13.756 ;
; ASn          ; IDE_IORDn     ; 13.562 ;        ;        ; 13.562 ;
; ASn          ; IDE_IOWRn     ; 14.978 ;        ;        ; 14.978 ;
; ASn          ; JOY_RHn       ; 16.667 ;        ;        ; 16.667 ;
; ASn          ; JOY_RLn       ; 19.258 ;        ;        ; 19.258 ;
; ASn          ; JOY_WEn       ;        ; 18.892 ; 18.892 ;        ;
; ASn          ; JOY_WL        ;        ; 13.471 ; 13.471 ;        ;
; ASn          ; RAM_ADR[8]    ;        ; 18.145 ; 18.145 ;        ;
; ASn          ; RAM_BA[0]     ;        ; 16.502 ; 16.502 ;        ;
; ASn          ; RAM_BA[1]     ;        ; 14.480 ; 14.480 ;        ;
; ASn          ; RAM_CAS0n     ;        ; 16.664 ; 16.664 ;        ;
; ASn          ; RAM_CAS1n     ; 16.660 ;        ;        ; 16.660 ;
; ASn          ; RAM_DATA[0]   ; 32.170 ; 31.884 ; 31.884 ; 32.170 ;
; ASn          ; RAM_DATA[1]   ; 32.087 ; 31.581 ; 31.581 ; 32.087 ;
; ASn          ; RAM_DATA[2]   ; 31.418 ; 30.591 ; 30.591 ; 31.418 ;
; ASn          ; RAM_DATA[3]   ; 32.193 ; 31.264 ; 31.264 ; 32.193 ;
; ASn          ; RAM_DATA[4]   ; 30.840 ; 30.740 ; 30.740 ; 30.840 ;
; ASn          ; RAM_DATA[5]   ; 33.614 ; 34.587 ; 34.587 ; 33.614 ;
; ASn          ; RAM_DATA[6]   ; 32.702 ; 32.045 ; 32.045 ; 32.702 ;
; ASn          ; RAM_DATA[7]   ; 33.149 ; 32.215 ; 32.215 ; 33.149 ;
; ASn          ; RAM_DATA[8]   ; 32.452 ; 32.590 ; 32.590 ; 32.452 ;
; ASn          ; RAM_DATA[9]   ; 29.800 ; 30.191 ; 30.191 ; 29.800 ;
; ASn          ; RAM_DATA[10]  ; 28.707 ; 28.179 ; 28.179 ; 28.707 ;
; ASn          ; RAM_DATA[11]  ; 30.832 ; 30.832 ; 30.832 ; 30.832 ;
; ASn          ; RAM_DATA[12]  ; 30.133 ; 29.485 ; 29.485 ; 30.133 ;
; ASn          ; RAM_DATA[13]  ; 30.215 ; 30.215 ; 30.215 ; 30.215 ;
; ASn          ; RAM_DATA[14]  ; 32.369 ; 32.369 ; 32.369 ; 32.369 ;
; ASn          ; RAM_DATA[15]  ; 30.891 ; 30.891 ; 30.891 ; 30.891 ;
; ASn          ; RAM_DQM0H     ;        ; 17.850 ; 17.850 ;        ;
; ASn          ; RAM_DQM0L     ;        ; 17.046 ; 17.046 ;        ;
; ASn          ; RAM_DQM1H     ; 16.098 ;        ;        ; 16.098 ;
; ASn          ; RAM_DQM1L     ; 16.999 ;        ;        ; 16.999 ;
; ASn          ; RAM_RAS0n     ;        ; 17.565 ; 17.565 ;        ;
; ASn          ; RAM_RAS1n     ; 16.924 ;        ;        ; 16.924 ;
; ASn          ; ROM0n         ; 17.610 ;        ;        ; 17.610 ;
; ASn          ; ROM1n         ; 17.229 ;        ;        ; 17.229 ;
; ASn          ; ROM2n         ; 15.327 ;        ;        ; 15.327 ;
; ASn          ; ROM3n         ; 17.515 ;        ;        ; 17.515 ;
; ASn          ; ROM4n         ; 18.810 ;        ;        ; 18.810 ;
; ASn          ; ROM5n         ; 14.300 ;        ;        ; 14.300 ;
; ASn          ; ROM6n         ; 17.723 ;        ;        ; 17.723 ;
; COM_CTS      ; DATA[2]       ;        ; 22.061 ; 22.061 ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 22.349 ; 22.349 ;        ;
; COM_DCD      ; DATA[1]       ;        ; 22.235 ; 22.235 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 22.767 ; 22.767 ;        ;
; COM_RI       ; DATA[6]       ;        ; 21.072 ; 21.072 ;        ;
; COM_RI       ; RAM_DATA[6]   ;        ; 23.558 ; 23.558 ;        ;
; CONFIG[1]    ; DATA[7]       ; 24.247 ; 24.247 ; 24.247 ; 24.247 ;
; CONFIG[1]    ; HSYNC         ; 14.469 ; 14.469 ; 14.469 ; 14.469 ;
; CONFIG[1]    ; RAM_DATA[7]   ; 26.668 ; 26.668 ; 26.668 ; 26.668 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 16.363 ; 16.363 ; 16.363 ; 16.363 ;
; CONFIG[1]    ; RAM_DATA[13]  ; 16.801 ; 16.801 ; 16.801 ; 16.801 ;
; CONFIG[1]    ; RAM_DATA[14]  ; 16.938 ; 16.938 ; 16.938 ; 16.938 ;
; CONFIG[1]    ; RAM_DATA[15]  ; 15.429 ; 15.429 ; 15.429 ; 15.429 ;
; CONFIG[1]    ; VSYNC         ; 14.171 ; 14.171 ; 14.171 ; 14.171 ;
; CONFIG[2]    ; DATA[7]       ; 22.962 ; 22.962 ; 22.962 ; 22.962 ;
; CONFIG[2]    ; HSYNC         ; 14.304 ; 14.304 ; 14.304 ; 14.304 ;
; CONFIG[2]    ; RAM_DATA[7]   ; 25.383 ; 25.383 ; 25.383 ; 25.383 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 16.565 ; 16.565 ; 16.565 ; 16.565 ;
; CONFIG[2]    ; RAM_DATA[13]  ; 17.003 ; 17.003 ; 17.003 ; 17.003 ;
; CONFIG[2]    ; RAM_DATA[14]  ; 17.140 ; 17.140 ; 17.140 ; 17.140 ;
; CONFIG[2]    ; RAM_DATA[15]  ; 15.631 ; 15.631 ; 15.631 ; 15.631 ;
; CONFIG[2]    ; VSYNC         ; 14.001 ; 14.001 ; 14.001 ; 14.001 ;
; CONFIG[3]    ; LDSn          ; 23.789 ; 24.013 ; 24.013 ; 23.789 ;
; CONFIG[3]    ; UDSn          ; 24.187 ; 24.411 ; 24.411 ; 24.187 ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 16.269 ; 16.269 ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 14.226 ; 14.226 ;        ;
; CONFIG[5]    ; ACSI_RDn      ; 26.021 ; 26.021 ; 26.021 ; 26.021 ;
; CONFIG[5]    ; ACSI_WRn      ; 26.298 ; 26.298 ; 26.298 ; 26.298 ;
; CONFIG[5]    ; BUTTONn       ; 23.596 ; 21.361 ; 21.361 ; 23.596 ;
; CONFIG[5]    ; CA1_OUT       ; 25.308 ; 23.073 ; 23.073 ; 25.308 ;
; CONFIG[5]    ; CD[0]         ; 36.205 ; 36.205 ; 36.205 ; 36.205 ;
; CONFIG[5]    ; CD[1]         ; 35.835 ; 35.835 ; 35.835 ; 35.835 ;
; CONFIG[5]    ; CD[2]         ; 32.497 ; 32.497 ; 32.497 ; 32.497 ;
; CONFIG[5]    ; CD[3]         ; 36.564 ; 36.564 ; 36.564 ; 36.564 ;
; CONFIG[5]    ; CD[4]         ; 36.687 ; 36.687 ; 36.687 ; 36.687 ;
; CONFIG[5]    ; CD[5]         ; 35.627 ; 35.627 ; 35.627 ; 35.627 ;
; CONFIG[5]    ; CD[6]         ; 36.510 ; 36.510 ; 36.510 ; 36.510 ;
; CONFIG[5]    ; CD[7]         ; 33.194 ; 33.194 ; 33.194 ; 33.194 ;
; CONFIG[5]    ; DATA[0]       ; 33.957 ; 33.957 ; 33.957 ; 33.957 ;
; CONFIG[5]    ; DATA[1]       ; 34.330 ; 34.233 ; 34.233 ; 34.330 ;
; CONFIG[5]    ; DATA[2]       ; 33.653 ; 34.002 ; 34.002 ; 33.653 ;
; CONFIG[5]    ; DATA[3]       ; 35.474 ; 35.299 ; 35.299 ; 35.474 ;
; CONFIG[5]    ; DATA[4]       ; 34.948 ; 34.779 ; 34.779 ; 34.948 ;
; CONFIG[5]    ; DATA[5]       ; 35.521 ; 35.342 ; 35.342 ; 35.521 ;
; CONFIG[5]    ; DATA[6]       ; 33.538 ; 33.417 ; 33.417 ; 33.538 ;
; CONFIG[5]    ; DATA[7]       ; 34.406 ; 33.761 ; 33.761 ; 34.406 ;
; CONFIG[5]    ; DATA[8]       ; 35.411 ; 35.549 ; 35.549 ; 35.411 ;
; CONFIG[5]    ; DATA[9]       ; 33.794 ; 34.217 ; 34.217 ; 33.794 ;
; CONFIG[5]    ; DATA[10]      ; 32.592 ; 32.206 ; 32.206 ; 32.592 ;
; CONFIG[5]    ; DATA[11]      ; 33.112 ; 33.112 ; 33.112 ; 33.112 ;
; CONFIG[5]    ; DATA[12]      ; 32.963 ; 32.495 ; 32.495 ; 32.963 ;
; CONFIG[5]    ; DATA[13]      ; 33.884 ; 33.723 ; 33.723 ; 33.884 ;
; CONFIG[5]    ; DATA[14]      ; 33.912 ; 33.912 ; 33.912 ; 33.912 ;
; CONFIG[5]    ; DATA[15]      ; 34.150 ; 34.150 ; 34.150 ; 34.150 ;
; CONFIG[5]    ; DTACKn        ; 27.961 ; 27.961 ; 27.961 ; 27.961 ;
; CONFIG[5]    ; FLASH_CEn     ; 25.857 ; 25.712 ; 25.712 ; 25.857 ;
; CONFIG[5]    ; FLASH_OEn     ; 25.787 ; 25.642 ; 25.642 ; 25.787 ;
; CONFIG[5]    ; IDE_CS0n      ; 21.368 ; 19.133 ; 19.133 ; 21.368 ;
; CONFIG[5]    ; IDE_CS1n      ; 22.309 ; 20.074 ; 20.074 ; 22.309 ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 21.334 ; 19.099 ; 19.099 ; 21.334 ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 21.680 ; 19.445 ; 19.445 ; 21.680 ;
; CONFIG[5]    ; IDE_IORDn     ; 21.741 ; 19.506 ; 19.506 ; 21.741 ;
; CONFIG[5]    ; IDE_IOWRn     ; 23.145 ; 20.910 ; 20.910 ; 23.145 ;
; CONFIG[5]    ; JOY_RHn       ; 23.435 ; 21.200 ; 21.200 ; 23.435 ;
; CONFIG[5]    ; JOY_RLn       ; 26.026 ; 23.791 ; 23.791 ; 26.026 ;
; CONFIG[5]    ; JOY_WEn       ; 23.425 ; 25.660 ; 25.660 ; 23.425 ;
; CONFIG[5]    ; JOY_WL        ; 20.100 ; 22.335 ; 22.335 ; 20.100 ;
; CONFIG[5]    ; RAM_ADR[8]    ; 25.841 ; 24.211 ; 24.211 ; 25.841 ;
; CONFIG[5]    ; RAM_BA[0]     ; 24.198 ; 22.568 ; 22.568 ; 24.198 ;
; CONFIG[5]    ; RAM_BA[1]     ; 22.176 ; 20.546 ; 20.546 ; 22.176 ;
; CONFIG[5]    ; RAM_CAS0n     ; 24.360 ; 22.730 ; 22.730 ; 24.360 ;
; CONFIG[5]    ; RAM_CAS1n     ; 22.726 ; 24.356 ; 24.356 ; 22.726 ;
; CONFIG[5]    ; RAM_DATA[0]   ; 35.605 ; 35.605 ; 35.605 ; 35.605 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 34.862 ; 34.765 ; 34.765 ; 34.862 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 33.941 ; 34.290 ; 34.290 ; 33.941 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 35.425 ; 35.250 ; 35.250 ; 35.425 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 34.150 ; 33.981 ; 33.981 ; 34.150 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 38.032 ; 37.853 ; 37.853 ; 38.032 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 36.024 ; 35.903 ; 35.903 ; 36.024 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 36.827 ; 36.182 ; 36.182 ; 36.827 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 37.268 ; 37.406 ; 37.406 ; 37.268 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 33.946 ; 34.369 ; 34.369 ; 33.946 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 32.860 ; 32.474 ; 32.474 ; 32.860 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 34.273 ; 34.273 ; 34.273 ; 34.273 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 34.089 ; 33.621 ; 33.621 ; 34.089 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 34.120 ; 33.959 ; 33.959 ; 34.120 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 36.278 ; 36.278 ; 36.278 ; 36.278 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 34.472 ; 34.472 ; 34.472 ; 34.472 ;
; CONFIG[5]    ; RAM_DQM0H     ; 25.546 ; 23.916 ; 23.916 ; 25.546 ;
; CONFIG[5]    ; RAM_DQM0L     ; 24.742 ; 23.112 ; 23.112 ; 24.742 ;
; CONFIG[5]    ; RAM_DQM1H     ; 22.164 ; 23.794 ; 23.794 ; 22.164 ;
; CONFIG[5]    ; RAM_DQM1L     ; 23.065 ; 24.695 ; 24.695 ; 23.065 ;
; CONFIG[5]    ; RAM_RAS0n     ; 25.261 ; 23.631 ; 23.631 ; 25.261 ;
; CONFIG[5]    ; RAM_RAS1n     ; 22.990 ; 24.620 ; 24.620 ; 22.990 ;
; CONFIG[5]    ; ROM0n         ; 21.025 ; 19.594 ; 19.594 ; 21.025 ;
; CONFIG[5]    ; ROM1n         ; 21.242 ; 19.213 ; 19.213 ; 21.242 ;
; CONFIG[5]    ; ROM2n         ; 22.521 ; 22.376 ; 22.376 ; 22.521 ;
; CONFIG[5]    ; ROM3n         ; 22.100 ; 19.865 ; 19.865 ; 22.100 ;
; CONFIG[5]    ; ROM4n         ; 23.076 ; 22.457 ; 22.457 ; 23.076 ;
; CONFIG[5]    ; ROM5n         ; 21.962 ; 20.776 ; 20.776 ; 21.962 ;
; CONFIG[5]    ; ROM6n         ; 21.993 ; 19.758 ; 19.758 ; 21.993 ;
; CONFIG[6]    ; DATA[0]       ; 24.513 ; 24.513 ; 24.513 ; 24.513 ;
; CONFIG[6]    ; DATA[1]       ; 23.547 ; 23.547 ; 23.547 ; 23.547 ;
; CONFIG[6]    ; DATA[2]       ; 24.567 ; 24.567 ; 24.567 ; 24.567 ;
; CONFIG[6]    ; DATA[3]       ; 24.087 ; 24.087 ; 24.087 ; 24.087 ;
; CONFIG[6]    ; DATA[4]       ; 24.297 ; 24.297 ; 24.297 ; 24.297 ;
; CONFIG[6]    ; DATA[5]       ; 25.485 ; 25.485 ; 25.485 ; 25.485 ;
; CONFIG[6]    ; DATA[6]       ; 23.780 ; 23.780 ; 23.780 ; 23.780 ;
; CONFIG[6]    ; DATA[7]       ; 22.437 ; 22.437 ; 22.437 ; 22.437 ;
; CONFIG[6]    ; DATA[8]       ; 24.693 ; 24.693 ; 24.693 ; 24.693 ;
; CONFIG[6]    ; DATA[9]       ; 24.521 ; 24.521 ; 24.521 ; 24.521 ;
; CONFIG[6]    ; DATA[10]      ; 23.556 ; 23.556 ; 23.556 ; 23.556 ;
; CONFIG[6]    ; DATA[11]      ; 24.102 ; 24.102 ; 24.102 ; 24.102 ;
; CONFIG[6]    ; DATA[12]      ; 22.932 ; 22.932 ; 22.932 ; 22.932 ;
; CONFIG[6]    ; DATA[13]      ; 23.958 ; 23.958 ; 23.958 ; 23.958 ;
; CONFIG[6]    ; DATA[14]      ; 21.231 ; 21.231 ; 21.231 ; 21.231 ;
; CONFIG[6]    ; DATA[15]      ; 22.214 ; 22.214 ; 22.214 ; 22.214 ;
; CONFIG[6]    ; DTACKn        ; 18.868 ; 18.868 ; 18.868 ; 18.868 ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 15.059 ; 15.059 ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 14.809 ; 14.809 ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 18.045 ; 18.045 ; 18.045 ; 18.045 ;
; CONFIG[6]    ; FLASH_OEn     ; 17.975 ; 17.975 ; 17.975 ; 17.975 ;
; CONFIG[6]    ; RAM_DATA[0]   ; 26.161 ; 26.161 ; 26.161 ; 26.161 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 24.079 ; 24.079 ; 24.079 ; 24.079 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 24.855 ; 24.855 ; 24.855 ; 24.855 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 24.038 ; 24.038 ; 24.038 ; 24.038 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 23.499 ; 23.499 ; 23.499 ; 23.499 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 27.996 ; 27.996 ; 27.996 ; 27.996 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 26.266 ; 26.266 ; 26.266 ; 26.266 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 24.858 ; 24.858 ; 24.858 ; 24.858 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 26.550 ; 26.550 ; 26.550 ; 26.550 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 24.673 ; 24.673 ; 24.673 ; 24.673 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 23.824 ; 23.824 ; 23.824 ; 23.824 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 25.263 ; 25.263 ; 25.263 ; 25.263 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 24.058 ; 24.058 ; 24.058 ; 24.058 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 24.194 ; 24.194 ; 24.194 ; 24.194 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 23.597 ; 23.597 ; 23.597 ; 23.597 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 22.536 ; 22.536 ; 22.536 ; 22.536 ;
; CONFIG[6]    ; ROM2n         ; 14.709 ; 14.709 ; 14.709 ; 14.709 ;
; CRT_PIN3     ; DATA[7]       ; 19.095 ; 19.095 ; 19.095 ; 19.095 ;
; CRT_PIN3     ; RAM_DATA[7]   ; 21.516 ; 21.516 ; 21.516 ; 21.516 ;
; CRT_PIN3     ; RAM_DATA[12]  ; 11.813 ; 11.813 ; 11.813 ; 11.813 ;
; CRT_PIN3     ; RAM_DATA[13]  ; 12.251 ; 12.251 ; 12.251 ; 12.251 ;
; CRT_PIN3     ; RAM_DATA[14]  ; 12.388 ; 12.388 ; 12.388 ; 12.388 ;
; CRT_PIN3     ; RAM_DATA[15]  ; 10.879 ; 10.879 ; 10.879 ; 10.879 ;
; DATA[0]      ; DATA[0]       ; 21.384 ;        ;        ; 21.384 ;
; DATA[0]      ; RAM_DATA[0]   ; 23.032 ;        ;        ; 23.032 ;
; DATA[1]      ; DATA[1]       ; 21.273 ;        ;        ; 21.273 ;
; DATA[1]      ; RAM_DATA[1]   ; 21.805 ;        ;        ; 21.805 ;
; DATA[2]      ; DATA[2]       ; 22.735 ;        ;        ; 22.735 ;
; DATA[2]      ; RAM_DATA[2]   ; 23.023 ;        ;        ; 23.023 ;
; DATA[3]      ; DATA[3]       ; 21.749 ;        ;        ; 21.749 ;
; DATA[3]      ; RAM_DATA[3]   ; 21.700 ;        ;        ; 21.700 ;
; DATA[4]      ; DATA[4]       ; 21.917 ;        ;        ; 21.917 ;
; DATA[4]      ; RAM_DATA[4]   ; 21.119 ;        ;        ; 21.119 ;
; DATA[5]      ; DATA[5]       ; 22.662 ;        ;        ; 22.662 ;
; DATA[5]      ; RAM_DATA[5]   ; 25.173 ;        ;        ; 25.173 ;
; DATA[6]      ; DATA[6]       ; 21.339 ;        ;        ; 21.339 ;
; DATA[6]      ; RAM_DATA[6]   ; 23.825 ;        ;        ; 23.825 ;
; DATA[7]      ; DATA[7]       ; 22.073 ;        ;        ; 22.073 ;
; DATA[7]      ; RAM_DATA[7]   ; 24.494 ;        ;        ; 24.494 ;
; DATA[8]      ; DATA[8]       ; 22.913 ;        ;        ; 22.913 ;
; DATA[8]      ; RAM_DATA[8]   ; 24.770 ;        ;        ; 24.770 ;
; DATA[9]      ; DATA[9]       ; 21.317 ;        ;        ; 21.317 ;
; DATA[9]      ; RAM_DATA[9]   ; 21.469 ;        ;        ; 21.469 ;
; DATA[10]     ; DATA[10]      ; 20.498 ;        ;        ; 20.498 ;
; DATA[10]     ; RAM_DATA[10]  ; 20.766 ;        ;        ; 20.766 ;
; DATA[11]     ; DATA[11]      ; 21.466 ;        ;        ; 21.466 ;
; DATA[11]     ; RAM_DATA[11]  ; 22.627 ;        ;        ; 22.627 ;
; DATA[12]     ; DATA[12]      ; 19.550 ;        ;        ; 19.550 ;
; DATA[12]     ; RAM_DATA[12]  ; 20.676 ;        ;        ; 20.676 ;
; DATA[13]     ; DATA[13]      ; 22.129 ;        ;        ; 22.129 ;
; DATA[13]     ; RAM_DATA[13]  ; 22.365 ;        ;        ; 22.365 ;
; DATA[14]     ; DATA[14]      ; 15.246 ;        ;        ; 15.246 ;
; DATA[14]     ; RAM_DATA[14]  ; 17.612 ;        ;        ; 17.612 ;
; DATA[15]     ; DATA[15]      ; 17.491 ;        ;        ; 17.491 ;
; DATA[15]     ; RAM_DATA[15]  ; 17.813 ;        ;        ; 17.813 ;
; FC[0]        ; ACSI_RDn      ; 20.971 ; 20.971 ; 20.971 ; 20.971 ;
; FC[0]        ; ACSI_WRn      ; 21.248 ; 21.248 ; 21.248 ; 21.248 ;
; FC[0]        ; BUTTONn       ; 18.528 ; 18.528 ; 18.528 ; 18.528 ;
; FC[0]        ; CA1_OUT       ; 20.258 ; 20.258 ; 20.258 ; 20.258 ;
; FC[0]        ; CD[0]         ; 31.155 ; 31.155 ; 31.155 ; 31.155 ;
; FC[0]        ; CD[1]         ; 30.785 ; 30.785 ; 30.785 ; 30.785 ;
; FC[0]        ; CD[2]         ; 27.447 ; 27.447 ; 27.447 ; 27.447 ;
; FC[0]        ; CD[3]         ; 31.514 ; 31.514 ; 31.514 ; 31.514 ;
; FC[0]        ; CD[4]         ; 31.637 ; 31.637 ; 31.637 ; 31.637 ;
; FC[0]        ; CD[5]         ; 30.577 ; 30.577 ; 30.577 ; 30.577 ;
; FC[0]        ; CD[6]         ; 31.460 ; 31.460 ; 31.460 ; 31.460 ;
; FC[0]        ; CD[7]         ; 28.144 ; 28.144 ; 28.144 ; 28.144 ;
; FC[0]        ; DATA[0]       ; 31.941 ; 31.941 ; 31.941 ; 31.941 ;
; FC[0]        ; DATA[1]       ; 32.357 ; 32.357 ; 32.357 ; 32.357 ;
; FC[0]        ; DATA[2]       ; 31.385 ; 31.385 ; 31.385 ; 31.385 ;
; FC[0]        ; DATA[3]       ; 33.681 ; 33.681 ; 33.681 ; 33.681 ;
; FC[0]        ; DATA[4]       ; 32.488 ; 32.488 ; 32.488 ; 32.488 ;
; FC[0]        ; DATA[5]       ; 32.262 ; 32.262 ; 32.262 ; 32.262 ;
; FC[0]        ; DATA[6]       ; 30.857 ; 30.857 ; 30.857 ; 30.857 ;
; FC[0]        ; DATA[7]       ; 32.025 ; 32.025 ; 32.025 ; 32.025 ;
; FC[0]        ; DATA[8]       ; 32.987 ; 32.987 ; 32.987 ; 32.987 ;
; FC[0]        ; DATA[9]       ; 31.946 ; 31.946 ; 31.946 ; 31.946 ;
; FC[0]        ; DATA[10]      ; 30.164 ; 30.164 ; 30.164 ; 30.164 ;
; FC[0]        ; DATA[11]      ; 30.957 ; 30.957 ; 30.957 ; 30.957 ;
; FC[0]        ; DATA[12]      ; 30.371 ; 30.371 ; 30.371 ; 30.371 ;
; FC[0]        ; DATA[13]      ; 31.448 ; 31.448 ; 31.448 ; 31.448 ;
; FC[0]        ; DATA[14]      ; 32.253 ; 32.253 ; 32.253 ; 32.253 ;
; FC[0]        ; DATA[15]      ; 32.536 ; 32.536 ; 32.536 ; 32.536 ;
; FC[0]        ; DTACKn        ; 24.337 ; 24.337 ; 24.337 ; 24.337 ;
; FC[0]        ; FLASH_CEn     ; 18.470 ; 18.470 ; 18.470 ; 18.470 ;
; FC[0]        ; FLASH_OEn     ; 18.400 ; 18.400 ; 18.400 ; 18.400 ;
; FC[0]        ; JOY_RHn       ; 21.012 ; 21.012 ; 21.012 ; 21.012 ;
; FC[0]        ; JOY_RLn       ; 23.603 ; 23.603 ; 23.603 ; 23.603 ;
; FC[0]        ; JOY_WEn       ; 23.237 ; 23.237 ; 23.237 ; 23.237 ;
; FC[0]        ; JOY_WL        ; 17.816 ; 17.816 ; 17.816 ; 17.816 ;
; FC[0]        ; RAM_ADR[8]    ; 17.955 ; 17.955 ; 17.955 ; 17.955 ;
; FC[0]        ; RAM_BA[0]     ; 16.312 ; 16.312 ; 16.312 ; 16.312 ;
; FC[0]        ; RAM_BA[1]     ; 14.290 ; 14.290 ; 14.290 ; 14.290 ;
; FC[0]        ; RAM_CAS0n     ; 16.474 ; 16.474 ; 16.474 ; 16.474 ;
; FC[0]        ; RAM_CAS1n     ; 16.470 ; 16.470 ; 16.470 ; 16.470 ;
; FC[0]        ; RAM_DATA[0]   ; 33.589 ; 33.589 ; 33.589 ; 33.589 ;
; FC[0]        ; RAM_DATA[1]   ; 32.889 ; 32.889 ; 32.889 ; 32.889 ;
; FC[0]        ; RAM_DATA[2]   ; 31.673 ; 31.673 ; 31.673 ; 31.673 ;
; FC[0]        ; RAM_DATA[3]   ; 33.632 ; 33.632 ; 33.632 ; 33.632 ;
; FC[0]        ; RAM_DATA[4]   ; 31.690 ; 31.690 ; 31.690 ; 31.690 ;
; FC[0]        ; RAM_DATA[5]   ; 34.773 ; 34.773 ; 34.773 ; 34.773 ;
; FC[0]        ; RAM_DATA[6]   ; 33.343 ; 33.343 ; 33.343 ; 33.343 ;
; FC[0]        ; RAM_DATA[7]   ; 34.446 ; 34.446 ; 34.446 ; 34.446 ;
; FC[0]        ; RAM_DATA[8]   ; 34.844 ; 34.844 ; 34.844 ; 34.844 ;
; FC[0]        ; RAM_DATA[9]   ; 32.098 ; 32.098 ; 32.098 ; 32.098 ;
; FC[0]        ; RAM_DATA[10]  ; 30.432 ; 30.432 ; 30.432 ; 30.432 ;
; FC[0]        ; RAM_DATA[11]  ; 32.118 ; 32.118 ; 32.118 ; 32.118 ;
; FC[0]        ; RAM_DATA[12]  ; 31.497 ; 31.497 ; 31.497 ; 31.497 ;
; FC[0]        ; RAM_DATA[13]  ; 31.684 ; 31.684 ; 31.684 ; 31.684 ;
; FC[0]        ; RAM_DATA[14]  ; 34.619 ; 34.619 ; 34.619 ; 34.619 ;
; FC[0]        ; RAM_DATA[15]  ; 32.858 ; 32.858 ; 32.858 ; 32.858 ;
; FC[0]        ; RAM_DQM0H     ; 17.660 ; 17.660 ; 17.660 ; 17.660 ;
; FC[0]        ; RAM_DQM0L     ; 16.856 ; 16.856 ; 16.856 ; 16.856 ;
; FC[0]        ; RAM_DQM1H     ; 15.908 ; 15.908 ; 15.908 ; 15.908 ;
; FC[0]        ; RAM_DQM1L     ; 16.809 ; 16.809 ; 16.809 ; 16.809 ;
; FC[0]        ; RAM_RAS0n     ; 17.375 ; 17.375 ; 17.375 ; 17.375 ;
; FC[0]        ; RAM_RAS1n     ; 16.734 ; 16.734 ; 16.734 ; 16.734 ;
; FC[0]        ; ROM0n         ; 17.417 ; 17.417 ; 17.417 ; 17.417 ;
; FC[0]        ; ROM1n         ; 17.036 ; 17.036 ; 17.036 ; 17.036 ;
; FC[0]        ; ROM2n         ; 15.134 ; 15.134 ; 15.134 ; 15.134 ;
; FC[0]        ; ROM3n         ; 17.322 ; 17.322 ; 17.322 ; 17.322 ;
; FC[0]        ; ROM4n         ; 18.617 ; 18.617 ; 18.617 ; 18.617 ;
; FC[0]        ; ROM5n         ; 14.107 ; 14.107 ; 14.107 ; 14.107 ;
; FC[0]        ; ROM6n         ; 17.530 ; 17.530 ; 17.530 ; 17.530 ;
; FC[1]        ; ACSI_RDn      ; 20.652 ; 20.652 ; 20.652 ; 20.652 ;
; FC[1]        ; ACSI_WRn      ; 20.929 ; 20.929 ; 20.929 ; 20.929 ;
; FC[1]        ; BUTTONn       ; 18.231 ; 18.231 ; 18.231 ; 18.231 ;
; FC[1]        ; CA1_OUT       ; 19.939 ; 19.939 ; 19.939 ; 19.939 ;
; FC[1]        ; CD[0]         ; 30.836 ; 30.836 ; 30.836 ; 30.836 ;
; FC[1]        ; CD[1]         ; 30.466 ; 30.466 ; 30.466 ; 30.466 ;
; FC[1]        ; CD[2]         ; 27.128 ; 27.128 ; 27.128 ; 27.128 ;
; FC[1]        ; CD[3]         ; 31.195 ; 31.195 ; 31.195 ; 31.195 ;
; FC[1]        ; CD[4]         ; 31.318 ; 31.318 ; 31.318 ; 31.318 ;
; FC[1]        ; CD[5]         ; 30.258 ; 30.258 ; 30.258 ; 30.258 ;
; FC[1]        ; CD[6]         ; 31.141 ; 31.141 ; 31.141 ; 31.141 ;
; FC[1]        ; CD[7]         ; 27.825 ; 27.825 ; 27.825 ; 27.825 ;
; FC[1]        ; DATA[0]       ; 31.236 ; 31.236 ; 31.236 ; 31.236 ;
; FC[1]        ; DATA[1]       ; 31.652 ; 31.652 ; 31.652 ; 31.652 ;
; FC[1]        ; DATA[2]       ; 30.680 ; 30.680 ; 30.680 ; 30.680 ;
; FC[1]        ; DATA[3]       ; 32.976 ; 32.976 ; 32.976 ; 32.976 ;
; FC[1]        ; DATA[4]       ; 31.783 ; 31.783 ; 31.783 ; 31.783 ;
; FC[1]        ; DATA[5]       ; 31.943 ; 31.943 ; 31.943 ; 31.943 ;
; FC[1]        ; DATA[6]       ; 30.152 ; 30.152 ; 30.152 ; 30.152 ;
; FC[1]        ; DATA[7]       ; 31.320 ; 31.320 ; 31.320 ; 31.320 ;
; FC[1]        ; DATA[8]       ; 32.658 ; 32.658 ; 32.658 ; 32.658 ;
; FC[1]        ; DATA[9]       ; 31.326 ; 31.326 ; 31.326 ; 31.326 ;
; FC[1]        ; DATA[10]      ; 29.459 ; 29.459 ; 29.459 ; 29.459 ;
; FC[1]        ; DATA[11]      ; 30.252 ; 30.252 ; 30.252 ; 30.252 ;
; FC[1]        ; DATA[12]      ; 29.695 ; 29.695 ; 29.695 ; 29.695 ;
; FC[1]        ; DATA[13]      ; 30.993 ; 30.993 ; 30.993 ; 30.993 ;
; FC[1]        ; DATA[14]      ; 31.548 ; 31.548 ; 31.548 ; 31.548 ;
; FC[1]        ; DATA[15]      ; 31.831 ; 31.831 ; 31.831 ; 31.831 ;
; FC[1]        ; DTACKn        ; 23.632 ; 23.632 ; 23.632 ; 23.632 ;
; FC[1]        ; FLASH_CEn     ; 18.103 ; 18.103 ; 18.103 ; 18.103 ;
; FC[1]        ; FLASH_OEn     ; 18.033 ; 18.033 ; 18.033 ; 18.033 ;
; FC[1]        ; JOY_RHn       ; 20.693 ; 20.693 ; 20.693 ; 20.693 ;
; FC[1]        ; JOY_RLn       ; 23.284 ; 23.284 ; 23.284 ; 23.284 ;
; FC[1]        ; JOY_WEn       ; 22.918 ; 22.918 ; 22.918 ; 22.918 ;
; FC[1]        ; JOY_WL        ; 17.497 ; 17.497 ; 17.497 ; 17.497 ;
; FC[1]        ; RAM_ADR[8]    ; 17.601 ; 17.601 ; 17.601 ; 17.601 ;
; FC[1]        ; RAM_BA[0]     ; 15.958 ; 15.958 ; 15.958 ; 15.958 ;
; FC[1]        ; RAM_BA[1]     ; 13.936 ; 13.936 ; 13.936 ; 13.936 ;
; FC[1]        ; RAM_CAS0n     ; 16.120 ; 16.120 ; 16.120 ; 16.120 ;
; FC[1]        ; RAM_CAS1n     ; 16.116 ; 16.116 ; 16.116 ; 16.116 ;
; FC[1]        ; RAM_DATA[0]   ; 32.884 ; 32.884 ; 32.884 ; 32.884 ;
; FC[1]        ; RAM_DATA[1]   ; 32.184 ; 32.184 ; 32.184 ; 32.184 ;
; FC[1]        ; RAM_DATA[2]   ; 30.968 ; 30.968 ; 30.968 ; 30.968 ;
; FC[1]        ; RAM_DATA[3]   ; 32.927 ; 32.927 ; 32.927 ; 32.927 ;
; FC[1]        ; RAM_DATA[4]   ; 30.985 ; 30.985 ; 30.985 ; 30.985 ;
; FC[1]        ; RAM_DATA[5]   ; 34.454 ; 34.454 ; 34.454 ; 34.454 ;
; FC[1]        ; RAM_DATA[6]   ; 32.638 ; 32.638 ; 32.638 ; 32.638 ;
; FC[1]        ; RAM_DATA[7]   ; 33.741 ; 33.741 ; 33.741 ; 33.741 ;
; FC[1]        ; RAM_DATA[8]   ; 34.515 ; 34.515 ; 34.515 ; 34.515 ;
; FC[1]        ; RAM_DATA[9]   ; 31.478 ; 31.478 ; 31.478 ; 31.478 ;
; FC[1]        ; RAM_DATA[10]  ; 29.727 ; 29.727 ; 29.727 ; 29.727 ;
; FC[1]        ; RAM_DATA[11]  ; 31.413 ; 31.413 ; 31.413 ; 31.413 ;
; FC[1]        ; RAM_DATA[12]  ; 30.821 ; 30.821 ; 30.821 ; 30.821 ;
; FC[1]        ; RAM_DATA[13]  ; 31.229 ; 31.229 ; 31.229 ; 31.229 ;
; FC[1]        ; RAM_DATA[14]  ; 33.914 ; 33.914 ; 33.914 ; 33.914 ;
; FC[1]        ; RAM_DATA[15]  ; 32.153 ; 32.153 ; 32.153 ; 32.153 ;
; FC[1]        ; RAM_DQM0H     ; 17.306 ; 17.306 ; 17.306 ; 17.306 ;
; FC[1]        ; RAM_DQM0L     ; 16.502 ; 16.502 ; 16.502 ; 16.502 ;
; FC[1]        ; RAM_DQM1H     ; 15.554 ; 15.554 ; 15.554 ; 15.554 ;
; FC[1]        ; RAM_DQM1L     ; 16.455 ; 16.455 ; 16.455 ; 16.455 ;
; FC[1]        ; RAM_RAS0n     ; 17.021 ; 17.021 ; 17.021 ; 17.021 ;
; FC[1]        ; RAM_RAS1n     ; 16.380 ; 16.380 ; 16.380 ; 16.380 ;
; FC[1]        ; ROM0n         ; 17.050 ; 17.050 ; 17.050 ; 17.050 ;
; FC[1]        ; ROM1n         ; 16.669 ; 16.669 ; 16.669 ; 16.669 ;
; FC[1]        ; ROM2n         ; 14.767 ; 14.767 ; 14.767 ; 14.767 ;
; FC[1]        ; ROM3n         ; 16.955 ; 16.955 ; 16.955 ; 16.955 ;
; FC[1]        ; ROM4n         ; 18.250 ; 18.250 ; 18.250 ; 18.250 ;
; FC[1]        ; ROM5n         ; 13.740 ; 13.740 ; 13.740 ; 13.740 ;
; FC[1]        ; ROM6n         ; 17.163 ; 17.163 ; 17.163 ; 17.163 ;
; FC[2]        ; ACSI_RDn      ; 20.571 ; 20.571 ; 20.571 ; 20.571 ;
; FC[2]        ; ACSI_WRn      ; 20.848 ; 20.848 ; 20.848 ; 20.848 ;
; FC[2]        ; CA1_OUT       ;        ; 19.858 ; 19.858 ;        ;
; FC[2]        ; CD[0]         ; 30.755 ; 30.755 ; 30.755 ; 30.755 ;
; FC[2]        ; CD[1]         ; 30.385 ; 30.385 ; 30.385 ; 30.385 ;
; FC[2]        ; CD[2]         ; 27.047 ; 27.047 ; 27.047 ; 27.047 ;
; FC[2]        ; CD[3]         ; 31.114 ; 31.114 ; 31.114 ; 31.114 ;
; FC[2]        ; CD[4]         ; 31.237 ; 31.237 ; 31.237 ; 31.237 ;
; FC[2]        ; CD[5]         ; 30.177 ; 30.177 ; 30.177 ; 30.177 ;
; FC[2]        ; CD[6]         ; 31.060 ; 31.060 ; 31.060 ; 31.060 ;
; FC[2]        ; CD[7]         ; 27.744 ; 27.744 ; 27.744 ; 27.744 ;
; FC[2]        ; DATA[0]       ; 29.920 ; 30.798 ; 30.798 ; 29.920 ;
; FC[2]        ; DATA[1]       ; 30.879 ; 31.507 ; 31.507 ; 30.879 ;
; FC[2]        ; DATA[2]       ; 30.089 ; 29.842 ; 29.842 ; 30.089 ;
; FC[2]        ; DATA[3]       ; 31.759 ; 32.651 ; 32.651 ; 31.759 ;
; FC[2]        ; DATA[4]       ; 31.324 ; 31.424 ; 31.424 ; 31.324 ;
; FC[2]        ; DATA[5]       ; 31.862 ; 31.037 ; 31.037 ; 31.862 ;
; FC[2]        ; DATA[6]       ; 29.345 ; 29.245 ; 29.245 ; 29.345 ;
; FC[2]        ; DATA[7]       ; 29.580 ; 30.139 ; 30.139 ; 29.580 ;
; FC[2]        ; DATA[8]       ; 32.581 ; 32.443 ; 32.443 ; 32.581 ;
; FC[2]        ; DATA[9]       ; 31.249 ; 30.784 ; 30.784 ; 31.249 ;
; FC[2]        ; DATA[10]      ; 29.238 ; 29.238 ; 29.238 ; 29.238 ;
; FC[2]        ; DATA[11]      ; 30.144 ; 30.144 ; 30.144 ; 30.144 ;
; FC[2]        ; DATA[12]      ; 29.461 ; 29.618 ; 29.618 ; 29.461 ;
; FC[2]        ; DATA[13]      ; 30.755 ; 30.916 ; 30.916 ; 30.755 ;
; FC[2]        ; DATA[14]      ; 30.981 ; 30.981 ; 30.981 ; 30.981 ;
; FC[2]        ; DATA[15]      ; 31.182 ; 31.182 ; 31.182 ; 31.182 ;
; FC[2]        ; DTACKn        ; 23.053 ; 23.053 ; 23.053 ; 23.053 ;
; FC[2]        ; JOY_RHn       ;        ; 20.612 ; 20.612 ;        ;
; FC[2]        ; JOY_RLn       ;        ; 23.203 ; 23.203 ;        ;
; FC[2]        ; JOY_WEn       ; 22.837 ;        ;        ; 22.837 ;
; FC[2]        ; JOY_WL        ; 17.416 ;        ;        ; 17.416 ;
; FC[2]        ; RAM_DATA[0]   ; 31.568 ; 32.446 ; 32.446 ; 31.568 ;
; FC[2]        ; RAM_DATA[1]   ; 31.411 ; 32.039 ; 32.039 ; 31.411 ;
; FC[2]        ; RAM_DATA[2]   ; 30.377 ; 30.130 ; 30.130 ; 30.377 ;
; FC[2]        ; RAM_DATA[3]   ; 31.710 ; 32.602 ; 32.602 ; 31.710 ;
; FC[2]        ; RAM_DATA[4]   ; 30.526 ; 30.626 ; 30.626 ; 30.526 ;
; FC[2]        ; RAM_DATA[5]   ; 34.373 ; 33.548 ; 33.548 ; 34.373 ;
; FC[2]        ; RAM_DATA[6]   ; 31.831 ; 31.731 ; 31.731 ; 31.831 ;
; FC[2]        ; RAM_DATA[7]   ; 32.001 ; 32.560 ; 32.560 ; 32.001 ;
; FC[2]        ; RAM_DATA[8]   ; 34.438 ; 34.300 ; 34.300 ; 34.438 ;
; FC[2]        ; RAM_DATA[9]   ; 31.401 ; 30.936 ; 30.936 ; 31.401 ;
; FC[2]        ; RAM_DATA[10]  ; 29.506 ; 29.506 ; 29.506 ; 29.506 ;
; FC[2]        ; RAM_DATA[11]  ; 31.305 ; 31.305 ; 31.305 ; 31.305 ;
; FC[2]        ; RAM_DATA[12]  ; 30.587 ; 30.744 ; 30.744 ; 30.587 ;
; FC[2]        ; RAM_DATA[13]  ; 30.991 ; 31.152 ; 31.152 ; 30.991 ;
; FC[2]        ; RAM_DATA[14]  ; 33.347 ; 33.347 ; 33.347 ; 33.347 ;
; FC[2]        ; RAM_DATA[15]  ; 31.504 ; 31.504 ; 31.504 ; 31.504 ;
; HDINTn       ; DATA[5]       ; 27.248 ;        ;        ; 27.248 ;
; HDINTn       ; RAM_DATA[5]   ; 29.759 ;        ;        ; 29.759 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 27.168 ; 27.168 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 29.679 ; 29.679 ;        ;
; IDE_IORDY    ; DTACKn        ; 17.327 ; 17.327 ; 17.327 ; 17.327 ;
; LDSn         ; ACSI_RDn      ; 18.887 ; 18.887 ; 18.887 ; 18.887 ;
; LDSn         ; ACSI_WRn      ; 19.164 ; 19.164 ; 19.164 ; 19.164 ;
; LDSn         ; BUTTONn       ; 21.706 ;        ;        ; 21.706 ;
; LDSn         ; CA1_OUT       ; 18.174 ;        ;        ; 18.174 ;
; LDSn         ; CD[0]         ; 29.071 ; 29.071 ; 29.071 ; 29.071 ;
; LDSn         ; CD[1]         ; 28.701 ; 28.701 ; 28.701 ; 28.701 ;
; LDSn         ; CD[2]         ; 25.363 ; 25.363 ; 25.363 ; 25.363 ;
; LDSn         ; CD[3]         ; 29.430 ; 29.430 ; 29.430 ; 29.430 ;
; LDSn         ; CD[4]         ; 29.553 ; 29.553 ; 29.553 ; 29.553 ;
; LDSn         ; CD[5]         ; 28.493 ; 28.493 ; 28.493 ; 28.493 ;
; LDSn         ; CD[6]         ; 29.376 ; 29.376 ; 29.376 ; 29.376 ;
; LDSn         ; CD[7]         ; 26.060 ; 26.060 ; 26.060 ; 26.060 ;
; LDSn         ; DATA[0]       ; 30.265 ; 30.978 ; 30.978 ; 30.265 ;
; LDSn         ; DATA[1]       ; 30.974 ; 31.893 ; 31.893 ; 30.974 ;
; LDSn         ; DATA[2]       ; 30.834 ; 31.147 ; 31.147 ; 30.834 ;
; LDSn         ; DATA[3]       ; 32.439 ; 32.157 ; 32.157 ; 32.439 ;
; LDSn         ; DATA[4]       ; 32.482 ; 32.382 ; 32.382 ; 32.482 ;
; LDSn         ; DATA[5]       ; 31.947 ; 32.920 ; 32.920 ; 31.947 ;
; LDSn         ; DATA[6]       ; 30.303 ; 30.403 ; 30.403 ; 30.303 ;
; LDSn         ; DATA[7]       ; 31.197 ; 30.638 ; 30.638 ; 31.197 ;
; LDSn         ; DATA[8]       ; 31.177 ; 31.177 ; 31.177 ; 31.177 ;
; LDSn         ; DATA[9]       ; 30.339 ; 30.339 ; 30.339 ; 30.339 ;
; LDSn         ; DATA[10]      ; 29.150 ; 28.601 ; 28.601 ; 29.150 ;
; LDSn         ; DATA[11]      ; 30.362 ; 30.362 ; 30.362 ; 30.362 ;
; LDSn         ; DATA[12]      ; 29.718 ; 29.070 ; 29.070 ; 29.718 ;
; LDSn         ; DATA[13]      ; 30.670 ; 30.670 ; 30.670 ; 30.670 ;
; LDSn         ; DATA[14]      ; 30.847 ; 30.847 ; 30.847 ; 30.847 ;
; LDSn         ; DATA[15]      ; 31.413 ; 31.413 ; 31.413 ; 31.413 ;
; LDSn         ; DTACKn        ; 22.378 ; 22.378 ; 22.378 ; 22.378 ;
; LDSn         ; IDE_IORDn     ; 13.198 ;        ;        ; 13.198 ;
; LDSn         ; IDE_IOWRn     ; 14.606 ;        ;        ; 14.606 ;
; LDSn         ; JOY_RLn       ; 17.474 ;        ;        ; 17.474 ;
; LDSn         ; JOY_WEn       ;        ; 17.108 ; 17.108 ;        ;
; LDSn         ; JOY_WL        ;        ; 14.997 ; 14.997 ;        ;
; LDSn         ; RAM_CAS0n     ; 14.682 ;        ;        ; 14.682 ;
; LDSn         ; RAM_CAS1n     ; 14.667 ;        ;        ; 14.667 ;
; LDSn         ; RAM_DATA[0]   ; 31.913 ; 32.626 ; 32.626 ; 31.913 ;
; LDSn         ; RAM_DATA[1]   ; 31.506 ; 32.425 ; 32.425 ; 31.506 ;
; LDSn         ; RAM_DATA[2]   ; 31.122 ; 31.435 ; 31.435 ; 31.122 ;
; LDSn         ; RAM_DATA[3]   ; 32.390 ; 32.108 ; 32.108 ; 32.390 ;
; LDSn         ; RAM_DATA[4]   ; 31.684 ; 31.584 ; 31.584 ; 31.684 ;
; LDSn         ; RAM_DATA[5]   ; 34.458 ; 35.431 ; 35.431 ; 34.458 ;
; LDSn         ; RAM_DATA[6]   ; 32.789 ; 32.889 ; 32.889 ; 32.789 ;
; LDSn         ; RAM_DATA[7]   ; 33.618 ; 33.059 ; 33.059 ; 33.618 ;
; LDSn         ; RAM_DATA[8]   ; 33.034 ; 33.034 ; 33.034 ; 33.034 ;
; LDSn         ; RAM_DATA[9]   ; 30.491 ; 30.491 ; 30.491 ; 30.491 ;
; LDSn         ; RAM_DATA[10]  ; 29.418 ; 28.869 ; 28.869 ; 29.418 ;
; LDSn         ; RAM_DATA[11]  ; 31.523 ; 31.523 ; 31.523 ; 31.523 ;
; LDSn         ; RAM_DATA[12]  ; 30.844 ; 30.196 ; 30.196 ; 30.844 ;
; LDSn         ; RAM_DATA[13]  ; 30.906 ; 30.906 ; 30.906 ; 30.906 ;
; LDSn         ; RAM_DATA[14]  ; 33.213 ; 33.213 ; 33.213 ; 33.213 ;
; LDSn         ; RAM_DATA[15]  ; 31.735 ; 31.735 ; 31.735 ; 31.735 ;
; LDSn         ; RAM_DQM0L     ; 15.935 ;        ;        ; 15.935 ;
; LDSn         ; RAM_DQM1L     ; 15.885 ;        ;        ; 15.885 ;
; LPT_BSY      ; DATA[0]       ; 23.364 ;        ;        ; 23.364 ;
; LPT_BSY      ; RAM_DATA[0]   ; 25.012 ;        ;        ; 25.012 ;
; LPT_D[0]     ; DATA[8]       ; 23.497 ;        ;        ; 23.497 ;
; LPT_D[0]     ; RAM_DATA[8]   ; 25.354 ;        ;        ; 25.354 ;
; LPT_D[1]     ; DATA[9]       ; 22.649 ;        ;        ; 22.649 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 22.801 ;        ;        ; 22.801 ;
; LPT_D[2]     ; DATA[10]      ; 19.772 ;        ;        ; 19.772 ;
; LPT_D[2]     ; RAM_DATA[10]  ; 20.040 ;        ;        ; 20.040 ;
; LPT_D[3]     ; DATA[11]      ; 20.694 ;        ;        ; 20.694 ;
; LPT_D[3]     ; RAM_DATA[11]  ; 21.855 ;        ;        ; 21.855 ;
; LPT_D[4]     ; DATA[12]      ; 20.963 ;        ;        ; 20.963 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 22.089 ;        ;        ; 22.089 ;
; LPT_D[5]     ; DATA[13]      ; 22.544 ;        ;        ; 22.544 ;
; LPT_D[5]     ; RAM_DATA[13]  ; 22.780 ;        ;        ; 22.780 ;
; LPT_D[6]     ; DATA[14]      ; 21.673 ; 21.673 ; 21.673 ; 21.673 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 24.039 ; 24.039 ; 24.039 ; 24.039 ;
; LPT_D[7]     ; DATA[15]      ; 22.835 ; 22.835 ; 22.835 ; 22.835 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 23.157 ; 23.157 ; 23.157 ; 23.157 ;
; MIDI_IN      ; MIDI_TLR      ; 8.871  ;        ;        ; 8.871  ;
; RAM_DATA[0]  ; DATA[0]       ; 23.719 ;        ;        ; 23.719 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 25.367 ;        ;        ; 25.367 ;
; RAM_DATA[1]  ; DATA[1]       ; 23.635 ;        ;        ; 23.635 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 24.167 ;        ;        ; 24.167 ;
; RAM_DATA[2]  ; DATA[2]       ; 23.119 ;        ;        ; 23.119 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 23.407 ;        ;        ; 23.407 ;
; RAM_DATA[3]  ; DATA[3]       ; 24.926 ;        ;        ; 24.926 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 24.877 ;        ;        ; 24.877 ;
; RAM_DATA[4]  ; DATA[4]       ; 22.902 ;        ;        ; 22.902 ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 22.104 ;        ;        ; 22.104 ;
; RAM_DATA[5]  ; DATA[5]       ; 23.543 ;        ;        ; 23.543 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 26.054 ;        ;        ; 26.054 ;
; RAM_DATA[6]  ; DATA[6]       ; 21.134 ;        ;        ; 21.134 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 23.620 ;        ;        ; 23.620 ;
; RAM_DATA[7]  ; DATA[7]       ; 22.668 ;        ;        ; 22.668 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 25.089 ;        ;        ; 25.089 ;
; RAM_DATA[8]  ; DATA[8]       ; 24.818 ;        ;        ; 24.818 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 26.675 ;        ;        ; 26.675 ;
; RAM_DATA[9]  ; DATA[9]       ; 22.708 ;        ;        ; 22.708 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 22.860 ;        ;        ; 22.860 ;
; RAM_DATA[10] ; DATA[10]      ; 21.561 ;        ;        ; 21.561 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 21.829 ;        ;        ; 21.829 ;
; RAM_DATA[11] ; DATA[11]      ; 22.449 ;        ;        ; 22.449 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 23.610 ;        ;        ; 23.610 ;
; RAM_DATA[12] ; DATA[12]      ; 21.152 ;        ;        ; 21.152 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 22.278 ;        ;        ; 22.278 ;
; RAM_DATA[13] ; DATA[13]      ; 24.107 ;        ;        ; 24.107 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 24.343 ;        ;        ; 24.343 ;
; RAM_DATA[14] ; DATA[14]      ; 22.936 ; 22.936 ; 22.936 ; 22.936 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 25.302 ; 25.302 ; 25.302 ; 25.302 ;
; RAM_DATA[15] ; DATA[15]      ; 22.188 ; 22.188 ; 22.188 ; 22.188 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 22.510 ; 22.510 ; 22.510 ; 22.510 ;
; RWn          ; ACSI_RDn      ; 20.996 ; 20.996 ; 20.996 ; 20.996 ;
; RWn          ; ACSI_WRn      ; 21.273 ; 21.273 ; 21.273 ; 21.273 ;
; RWn          ; BUTTONn       ;        ; 21.438 ; 21.438 ;        ;
; RWn          ; CA1_OUT       ;        ; 20.283 ; 20.283 ;        ;
; RWn          ; CD[0]         ; 31.180 ; 31.180 ; 31.180 ; 31.180 ;
; RWn          ; CD[1]         ; 30.810 ; 30.810 ; 30.810 ; 30.810 ;
; RWn          ; CD[2]         ; 27.472 ; 27.472 ; 27.472 ; 27.472 ;
; RWn          ; CD[3]         ; 31.539 ; 31.539 ; 31.539 ; 31.539 ;
; RWn          ; CD[4]         ; 31.662 ; 31.662 ; 31.662 ; 31.662 ;
; RWn          ; CD[5]         ; 30.602 ; 30.602 ; 30.602 ; 30.602 ;
; RWn          ; CD[6]         ; 31.485 ; 31.485 ; 31.485 ; 31.485 ;
; RWn          ; CD[7]         ; 28.169 ; 28.169 ; 28.169 ; 28.169 ;
; RWn          ; DATA[0]       ; 30.659 ; 31.223 ; 31.223 ; 30.659 ;
; RWn          ; DATA[1]       ; 31.304 ; 31.978 ; 31.978 ; 31.304 ;
; RWn          ; DATA[2]       ; 30.514 ; 31.553 ; 31.553 ; 30.514 ;
; RWn          ; DATA[3]       ; 32.184 ; 33.076 ; 33.076 ; 32.184 ;
; RWn          ; DATA[4]       ; 31.749 ; 31.849 ; 31.849 ; 31.749 ;
; RWn          ; DATA[5]       ; 32.287 ; 31.462 ; 31.462 ; 32.287 ;
; RWn          ; DATA[6]       ; 29.897 ; 30.639 ; 30.639 ; 29.897 ;
; RWn          ; DATA[7]       ; 30.005 ; 31.151 ; 31.151 ; 30.005 ;
; RWn          ; DATA[8]       ; 32.868 ; 33.006 ; 33.006 ; 32.868 ;
; RWn          ; DATA[9]       ; 31.209 ; 31.674 ; 31.674 ; 31.209 ;
; RWn          ; DATA[10]      ; 29.663 ; 29.663 ; 29.663 ; 29.663 ;
; RWn          ; DATA[11]      ; 30.569 ; 30.569 ; 30.569 ; 30.569 ;
; RWn          ; DATA[12]      ; 30.043 ; 29.886 ; 29.886 ; 30.043 ;
; RWn          ; DATA[13]      ; 31.341 ; 31.180 ; 31.180 ; 31.341 ;
; RWn          ; DATA[14]      ; 31.406 ; 31.406 ; 31.406 ; 31.406 ;
; RWn          ; DATA[15]      ; 31.607 ; 31.607 ; 31.607 ; 31.607 ;
; RWn          ; DTACKn        ; 23.478 ; 23.478 ; 23.478 ; 23.478 ;
; RWn          ; FLASH_CEn     ;        ; 18.490 ; 18.490 ;        ;
; RWn          ; FLASH_OEn     ;        ; 18.420 ; 18.420 ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 13.832 ; 13.832 ;        ;
; RWn          ; IDE_D_EN_OUTn ; 13.848 ;        ;        ; 13.848 ;
; RWn          ; IDE_IORDn     ;        ; 13.909 ; 13.909 ;        ;
; RWn          ; IDE_IOWRn     ; 15.313 ;        ;        ; 15.313 ;
; RWn          ; JOY_RHn       ;        ; 21.037 ; 21.037 ;        ;
; RWn          ; JOY_RLn       ;        ; 23.628 ; 23.628 ;        ;
; RWn          ; JOY_WEn       ; 23.262 ;        ;        ; 23.262 ;
; RWn          ; JOY_WL        ; 17.841 ; 14.857 ; 14.857 ; 17.841 ;
; RWn          ; RAM_DATA[0]   ; 32.307 ; 32.871 ; 32.871 ; 32.307 ;
; RWn          ; RAM_DATA[1]   ; 31.836 ; 32.510 ; 32.510 ; 31.836 ;
; RWn          ; RAM_DATA[2]   ; 30.802 ; 31.841 ; 31.841 ; 30.802 ;
; RWn          ; RAM_DATA[3]   ; 32.135 ; 33.027 ; 33.027 ; 32.135 ;
; RWn          ; RAM_DATA[4]   ; 30.951 ; 31.051 ; 31.051 ; 30.951 ;
; RWn          ; RAM_DATA[5]   ; 34.798 ; 33.973 ; 33.973 ; 34.798 ;
; RWn          ; RAM_DATA[6]   ; 32.383 ; 33.125 ; 33.125 ; 32.383 ;
; RWn          ; RAM_DATA[7]   ; 32.426 ; 33.572 ; 33.572 ; 32.426 ;
; RWn          ; RAM_DATA[8]   ; 34.725 ; 34.863 ; 34.863 ; 34.725 ;
; RWn          ; RAM_DATA[9]   ; 31.361 ; 31.826 ; 31.826 ; 31.361 ;
; RWn          ; RAM_DATA[10]  ; 29.931 ; 29.931 ; 29.931 ; 29.931 ;
; RWn          ; RAM_DATA[11]  ; 31.730 ; 31.730 ; 31.730 ; 31.730 ;
; RWn          ; RAM_DATA[12]  ; 31.169 ; 31.012 ; 31.012 ; 31.169 ;
; RWn          ; RAM_DATA[13]  ; 31.577 ; 31.416 ; 31.416 ; 31.577 ;
; RWn          ; RAM_DATA[14]  ; 33.772 ; 33.772 ; 33.772 ; 33.772 ;
; RWn          ; RAM_DATA[15]  ; 31.929 ; 31.929 ; 31.929 ; 31.929 ;
; RWn          ; RAM_WEn       ; 13.866 ;        ;        ; 13.866 ;
; RWn          ; ROM0n         ;        ; 17.437 ; 17.437 ;        ;
; RWn          ; ROM1n         ;        ; 17.056 ; 17.056 ;        ;
; RWn          ; ROM2n         ;        ; 15.154 ; 15.154 ;        ;
; RWn          ; ROM3n         ;        ; 17.342 ; 17.342 ;        ;
; RWn          ; ROM4n         ;        ; 18.637 ; 18.637 ;        ;
; RWn          ; ROM5n         ;        ; 14.127 ; 14.127 ;        ;
; RWn          ; ROM6n         ;        ; 17.550 ; 17.550 ;        ;
; SCSI_ACKn    ; CD[0]         ; 17.133 ; 17.133 ; 17.133 ; 17.133 ;
; SCSI_ATNn    ; CD[1]         ; 17.985 ; 17.985 ; 17.985 ; 17.985 ;
; SCSI_BSYn    ; CD[6]         ; 21.530 ; 21.530 ; 21.530 ; 21.530 ;
; SCSI_D[0]    ; CD[0]         ; 17.625 ; 17.625 ; 17.625 ; 17.625 ;
; SCSI_D[1]    ; CD[1]         ; 17.839 ; 17.839 ; 17.839 ; 17.839 ;
; SCSI_D[2]    ; CD[2]         ;        ; 18.295 ; 18.295 ;        ;
; SCSI_D[3]    ; CD[3]         ; 18.504 ; 18.504 ; 18.504 ; 18.504 ;
; SCSI_D[4]    ; CD[4]         ; 20.605 ; 20.605 ; 20.605 ; 20.605 ;
; SCSI_D[5]    ; CD[5]         ; 20.094 ; 20.094 ; 20.094 ; 20.094 ;
; SCSI_D[6]    ; CD[6]         ; 21.308 ; 21.308 ; 21.308 ; 21.308 ;
; SCSI_D[7]    ; CD[7]         ; 18.404 ; 18.404 ; 18.404 ; 18.404 ;
; SCSI_DCn     ; CD[3]         ; 21.336 ; 21.336 ; 21.336 ; 21.336 ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 18.920 ; 18.920 ; 18.920 ; 18.920 ;
; SCSI_DCn     ; SCSI_D[0]     ; 18.404 ; 18.404 ; 18.404 ; 18.404 ;
; SCSI_DCn     ; SCSI_D[1]     ; 18.404 ; 18.404 ; 18.404 ; 18.404 ;
; SCSI_DCn     ; SCSI_D[2]     ; 17.579 ; 17.579 ; 17.579 ; 17.579 ;
; SCSI_DCn     ; SCSI_D[3]     ; 17.579 ; 17.579 ; 17.579 ; 17.579 ;
; SCSI_DCn     ; SCSI_D[4]     ; 17.262 ; 17.262 ; 17.262 ; 17.262 ;
; SCSI_DCn     ; SCSI_D[5]     ; 17.262 ; 17.262 ; 17.262 ; 17.262 ;
; SCSI_DCn     ; SCSI_D[6]     ; 17.255 ; 17.255 ; 17.255 ; 17.255 ;
; SCSI_DCn     ; SCSI_D[7]     ; 17.255 ; 17.255 ; 17.255 ; 17.255 ;
; SCSI_DCn     ; SCSI_DP       ; 18.414 ; 18.414 ; 18.414 ; 18.414 ;
; SCSI_DP      ; CD[0]         ; 17.137 ; 17.137 ; 17.137 ; 17.137 ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 13.580 ; 13.580 ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 13.568 ;        ;        ; 13.568 ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 13.123 ; 13.123 ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 13.304 ;        ;        ; 13.304 ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 13.259 ; 13.259 ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 13.095 ;        ;        ; 13.095 ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 13.163 ; 13.163 ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 13.245 ;        ;        ; 13.245 ;
; SCSI_IDn[1]  ; SCSI_DP       ; 14.948 ; 14.948 ; 14.948 ; 14.948 ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 13.143 ; 13.143 ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 13.119 ; 13.119 ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 12.685 ;        ;        ; 12.685 ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 12.864 ;        ;        ; 12.864 ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 12.816 ; 12.816 ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 12.644 ; 12.644 ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 12.710 ;        ;        ; 12.710 ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 12.800 ;        ;        ; 12.800 ;
; SCSI_IDn[2]  ; SCSI_DP       ; 14.503 ; 14.503 ; 14.503 ; 14.503 ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 13.816 ; 13.816 ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 13.780 ; 13.780 ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 13.390 ; 13.390 ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 13.568 ; 13.568 ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 13.421 ;        ;        ; 13.421 ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 13.238 ;        ;        ; 13.238 ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 13.351 ;        ;        ; 13.351 ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 13.437 ;        ;        ; 13.437 ;
; SCSI_IDn[3]  ; SCSI_DP       ; 15.140 ; 15.140 ; 15.140 ; 15.140 ;
; SCSI_IOn     ; CD[2]         ;        ; 17.794 ; 17.794 ;        ;
; SCSI_IOn     ; CD[3]         ; 19.966 ; 19.966 ; 19.966 ; 19.966 ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 17.550 ; 17.550 ; 17.550 ; 17.550 ;
; SCSI_IOn     ; SCSI_D[0]     ; 17.034 ; 17.034 ; 17.034 ; 17.034 ;
; SCSI_IOn     ; SCSI_D[1]     ; 17.034 ; 17.034 ; 17.034 ; 17.034 ;
; SCSI_IOn     ; SCSI_D[2]     ; 16.209 ; 16.209 ; 16.209 ; 16.209 ;
; SCSI_IOn     ; SCSI_D[3]     ; 16.209 ; 16.209 ; 16.209 ; 16.209 ;
; SCSI_IOn     ; SCSI_D[4]     ; 15.892 ; 15.892 ; 15.892 ; 15.892 ;
; SCSI_IOn     ; SCSI_D[5]     ; 15.892 ; 15.892 ; 15.892 ; 15.892 ;
; SCSI_IOn     ; SCSI_D[6]     ; 15.885 ; 15.885 ; 15.885 ; 15.885 ;
; SCSI_IOn     ; SCSI_D[7]     ; 15.885 ; 15.885 ; 15.885 ; 15.885 ;
; SCSI_IOn     ; SCSI_DP       ; 17.044 ; 17.044 ; 17.044 ; 17.044 ;
; SCSI_IOn     ; SCSI_RDn      ; 12.732 ;        ;        ; 12.732 ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 13.954 ; 13.954 ;        ;
; SCSI_MSGn    ; CD[3]         ; 20.130 ; 20.130 ; 20.130 ; 20.130 ;
; SCSI_MSGn    ; CD[4]         ; 21.135 ; 21.135 ; 21.135 ; 21.135 ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 17.714 ; 17.714 ; 17.714 ; 17.714 ;
; SCSI_MSGn    ; SCSI_D[0]     ; 17.198 ; 17.198 ; 17.198 ; 17.198 ;
; SCSI_MSGn    ; SCSI_D[1]     ; 17.198 ; 17.198 ; 17.198 ; 17.198 ;
; SCSI_MSGn    ; SCSI_D[2]     ; 16.373 ; 16.373 ; 16.373 ; 16.373 ;
; SCSI_MSGn    ; SCSI_D[3]     ; 16.373 ; 16.373 ; 16.373 ; 16.373 ;
; SCSI_MSGn    ; SCSI_D[4]     ; 16.056 ; 16.056 ; 16.056 ; 16.056 ;
; SCSI_MSGn    ; SCSI_D[5]     ; 16.056 ; 16.056 ; 16.056 ; 16.056 ;
; SCSI_MSGn    ; SCSI_D[6]     ; 16.049 ; 16.049 ; 16.049 ; 16.049 ;
; SCSI_MSGn    ; SCSI_D[7]     ; 16.049 ; 16.049 ; 16.049 ; 16.049 ;
; SCSI_MSGn    ; SCSI_DP       ; 17.208 ; 17.208 ; 17.208 ; 17.208 ;
; SCSI_REQn    ; CD[3]         ; 20.296 ; 20.296 ; 20.296 ; 20.296 ;
; SCSI_REQn    ; CD[5]         ; 20.609 ; 20.609 ; 20.609 ; 20.609 ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 17.880 ;        ;        ; 17.880 ;
; SCSI_REQn    ; SCSI_D[0]     ; 17.364 ; 17.364 ; 17.364 ; 17.364 ;
; SCSI_REQn    ; SCSI_D[1]     ; 17.364 ; 17.364 ; 17.364 ; 17.364 ;
; SCSI_REQn    ; SCSI_D[2]     ; 16.539 ; 16.539 ; 16.539 ; 16.539 ;
; SCSI_REQn    ; SCSI_D[3]     ; 16.539 ; 16.539 ; 16.539 ; 16.539 ;
; SCSI_REQn    ; SCSI_D[4]     ; 16.222 ; 16.222 ; 16.222 ; 16.222 ;
; SCSI_REQn    ; SCSI_D[5]     ; 16.222 ; 16.222 ; 16.222 ; 16.222 ;
; SCSI_REQn    ; SCSI_D[6]     ; 16.215 ; 16.215 ; 16.215 ; 16.215 ;
; SCSI_REQn    ; SCSI_D[7]     ; 16.215 ; 16.215 ; 16.215 ; 16.215 ;
; SCSI_REQn    ; SCSI_DP       ; 17.374 ; 17.374 ; 17.374 ; 17.374 ;
; SCSI_RSTn    ; CD[7]         ;        ; 19.202 ; 19.202 ;        ;
; SCSI_SELn    ; CD[1]         ; 16.732 ; 16.732 ; 16.732 ; 16.732 ;
; SD_AVR_ENn   ; RESETn        ;        ; 16.240 ; 16.240 ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 14.339 ; 14.339 ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 11.944 ; 11.944 ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 14.344 ;        ;        ; 14.344 ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 13.070 ;        ;        ; 13.070 ;
; SD_RESETn    ; ACSI_RDn      ; 22.787 ; 22.787 ; 22.787 ; 22.787 ;
; SD_RESETn    ; ACSI_WRn      ; 23.064 ; 23.064 ; 23.064 ; 23.064 ;
; SD_RESETn    ; CA1_OUT       ; 22.074 ;        ;        ; 22.074 ;
; SD_RESETn    ; CD[0]         ; 32.971 ; 32.971 ; 32.971 ; 32.971 ;
; SD_RESETn    ; CD[1]         ; 32.601 ; 32.601 ; 32.601 ; 32.601 ;
; SD_RESETn    ; CD[2]         ; 29.263 ; 29.263 ; 29.263 ; 29.263 ;
; SD_RESETn    ; CD[3]         ; 33.330 ; 33.330 ; 33.330 ; 33.330 ;
; SD_RESETn    ; CD[4]         ; 33.453 ; 33.453 ; 33.453 ; 33.453 ;
; SD_RESETn    ; CD[5]         ; 32.393 ; 32.393 ; 32.393 ; 32.393 ;
; SD_RESETn    ; CD[6]         ; 33.276 ; 33.276 ; 33.276 ; 33.276 ;
; SD_RESETn    ; CD[7]         ; 29.960 ; 29.960 ; 29.960 ; 29.960 ;
; SD_RESETn    ; COM_TxD       ; 17.159 ; 17.159 ; 17.159 ; 17.159 ;
; SD_RESETn    ; DATA[0]       ; 29.485 ; 29.485 ; 29.485 ; 29.485 ;
; SD_RESETn    ; DATA[1]       ; 30.032 ; 30.032 ; 30.032 ; 30.032 ;
; SD_RESETn    ; DATA[2]       ; 29.599 ; 29.599 ; 29.599 ; 29.599 ;
; SD_RESETn    ; DATA[3]       ; 30.887 ; 30.887 ; 30.887 ; 30.887 ;
; SD_RESETn    ; DATA[4]       ; 29.894 ; 29.976 ; 29.976 ; 29.894 ;
; SD_RESETn    ; DATA[5]       ; 29.871 ; 29.871 ; 29.871 ; 29.871 ;
; SD_RESETn    ; DATA[6]       ; 28.023 ; 28.023 ; 28.023 ; 28.023 ;
; SD_RESETn    ; DATA[7]       ; 29.403 ; 29.403 ; 29.403 ; 29.403 ;
; SD_RESETn    ; DATA[8]       ; 26.925 ; 28.326 ; 28.326 ; 26.925 ;
; SD_RESETn    ; DATA[9]       ; 25.833 ; 27.037 ; 27.037 ; 25.833 ;
; SD_RESETn    ; DATA[10]      ; 24.546 ; 25.485 ; 25.485 ; 24.546 ;
; SD_RESETn    ; DATA[11]      ; 25.704 ; 26.273 ; 26.273 ; 25.704 ;
; SD_RESETn    ; DATA[12]      ; 25.440 ; 26.185 ; 26.185 ; 25.440 ;
; SD_RESETn    ; DATA[13]      ; 25.800 ; 26.826 ; 26.826 ; 25.800 ;
; SD_RESETn    ; DATA[14]      ; 28.136 ; 28.136 ; 28.136 ; 28.136 ;
; SD_RESETn    ; DATA[15]      ; 28.702 ; 28.702 ; 28.702 ; 28.702 ;
; SD_RESETn    ; DTACKn        ; 21.951 ; 21.951 ; 21.951 ; 21.951 ;
; SD_RESETn    ; RAM_DATA[0]   ; 31.133 ; 31.133 ; 31.133 ; 31.133 ;
; SD_RESETn    ; RAM_DATA[1]   ; 30.564 ; 30.564 ; 30.564 ; 30.564 ;
; SD_RESETn    ; RAM_DATA[2]   ; 29.887 ; 29.887 ; 29.887 ; 29.887 ;
; SD_RESETn    ; RAM_DATA[3]   ; 30.838 ; 30.838 ; 30.838 ; 30.838 ;
; SD_RESETn    ; RAM_DATA[4]   ; 29.096 ; 29.178 ; 29.178 ; 29.096 ;
; SD_RESETn    ; RAM_DATA[5]   ; 32.382 ; 32.382 ; 32.382 ; 32.382 ;
; SD_RESETn    ; RAM_DATA[6]   ; 30.509 ; 30.509 ; 30.509 ; 30.509 ;
; SD_RESETn    ; RAM_DATA[7]   ; 31.824 ; 31.824 ; 31.824 ; 31.824 ;
; SD_RESETn    ; RAM_DATA[8]   ; 28.782 ; 30.183 ; 30.183 ; 28.782 ;
; SD_RESETn    ; RAM_DATA[9]   ; 25.985 ; 27.189 ; 27.189 ; 25.985 ;
; SD_RESETn    ; RAM_DATA[10]  ; 24.814 ; 25.753 ; 25.753 ; 24.814 ;
; SD_RESETn    ; RAM_DATA[11]  ; 26.865 ; 27.434 ; 27.434 ; 26.865 ;
; SD_RESETn    ; RAM_DATA[12]  ; 26.566 ; 27.311 ; 27.311 ; 26.566 ;
; SD_RESETn    ; RAM_DATA[13]  ; 26.036 ; 27.062 ; 27.062 ; 26.036 ;
; SD_RESETn    ; RAM_DATA[14]  ; 30.502 ; 30.502 ; 30.502 ; 30.502 ;
; SD_RESETn    ; RAM_DATA[15]  ; 29.024 ; 29.024 ; 29.024 ; 29.024 ;
; UDSn         ; ACSI_RDn      ; 18.525 ; 18.525 ; 18.525 ; 18.525 ;
; UDSn         ; ACSI_WRn      ; 18.802 ; 18.802 ; 18.802 ; 18.802 ;
; UDSn         ; CA1_OUT       ; 17.812 ;        ;        ; 17.812 ;
; UDSn         ; CD[0]         ; 28.709 ; 28.709 ; 28.709 ; 28.709 ;
; UDSn         ; CD[1]         ; 28.339 ; 28.339 ; 28.339 ; 28.339 ;
; UDSn         ; CD[2]         ; 25.001 ; 25.001 ; 25.001 ; 25.001 ;
; UDSn         ; CD[3]         ; 29.068 ; 29.068 ; 29.068 ; 29.068 ;
; UDSn         ; CD[4]         ; 29.191 ; 29.191 ; 29.191 ; 29.191 ;
; UDSn         ; CD[5]         ; 28.131 ; 28.131 ; 28.131 ; 28.131 ;
; UDSn         ; CD[6]         ; 29.014 ; 29.014 ; 29.014 ; 29.014 ;
; UDSn         ; CD[7]         ; 25.698 ; 25.698 ; 25.698 ; 25.698 ;
; UDSn         ; DATA[0]       ; 29.689 ; 28.502 ; 28.502 ; 29.689 ;
; UDSn         ; DATA[1]       ; 30.722 ; 28.998 ; 28.998 ; 30.722 ;
; UDSn         ; DATA[2]       ; 30.297 ; 28.460 ; 28.460 ; 30.297 ;
; UDSn         ; DATA[3]       ; 31.409 ; 30.196 ; 30.196 ; 31.409 ;
; UDSn         ; DATA[4]       ; 29.440 ; 29.440 ; 29.440 ; 29.440 ;
; UDSn         ; DATA[5]       ; 29.788 ; 29.788 ; 29.788 ; 29.788 ;
; UDSn         ; DATA[6]       ; 29.383 ; 28.632 ; 28.632 ; 29.383 ;
; UDSn         ; DATA[7]       ; 29.895 ; 28.540 ; 28.540 ; 29.895 ;
; UDSn         ; DATA[8]       ; 29.800 ; 29.938 ; 29.938 ; 29.800 ;
; UDSn         ; DATA[9]       ; 28.747 ; 29.206 ; 29.206 ; 28.747 ;
; UDSn         ; DATA[10]      ; 27.610 ; 27.078 ; 27.078 ; 27.610 ;
; UDSn         ; DATA[11]      ; 27.634 ; 28.287 ; 28.287 ; 27.634 ;
; UDSn         ; DATA[12]      ; 28.178 ; 27.530 ; 27.530 ; 28.178 ;
; UDSn         ; DATA[13]      ; 28.742 ; 28.664 ; 28.664 ; 28.742 ;
; UDSn         ; DATA[14]      ; 28.768 ; 28.768 ; 28.768 ; 28.768 ;
; UDSn         ; DATA[15]      ; 29.051 ; 29.051 ; 29.051 ; 29.051 ;
; UDSn         ; DTACKn        ; 20.852 ; 20.852 ; 20.852 ; 20.852 ;
; UDSn         ; JOY_RHn       ; 14.422 ;        ;        ; 14.422 ;
; UDSn         ; RAM_CAS0n     ; 14.288 ;        ;        ; 14.288 ;
; UDSn         ; RAM_CAS1n     ; 14.273 ;        ;        ; 14.273 ;
; UDSn         ; RAM_DATA[0]   ; 31.337 ; 30.150 ; 30.150 ; 31.337 ;
; UDSn         ; RAM_DATA[1]   ; 31.254 ; 29.530 ; 29.530 ; 31.254 ;
; UDSn         ; RAM_DATA[2]   ; 30.585 ; 28.748 ; 28.748 ; 30.585 ;
; UDSn         ; RAM_DATA[3]   ; 31.360 ; 30.147 ; 30.147 ; 31.360 ;
; UDSn         ; RAM_DATA[4]   ; 28.642 ; 28.642 ; 28.642 ; 28.642 ;
; UDSn         ; RAM_DATA[5]   ; 32.299 ; 32.299 ; 32.299 ; 32.299 ;
; UDSn         ; RAM_DATA[6]   ; 31.869 ; 31.118 ; 31.118 ; 31.869 ;
; UDSn         ; RAM_DATA[7]   ; 32.316 ; 30.961 ; 30.961 ; 32.316 ;
; UDSn         ; RAM_DATA[8]   ; 31.657 ; 31.795 ; 31.795 ; 31.657 ;
; UDSn         ; RAM_DATA[9]   ; 28.899 ; 29.358 ; 29.358 ; 28.899 ;
; UDSn         ; RAM_DATA[10]  ; 27.878 ; 27.346 ; 27.346 ; 27.878 ;
; UDSn         ; RAM_DATA[11]  ; 28.795 ; 29.448 ; 29.448 ; 28.795 ;
; UDSn         ; RAM_DATA[12]  ; 29.304 ; 28.656 ; 28.656 ; 29.304 ;
; UDSn         ; RAM_DATA[13]  ; 28.978 ; 28.900 ; 28.900 ; 28.978 ;
; UDSn         ; RAM_DATA[14]  ; 31.134 ; 31.134 ; 31.134 ; 31.134 ;
; UDSn         ; RAM_DATA[15]  ; 29.373 ; 29.373 ; 29.373 ; 29.373 ;
; UDSn         ; RAM_DQM0H     ; 15.397 ;        ;        ; 15.397 ;
; UDSn         ; RAM_DQM1H     ; 13.646 ;        ;        ; 13.646 ;
+--------------+---------------+--------+--------+--------+--------+


+------------------------------------------------------------------+
; Minimum Progagation Delay                                        ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 8.168  ; 8.168  ; 8.168  ; 8.168  ;
; ASn          ; ACSI_WRn      ; 8.249  ; 8.249  ; 8.249  ; 8.249  ;
; ASn          ; BUTTONn       ; 9.636  ;        ;        ; 9.636  ;
; ASn          ; CA1_OUT       ; 8.253  ;        ;        ; 8.253  ;
; ASn          ; CD[0]         ; 9.254  ; 8.970  ; 8.970  ; 9.254  ;
; ASn          ; CD[1]         ; 9.331  ; 9.049  ; 9.049  ; 9.331  ;
; ASn          ; CD[2]         ; 8.631  ; 8.356  ; 8.356  ; 8.631  ;
; ASn          ; CD[3]         ; 9.355  ; 9.212  ; 9.212  ; 9.355  ;
; ASn          ; CD[4]         ; 8.751  ; 8.751  ; 8.751  ; 8.751  ;
; ASn          ; CD[5]         ; 8.358  ; 8.358  ; 8.358  ; 8.358  ;
; ASn          ; CD[6]         ; 8.472  ; 8.472  ; 8.472  ; 8.472  ;
; ASn          ; CD[7]         ; 8.870  ; 8.870  ; 8.870  ; 8.870  ;
; ASn          ; DATA[0]       ; 8.762  ; 8.762  ; 8.762  ; 8.762  ;
; ASn          ; DATA[1]       ; 8.762  ; 8.762  ; 8.762  ; 8.762  ;
; ASn          ; DATA[2]       ; 8.749  ; 8.749  ; 8.749  ; 8.749  ;
; ASn          ; DATA[3]       ; 8.749  ; 8.749  ; 8.749  ; 8.749  ;
; ASn          ; DATA[4]       ; 8.736  ; 8.736  ; 8.736  ; 8.736  ;
; ASn          ; DATA[5]       ; 8.736  ; 8.736  ; 8.736  ; 8.736  ;
; ASn          ; DATA[6]       ; 8.707  ; 8.707  ; 8.707  ; 8.707  ;
; ASn          ; DATA[7]       ; 8.697  ; 8.697  ; 8.697  ; 8.697  ;
; ASn          ; DATA[8]       ; 8.745  ; 8.745  ; 8.745  ; 8.745  ;
; ASn          ; DATA[9]       ; 8.745  ; 8.745  ; 8.745  ; 8.745  ;
; ASn          ; DATA[10]      ; 8.876  ; 8.898  ; 8.898  ; 8.876  ;
; ASn          ; DATA[11]      ; 8.898  ; 8.814  ; 8.814  ; 8.898  ;
; ASn          ; DATA[12]      ; 8.765  ; 8.877  ; 8.877  ; 8.765  ;
; ASn          ; DATA[13]      ; 8.877  ; 8.877  ; 8.877  ; 8.877  ;
; ASn          ; DATA[14]      ; 8.872  ; 8.872  ; 8.872  ; 8.872  ;
; ASn          ; DATA[15]      ; 9.026  ; 9.026  ; 9.026  ; 9.026  ;
; ASn          ; DTACKn        ; 6.952  ; 6.952  ; 6.952  ; 6.952  ;
; ASn          ; FLASH_CEn     ; 8.731  ;        ;        ; 8.731  ;
; ASn          ; FLASH_OEn     ; 8.744  ;        ;        ; 8.744  ;
; ASn          ; IDE_CS0n      ; 6.702  ;        ;        ; 6.702  ;
; ASn          ; IDE_CS1n      ; 7.028  ;        ;        ; 7.028  ;
; ASn          ; IDE_D_EN_INn  ; 6.997  ;        ;        ; 6.997  ;
; ASn          ; IDE_D_EN_OUTn ; 6.835  ;        ;        ; 6.835  ;
; ASn          ; IDE_IORDn     ; 6.772  ;        ;        ; 6.772  ;
; ASn          ; IDE_IOWRn     ; 7.265  ;        ;        ; 7.265  ;
; ASn          ; JOY_RHn       ; 7.885  ;        ;        ; 7.885  ;
; ASn          ; JOY_RLn       ; 8.938  ;        ;        ; 8.938  ;
; ASn          ; JOY_WEn       ;        ; 8.789  ; 8.789  ;        ;
; ASn          ; JOY_WL        ;        ; 6.600  ; 6.600  ;        ;
; ASn          ; RAM_ADR[8]    ;        ; 8.453  ; 8.453  ;        ;
; ASn          ; RAM_BA[0]     ;        ; 7.875  ; 7.875  ;        ;
; ASn          ; RAM_BA[1]     ;        ; 7.111  ; 7.111  ;        ;
; ASn          ; RAM_CAS0n     ;        ; 7.959  ; 7.959  ;        ;
; ASn          ; RAM_CAS1n     ; 7.991  ;        ;        ; 7.991  ;
; ASn          ; RAM_DATA[0]   ; 10.112 ; 10.112 ; 10.112 ; 10.112 ;
; ASn          ; RAM_DATA[1]   ; 9.665  ; 9.665  ; 9.665  ; 9.665  ;
; ASn          ; RAM_DATA[2]   ; 9.543  ; 9.985  ; 9.985  ; 9.543  ;
; ASn          ; RAM_DATA[3]   ; 9.769  ; 10.204 ; 10.204 ; 9.769  ;
; ASn          ; RAM_DATA[4]   ; 9.352  ; 9.771  ; 9.771  ; 9.352  ;
; ASn          ; RAM_DATA[5]   ; 10.918 ; 10.918 ; 10.918 ; 10.918 ;
; ASn          ; RAM_DATA[6]   ; 9.989  ; 10.159 ; 10.159 ; 9.989  ;
; ASn          ; RAM_DATA[7]   ; 10.211 ; 10.494 ; 10.494 ; 10.211 ;
; ASn          ; RAM_DATA[8]   ; 10.661 ; 10.801 ; 10.801 ; 10.661 ;
; ASn          ; RAM_DATA[9]   ; 9.290  ; 9.723  ; 9.723  ; 9.290  ;
; ASn          ; RAM_DATA[10]  ; 9.075  ; 9.521  ; 9.521  ; 9.075  ;
; ASn          ; RAM_DATA[11]  ; 9.794  ; 9.303  ; 9.303  ; 9.794  ;
; ASn          ; RAM_DATA[12]  ; 9.284  ; 9.777  ; 9.777  ; 9.284  ;
; ASn          ; RAM_DATA[13]  ; 9.658  ; 9.694  ; 9.694  ; 9.658  ;
; ASn          ; RAM_DATA[14]  ; 9.851  ; 9.851  ; 9.851  ; 9.851  ;
; ASn          ; RAM_DATA[15]  ; 9.468  ; 9.468  ; 9.468  ; 9.468  ;
; ASn          ; RAM_DQM0H     ;        ; 8.473  ; 8.473  ;        ;
; ASn          ; RAM_DQM0L     ;        ; 8.059  ; 8.059  ;        ;
; ASn          ; RAM_DQM1H     ; 7.735  ;        ;        ; 7.735  ;
; ASn          ; RAM_DQM1L     ; 8.069  ;        ;        ; 8.069  ;
; ASn          ; RAM_RAS0n     ;        ; 8.225  ; 8.225  ;        ;
; ASn          ; RAM_RAS1n     ; 8.035  ;        ;        ; 8.035  ;
; ASn          ; ROM0n         ; 8.310  ;        ;        ; 8.310  ;
; ASn          ; ROM1n         ; 8.055  ;        ;        ; 8.055  ;
; ASn          ; ROM2n         ; 7.377  ;        ;        ; 7.377  ;
; ASn          ; ROM3n         ; 8.195  ;        ;        ; 8.195  ;
; ASn          ; ROM4n         ; 8.736  ;        ;        ; 8.736  ;
; ASn          ; ROM5n         ; 6.876  ;        ;        ; 6.876  ;
; ASn          ; ROM6n         ; 8.214  ;        ;        ; 8.214  ;
; COM_CTS      ; DATA[2]       ;        ; 9.622  ; 9.622  ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 9.828  ; 9.828  ;        ;
; COM_DCD      ; DATA[1]       ;        ; 9.709  ; 9.709  ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 9.975  ; 9.975  ;        ;
; COM_RI       ; DATA[6]       ;        ; 9.337  ; 9.337  ;        ;
; COM_RI       ; RAM_DATA[6]   ;        ; 10.399 ; 10.399 ;        ;
; CONFIG[1]    ; DATA[7]       ; 10.625 ; 10.625 ; 10.625 ; 10.625 ;
; CONFIG[1]    ; HSYNC         ; 7.064  ; 7.064  ; 7.064  ; 7.064  ;
; CONFIG[1]    ; RAM_DATA[7]   ; 11.687 ; 11.687 ; 11.687 ; 11.687 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 7.819  ; 7.819  ; 7.819  ; 7.819  ;
; CONFIG[1]    ; RAM_DATA[13]  ; 7.976  ; 7.976  ; 7.976  ; 7.976  ;
; CONFIG[1]    ; RAM_DATA[14]  ; 8.028  ; 8.028  ; 8.028  ; 8.028  ;
; CONFIG[1]    ; RAM_DATA[15]  ; 7.492  ; 7.492  ; 7.492  ; 7.492  ;
; CONFIG[1]    ; VSYNC         ; 6.943  ; 6.943  ; 6.943  ; 6.943  ;
; CONFIG[2]    ; DATA[7]       ; 10.178 ; 10.178 ; 10.178 ; 10.178 ;
; CONFIG[2]    ; HSYNC         ; 7.054  ; 7.054  ; 7.054  ; 7.054  ;
; CONFIG[2]    ; RAM_DATA[7]   ; 11.240 ; 11.240 ; 11.240 ; 11.240 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 7.914  ; 7.914  ; 7.914  ; 7.914  ;
; CONFIG[2]    ; RAM_DATA[13]  ; 8.071  ; 8.071  ; 8.071  ; 8.071  ;
; CONFIG[2]    ; RAM_DATA[14]  ; 8.123  ; 8.123  ; 8.123  ; 8.123  ;
; CONFIG[2]    ; RAM_DATA[15]  ; 7.587  ; 7.587  ; 7.587  ; 7.587  ;
; CONFIG[2]    ; VSYNC         ; 6.927  ; 6.927  ; 6.927  ; 6.927  ;
; CONFIG[3]    ; LDSn          ; 10.464 ; 10.504 ; 10.504 ; 10.464 ;
; CONFIG[3]    ; UDSn          ; 10.614 ; 10.654 ; 10.654 ; 10.614 ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 7.654  ; 7.654  ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 6.940  ; 6.940  ;        ;
; CONFIG[5]    ; ACSI_RDn      ; 10.237 ; 10.237 ; 10.237 ; 10.237 ;
; CONFIG[5]    ; ACSI_WRn      ; 10.318 ; 10.318 ; 10.318 ; 10.318 ;
; CONFIG[5]    ; BUTTONn       ; 9.607  ; 9.607  ; 9.607  ; 9.607  ;
; CONFIG[5]    ; CA1_OUT       ; 10.322 ; 10.322 ; 10.322 ; 10.322 ;
; CONFIG[5]    ; CD[0]         ; 11.039 ; 11.039 ; 11.039 ; 11.039 ;
; CONFIG[5]    ; CD[1]         ; 11.118 ; 11.118 ; 11.118 ; 11.118 ;
; CONFIG[5]    ; CD[2]         ; 10.425 ; 10.425 ; 10.425 ; 10.425 ;
; CONFIG[5]    ; CD[3]         ; 11.281 ; 11.281 ; 11.281 ; 11.281 ;
; CONFIG[5]    ; CD[4]         ; 10.820 ; 10.820 ; 10.820 ; 10.820 ;
; CONFIG[5]    ; CD[5]         ; 10.427 ; 10.427 ; 10.427 ; 10.427 ;
; CONFIG[5]    ; CD[6]         ; 10.541 ; 10.541 ; 10.541 ; 10.541 ;
; CONFIG[5]    ; CD[7]         ; 10.939 ; 10.939 ; 10.939 ; 10.939 ;
; CONFIG[5]    ; DATA[0]       ; 8.732  ; 8.732  ; 8.732  ; 8.732  ;
; CONFIG[5]    ; DATA[1]       ; 8.732  ; 8.732  ; 8.732  ; 8.732  ;
; CONFIG[5]    ; DATA[2]       ; 8.719  ; 8.719  ; 8.719  ; 8.719  ;
; CONFIG[5]    ; DATA[3]       ; 8.719  ; 8.719  ; 8.719  ; 8.719  ;
; CONFIG[5]    ; DATA[4]       ; 8.706  ; 8.706  ; 8.706  ; 8.706  ;
; CONFIG[5]    ; DATA[5]       ; 8.706  ; 8.706  ; 8.706  ; 8.706  ;
; CONFIG[5]    ; DATA[6]       ; 8.677  ; 8.677  ; 8.677  ; 8.677  ;
; CONFIG[5]    ; DATA[7]       ; 8.667  ; 8.667  ; 8.667  ; 8.667  ;
; CONFIG[5]    ; DATA[8]       ; 8.715  ; 8.715  ; 8.715  ; 8.715  ;
; CONFIG[5]    ; DATA[9]       ; 8.715  ; 8.715  ; 8.715  ; 8.715  ;
; CONFIG[5]    ; DATA[10]      ; 8.868  ; 8.868  ; 8.868  ; 8.868  ;
; CONFIG[5]    ; DATA[11]      ; 8.868  ; 8.868  ; 8.868  ; 8.868  ;
; CONFIG[5]    ; DATA[12]      ; 8.847  ; 8.847  ; 8.847  ; 8.847  ;
; CONFIG[5]    ; DATA[13]      ; 8.847  ; 8.847  ; 8.847  ; 8.847  ;
; CONFIG[5]    ; DATA[14]      ; 9.006  ; 9.006  ; 9.006  ; 9.006  ;
; CONFIG[5]    ; DATA[15]      ; 8.996  ; 8.996  ; 8.996  ; 8.996  ;
; CONFIG[5]    ; DTACKn        ; 9.021  ; 9.021  ; 9.021  ; 9.021  ;
; CONFIG[5]    ; FLASH_CEn     ; 9.587  ; 9.587  ; 9.587  ; 9.587  ;
; CONFIG[5]    ; FLASH_OEn     ; 9.600  ; 9.600  ; 9.600  ; 9.600  ;
; CONFIG[5]    ; IDE_CS0n      ; 8.646  ; 8.646  ; 8.646  ; 8.646  ;
; CONFIG[5]    ; IDE_CS1n      ; 8.972  ; 8.972  ; 8.972  ; 8.972  ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 8.727  ; 8.727  ; 8.727  ; 8.727  ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 8.779  ; 8.779  ; 8.779  ; 8.779  ;
; CONFIG[5]    ; IDE_IORDn     ; 8.802  ; 8.802  ; 8.802  ; 8.802  ;
; CONFIG[5]    ; IDE_IOWRn     ; 9.282  ; 9.282  ; 9.282  ; 9.282  ;
; CONFIG[5]    ; JOY_RHn       ; 9.546  ; 9.546  ; 9.546  ; 9.546  ;
; CONFIG[5]    ; JOY_RLn       ; 10.599 ; 10.599 ; 10.599 ; 10.599 ;
; CONFIG[5]    ; JOY_WEn       ; 10.450 ; 10.450 ; 10.450 ; 10.450 ;
; CONFIG[5]    ; JOY_WL        ; 8.978  ; 8.978  ; 8.978  ; 8.978  ;
; CONFIG[5]    ; RAM_ADR[8]    ; 9.221  ; 8.404  ; 8.404  ; 9.221  ;
; CONFIG[5]    ; RAM_BA[0]     ; 8.643  ; 7.826  ; 7.826  ; 8.643  ;
; CONFIG[5]    ; RAM_BA[1]     ; 7.776  ; 7.062  ; 7.062  ; 7.776  ;
; CONFIG[5]    ; RAM_CAS0n     ; 8.578  ; 7.910  ; 7.910  ; 8.578  ;
; CONFIG[5]    ; RAM_CAS1n     ; 7.942  ; 8.610  ; 8.610  ; 7.942  ;
; CONFIG[5]    ; RAM_DATA[0]   ; 10.998 ; 10.998 ; 10.998 ; 10.998 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 10.812 ; 10.812 ; 10.812 ; 10.812 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 10.763 ; 10.763 ; 10.763 ; 10.763 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 11.347 ; 11.347 ; 11.347 ; 11.347 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 10.626 ; 10.626 ; 10.626 ; 10.626 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 11.538 ; 11.538 ; 11.538 ; 11.538 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 11.316 ; 11.316 ; 11.316 ; 11.316 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 11.861 ; 11.861 ; 11.861 ; 11.861 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 11.752 ; 11.752 ; 11.752 ; 11.752 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 11.077 ; 11.077 ; 11.077 ; 11.077 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 10.680 ; 10.680 ; 10.680 ; 10.680 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 10.921 ; 10.921 ; 10.921 ; 10.921 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 11.032 ; 11.032 ; 11.032 ; 11.032 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 11.404 ; 11.404 ; 11.404 ; 11.404 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 11.716 ; 11.716 ; 11.716 ; 11.716 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 11.101 ; 11.101 ; 11.101 ; 11.101 ;
; CONFIG[5]    ; RAM_DQM0H     ; 9.092  ; 8.424  ; 8.424  ; 9.092  ;
; CONFIG[5]    ; RAM_DQM0L     ; 8.678  ; 8.010  ; 8.010  ; 8.678  ;
; CONFIG[5]    ; RAM_DQM1H     ; 7.686  ; 8.354  ; 8.354  ; 7.686  ;
; CONFIG[5]    ; RAM_DQM1L     ; 8.020  ; 8.688  ; 8.688  ; 8.020  ;
; CONFIG[5]    ; RAM_RAS0n     ; 8.844  ; 8.176  ; 8.176  ; 8.844  ;
; CONFIG[5]    ; RAM_RAS1n     ; 7.986  ; 8.654  ; 8.654  ; 7.986  ;
; CONFIG[5]    ; ROM0n         ; 8.506  ; 8.506  ; 8.506  ; 8.506  ;
; CONFIG[5]    ; ROM1n         ; 8.259  ; 8.137  ; 8.137  ; 8.259  ;
; CONFIG[5]    ; ROM2n         ; 8.233  ; 8.233  ; 8.233  ; 8.233  ;
; CONFIG[5]    ; ROM3n         ; 8.936  ; 8.914  ; 8.914  ; 8.936  ;
; CONFIG[5]    ; ROM4n         ; 9.079  ; 9.101  ; 9.101  ; 9.079  ;
; CONFIG[5]    ; ROM5n         ; 8.349  ; 8.349  ; 8.349  ; 8.349  ;
; CONFIG[5]    ; ROM6n         ; 8.826  ; 8.804  ; 8.804  ; 8.826  ;
; CONFIG[6]    ; DATA[0]       ; 10.893 ; 10.893 ; 10.893 ; 10.893 ;
; CONFIG[6]    ; DATA[1]       ; 10.384 ; 10.384 ; 10.384 ; 10.384 ;
; CONFIG[6]    ; DATA[2]       ; 10.893 ; 10.893 ; 10.893 ; 10.893 ;
; CONFIG[6]    ; DATA[3]       ; 10.739 ; 10.739 ; 10.739 ; 10.739 ;
; CONFIG[6]    ; DATA[4]       ; 10.770 ; 10.770 ; 10.770 ; 10.770 ;
; CONFIG[6]    ; DATA[5]       ; 11.272 ; 11.272 ; 11.272 ; 11.272 ;
; CONFIG[6]    ; DATA[6]       ; 10.678 ; 10.678 ; 10.678 ; 10.678 ;
; CONFIG[6]    ; DATA[7]       ; 10.000 ; 10.000 ; 10.000 ; 10.000 ;
; CONFIG[6]    ; DATA[8]       ; 10.939 ; 10.939 ; 10.939 ; 10.939 ;
; CONFIG[6]    ; DATA[9]       ; 10.850 ; 10.850 ; 10.850 ; 10.850 ;
; CONFIG[6]    ; DATA[10]      ; 10.387 ; 10.387 ; 10.387 ; 10.387 ;
; CONFIG[6]    ; DATA[11]      ; 10.722 ; 10.722 ; 10.722 ; 10.722 ;
; CONFIG[6]    ; DATA[12]      ; 10.222 ; 10.222 ; 10.222 ; 10.222 ;
; CONFIG[6]    ; DATA[13]      ; 10.665 ; 10.665 ; 10.665 ; 10.665 ;
; CONFIG[6]    ; DATA[14]      ; 9.744  ; 9.744  ; 9.744  ; 9.744  ;
; CONFIG[6]    ; DATA[15]      ; 10.107 ; 10.107 ; 10.107 ; 10.107 ;
; CONFIG[6]    ; DTACKn        ; 8.630  ; 8.630  ; 8.630  ; 8.630  ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 7.379  ; 7.379  ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 7.219  ; 7.219  ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 8.534  ; 8.534  ; 8.534  ; 8.534  ;
; CONFIG[6]    ; FLASH_OEn     ; 8.547  ; 8.547  ; 8.547  ; 8.547  ;
; CONFIG[6]    ; RAM_DATA[0]   ; 11.645 ; 11.645 ; 11.645 ; 11.645 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 10.650 ; 10.650 ; 10.650 ; 10.650 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 11.099 ; 11.099 ; 11.099 ; 11.099 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 10.730 ; 10.730 ; 10.730 ; 10.730 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 10.575 ; 10.575 ; 10.575 ; 10.575 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 12.371 ; 12.371 ; 12.371 ; 12.371 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 11.740 ; 11.740 ; 11.740 ; 11.740 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 11.062 ; 11.062 ; 11.062 ; 11.062 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 11.817 ; 11.817 ; 11.817 ; 11.817 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 11.013 ; 11.013 ; 11.013 ; 11.013 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 10.586 ; 10.586 ; 10.586 ; 10.586 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 11.211 ; 11.211 ; 11.211 ; 11.211 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 10.741 ; 10.741 ; 10.741 ; 10.741 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 10.858 ; 10.858 ; 10.858 ; 10.858 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 10.723 ; 10.723 ; 10.723 ; 10.723 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 10.340 ; 10.340 ; 10.340 ; 10.340 ;
; CONFIG[6]    ; ROM2n         ; 7.180  ; 7.180  ; 7.180  ; 7.180  ;
; CRT_PIN3     ; DATA[7]       ; 7.794  ; 7.794  ; 7.794  ; 7.794  ;
; CRT_PIN3     ; RAM_DATA[7]   ; 8.856  ; 8.856  ; 8.856  ; 8.856  ;
; CRT_PIN3     ; RAM_DATA[12]  ; 5.169  ; 5.169  ; 5.169  ; 5.169  ;
; CRT_PIN3     ; RAM_DATA[13]  ; 5.326  ; 5.326  ; 5.326  ; 5.326  ;
; CRT_PIN3     ; RAM_DATA[14]  ; 5.378  ; 5.378  ; 5.378  ; 5.378  ;
; CRT_PIN3     ; RAM_DATA[15]  ; 4.842  ; 4.842  ; 4.842  ; 4.842  ;
; DATA[0]      ; DATA[0]       ; 7.216  ;        ;        ; 7.216  ;
; DATA[0]      ; RAM_DATA[0]   ; 7.968  ;        ;        ; 7.968  ;
; DATA[1]      ; DATA[1]       ; 7.819  ;        ;        ; 7.819  ;
; DATA[1]      ; RAM_DATA[1]   ; 8.085  ;        ;        ; 8.085  ;
; DATA[2]      ; DATA[2]       ; 7.325  ;        ;        ; 7.325  ;
; DATA[2]      ; RAM_DATA[2]   ; 7.531  ;        ;        ; 7.531  ;
; DATA[3]      ; DATA[3]       ; 7.976  ;        ;        ; 7.976  ;
; DATA[3]      ; RAM_DATA[3]   ; 7.967  ;        ;        ; 7.967  ;
; DATA[4]      ; DATA[4]       ; 7.874  ;        ;        ; 7.874  ;
; DATA[4]      ; RAM_DATA[4]   ; 7.679  ;        ;        ; 7.679  ;
; DATA[5]      ; DATA[5]       ; 8.047  ;        ;        ; 8.047  ;
; DATA[5]      ; RAM_DATA[5]   ; 9.146  ;        ;        ; 9.146  ;
; DATA[6]      ; DATA[6]       ; 7.751  ;        ;        ; 7.751  ;
; DATA[6]      ; RAM_DATA[6]   ; 8.813  ;        ;        ; 8.813  ;
; DATA[7]      ; DATA[7]       ; 8.412  ;        ;        ; 8.412  ;
; DATA[7]      ; RAM_DATA[7]   ; 9.474  ;        ;        ; 9.474  ;
; DATA[8]      ; DATA[8]       ; 7.911  ;        ;        ; 7.911  ;
; DATA[8]      ; RAM_DATA[8]   ; 8.789  ;        ;        ; 8.789  ;
; DATA[9]      ; DATA[9]       ; 7.495  ;        ;        ; 7.495  ;
; DATA[9]      ; RAM_DATA[9]   ; 7.658  ;        ;        ; 7.658  ;
; DATA[10]     ; DATA[10]      ; 6.988  ;        ;        ; 6.988  ;
; DATA[10]     ; RAM_DATA[10]  ; 7.187  ;        ;        ; 7.187  ;
; DATA[11]     ; DATA[11]      ; 7.704  ;        ;        ; 7.704  ;
; DATA[11]     ; RAM_DATA[11]  ; 8.193  ;        ;        ; 8.193  ;
; DATA[12]     ; DATA[12]      ; 7.903  ;        ;        ; 7.903  ;
; DATA[12]     ; RAM_DATA[12]  ; 8.422  ;        ;        ; 8.422  ;
; DATA[13]     ; DATA[13]      ; 7.910  ;        ;        ; 7.910  ;
; DATA[13]     ; RAM_DATA[13]  ; 8.103  ;        ;        ; 8.103  ;
; DATA[14]     ; DATA[14]      ; 7.384  ;        ;        ; 7.384  ;
; DATA[14]     ; RAM_DATA[14]  ; 8.363  ;        ;        ; 8.363  ;
; DATA[15]     ; DATA[15]      ; 8.298  ;        ;        ; 8.298  ;
; DATA[15]     ; RAM_DATA[15]  ; 8.531  ;        ;        ; 8.531  ;
; FC[0]        ; ACSI_RDn      ; 9.488  ; 9.488  ; 9.488  ; 9.488  ;
; FC[0]        ; ACSI_WRn      ; 9.569  ; 9.569  ; 9.569  ; 9.569  ;
; FC[0]        ; BUTTONn       ; 8.705  ; 8.705  ; 8.705  ; 8.705  ;
; FC[0]        ; CA1_OUT       ; 9.573  ; 9.573  ; 9.573  ; 9.573  ;
; FC[0]        ; CD[0]         ; 10.290 ; 10.290 ; 10.290 ; 10.290 ;
; FC[0]        ; CD[1]         ; 10.369 ; 10.369 ; 10.369 ; 10.369 ;
; FC[0]        ; CD[2]         ; 9.676  ; 9.676  ; 9.676  ; 9.676  ;
; FC[0]        ; CD[3]         ; 10.532 ; 10.532 ; 10.532 ; 10.532 ;
; FC[0]        ; CD[4]         ; 10.071 ; 10.071 ; 10.071 ; 10.071 ;
; FC[0]        ; CD[5]         ; 9.678  ; 9.678  ; 9.678  ; 9.678  ;
; FC[0]        ; CD[6]         ; 9.792  ; 9.792  ; 9.792  ; 9.792  ;
; FC[0]        ; CD[7]         ; 10.190 ; 10.190 ; 10.190 ; 10.190 ;
; FC[0]        ; DATA[0]       ; 9.026  ; 9.026  ; 9.026  ; 9.026  ;
; FC[0]        ; DATA[1]       ; 8.757  ; 8.757  ; 8.757  ; 8.757  ;
; FC[0]        ; DATA[2]       ; 8.638  ; 8.638  ; 8.638  ; 8.638  ;
; FC[0]        ; DATA[3]       ; 9.079  ; 9.079  ; 9.079  ; 9.079  ;
; FC[0]        ; DATA[4]       ; 8.848  ; 8.848  ; 8.848  ; 8.848  ;
; FC[0]        ; DATA[5]       ; 10.167 ; 10.167 ; 10.167 ; 10.167 ;
; FC[0]        ; DATA[6]       ; 8.228  ; 8.228  ; 8.228  ; 8.228  ;
; FC[0]        ; DATA[7]       ; 8.450  ; 8.450  ; 8.450  ; 8.450  ;
; FC[0]        ; DATA[8]       ; 9.159  ; 9.159  ; 9.159  ; 9.159  ;
; FC[0]        ; DATA[9]       ; 8.428  ; 8.428  ; 8.428  ; 8.428  ;
; FC[0]        ; DATA[10]      ; 8.177  ; 8.177  ; 8.177  ; 8.177  ;
; FC[0]        ; DATA[11]      ; 8.606  ; 8.606  ; 8.606  ; 8.606  ;
; FC[0]        ; DATA[12]      ; 8.066  ; 8.066  ; 8.066  ; 8.066  ;
; FC[0]        ; DATA[13]      ; 8.766  ; 8.766  ; 8.766  ; 8.766  ;
; FC[0]        ; DATA[14]      ; 8.528  ; 8.528  ; 8.528  ; 8.528  ;
; FC[0]        ; DATA[15]      ; 8.490  ; 8.490  ; 8.490  ; 8.490  ;
; FC[0]        ; DTACKn        ; 7.281  ; 7.281  ; 7.281  ; 7.281  ;
; FC[0]        ; FLASH_CEn     ; 8.676  ; 8.676  ; 8.676  ; 8.676  ;
; FC[0]        ; FLASH_OEn     ; 8.689  ; 8.689  ; 8.689  ; 8.689  ;
; FC[0]        ; JOY_RHn       ; 9.710  ; 9.710  ; 9.710  ; 9.710  ;
; FC[0]        ; JOY_RLn       ; 10.763 ; 10.763 ; 10.763 ; 10.763 ;
; FC[0]        ; JOY_WEn       ; 10.614 ; 10.614 ; 10.614 ; 10.614 ;
; FC[0]        ; JOY_WL        ; 8.425  ; 8.425  ; 8.425  ; 8.425  ;
; FC[0]        ; RAM_ADR[8]    ; 8.399  ; 8.399  ; 8.399  ; 8.399  ;
; FC[0]        ; RAM_BA[0]     ; 7.821  ; 7.821  ; 7.821  ; 7.821  ;
; FC[0]        ; RAM_BA[1]     ; 7.057  ; 7.057  ; 7.057  ; 7.057  ;
; FC[0]        ; RAM_CAS0n     ; 7.905  ; 7.905  ; 7.905  ; 7.905  ;
; FC[0]        ; RAM_CAS1n     ; 7.937  ; 7.937  ; 7.937  ; 7.937  ;
; FC[0]        ; RAM_DATA[0]   ; 9.778  ; 9.778  ; 9.778  ; 9.778  ;
; FC[0]        ; RAM_DATA[1]   ; 9.023  ; 9.023  ; 9.023  ; 9.023  ;
; FC[0]        ; RAM_DATA[2]   ; 8.844  ; 8.844  ; 8.844  ; 8.844  ;
; FC[0]        ; RAM_DATA[3]   ; 9.070  ; 9.070  ; 9.070  ; 9.070  ;
; FC[0]        ; RAM_DATA[4]   ; 8.653  ; 8.653  ; 8.653  ; 8.653  ;
; FC[0]        ; RAM_DATA[5]   ; 11.266 ; 11.266 ; 11.266 ; 11.266 ;
; FC[0]        ; RAM_DATA[6]   ; 9.290  ; 9.290  ; 9.290  ; 9.290  ;
; FC[0]        ; RAM_DATA[7]   ; 9.512  ; 9.512  ; 9.512  ; 9.512  ;
; FC[0]        ; RAM_DATA[8]   ; 10.037 ; 10.037 ; 10.037 ; 10.037 ;
; FC[0]        ; RAM_DATA[9]   ; 8.591  ; 8.591  ; 8.591  ; 8.591  ;
; FC[0]        ; RAM_DATA[10]  ; 8.376  ; 8.376  ; 8.376  ; 8.376  ;
; FC[0]        ; RAM_DATA[11]  ; 9.095  ; 9.095  ; 9.095  ; 9.095  ;
; FC[0]        ; RAM_DATA[12]  ; 8.585  ; 8.585  ; 8.585  ; 8.585  ;
; FC[0]        ; RAM_DATA[13]  ; 8.959  ; 8.959  ; 8.959  ; 8.959  ;
; FC[0]        ; RAM_DATA[14]  ; 9.507  ; 9.507  ; 9.507  ; 9.507  ;
; FC[0]        ; RAM_DATA[15]  ; 8.723  ; 8.723  ; 8.723  ; 8.723  ;
; FC[0]        ; RAM_DQM0H     ; 8.419  ; 8.419  ; 8.419  ; 8.419  ;
; FC[0]        ; RAM_DQM0L     ; 8.005  ; 8.005  ; 8.005  ; 8.005  ;
; FC[0]        ; RAM_DQM1H     ; 7.681  ; 7.681  ; 7.681  ; 7.681  ;
; FC[0]        ; RAM_DQM1L     ; 8.015  ; 8.015  ; 8.015  ; 8.015  ;
; FC[0]        ; RAM_RAS0n     ; 8.171  ; 8.171  ; 8.171  ; 8.171  ;
; FC[0]        ; RAM_RAS1n     ; 7.981  ; 7.981  ; 7.981  ; 7.981  ;
; FC[0]        ; ROM0n         ; 8.255  ; 8.255  ; 8.255  ; 8.255  ;
; FC[0]        ; ROM1n         ; 8.000  ; 8.000  ; 8.000  ; 8.000  ;
; FC[0]        ; ROM2n         ; 7.322  ; 7.322  ; 7.322  ; 7.322  ;
; FC[0]        ; ROM3n         ; 8.140  ; 8.140  ; 8.140  ; 8.140  ;
; FC[0]        ; ROM4n         ; 8.681  ; 8.681  ; 8.681  ; 8.681  ;
; FC[0]        ; ROM5n         ; 6.821  ; 6.821  ; 6.821  ; 6.821  ;
; FC[0]        ; ROM6n         ; 8.159  ; 8.159  ; 8.159  ; 8.159  ;
; FC[1]        ; ACSI_RDn      ; 9.320  ; 9.320  ; 9.320  ; 9.320  ;
; FC[1]        ; ACSI_WRn      ; 9.401  ; 9.401  ; 9.401  ; 9.401  ;
; FC[1]        ; BUTTONn       ; 8.535  ; 8.535  ; 8.535  ; 8.535  ;
; FC[1]        ; CA1_OUT       ; 9.405  ; 9.405  ; 9.405  ; 9.405  ;
; FC[1]        ; CD[0]         ; 10.122 ; 10.122 ; 10.122 ; 10.122 ;
; FC[1]        ; CD[1]         ; 10.201 ; 10.201 ; 10.201 ; 10.201 ;
; FC[1]        ; CD[2]         ; 9.508  ; 9.508  ; 9.508  ; 9.508  ;
; FC[1]        ; CD[3]         ; 10.364 ; 10.364 ; 10.364 ; 10.364 ;
; FC[1]        ; CD[4]         ; 9.903  ; 9.903  ; 9.903  ; 9.903  ;
; FC[1]        ; CD[5]         ; 9.510  ; 9.510  ; 9.510  ; 9.510  ;
; FC[1]        ; CD[6]         ; 9.624  ; 9.624  ; 9.624  ; 9.624  ;
; FC[1]        ; CD[7]         ; 10.022 ; 10.022 ; 10.022 ; 10.022 ;
; FC[1]        ; DATA[0]       ; 9.031  ; 9.031  ; 9.031  ; 9.031  ;
; FC[1]        ; DATA[1]       ; 8.762  ; 8.762  ; 8.762  ; 8.762  ;
; FC[1]        ; DATA[2]       ; 8.643  ; 8.643  ; 8.643  ; 8.643  ;
; FC[1]        ; DATA[3]       ; 9.084  ; 9.084  ; 9.084  ; 9.084  ;
; FC[1]        ; DATA[4]       ; 8.853  ; 8.853  ; 8.853  ; 8.853  ;
; FC[1]        ; DATA[5]       ; 9.997  ; 9.997  ; 9.997  ; 9.997  ;
; FC[1]        ; DATA[6]       ; 8.233  ; 8.233  ; 8.233  ; 8.233  ;
; FC[1]        ; DATA[7]       ; 8.455  ; 8.455  ; 8.455  ; 8.455  ;
; FC[1]        ; DATA[8]       ; 9.164  ; 9.164  ; 9.164  ; 9.164  ;
; FC[1]        ; DATA[9]       ; 8.433  ; 8.433  ; 8.433  ; 8.433  ;
; FC[1]        ; DATA[10]      ; 8.182  ; 8.182  ; 8.182  ; 8.182  ;
; FC[1]        ; DATA[11]      ; 8.611  ; 8.611  ; 8.611  ; 8.611  ;
; FC[1]        ; DATA[12]      ; 8.071  ; 8.071  ; 8.071  ; 8.071  ;
; FC[1]        ; DATA[13]      ; 8.771  ; 8.771  ; 8.771  ; 8.771  ;
; FC[1]        ; DATA[14]      ; 8.533  ; 8.533  ; 8.533  ; 8.533  ;
; FC[1]        ; DATA[15]      ; 8.495  ; 8.495  ; 8.495  ; 8.495  ;
; FC[1]        ; DTACKn        ; 7.111  ; 7.111  ; 7.111  ; 7.111  ;
; FC[1]        ; FLASH_CEn     ; 8.498  ; 8.498  ; 8.498  ; 8.498  ;
; FC[1]        ; FLASH_OEn     ; 8.511  ; 8.511  ; 8.511  ; 8.511  ;
; FC[1]        ; JOY_RHn       ; 9.542  ; 9.542  ; 9.542  ; 9.542  ;
; FC[1]        ; JOY_RLn       ; 10.595 ; 10.595 ; 10.595 ; 10.595 ;
; FC[1]        ; JOY_WEn       ; 10.446 ; 10.446 ; 10.446 ; 10.446 ;
; FC[1]        ; JOY_WL        ; 8.257  ; 8.257  ; 8.257  ; 8.257  ;
; FC[1]        ; RAM_ADR[8]    ; 8.232  ; 8.232  ; 8.232  ; 8.232  ;
; FC[1]        ; RAM_BA[0]     ; 7.654  ; 7.654  ; 7.654  ; 7.654  ;
; FC[1]        ; RAM_BA[1]     ; 6.890  ; 6.890  ; 6.890  ; 6.890  ;
; FC[1]        ; RAM_CAS0n     ; 7.738  ; 7.738  ; 7.738  ; 7.738  ;
; FC[1]        ; RAM_CAS1n     ; 7.770  ; 7.770  ; 7.770  ; 7.770  ;
; FC[1]        ; RAM_DATA[0]   ; 9.783  ; 9.783  ; 9.783  ; 9.783  ;
; FC[1]        ; RAM_DATA[1]   ; 9.028  ; 9.028  ; 9.028  ; 9.028  ;
; FC[1]        ; RAM_DATA[2]   ; 8.849  ; 8.849  ; 8.849  ; 8.849  ;
; FC[1]        ; RAM_DATA[3]   ; 9.075  ; 9.075  ; 9.075  ; 9.075  ;
; FC[1]        ; RAM_DATA[4]   ; 8.658  ; 8.658  ; 8.658  ; 8.658  ;
; FC[1]        ; RAM_DATA[5]   ; 11.096 ; 11.096 ; 11.096 ; 11.096 ;
; FC[1]        ; RAM_DATA[6]   ; 9.295  ; 9.295  ; 9.295  ; 9.295  ;
; FC[1]        ; RAM_DATA[7]   ; 9.517  ; 9.517  ; 9.517  ; 9.517  ;
; FC[1]        ; RAM_DATA[8]   ; 10.042 ; 10.042 ; 10.042 ; 10.042 ;
; FC[1]        ; RAM_DATA[9]   ; 8.596  ; 8.596  ; 8.596  ; 8.596  ;
; FC[1]        ; RAM_DATA[10]  ; 8.381  ; 8.381  ; 8.381  ; 8.381  ;
; FC[1]        ; RAM_DATA[11]  ; 9.100  ; 9.100  ; 9.100  ; 9.100  ;
; FC[1]        ; RAM_DATA[12]  ; 8.590  ; 8.590  ; 8.590  ; 8.590  ;
; FC[1]        ; RAM_DATA[13]  ; 8.964  ; 8.964  ; 8.964  ; 8.964  ;
; FC[1]        ; RAM_DATA[14]  ; 9.512  ; 9.512  ; 9.512  ; 9.512  ;
; FC[1]        ; RAM_DATA[15]  ; 8.728  ; 8.728  ; 8.728  ; 8.728  ;
; FC[1]        ; RAM_DQM0H     ; 8.252  ; 8.252  ; 8.252  ; 8.252  ;
; FC[1]        ; RAM_DQM0L     ; 7.838  ; 7.838  ; 7.838  ; 7.838  ;
; FC[1]        ; RAM_DQM1H     ; 7.514  ; 7.514  ; 7.514  ; 7.514  ;
; FC[1]        ; RAM_DQM1L     ; 7.848  ; 7.848  ; 7.848  ; 7.848  ;
; FC[1]        ; RAM_RAS0n     ; 8.004  ; 8.004  ; 8.004  ; 8.004  ;
; FC[1]        ; RAM_RAS1n     ; 7.814  ; 7.814  ; 7.814  ; 7.814  ;
; FC[1]        ; ROM0n         ; 8.077  ; 8.077  ; 8.077  ; 8.077  ;
; FC[1]        ; ROM1n         ; 7.822  ; 7.822  ; 7.822  ; 7.822  ;
; FC[1]        ; ROM2n         ; 7.144  ; 7.144  ; 7.144  ; 7.144  ;
; FC[1]        ; ROM3n         ; 7.962  ; 7.962  ; 7.962  ; 7.962  ;
; FC[1]        ; ROM4n         ; 8.503  ; 8.503  ; 8.503  ; 8.503  ;
; FC[1]        ; ROM5n         ; 6.643  ; 6.643  ; 6.643  ; 6.643  ;
; FC[1]        ; ROM6n         ; 7.981  ; 7.981  ; 7.981  ; 7.981  ;
; FC[2]        ; ACSI_RDn      ; 9.303  ; 9.303  ; 9.303  ; 9.303  ;
; FC[2]        ; ACSI_WRn      ; 9.384  ; 9.384  ; 9.384  ; 9.384  ;
; FC[2]        ; CA1_OUT       ;        ; 9.388  ; 9.388  ;        ;
; FC[2]        ; CD[0]         ; 10.105 ; 10.389 ; 10.389 ; 10.105 ;
; FC[2]        ; CD[1]         ; 10.184 ; 10.466 ; 10.466 ; 10.184 ;
; FC[2]        ; CD[2]         ; 9.491  ; 9.766  ; 9.766  ; 9.491  ;
; FC[2]        ; CD[3]         ; 10.347 ; 10.490 ; 10.490 ; 10.347 ;
; FC[2]        ; CD[4]         ; 9.886  ; 9.886  ; 9.886  ; 9.886  ;
; FC[2]        ; CD[5]         ; 9.493  ; 9.493  ; 9.493  ; 9.493  ;
; FC[2]        ; CD[6]         ; 9.607  ; 9.607  ; 9.607  ; 9.607  ;
; FC[2]        ; CD[7]         ; 10.005 ; 10.005 ; 10.005 ; 10.005 ;
; FC[2]        ; DATA[0]       ; 9.967  ; 9.967  ; 9.967  ; 9.967  ;
; FC[2]        ; DATA[1]       ; 10.006 ; 10.006 ; 10.006 ; 10.006 ;
; FC[2]        ; DATA[2]       ; 10.728 ; 10.195 ; 10.195 ; 10.728 ;
; FC[2]        ; DATA[3]       ; 11.369 ; 10.636 ; 10.636 ; 11.369 ;
; FC[2]        ; DATA[4]       ; 11.086 ; 10.405 ; 10.405 ; 11.086 ;
; FC[2]        ; DATA[5]       ; 10.880 ; 10.535 ; 10.535 ; 10.880 ;
; FC[2]        ; DATA[6]       ; 10.158 ; 9.635  ; 9.635  ; 10.158 ;
; FC[2]        ; DATA[7]       ; 10.463 ; 10.007 ; 10.007 ; 10.463 ;
; FC[2]        ; DATA[8]       ; 11.514 ; 10.557 ; 10.557 ; 11.514 ;
; FC[2]        ; DATA[9]       ; 11.151 ; 9.985  ; 9.985  ; 11.151 ;
; FC[2]        ; DATA[10]      ; 10.622 ; 9.734  ; 9.734  ; 10.622 ;
; FC[2]        ; DATA[11]      ; 10.935 ; 10.081 ; 10.081 ; 10.935 ;
; FC[2]        ; DATA[12]      ; 10.849 ; 9.623  ; 9.623  ; 10.849 ;
; FC[2]        ; DATA[13]      ; 11.092 ; 10.323 ; 10.323 ; 11.092 ;
; FC[2]        ; DATA[14]      ; 9.766  ; 9.766  ; 9.766  ; 9.766  ;
; FC[2]        ; DATA[15]      ; 10.022 ; 10.022 ; 10.022 ; 10.022 ;
; FC[2]        ; DTACKn        ; 8.014  ; 8.014  ; 8.014  ; 8.014  ;
; FC[2]        ; JOY_RHn       ;        ; 9.525  ; 9.525  ;        ;
; FC[2]        ; JOY_RLn       ;        ; 10.578 ; 10.578 ;        ;
; FC[2]        ; JOY_WEn       ; 10.429 ;        ;        ; 10.429 ;
; FC[2]        ; JOY_WL        ; 8.240  ;        ;        ; 8.240  ;
; FC[2]        ; RAM_DATA[0]   ; 10.719 ; 10.719 ; 10.719 ; 10.719 ;
; FC[2]        ; RAM_DATA[1]   ; 10.272 ; 10.272 ; 10.272 ; 10.272 ;
; FC[2]        ; RAM_DATA[2]   ; 10.934 ; 10.401 ; 10.401 ; 10.934 ;
; FC[2]        ; RAM_DATA[3]   ; 11.360 ; 10.627 ; 10.627 ; 11.360 ;
; FC[2]        ; RAM_DATA[4]   ; 10.891 ; 10.210 ; 10.210 ; 10.891 ;
; FC[2]        ; RAM_DATA[5]   ; 11.979 ; 11.634 ; 11.634 ; 11.979 ;
; FC[2]        ; RAM_DATA[6]   ; 11.220 ; 10.697 ; 10.697 ; 11.220 ;
; FC[2]        ; RAM_DATA[7]   ; 11.525 ; 11.069 ; 11.069 ; 11.525 ;
; FC[2]        ; RAM_DATA[8]   ; 12.392 ; 11.435 ; 11.435 ; 12.392 ;
; FC[2]        ; RAM_DATA[9]   ; 11.314 ; 10.148 ; 10.148 ; 11.314 ;
; FC[2]        ; RAM_DATA[10]  ; 10.821 ; 9.933  ; 9.933  ; 10.821 ;
; FC[2]        ; RAM_DATA[11]  ; 11.424 ; 10.570 ; 10.570 ; 11.424 ;
; FC[2]        ; RAM_DATA[12]  ; 11.368 ; 10.142 ; 10.142 ; 11.368 ;
; FC[2]        ; RAM_DATA[13]  ; 11.285 ; 10.516 ; 10.516 ; 11.285 ;
; FC[2]        ; RAM_DATA[14]  ; 10.745 ; 10.745 ; 10.745 ; 10.745 ;
; FC[2]        ; RAM_DATA[15]  ; 10.255 ; 10.255 ; 10.255 ; 10.255 ;
; HDINTn       ; DATA[5]       ; 11.773 ;        ;        ; 11.773 ;
; HDINTn       ; RAM_DATA[5]   ; 12.872 ;        ;        ; 12.872 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 11.708 ; 11.708 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 12.807 ; 12.807 ;        ;
; IDE_IORDY    ; DTACKn        ; 7.994  ; 7.994  ; 7.994  ; 7.994  ;
; LDSn         ; ACSI_RDn      ; 8.612  ; 8.612  ; 8.612  ; 8.612  ;
; LDSn         ; ACSI_WRn      ; 8.693  ; 8.693  ; 8.693  ; 8.693  ;
; LDSn         ; BUTTONn       ; 9.948  ;        ;        ; 9.948  ;
; LDSn         ; CA1_OUT       ; 8.697  ;        ;        ; 8.697  ;
; LDSn         ; CD[0]         ; 9.698  ; 9.414  ; 9.414  ; 9.698  ;
; LDSn         ; CD[1]         ; 9.775  ; 9.493  ; 9.493  ; 9.775  ;
; LDSn         ; CD[2]         ; 9.075  ; 8.800  ; 8.800  ; 9.075  ;
; LDSn         ; CD[3]         ; 9.799  ; 9.656  ; 9.656  ; 9.799  ;
; LDSn         ; CD[4]         ; 9.195  ; 9.195  ; 9.195  ; 9.195  ;
; LDSn         ; CD[5]         ; 8.802  ; 8.802  ; 8.802  ; 8.802  ;
; LDSn         ; CD[6]         ; 8.916  ; 8.916  ; 8.916  ; 8.916  ;
; LDSn         ; CD[7]         ; 9.314  ; 9.314  ; 9.314  ; 9.314  ;
; LDSn         ; DATA[0]       ; 9.089  ; 9.089  ; 9.089  ; 9.089  ;
; LDSn         ; DATA[1]       ; 9.089  ; 9.089  ; 9.089  ; 9.089  ;
; LDSn         ; DATA[2]       ; 9.076  ; 9.076  ; 9.076  ; 9.076  ;
; LDSn         ; DATA[3]       ; 9.076  ; 9.076  ; 9.076  ; 9.076  ;
; LDSn         ; DATA[4]       ; 9.063  ; 9.063  ; 9.063  ; 9.063  ;
; LDSn         ; DATA[5]       ; 9.063  ; 9.063  ; 9.063  ; 9.063  ;
; LDSn         ; DATA[6]       ; 9.034  ; 9.034  ; 9.034  ; 9.034  ;
; LDSn         ; DATA[7]       ; 9.024  ; 9.024  ; 9.024  ; 9.024  ;
; LDSn         ; DATA[8]       ; 9.072  ; 9.072  ; 9.072  ; 9.072  ;
; LDSn         ; DATA[9]       ; 9.072  ; 9.072  ; 9.072  ; 9.072  ;
; LDSn         ; DATA[10]      ; 9.225  ; 9.225  ; 9.225  ; 9.225  ;
; LDSn         ; DATA[11]      ; 9.225  ; 9.141  ; 9.141  ; 9.225  ;
; LDSn         ; DATA[12]      ; 9.204  ; 9.204  ; 9.204  ; 9.204  ;
; LDSn         ; DATA[13]      ; 9.204  ; 9.204  ; 9.204  ; 9.204  ;
; LDSn         ; DATA[14]      ; 9.363  ; 9.363  ; 9.363  ; 9.363  ;
; LDSn         ; DATA[15]      ; 9.353  ; 9.353  ; 9.353  ; 9.353  ;
; LDSn         ; DTACKn        ; 7.396  ; 7.396  ; 7.396  ; 7.396  ;
; LDSn         ; IDE_IORDn     ; 6.550  ;        ;        ; 6.550  ;
; LDSn         ; IDE_IOWRn     ; 7.033  ;        ;        ; 7.033  ;
; LDSn         ; JOY_RLn       ; 8.347  ;        ;        ; 8.347  ;
; LDSn         ; JOY_WEn       ;        ; 8.198  ; 8.198  ;        ;
; LDSn         ; JOY_WL        ;        ; 7.193  ; 7.193  ;        ;
; LDSn         ; RAM_CAS0n     ; 7.109  ;        ;        ; 7.109  ;
; LDSn         ; RAM_CAS1n     ; 7.129  ;        ;        ; 7.129  ;
; LDSn         ; RAM_DATA[0]   ; 10.291 ; 10.579 ; 10.579 ; 10.291 ;
; LDSn         ; RAM_DATA[1]   ; 10.019 ; 10.314 ; 10.314 ; 10.019 ;
; LDSn         ; RAM_DATA[2]   ; 10.209 ; 10.312 ; 10.312 ; 10.209 ;
; LDSn         ; RAM_DATA[3]   ; 10.473 ; 10.531 ; 10.531 ; 10.473 ;
; LDSn         ; RAM_DATA[4]   ; 10.098 ; 10.098 ; 10.098 ; 10.098 ;
; LDSn         ; RAM_DATA[5]   ; 11.315 ; 11.315 ; 11.315 ; 11.315 ;
; LDSn         ; RAM_DATA[6]   ; 10.556 ; 10.556 ; 10.556 ; 10.556 ;
; LDSn         ; RAM_DATA[7]   ; 10.891 ; 10.891 ; 10.891 ; 10.891 ;
; LDSn         ; RAM_DATA[8]   ; 10.988 ; 11.183 ; 11.183 ; 10.988 ;
; LDSn         ; RAM_DATA[9]   ; 10.276 ; 10.232 ; 10.232 ; 10.276 ;
; LDSn         ; RAM_DATA[10]  ; 9.670  ; 9.670  ; 9.670  ; 9.670  ;
; LDSn         ; RAM_DATA[11]  ; 10.195 ; 9.630  ; 9.630  ; 10.195 ;
; LDSn         ; RAM_DATA[12]  ; 10.036 ; 10.049 ; 10.049 ; 10.036 ;
; LDSn         ; RAM_DATA[13]  ; 10.449 ; 10.449 ; 10.449 ; 10.449 ;
; LDSn         ; RAM_DATA[14]  ; 10.535 ; 10.535 ; 10.535 ; 10.535 ;
; LDSn         ; RAM_DATA[15]  ; 10.152 ; 10.152 ; 10.152 ; 10.152 ;
; LDSn         ; RAM_DQM0L     ; 7.576  ;        ;        ; 7.576  ;
; LDSn         ; RAM_DQM1L     ; 7.582  ;        ;        ; 7.582  ;
; LPT_BSY      ; DATA[0]       ; 10.303 ;        ;        ; 10.303 ;
; LPT_BSY      ; RAM_DATA[0]   ; 11.055 ;        ;        ; 11.055 ;
; LPT_D[0]     ; DATA[8]       ; 10.273 ;        ;        ; 10.273 ;
; LPT_D[0]     ; RAM_DATA[8]   ; 11.151 ;        ;        ; 11.151 ;
; LPT_D[1]     ; DATA[9]       ; 9.971  ;        ;        ; 9.971  ;
; LPT_D[1]     ; RAM_DATA[9]   ; 10.134 ;        ;        ; 10.134 ;
; LPT_D[2]     ; DATA[10]      ; 8.886  ;        ;        ; 8.886  ;
; LPT_D[2]     ; RAM_DATA[10]  ; 9.085  ;        ;        ; 9.085  ;
; LPT_D[3]     ; DATA[11]      ; 9.230  ;        ;        ; 9.230  ;
; LPT_D[3]     ; RAM_DATA[11]  ; 9.719  ;        ;        ; 9.719  ;
; LPT_D[4]     ; DATA[12]      ; 9.364  ;        ;        ; 9.364  ;
; LPT_D[4]     ; RAM_DATA[12]  ; 9.883  ;        ;        ; 9.883  ;
; LPT_D[5]     ; DATA[13]      ; 9.932  ;        ;        ; 9.932  ;
; LPT_D[5]     ; RAM_DATA[13]  ; 10.125 ;        ;        ; 10.125 ;
; LPT_D[6]     ; DATA[14]      ; 9.627  ; 9.627  ; 9.627  ; 9.627  ;
; LPT_D[6]     ; RAM_DATA[14]  ; 10.606 ; 10.606 ; 10.606 ; 10.606 ;
; LPT_D[7]     ; DATA[15]      ; 10.085 ; 10.085 ; 10.085 ; 10.085 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 10.318 ; 10.318 ; 10.318 ; 10.318 ;
; MIDI_IN      ; MIDI_TLR      ; 4.717  ;        ;        ; 4.717  ;
; RAM_DATA[0]  ; DATA[0]       ; 10.401 ;        ;        ; 10.401 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 11.153 ;        ;        ; 11.153 ;
; RAM_DATA[1]  ; DATA[1]       ; 10.335 ;        ;        ; 10.335 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 10.601 ;        ;        ; 10.601 ;
; RAM_DATA[2]  ; DATA[2]       ; 10.144 ;        ;        ; 10.144 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 10.350 ;        ;        ; 10.350 ;
; RAM_DATA[3]  ; DATA[3]       ; 10.998 ;        ;        ; 10.998 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 10.989 ;        ;        ; 10.989 ;
; RAM_DATA[4]  ; DATA[4]       ; 9.969  ;        ;        ; 9.969  ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 9.774  ;        ;        ; 9.774  ;
; RAM_DATA[5]  ; DATA[5]       ; 10.237 ;        ;        ; 10.237 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 11.336 ;        ;        ; 11.336 ;
; RAM_DATA[6]  ; DATA[6]       ; 9.403  ;        ;        ; 9.403  ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 10.465 ;        ;        ; 10.465 ;
; RAM_DATA[7]  ; DATA[7]       ; 9.942  ;        ;        ; 9.942  ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 11.004 ;        ;        ; 11.004 ;
; RAM_DATA[8]  ; DATA[8]       ; 10.883 ;        ;        ; 10.883 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 11.761 ;        ;        ; 11.761 ;
; RAM_DATA[9]  ; DATA[9]       ; 9.909  ;        ;        ; 9.909  ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 10.072 ;        ;        ; 10.072 ;
; RAM_DATA[10] ; DATA[10]      ; 9.475  ;        ;        ; 9.475  ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 9.674  ;        ;        ; 9.674  ;
; RAM_DATA[11] ; DATA[11]      ; 9.839  ;        ;        ; 9.839  ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 10.328 ;        ;        ; 10.328 ;
; RAM_DATA[12] ; DATA[12]      ; 9.414  ;        ;        ; 9.414  ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 9.933  ;        ;        ; 9.933  ;
; RAM_DATA[13] ; DATA[13]      ; 10.593 ;        ;        ; 10.593 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 10.786 ;        ;        ; 10.786 ;
; RAM_DATA[14] ; DATA[14]      ; 10.056 ; 10.056 ; 10.056 ; 10.056 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 11.035 ; 11.035 ; 11.035 ; 11.035 ;
; RAM_DATA[15] ; DATA[15]      ; 9.756  ; 9.756  ; 9.756  ; 9.756  ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 9.989  ; 9.989  ; 9.989  ; 9.989  ;
; RWn          ; ACSI_RDn      ; 9.423  ; 6.722  ; 6.722  ; 9.423  ;
; RWn          ; ACSI_WRn      ; 6.797  ; 9.504  ; 9.504  ; 6.797  ;
; RWn          ; BUTTONn       ;        ; 9.776  ; 9.776  ;        ;
; RWn          ; CA1_OUT       ;        ; 9.508  ; 9.508  ;        ;
; RWn          ; CD[0]         ; 7.808  ; 7.524  ; 7.524  ; 7.808  ;
; RWn          ; CD[1]         ; 7.885  ; 7.603  ; 7.603  ; 7.885  ;
; RWn          ; CD[2]         ; 7.185  ; 6.910  ; 6.910  ; 7.185  ;
; RWn          ; CD[3]         ; 7.909  ; 7.766  ; 7.766  ; 7.909  ;
; RWn          ; CD[4]         ; 7.305  ; 7.305  ; 7.305  ; 7.305  ;
; RWn          ; CD[5]         ; 6.912  ; 6.912  ; 6.912  ; 6.912  ;
; RWn          ; CD[6]         ; 7.026  ; 7.026  ; 7.026  ; 7.026  ;
; RWn          ; CD[7]         ; 7.424  ; 7.424  ; 7.424  ; 7.424  ;
; RWn          ; DATA[0]       ; 8.644  ; 8.537  ; 8.537  ; 8.644  ;
; RWn          ; DATA[1]       ; 8.914  ; 8.896  ; 8.896  ; 8.914  ;
; RWn          ; DATA[2]       ; 8.619  ; 8.105  ; 8.105  ; 8.619  ;
; RWn          ; DATA[3]       ; 8.901  ; 8.901  ; 8.901  ; 8.901  ;
; RWn          ; DATA[4]       ; 8.888  ; 8.888  ; 8.888  ; 8.888  ;
; RWn          ; DATA[5]       ; 8.529  ; 8.529  ; 8.529  ; 8.529  ;
; RWn          ; DATA[6]       ; 7.835  ; 7.835  ; 7.835  ; 7.835  ;
; RWn          ; DATA[7]       ; 8.148  ; 8.148  ; 8.148  ; 8.148  ;
; RWn          ; DATA[8]       ; 8.897  ; 8.897  ; 8.897  ; 8.897  ;
; RWn          ; DATA[9]       ; 8.882  ; 8.395  ; 8.395  ; 8.882  ;
; RWn          ; DATA[10]      ; 8.447  ; 8.171  ; 8.171  ; 8.447  ;
; RWn          ; DATA[11]      ; 8.731  ; 8.609  ; 8.609  ; 8.731  ;
; RWn          ; DATA[12]      ; 8.656  ; 8.557  ; 8.557  ; 8.656  ;
; RWn          ; DATA[13]      ; 9.029  ; 8.640  ; 8.640  ; 9.029  ;
; RWn          ; DATA[14]      ; 7.945  ; 7.945  ; 7.945  ; 7.945  ;
; RWn          ; DATA[15]      ; 8.308  ; 8.308  ; 8.308  ; 8.308  ;
; RWn          ; DTACKn        ; 8.134  ; 8.134  ; 8.134  ; 8.134  ;
; RWn          ; FLASH_CEn     ;        ; 8.609  ; 8.609  ;        ;
; RWn          ; FLASH_OEn     ;        ; 8.622  ; 8.622  ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 6.876  ; 6.876  ;        ;
; RWn          ; IDE_D_EN_OUTn ; 6.826  ;        ;        ; 6.826  ;
; RWn          ; IDE_IORDn     ;        ; 6.869  ; 6.869  ;        ;
; RWn          ; IDE_IOWRn     ; 7.329  ;        ;        ; 7.329  ;
; RWn          ; JOY_RHn       ;        ; 7.465  ; 7.465  ;        ;
; RWn          ; JOY_RLn       ;        ; 8.518  ; 8.518  ;        ;
; RWn          ; JOY_WEn       ; 8.369  ;        ;        ; 8.369  ;
; RWn          ; JOY_WL        ; 8.360  ; 7.143  ; 7.143  ; 8.360  ;
; RWn          ; RAM_DATA[0]   ; 7.740  ; 7.740  ; 7.740  ; 7.740  ;
; RWn          ; RAM_DATA[1]   ; 7.445  ; 7.445  ; 7.445  ; 7.445  ;
; RWn          ; RAM_DATA[2]   ; 7.087  ; 7.087  ; 7.087  ; 7.087  ;
; RWn          ; RAM_DATA[3]   ; 7.201  ; 7.201  ; 7.201  ; 7.201  ;
; RWn          ; RAM_DATA[4]   ; 7.147  ; 7.147  ; 7.147  ; 7.147  ;
; RWn          ; RAM_DATA[5]   ; 7.763  ; 7.763  ; 7.763  ; 7.763  ;
; RWn          ; RAM_DATA[6]   ; 7.719  ; 7.719  ; 7.719  ; 7.719  ;
; RWn          ; RAM_DATA[7]   ; 7.763  ; 7.763  ; 7.763  ; 7.763  ;
; RWn          ; RAM_DATA[8]   ; 7.500  ; 7.500  ; 7.500  ; 7.500  ;
; RWn          ; RAM_DATA[9]   ; 7.165  ; 7.165  ; 7.165  ; 7.165  ;
; RWn          ; RAM_DATA[10]  ; 6.918  ; 6.918  ; 6.918  ; 6.918  ;
; RWn          ; RAM_DATA[11]  ; 7.022  ; 7.022  ; 7.022  ; 7.022  ;
; RWn          ; RAM_DATA[12]  ; 7.092  ; 7.092  ; 7.092  ; 7.092  ;
; RWn          ; RAM_DATA[13]  ; 6.992  ; 6.992  ; 6.992  ; 6.992  ;
; RWn          ; RAM_DATA[14]  ; 7.308  ; 7.308  ; 7.308  ; 7.308  ;
; RWn          ; RAM_DATA[15]  ; 6.881  ; 6.881  ; 6.881  ; 6.881  ;
; RWn          ; RAM_WEn       ; 6.778  ;        ;        ; 6.778  ;
; RWn          ; ROM0n         ;        ; 8.188  ; 8.188  ;        ;
; RWn          ; ROM1n         ;        ; 7.933  ; 7.933  ;        ;
; RWn          ; ROM2n         ;        ; 7.255  ; 7.255  ;        ;
; RWn          ; ROM3n         ;        ; 8.073  ; 8.073  ;        ;
; RWn          ; ROM4n         ;        ; 8.614  ; 8.614  ;        ;
; RWn          ; ROM5n         ;        ; 6.754  ; 6.754  ;        ;
; RWn          ; ROM6n         ;        ; 8.092  ; 8.092  ;        ;
; SCSI_ACKn    ; CD[0]         ; 7.846  ; 7.846  ; 7.846  ; 7.846  ;
; SCSI_ATNn    ; CD[1]         ; 8.363  ; 8.363  ; 8.363  ; 8.363  ;
; SCSI_BSYn    ; CD[6]         ; 9.673  ; 9.673  ; 9.673  ; 9.673  ;
; SCSI_D[0]    ; CD[0]         ; 7.986  ; 7.986  ; 7.986  ; 7.986  ;
; SCSI_D[1]    ; CD[1]         ; 8.119  ; 8.119  ; 8.119  ; 8.119  ;
; SCSI_D[2]    ; CD[2]         ;        ; 8.333  ; 8.333  ;        ;
; SCSI_D[3]    ; CD[3]         ; 8.336  ; 8.336  ; 8.336  ; 8.336  ;
; SCSI_D[4]    ; CD[4]         ; 9.159  ; 9.159  ; 9.159  ; 9.159  ;
; SCSI_D[5]    ; CD[5]         ; 9.101  ; 9.101  ; 9.101  ; 9.101  ;
; SCSI_D[6]    ; CD[6]         ; 9.426  ; 9.426  ; 9.426  ; 9.426  ;
; SCSI_D[7]    ; CD[7]         ; 8.245  ; 8.245  ; 8.245  ; 8.245  ;
; SCSI_DCn     ; CD[3]         ; 8.147  ; 8.147  ; 8.147  ; 8.147  ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 8.586  ; 8.586  ; 8.586  ; 8.586  ;
; SCSI_DCn     ; SCSI_D[0]     ; 8.360  ; 8.360  ; 8.360  ; 8.360  ;
; SCSI_DCn     ; SCSI_D[1]     ; 8.360  ; 8.360  ; 8.360  ; 8.360  ;
; SCSI_DCn     ; SCSI_D[2]     ; 8.061  ; 8.061  ; 8.061  ; 8.061  ;
; SCSI_DCn     ; SCSI_D[3]     ; 8.061  ; 8.061  ; 8.061  ; 8.061  ;
; SCSI_DCn     ; SCSI_D[4]     ; 7.932  ; 7.932  ; 7.932  ; 7.932  ;
; SCSI_DCn     ; SCSI_D[5]     ; 7.932  ; 7.932  ; 7.932  ; 7.932  ;
; SCSI_DCn     ; SCSI_D[6]     ; 7.927  ; 7.927  ; 7.927  ; 7.927  ;
; SCSI_DCn     ; SCSI_D[7]     ; 7.927  ; 7.927  ; 7.927  ; 7.927  ;
; SCSI_DCn     ; SCSI_DP       ; 8.370  ; 8.370  ; 8.370  ; 8.370  ;
; SCSI_DP      ; CD[0]         ; 7.837  ; 7.837  ; 7.837  ; 7.837  ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 6.498  ; 6.498  ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 6.473  ;        ;        ; 6.473  ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 6.358  ; 6.358  ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 6.377  ;        ;        ; 6.377  ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 6.380  ; 6.380  ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 6.291  ;        ;        ; 6.291  ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 6.345  ; 6.345  ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 6.339  ;        ;        ; 6.339  ;
; SCSI_IDn[1]  ; SCSI_DP       ; 6.712  ; 6.712  ; 6.712  ; 6.712  ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 6.307  ; 6.307  ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 6.296  ; 6.296  ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 6.165  ;        ;        ; 6.165  ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 6.208  ;        ;        ; 6.208  ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 6.183  ; 6.183  ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 6.114  ; 6.114  ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 6.138  ;        ;        ; 6.138  ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 6.164  ;        ;        ; 6.164  ;
; SCSI_IDn[2]  ; SCSI_DP       ; 6.535  ; 6.535  ; 6.535  ; 6.535  ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 6.581  ; 6.581  ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 6.568  ; 6.568  ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 6.440  ; 6.440  ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 6.482  ; 6.482  ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 6.451  ;        ;        ; 6.451  ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 6.375  ;        ;        ; 6.375  ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 6.410  ;        ;        ; 6.410  ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 6.436  ;        ;        ; 6.436  ;
; SCSI_IDn[3]  ; SCSI_DP       ; 6.807  ; 6.807  ; 6.807  ; 6.807  ;
; SCSI_IOn     ; CD[2]         ;        ; 8.136  ; 8.136  ;        ;
; SCSI_IOn     ; CD[3]         ; 8.791  ; 8.791  ; 8.791  ; 8.791  ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 6.881  ; 7.955  ; 7.955  ; 6.881  ;
; SCSI_IOn     ; SCSI_D[0]     ; 6.655  ; 6.655  ; 6.655  ; 6.655  ;
; SCSI_IOn     ; SCSI_D[1]     ; 6.655  ; 6.655  ; 6.655  ; 6.655  ;
; SCSI_IOn     ; SCSI_D[2]     ; 6.356  ; 6.356  ; 6.356  ; 6.356  ;
; SCSI_IOn     ; SCSI_D[3]     ; 6.356  ; 6.356  ; 6.356  ; 6.356  ;
; SCSI_IOn     ; SCSI_D[4]     ; 6.227  ; 6.227  ; 6.227  ; 6.227  ;
; SCSI_IOn     ; SCSI_D[5]     ; 6.227  ; 6.227  ; 6.227  ; 6.227  ;
; SCSI_IOn     ; SCSI_D[6]     ; 6.222  ; 6.222  ; 6.222  ; 6.222  ;
; SCSI_IOn     ; SCSI_D[7]     ; 6.222  ; 6.222  ; 6.222  ; 6.222  ;
; SCSI_IOn     ; SCSI_DP       ; 6.665  ; 6.665  ; 6.665  ; 6.665  ;
; SCSI_IOn     ; SCSI_RDn      ; 6.315  ;        ;        ; 6.315  ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 6.741  ; 6.741  ;        ;
; SCSI_MSGn    ; CD[3]         ; 9.033  ; 9.033  ; 9.033  ; 9.033  ;
; SCSI_MSGn    ; CD[4]         ; 9.510  ; 9.510  ; 9.510  ; 9.510  ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 8.197  ; 8.197  ; 8.197  ; 8.197  ;
; SCSI_MSGn    ; SCSI_D[0]     ; 7.971  ; 7.971  ; 7.971  ; 7.971  ;
; SCSI_MSGn    ; SCSI_D[1]     ; 7.971  ; 7.971  ; 7.971  ; 7.971  ;
; SCSI_MSGn    ; SCSI_D[2]     ; 7.672  ; 7.672  ; 7.672  ; 7.672  ;
; SCSI_MSGn    ; SCSI_D[3]     ; 7.672  ; 7.672  ; 7.672  ; 7.672  ;
; SCSI_MSGn    ; SCSI_D[4]     ; 7.543  ; 7.543  ; 7.543  ; 7.543  ;
; SCSI_MSGn    ; SCSI_D[5]     ; 7.543  ; 7.543  ; 7.543  ; 7.543  ;
; SCSI_MSGn    ; SCSI_D[6]     ; 7.538  ; 7.538  ; 7.538  ; 7.538  ;
; SCSI_MSGn    ; SCSI_D[7]     ; 7.538  ; 7.538  ; 7.538  ; 7.538  ;
; SCSI_MSGn    ; SCSI_DP       ; 7.981  ; 7.981  ; 7.981  ; 7.981  ;
; SCSI_REQn    ; CD[3]         ; 9.043  ; 9.043  ; 9.043  ; 9.043  ;
; SCSI_REQn    ; CD[5]         ; 9.406  ; 9.406  ; 9.406  ; 9.406  ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 8.207  ;        ;        ; 8.207  ;
; SCSI_REQn    ; SCSI_D[0]     ; 7.981  ; 7.981  ; 7.981  ; 7.981  ;
; SCSI_REQn    ; SCSI_D[1]     ; 7.981  ; 7.981  ; 7.981  ; 7.981  ;
; SCSI_REQn    ; SCSI_D[2]     ; 7.682  ; 7.682  ; 7.682  ; 7.682  ;
; SCSI_REQn    ; SCSI_D[3]     ; 7.682  ; 7.682  ; 7.682  ; 7.682  ;
; SCSI_REQn    ; SCSI_D[4]     ; 7.553  ; 7.553  ; 7.553  ; 7.553  ;
; SCSI_REQn    ; SCSI_D[5]     ; 7.553  ; 7.553  ; 7.553  ; 7.553  ;
; SCSI_REQn    ; SCSI_D[6]     ; 7.548  ; 7.548  ; 7.548  ; 7.548  ;
; SCSI_REQn    ; SCSI_D[7]     ; 7.548  ; 7.548  ; 7.548  ; 7.548  ;
; SCSI_REQn    ; SCSI_DP       ; 7.991  ; 7.991  ; 7.991  ; 7.991  ;
; SCSI_RSTn    ; CD[7]         ;        ; 8.697  ; 8.697  ;        ;
; SCSI_SELn    ; CD[1]         ; 7.734  ; 7.734  ; 7.734  ; 7.734  ;
; SD_AVR_ENn   ; RESETn        ;        ; 7.858  ; 7.858  ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 6.964  ; 6.964  ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 6.014  ; 6.014  ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 7.086  ;        ;        ; 7.086  ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 6.502  ;        ;        ; 6.502  ;
; SD_RESETn    ; ACSI_RDn      ; 10.050 ; 10.050 ; 10.050 ; 10.050 ;
; SD_RESETn    ; ACSI_WRn      ; 10.131 ; 10.131 ; 10.131 ; 10.131 ;
; SD_RESETn    ; CA1_OUT       ; 10.135 ;        ;        ; 10.135 ;
; SD_RESETn    ; CD[0]         ; 11.136 ; 10.852 ; 10.852 ; 11.136 ;
; SD_RESETn    ; CD[1]         ; 11.213 ; 10.931 ; 10.931 ; 11.213 ;
; SD_RESETn    ; CD[2]         ; 10.513 ; 10.238 ; 10.238 ; 10.513 ;
; SD_RESETn    ; CD[3]         ; 11.237 ; 11.094 ; 11.094 ; 11.237 ;
; SD_RESETn    ; CD[4]         ; 10.633 ; 10.633 ; 10.633 ; 10.633 ;
; SD_RESETn    ; CD[5]         ; 10.240 ; 10.240 ; 10.240 ; 10.240 ;
; SD_RESETn    ; CD[6]         ; 10.354 ; 10.354 ; 10.354 ; 10.354 ;
; SD_RESETn    ; CD[7]         ; 10.752 ; 10.752 ; 10.752 ; 10.752 ;
; SD_RESETn    ; COM_TxD       ; 7.967  ; 7.967  ; 7.967  ; 7.967  ;
; SD_RESETn    ; DATA[0]       ; 11.004 ; 11.004 ; 11.004 ; 11.004 ;
; SD_RESETn    ; DATA[1]       ; 11.331 ; 11.463 ; 11.463 ; 11.331 ;
; SD_RESETn    ; DATA[2]       ; 10.793 ; 11.179 ; 11.179 ; 10.793 ;
; SD_RESETn    ; DATA[3]       ; 11.769 ; 11.769 ; 11.769 ; 11.769 ;
; SD_RESETn    ; DATA[4]       ; 11.486 ; 11.486 ; 11.486 ; 11.486 ;
; SD_RESETn    ; DATA[5]       ; 11.212 ; 11.217 ; 11.217 ; 11.212 ;
; SD_RESETn    ; DATA[6]       ; 10.523 ; 10.523 ; 10.523 ; 10.523 ;
; SD_RESETn    ; DATA[7]       ; 10.836 ; 10.836 ; 10.836 ; 10.836 ;
; SD_RESETn    ; DATA[8]       ; 11.791 ; 12.172 ; 12.172 ; 11.791 ;
; SD_RESETn    ; DATA[9]       ; 11.350 ; 11.674 ; 11.674 ; 11.350 ;
; SD_RESETn    ; DATA[10]      ; 10.859 ; 11.073 ; 11.073 ; 10.859 ;
; SD_RESETn    ; DATA[11]      ; 11.297 ; 11.400 ; 11.400 ; 11.297 ;
; SD_RESETn    ; DATA[12]      ; 11.245 ; 11.412 ; 11.412 ; 11.245 ;
; SD_RESETn    ; DATA[13]      ; 11.328 ; 11.595 ; 11.595 ; 11.328 ;
; SD_RESETn    ; DATA[14]      ; 10.238 ; 10.238 ; 10.238 ; 10.238 ;
; SD_RESETn    ; DATA[15]      ; 10.601 ; 10.601 ; 10.601 ; 10.601 ;
; SD_RESETn    ; DTACKn        ; 8.078  ; 8.078  ; 8.078  ; 8.078  ;
; SD_RESETn    ; RAM_DATA[0]   ; 11.756 ; 11.756 ; 11.756 ; 11.756 ;
; SD_RESETn    ; RAM_DATA[1]   ; 11.597 ; 11.729 ; 11.729 ; 11.597 ;
; SD_RESETn    ; RAM_DATA[2]   ; 10.999 ; 11.385 ; 11.385 ; 10.999 ;
; SD_RESETn    ; RAM_DATA[3]   ; 11.760 ; 11.760 ; 11.760 ; 11.760 ;
; SD_RESETn    ; RAM_DATA[4]   ; 11.291 ; 11.291 ; 11.291 ; 11.291 ;
; SD_RESETn    ; RAM_DATA[5]   ; 12.311 ; 12.316 ; 12.316 ; 12.311 ;
; SD_RESETn    ; RAM_DATA[6]   ; 11.585 ; 11.585 ; 11.585 ; 11.585 ;
; SD_RESETn    ; RAM_DATA[7]   ; 11.898 ; 11.898 ; 11.898 ; 11.898 ;
; SD_RESETn    ; RAM_DATA[8]   ; 12.669 ; 13.050 ; 13.050 ; 12.669 ;
; SD_RESETn    ; RAM_DATA[9]   ; 11.513 ; 11.837 ; 11.837 ; 11.513 ;
; SD_RESETn    ; RAM_DATA[10]  ; 11.058 ; 11.272 ; 11.272 ; 11.058 ;
; SD_RESETn    ; RAM_DATA[11]  ; 11.786 ; 11.889 ; 11.889 ; 11.786 ;
; SD_RESETn    ; RAM_DATA[12]  ; 11.764 ; 11.931 ; 11.931 ; 11.764 ;
; SD_RESETn    ; RAM_DATA[13]  ; 11.521 ; 11.788 ; 11.788 ; 11.521 ;
; SD_RESETn    ; RAM_DATA[14]  ; 11.217 ; 11.217 ; 11.217 ; 11.217 ;
; SD_RESETn    ; RAM_DATA[15]  ; 10.834 ; 10.834 ; 10.834 ; 10.834 ;
; UDSn         ; ACSI_RDn      ; 8.359  ; 8.359  ; 8.359  ; 8.359  ;
; UDSn         ; ACSI_WRn      ; 8.440  ; 8.440  ; 8.440  ; 8.440  ;
; UDSn         ; CA1_OUT       ; 8.444  ;        ;        ; 8.444  ;
; UDSn         ; CD[0]         ; 9.445  ; 9.161  ; 9.161  ; 9.445  ;
; UDSn         ; CD[1]         ; 9.522  ; 9.240  ; 9.240  ; 9.522  ;
; UDSn         ; CD[2]         ; 8.822  ; 8.547  ; 8.547  ; 8.822  ;
; UDSn         ; CD[3]         ; 9.546  ; 9.403  ; 9.403  ; 9.546  ;
; UDSn         ; CD[4]         ; 8.942  ; 8.942  ; 8.942  ; 8.942  ;
; UDSn         ; CD[5]         ; 8.549  ; 8.549  ; 8.549  ; 8.549  ;
; UDSn         ; CD[6]         ; 8.663  ; 8.663  ; 8.663  ; 8.663  ;
; UDSn         ; CD[7]         ; 9.061  ; 9.061  ; 9.061  ; 9.061  ;
; UDSn         ; DATA[0]       ; 8.411  ; 8.411  ; 8.411  ; 8.411  ;
; UDSn         ; DATA[1]       ; 8.411  ; 8.411  ; 8.411  ; 8.411  ;
; UDSn         ; DATA[2]       ; 8.398  ; 8.398  ; 8.398  ; 8.398  ;
; UDSn         ; DATA[3]       ; 8.398  ; 8.398  ; 8.398  ; 8.398  ;
; UDSn         ; DATA[4]       ; 8.385  ; 8.385  ; 8.385  ; 8.385  ;
; UDSn         ; DATA[5]       ; 8.385  ; 8.385  ; 8.385  ; 8.385  ;
; UDSn         ; DATA[6]       ; 8.356  ; 8.356  ; 8.356  ; 8.356  ;
; UDSn         ; DATA[7]       ; 8.346  ; 8.346  ; 8.346  ; 8.346  ;
; UDSn         ; DATA[8]       ; 8.394  ; 8.394  ; 8.394  ; 8.394  ;
; UDSn         ; DATA[9]       ; 8.394  ; 8.394  ; 8.394  ; 8.394  ;
; UDSn         ; DATA[10]      ; 8.547  ; 8.547  ; 8.547  ; 8.547  ;
; UDSn         ; DATA[11]      ; 8.547  ; 8.463  ; 8.463  ; 8.547  ;
; UDSn         ; DATA[12]      ; 8.526  ; 8.526  ; 8.526  ; 8.526  ;
; UDSn         ; DATA[13]      ; 8.526  ; 8.526  ; 8.526  ; 8.526  ;
; UDSn         ; DATA[14]      ; 8.685  ; 8.685  ; 8.685  ; 8.685  ;
; UDSn         ; DATA[15]      ; 8.675  ; 8.675  ; 8.675  ; 8.675  ;
; UDSn         ; DTACKn        ; 7.143  ; 7.143  ; 7.143  ; 7.143  ;
; UDSn         ; JOY_RHn       ; 7.060  ;        ;        ; 7.060  ;
; UDSn         ; RAM_CAS0n     ; 6.967  ;        ;        ; 6.967  ;
; UDSn         ; RAM_CAS1n     ; 6.987  ;        ;        ; 6.987  ;
; UDSn         ; RAM_DATA[0]   ; 9.901  ; 9.901  ; 9.901  ; 9.901  ;
; UDSn         ; RAM_DATA[1]   ; 9.341  ; 9.636  ; 9.636  ; 9.341  ;
; UDSn         ; RAM_DATA[2]   ; 9.531  ; 9.634  ; 9.634  ; 9.531  ;
; UDSn         ; RAM_DATA[3]   ; 9.795  ; 9.853  ; 9.853  ; 9.795  ;
; UDSn         ; RAM_DATA[4]   ; 9.420  ; 9.420  ; 9.420  ; 9.420  ;
; UDSn         ; RAM_DATA[5]   ; 10.754 ; 10.780 ; 10.780 ; 10.754 ;
; UDSn         ; RAM_DATA[6]   ; 9.878  ; 10.109 ; 10.109 ; 9.878  ;
; UDSn         ; RAM_DATA[7]   ; 10.302 ; 10.430 ; 10.430 ; 10.302 ;
; UDSn         ; RAM_DATA[8]   ; 10.310 ; 10.505 ; 10.505 ; 10.310 ;
; UDSn         ; RAM_DATA[9]   ; 9.664  ; 9.554  ; 9.554  ; 9.664  ;
; UDSn         ; RAM_DATA[10]  ; 9.170  ; 9.170  ; 9.170  ; 9.170  ;
; UDSn         ; RAM_DATA[11]  ; 9.517  ; 8.952  ; 8.952  ; 9.517  ;
; UDSn         ; RAM_DATA[12]  ; 9.658  ; 9.669  ; 9.669  ; 9.658  ;
; UDSn         ; RAM_DATA[13]  ; 9.894  ; 9.894  ; 9.894  ; 9.894  ;
; UDSn         ; RAM_DATA[14]  ; 9.889  ; 9.889  ; 9.889  ; 9.889  ;
; UDSn         ; RAM_DATA[15]  ; 9.506  ; 9.506  ; 9.506  ; 9.506  ;
; UDSn         ; RAM_DQM0H     ; 7.461  ;        ;        ; 7.461  ;
; UDSn         ; RAM_DQM1H     ; 6.725  ;        ;        ; 6.725  ;
+--------------+---------------+--------+--------+--------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                 ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+--------------+------------+
; From Clock                                                 ; To Clock                                                   ; RR Paths     ; FR Paths   ; RF Paths     ; FF Paths   ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+--------------+------------+
; CLK_PLL1                                                   ; CLK_PLL1                                                   ; 51           ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; CODEC_SCLK                                                 ; 102503       ; 9122       ; 94           ; 487        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path   ; false path ; false path   ; false path ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 120          ; 120        ; 5            ; 5          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; 10034874   ; > 2147483647 ; 590097     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; 10034874   ; > 2147483647 ; 590097     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 568887       ; 0          ; 29781        ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 568887       ; 0          ; 29781        ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 863749       ; 0          ; 50836        ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 863749       ; 0          ; 50836        ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1            ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 129          ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path   ; false path ; false path   ; false path ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 120          ; 120        ; 5            ; 5          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; 10034874   ; > 2147483647 ; 590097     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; 10034874   ; > 2147483647 ; 590097     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 568887       ; 0          ; 29781        ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 568887       ; 0          ; 29781        ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 863749       ; 0          ; 50836        ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 863749       ; 0          ; 50836        ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1            ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 129          ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 78           ; 78         ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; 956319     ; 163630308    ; 568        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; 956319     ; 163630308    ; 568        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 165509       ; 0          ; 144          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 165509       ; 0          ; 144          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 60663        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 60663        ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 11           ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 78           ; 78         ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; 956319     ; 163630308    ; 568        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; 956319     ; 163630308    ; 568        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 165509       ; 0          ; 144          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 165509       ; 0          ; 144          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 60663        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 60663        ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 11           ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; false path   ; 0          ; 0            ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 1            ; 1          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; > 2147483647 ; 162650     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; > 2147483647 ; 162650     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 6455         ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 6455         ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 2207301      ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 2207301      ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; false path   ; 0          ; 0            ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 1            ; 1          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; > 2147483647 ; 162650     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; > 2147483647 ; 162650     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 6455         ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 6455         ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 2207301      ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 2207301      ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 3            ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 10           ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 18           ; 0          ; 0            ; 0          ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+--------------+------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                  ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+--------------+------------+
; From Clock                                                 ; To Clock                                                   ; RR Paths     ; FR Paths   ; RF Paths     ; FF Paths   ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+--------------+------------+
; CLK_PLL1                                                   ; CLK_PLL1                                                   ; 51           ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; CODEC_SCLK                                                 ; 102503       ; 9122       ; 94           ; 487        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path   ; false path ; false path   ; false path ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 120          ; 120        ; 5            ; 5          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; 10034874   ; > 2147483647 ; 590097     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; 10034874   ; > 2147483647 ; 590097     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 568887       ; 0          ; 29781        ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 568887       ; 0          ; 29781        ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 863749       ; 0          ; 50836        ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 863749       ; 0          ; 50836        ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1            ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 129          ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path   ; false path ; false path   ; false path ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 120          ; 120        ; 5            ; 5          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; 10034874   ; > 2147483647 ; 590097     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; 10034874   ; > 2147483647 ; 590097     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 568887       ; 0          ; 29781        ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 568887       ; 0          ; 29781        ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 863749       ; 0          ; 50836        ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 863749       ; 0          ; 50836        ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1            ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 129          ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 78           ; 78         ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; 956319     ; 163630308    ; 568        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; 956319     ; 163630308    ; 568        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 165509       ; 0          ; 144          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 165509       ; 0          ; 144          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 60663        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 60663        ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 11           ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 78           ; 78         ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; 956319     ; 163630308    ; 568        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; 956319     ; 163630308    ; 568        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 165509       ; 0          ; 144          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 165509       ; 0          ; 144          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 60663        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 60663        ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 11           ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; false path   ; 0          ; 0            ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 1            ; 1          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; > 2147483647 ; 162650     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; > 2147483647 ; 162650     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 6455         ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 6455         ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 2207301      ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 2207301      ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; false path   ; 0          ; 0            ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 1            ; 1          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; > 2147483647 ; 162650     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; > 2147483647 ; 162650     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 6455         ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 6455         ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 2207301      ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 2207301      ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 3            ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 10           ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 18           ; 0          ; 0            ; 0          ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+--------------+------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                      ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                 ; To Clock                                                   ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; CLK_PLL1                                                   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; CODEC_SCLK                                                 ; CODEC_SCLK                                                 ; 0          ; 0        ; 0          ; 1        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 17880      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 17880      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 23352      ; 0        ; 816        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 23352      ; 0        ; 816        ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 17880      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 17880      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 23352      ; 0        ; 816        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 23352      ; 0        ; 816        ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 9192       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 9192       ; 0        ; 0          ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 9192       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 9192       ; 0        ; 0          ; 0        ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                       ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                 ; To Clock                                                   ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; CLK_PLL1                                                   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; CODEC_SCLK                                                 ; CODEC_SCLK                                                 ; 0          ; 0        ; 0          ; 1        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 17880      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 17880      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 23352      ; 0        ; 816        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 23352      ; 0        ; 816        ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 17880      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 17880      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 23352      ; 0        ; 816        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 23352      ; 0        ; 816        ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 9192       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 9192       ; 0        ; 0          ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 9192       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 9192       ; 0        ; 0          ; 0        ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+-------------------------------------------------+
; Unconstrained Paths                             ;
+---------------------------------+-------+-------+
; Property                        ; Setup ; Hold  ;
+---------------------------------+-------+-------+
; Illegal Clocks                  ; 0     ; 0     ;
; Unconstrained Clocks            ; 0     ; 0     ;
; Unconstrained Input Ports       ; 136   ; 136   ;
; Unconstrained Input Port Paths  ; 29218 ; 29218 ;
; Unconstrained Output Ports      ; 234   ; 234   ;
; Unconstrained Output Port Paths ; 31993 ; 31993 ;
+---------------------------------+-------+-------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
    Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
    Info: Processing started: Thu Dec 09 15:45:46 2021
Info: Command: quartus_sta SUSKA-III-C -c SUSKA-III-C
Info: qsta_default_script.tcl version: #1
Warning: Parallel compilation is not licensed and has been disabled
Info: Reading SDC File: '../../../rtl/vhdl/SUSKA-III-C/suska_cycloneII_core_ste.sdc'
Info: Deriving PLL Clocks
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[1]} -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1} {I_SYSCLOCKS|altpll_component|pll|clk[0]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[0]} -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0} {I_SYSCLOCKS|altpll_component|pll|clk[0]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[1]} -multiply_by 2 -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1} {I_SYSCLOCKS|altpll_component|pll|clk[1]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1} {I_SYSCLOCKS|altpll_component|pll|clk[1]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[1]} -multiply_by 3 -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1} {I_SYSCLOCKS|altpll_component|pll|clk[2]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2} {I_SYSCLOCKS|altpll_component|pll|clk[2]}
    Info: create_generated_clock -source {I_AUXCLOCKS|altpll_component|pll|inclk[0]} -divide_by 5 -multiply_by 8 -duty_cycle 50.00 -name {cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0} {I_AUXCLOCKS|altpll_component|pll|clk[0]}
    Info: create_generated_clock -source {I_AUXCLOCKS|altpll_component|pll|inclk[0]} -divide_by 13 -multiply_by 32 -duty_cycle 50.00 -name {cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1} {I_AUXCLOCKS|altpll_component|pll|clk[1]}
    Info: create_generated_clock -source {I_AUXCLOCKS|altpll_component|pll|inclk[0]} -duty_cycle 50.00 -name {cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2} {I_AUXCLOCKS|altpll_component|pll|clk[2]}
Info: Analyzing Slow Model
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -15.012
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:   -15.012     -5654.283 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:   -15.012     -5654.283 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:   -14.850     -1984.888 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:   -14.850     -1984.888 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:   -12.179      -347.707 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:   -12.179      -347.707 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:    22.922         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    30.318         0.000 CODEC_SCLK 
    Info:    38.203         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    59.724         0.000 CLK_PLL1 
    Info:    60.376         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
Info: Worst-case hold slack is 0.228
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.228         0.000 CODEC_SCLK 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:     0.445         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:     0.445         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.445         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:     0.615         0.000 CLK_PLL1 
Info: Worst-case recovery slack is 20.664
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    20.664         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    20.664         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    20.664         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    20.664         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    78.914         0.000 CODEC_SCLK 
Info: Worst-case removal slack is 2.196
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     2.196         0.000 CODEC_SCLK 
    Info:     2.424         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     2.424         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     2.574         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     2.574         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
Info: Worst-case minimum pulse width slack is 7.852
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     7.852         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:     7.852         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:    11.584         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.061         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.061         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    18.420         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    28.943         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    28.943         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    30.139         0.000 CLK_PLL1 
    Info:    30.139         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:    31.250         0.000 CLK_PLL2 
    Info:    31.250         0.000 CRT_PIN4_CLK1 
    Info:    38.136         0.000 CODEC_SCLK 
Info: The selected device family is not supported by the report_metastability command.
Info: Analyzing Fast Model
Info: Worst-case setup slack is 1.069
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     1.069         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     1.069         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:     1.138         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     1.138         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     3.048         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:     3.048         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:    24.422         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    36.626         0.000 CODEC_SCLK 
    Info:    38.707         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    61.367         0.000 CLK_PLL1 
    Info:    61.685         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
Info: Worst-case hold slack is 0.073
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.073         0.000 CODEC_SCLK 
    Info:     0.215         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     0.215         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:     0.215         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.215         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     0.215         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:     0.215         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:     0.215         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:     0.215         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.215         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:     0.239         0.000 CLK_PLL1 
Info: Worst-case recovery slack is 26.724
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    26.724         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    26.724         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    26.726         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    26.726         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    80.188         0.000 CODEC_SCLK 
Info: Worst-case removal slack is 1.063
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     1.063         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     1.063         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     1.073         0.000 CODEC_SCLK 
    Info:     1.088         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     1.088         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
Info: Worst-case minimum pulse width slack is 8.289
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     8.289         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:     8.289         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:    11.695         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.498         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.498         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    18.531         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    29.231         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    29.231         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    30.250         0.000 CLK_PLL1 
    Info:    30.250         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:    31.250         0.000 CLK_PLL2 
    Info:    31.250         0.000 CRT_PIN4_CLK1 
    Info:    38.573         0.000 CODEC_SCLK 
Info: The selected device family is not supported by the report_metastability command.
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 536 megabytes
    Info: Processing ended: Thu Dec 09 15:46:14 2021
    Info: Elapsed time: 00:00:28
    Info: Total CPU time (on all processors): 00:00:28


